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authorYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>2011-02-25 02:40:16 -0500
committerPaul Mundt <lethal@linux-sh.org>2011-03-10 22:36:29 -0500
commit8ac53ed537a4a32d81279d37476bfaeb2aff15ab (patch)
tree2a0ffa6997403201f837ba771a6e655fffc5fe59 /arch/sh/kernel/cpu/sh4a
parent53bc18ef4d8cb287c0667389fa05721aedf54e15 (diff)
sh: dmaengine support for SH7757
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/cpu/sh4a')
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7757.c518
1 files changed, 517 insertions, 1 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
index 480f6651164f..423dabf542d3 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * SH7757 Setup 2 * SH7757 Setup
3 * 3 *
4 * Copyright (C) 2009 Renesas Solutions Corp. 4 * Copyright (C) 2009, 2011 Renesas Solutions Corp.
5 * 5 *
6 * based on setup-sh7785.c : Copyright (C) 2007 Paul Mundt 6 * based on setup-sh7785.c : Copyright (C) 2007 Paul Mundt
7 * 7 *
@@ -16,6 +16,10 @@
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/mm.h> 17#include <linux/mm.h>
18#include <linux/sh_timer.h> 18#include <linux/sh_timer.h>
19#include <linux/sh_dma.h>
20
21#include <cpu/dma-register.h>
22#include <cpu/sh7757.h>
19 23
20static struct plat_sci_port scif2_platform_data = { 24static struct plat_sci_port scif2_platform_data = {
21 .mapbase = 0xfe4b0000, /* SCIF2 */ 25 .mapbase = 0xfe4b0000, /* SCIF2 */
@@ -136,6 +140,514 @@ static struct resource spi0_resources[] = {
136 }, 140 },
137}; 141};
138 142
143/* DMA */
144static const struct sh_dmae_slave_config sh7757_dmae0_slaves[] = {
145 {
146 .slave_id = SHDMA_SLAVE_SDHI_TX,
147 .addr = 0x1fe50030,
148 .chcr = SM_INC | 0x800 | 0x40000000 |
149 TS_INDEX2VAL(XMIT_SZ_16BIT),
150 .mid_rid = 0xc5,
151 },
152 {
153 .slave_id = SHDMA_SLAVE_SDHI_RX,
154 .addr = 0x1fe50030,
155 .chcr = DM_INC | 0x800 | 0x40000000 |
156 TS_INDEX2VAL(XMIT_SZ_16BIT),
157 .mid_rid = 0xc6,
158 },
159 {
160 .slave_id = SHDMA_SLAVE_MMCIF_TX,
161 .addr = 0x1fcb0034,
162 .chcr = SM_INC | 0x800 | 0x40000000 |
163 TS_INDEX2VAL(XMIT_SZ_32BIT),
164 .mid_rid = 0xd3,
165 },
166 {
167 .slave_id = SHDMA_SLAVE_MMCIF_RX,
168 .addr = 0x1fcb0034,
169 .chcr = DM_INC | 0x800 | 0x40000000 |
170 TS_INDEX2VAL(XMIT_SZ_32BIT),
171 .mid_rid = 0xd7,
172 },
173};
174
175static const struct sh_dmae_slave_config sh7757_dmae1_slaves[] = {
176 {
177 .slave_id = SHDMA_SLAVE_SCIF2_TX,
178 .addr = 0x1f4b000c,
179 .chcr = SM_INC | 0x800 | 0x40000000 |
180 TS_INDEX2VAL(XMIT_SZ_8BIT),
181 .mid_rid = 0x21,
182 },
183 {
184 .slave_id = SHDMA_SLAVE_SCIF2_RX,
185 .addr = 0x1f4b0014,
186 .chcr = SM_INC | 0x800 | 0x40000000 |
187 TS_INDEX2VAL(XMIT_SZ_8BIT),
188 .mid_rid = 0x22,
189 },
190 {
191 .slave_id = SHDMA_SLAVE_SCIF3_TX,
192 .addr = 0x1f4c000c,
193 .chcr = SM_INC | 0x800 | 0x40000000 |
194 TS_INDEX2VAL(XMIT_SZ_8BIT),
195 .mid_rid = 0x29,
196 },
197 {
198 .slave_id = SHDMA_SLAVE_SCIF3_RX,
199 .addr = 0x1f4c0014,
200 .chcr = SM_INC | 0x800 | 0x40000000 |
201 TS_INDEX2VAL(XMIT_SZ_8BIT),
202 .mid_rid = 0x2a,
203 },
204 {
205 .slave_id = SHDMA_SLAVE_SCIF4_TX,
206 .addr = 0x1f4d000c,
207 .chcr = SM_INC | 0x800 | 0x40000000 |
208 TS_INDEX2VAL(XMIT_SZ_8BIT),
209 .mid_rid = 0x41,
210 },
211 {
212 .slave_id = SHDMA_SLAVE_SCIF4_RX,
213 .addr = 0x1f4d0014,
214 .chcr = SM_INC | 0x800 | 0x40000000 |
215 TS_INDEX2VAL(XMIT_SZ_8BIT),
216 .mid_rid = 0x42,
217 },
218};
219
220static const struct sh_dmae_slave_config sh7757_dmae2_slaves[] = {
221 {
222 .slave_id = SHDMA_SLAVE_RIIC0_TX,
223 .addr = 0x1e500012,
224 .chcr = SM_INC | 0x800 | 0x40000000 |
225 TS_INDEX2VAL(XMIT_SZ_8BIT),
226 .mid_rid = 0x21,
227 },
228 {
229 .slave_id = SHDMA_SLAVE_RIIC0_RX,
230 .addr = 0x1e500013,
231 .chcr = SM_INC | 0x800 | 0x40000000 |
232 TS_INDEX2VAL(XMIT_SZ_8BIT),
233 .mid_rid = 0x22,
234 },
235 {
236 .slave_id = SHDMA_SLAVE_RIIC1_TX,
237 .addr = 0x1e510012,
238 .chcr = SM_INC | 0x800 | 0x40000000 |
239 TS_INDEX2VAL(XMIT_SZ_8BIT),
240 .mid_rid = 0x29,
241 },
242 {
243 .slave_id = SHDMA_SLAVE_RIIC1_RX,
244 .addr = 0x1e510013,
245 .chcr = SM_INC | 0x800 | 0x40000000 |
246 TS_INDEX2VAL(XMIT_SZ_8BIT),
247 .mid_rid = 0x2a,
248 },
249 {
250 .slave_id = SHDMA_SLAVE_RIIC2_TX,
251 .addr = 0x1e520012,
252 .chcr = SM_INC | 0x800 | 0x40000000 |
253 TS_INDEX2VAL(XMIT_SZ_8BIT),
254 .mid_rid = 0xa1,
255 },
256 {
257 .slave_id = SHDMA_SLAVE_RIIC2_RX,
258 .addr = 0x1e520013,
259 .chcr = SM_INC | 0x800 | 0x40000000 |
260 TS_INDEX2VAL(XMIT_SZ_8BIT),
261 .mid_rid = 0xa2,
262 },
263 {
264 .slave_id = SHDMA_SLAVE_RIIC3_TX,
265 .addr = 0x1e530012,
266 .chcr = SM_INC | 0x800 | 0x40000000 |
267 TS_INDEX2VAL(XMIT_SZ_8BIT),
268 .mid_rid = 0xab,
269 },
270 {
271 .slave_id = SHDMA_SLAVE_RIIC3_RX,
272 .addr = 0x1e530013,
273 .chcr = SM_INC | 0x800 | 0x40000000 |
274 TS_INDEX2VAL(XMIT_SZ_8BIT),
275 .mid_rid = 0xaf,
276 },
277 {
278 .slave_id = SHDMA_SLAVE_RIIC4_TX,
279 .addr = 0x1e540012,
280 .chcr = SM_INC | 0x800 | 0x40000000 |
281 TS_INDEX2VAL(XMIT_SZ_8BIT),
282 .mid_rid = 0xc1,
283 },
284 {
285 .slave_id = SHDMA_SLAVE_RIIC4_RX,
286 .addr = 0x1e540013,
287 .chcr = SM_INC | 0x800 | 0x40000000 |
288 TS_INDEX2VAL(XMIT_SZ_8BIT),
289 .mid_rid = 0xc2,
290 },
291};
292
293static const struct sh_dmae_slave_config sh7757_dmae3_slaves[] = {
294 {
295 .slave_id = SHDMA_SLAVE_RIIC5_TX,
296 .addr = 0x1e550012,
297 .chcr = SM_INC | 0x800 | 0x40000000 |
298 TS_INDEX2VAL(XMIT_SZ_8BIT),
299 .mid_rid = 0x21,
300 },
301 {
302 .slave_id = SHDMA_SLAVE_RIIC5_RX,
303 .addr = 0x1e550013,
304 .chcr = SM_INC | 0x800 | 0x40000000 |
305 TS_INDEX2VAL(XMIT_SZ_8BIT),
306 .mid_rid = 0x22,
307 },
308 {
309 .slave_id = SHDMA_SLAVE_RIIC6_TX,
310 .addr = 0x1e560012,
311 .chcr = SM_INC | 0x800 | 0x40000000 |
312 TS_INDEX2VAL(XMIT_SZ_8BIT),
313 .mid_rid = 0x29,
314 },
315 {
316 .slave_id = SHDMA_SLAVE_RIIC6_RX,
317 .addr = 0x1e560013,
318 .chcr = SM_INC | 0x800 | 0x40000000 |
319 TS_INDEX2VAL(XMIT_SZ_8BIT),
320 .mid_rid = 0x2a,
321 },
322 {
323 .slave_id = SHDMA_SLAVE_RIIC7_TX,
324 .addr = 0x1e570012,
325 .chcr = SM_INC | 0x800 | 0x40000000 |
326 TS_INDEX2VAL(XMIT_SZ_8BIT),
327 .mid_rid = 0x41,
328 },
329 {
330 .slave_id = SHDMA_SLAVE_RIIC7_RX,
331 .addr = 0x1e570013,
332 .chcr = SM_INC | 0x800 | 0x40000000 |
333 TS_INDEX2VAL(XMIT_SZ_8BIT),
334 .mid_rid = 0x42,
335 },
336 {
337 .slave_id = SHDMA_SLAVE_RIIC8_TX,
338 .addr = 0x1e580012,
339 .chcr = SM_INC | 0x800 | 0x40000000 |
340 TS_INDEX2VAL(XMIT_SZ_8BIT),
341 .mid_rid = 0x45,
342 },
343 {
344 .slave_id = SHDMA_SLAVE_RIIC8_RX,
345 .addr = 0x1e580013,
346 .chcr = SM_INC | 0x800 | 0x40000000 |
347 TS_INDEX2VAL(XMIT_SZ_8BIT),
348 .mid_rid = 0x46,
349 },
350 {
351 .slave_id = SHDMA_SLAVE_RIIC9_TX,
352 .addr = 0x1e590012,
353 .chcr = SM_INC | 0x800 | 0x40000000 |
354 TS_INDEX2VAL(XMIT_SZ_8BIT),
355 .mid_rid = 0x51,
356 },
357 {
358 .slave_id = SHDMA_SLAVE_RIIC9_RX,
359 .addr = 0x1e590013,
360 .chcr = SM_INC | 0x800 | 0x40000000 |
361 TS_INDEX2VAL(XMIT_SZ_8BIT),
362 .mid_rid = 0x52,
363 },
364};
365
366static const struct sh_dmae_channel sh7757_dmae_channels[] = {
367 {
368 .offset = 0,
369 .dmars = 0,
370 .dmars_bit = 0,
371 }, {
372 .offset = 0x10,
373 .dmars = 0,
374 .dmars_bit = 8,
375 }, {
376 .offset = 0x20,
377 .dmars = 4,
378 .dmars_bit = 0,
379 }, {
380 .offset = 0x30,
381 .dmars = 4,
382 .dmars_bit = 8,
383 }, {
384 .offset = 0x50,
385 .dmars = 8,
386 .dmars_bit = 0,
387 }, {
388 .offset = 0x60,
389 .dmars = 8,
390 .dmars_bit = 8,
391 }
392};
393
394static const unsigned int ts_shift[] = TS_SHIFT;
395
396static struct sh_dmae_pdata dma0_platform_data = {
397 .slave = sh7757_dmae0_slaves,
398 .slave_num = ARRAY_SIZE(sh7757_dmae0_slaves),
399 .channel = sh7757_dmae_channels,
400 .channel_num = ARRAY_SIZE(sh7757_dmae_channels),
401 .ts_low_shift = CHCR_TS_LOW_SHIFT,
402 .ts_low_mask = CHCR_TS_LOW_MASK,
403 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
404 .ts_high_mask = CHCR_TS_HIGH_MASK,
405 .ts_shift = ts_shift,
406 .ts_shift_num = ARRAY_SIZE(ts_shift),
407 .dmaor_init = DMAOR_INIT,
408};
409
410static struct sh_dmae_pdata dma1_platform_data = {
411 .slave = sh7757_dmae1_slaves,
412 .slave_num = ARRAY_SIZE(sh7757_dmae1_slaves),
413 .channel = sh7757_dmae_channels,
414 .channel_num = ARRAY_SIZE(sh7757_dmae_channels),
415 .ts_low_shift = CHCR_TS_LOW_SHIFT,
416 .ts_low_mask = CHCR_TS_LOW_MASK,
417 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
418 .ts_high_mask = CHCR_TS_HIGH_MASK,
419 .ts_shift = ts_shift,
420 .ts_shift_num = ARRAY_SIZE(ts_shift),
421 .dmaor_init = DMAOR_INIT,
422};
423
424static struct sh_dmae_pdata dma2_platform_data = {
425 .slave = sh7757_dmae2_slaves,
426 .slave_num = ARRAY_SIZE(sh7757_dmae2_slaves),
427 .channel = sh7757_dmae_channels,
428 .channel_num = ARRAY_SIZE(sh7757_dmae_channels),
429 .ts_low_shift = CHCR_TS_LOW_SHIFT,
430 .ts_low_mask = CHCR_TS_LOW_MASK,
431 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
432 .ts_high_mask = CHCR_TS_HIGH_MASK,
433 .ts_shift = ts_shift,
434 .ts_shift_num = ARRAY_SIZE(ts_shift),
435 .dmaor_init = DMAOR_INIT,
436};
437
438static struct sh_dmae_pdata dma3_platform_data = {
439 .slave = sh7757_dmae3_slaves,
440 .slave_num = ARRAY_SIZE(sh7757_dmae3_slaves),
441 .channel = sh7757_dmae_channels,
442 .channel_num = ARRAY_SIZE(sh7757_dmae_channels),
443 .ts_low_shift = CHCR_TS_LOW_SHIFT,
444 .ts_low_mask = CHCR_TS_LOW_MASK,
445 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
446 .ts_high_mask = CHCR_TS_HIGH_MASK,
447 .ts_shift = ts_shift,
448 .ts_shift_num = ARRAY_SIZE(ts_shift),
449 .dmaor_init = DMAOR_INIT,
450};
451
452/* channel 0 to 5 */
453static struct resource sh7757_dmae0_resources[] = {
454 [0] = {
455 /* Channel registers and DMAOR */
456 .start = 0xff608020,
457 .end = 0xff60808f,
458 .flags = IORESOURCE_MEM,
459 },
460 [1] = {
461 /* DMARSx */
462 .start = 0xff609000,
463 .end = 0xff60900b,
464 .flags = IORESOURCE_MEM,
465 },
466 {
467 .start = 34,
468 .end = 34,
469 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
470 },
471};
472
473/* channel 6 to 11 */
474static struct resource sh7757_dmae1_resources[] = {
475 [0] = {
476 /* Channel registers and DMAOR */
477 .start = 0xff618020,
478 .end = 0xff61808f,
479 .flags = IORESOURCE_MEM,
480 },
481 [1] = {
482 /* DMARSx */
483 .start = 0xff619000,
484 .end = 0xff61900b,
485 .flags = IORESOURCE_MEM,
486 },
487 {
488 /* DMA error */
489 .start = 34,
490 .end = 34,
491 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
492 },
493 {
494 /* IRQ for channels 4 */
495 .start = 46,
496 .end = 46,
497 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
498 },
499 {
500 /* IRQ for channels 5 */
501 .start = 46,
502 .end = 46,
503 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
504 },
505 {
506 /* IRQ for channels 6 */
507 .start = 88,
508 .end = 88,
509 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
510 },
511 {
512 /* IRQ for channels 7 */
513 .start = 88,
514 .end = 88,
515 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
516 },
517 {
518 /* IRQ for channels 8 */
519 .start = 88,
520 .end = 88,
521 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
522 },
523 {
524 /* IRQ for channels 9 */
525 .start = 88,
526 .end = 88,
527 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
528 },
529 {
530 /* IRQ for channels 10 */
531 .start = 88,
532 .end = 88,
533 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
534 },
535 {
536 /* IRQ for channels 11 */
537 .start = 88,
538 .end = 88,
539 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
540 },
541};
542
543/* channel 12 to 17 */
544static struct resource sh7757_dmae2_resources[] = {
545 [0] = {
546 /* Channel registers and DMAOR */
547 .start = 0xff708020,
548 .end = 0xff70808f,
549 .flags = IORESOURCE_MEM,
550 },
551 [1] = {
552 /* DMARSx */
553 .start = 0xff709000,
554 .end = 0xff70900b,
555 .flags = IORESOURCE_MEM,
556 },
557 {
558 /* DMA error */
559 .start = 323,
560 .end = 323,
561 .flags = IORESOURCE_IRQ,
562 },
563 {
564 /* IRQ for channels 12 to 16 */
565 .start = 272,
566 .end = 276,
567 .flags = IORESOURCE_IRQ,
568 },
569 {
570 /* IRQ for channel 17 */
571 .start = 279,
572 .end = 279,
573 .flags = IORESOURCE_IRQ,
574 },
575};
576
577/* channel 18 to 23 */
578static struct resource sh7757_dmae3_resources[] = {
579 [0] = {
580 /* Channel registers and DMAOR */
581 .start = 0xff718020,
582 .end = 0xff71808f,
583 .flags = IORESOURCE_MEM,
584 },
585 [1] = {
586 /* DMARSx */
587 .start = 0xff719000,
588 .end = 0xff71900b,
589 .flags = IORESOURCE_MEM,
590 },
591 {
592 /* DMA error */
593 .start = 324,
594 .end = 324,
595 .flags = IORESOURCE_IRQ,
596 },
597 {
598 /* IRQ for channels 18 to 22 */
599 .start = 280,
600 .end = 284,
601 .flags = IORESOURCE_IRQ,
602 },
603 {
604 /* IRQ for channel 23 */
605 .start = 288,
606 .end = 288,
607 .flags = IORESOURCE_IRQ,
608 },
609};
610
611static struct platform_device dma0_device = {
612 .name = "sh-dma-engine",
613 .id = 0,
614 .resource = sh7757_dmae0_resources,
615 .num_resources = ARRAY_SIZE(sh7757_dmae0_resources),
616 .dev = {
617 .platform_data = &dma0_platform_data,
618 },
619};
620
621static struct platform_device dma1_device = {
622 .name = "sh-dma-engine",
623 .id = 1,
624 .resource = sh7757_dmae1_resources,
625 .num_resources = ARRAY_SIZE(sh7757_dmae1_resources),
626 .dev = {
627 .platform_data = &dma1_platform_data,
628 },
629};
630
631static struct platform_device dma2_device = {
632 .name = "sh-dma-engine",
633 .id = 2,
634 .resource = sh7757_dmae2_resources,
635 .num_resources = ARRAY_SIZE(sh7757_dmae2_resources),
636 .dev = {
637 .platform_data = &dma2_platform_data,
638 },
639};
640
641static struct platform_device dma3_device = {
642 .name = "sh-dma-engine",
643 .id = 3,
644 .resource = sh7757_dmae3_resources,
645 .num_resources = ARRAY_SIZE(sh7757_dmae3_resources),
646 .dev = {
647 .platform_data = &dma3_platform_data,
648 },
649};
650
139static struct platform_device spi0_device = { 651static struct platform_device spi0_device = {
140 .name = "sh_spi", 652 .name = "sh_spi",
141 .id = 0, 653 .id = 0,
@@ -153,6 +665,10 @@ static struct platform_device *sh7757_devices[] __initdata = {
153 &scif4_device, 665 &scif4_device,
154 &tmu0_device, 666 &tmu0_device,
155 &tmu1_device, 667 &tmu1_device,
668 &dma0_device,
669 &dma1_device,
670 &dma2_device,
671 &dma3_device,
156 &spi0_device, 672 &spi0_device,
157}; 673};
158 674
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-16 01:22:21 -0500