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authorPaul Mundt <lethal@linux-sh.org>2009-10-10 09:45:41 -0400
committerPaul Mundt <lethal@linux-sh.org>2009-10-10 09:45:41 -0400
commit3d4e0cfb3372ee7754f743ab90944540cef4ecc6 (patch)
tree1edc7676f41fd66f3a1a3db3a1f77e51bbf8931f /arch/sh/kernel/cpu/sh4a
parent2a8bc923455f320da6c460258c21d2235ab2edc8 (diff)
sh: Reinstate ILSEL -> IRL intc mappings for SH-X3 proto CPU.
In the multi-evt conversion for the SH-X3 proto CPU, IRLs were dropped down to a single unique masking source, which ended up blowing up on ILSEL-based IRQs which have special semantics that otherwise confuse the intc code. While this does result in intc spewing about not having a unique masking source, we don't really care. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/cpu/sh4a')
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-shx3.c28
1 files changed, 18 insertions, 10 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
index e848443deeb9..485330cf8549 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
@@ -268,7 +268,11 @@ enum {
268 UNUSED = 0, 268 UNUSED = 0,
269 269
270 /* interrupt sources */ 270 /* interrupt sources */
271 IRL, IRQ0, IRQ1, IRQ2, IRQ3, 271 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
272 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
273 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
274 IRL_HHLL, IRL_HHLH, IRL_HHHL,
275 IRQ0, IRQ1, IRQ2, IRQ3,
272 HUDII, 276 HUDII,
273 TMU0, TMU1, TMU2, TMU3, TMU4, TMU5, 277 TMU0, TMU1, TMU2, TMU3, TMU4, TMU5,
274 PCII0, PCII1, PCII2, PCII3, PCII4, 278 PCII0, PCII1, PCII2, PCII3, PCII4,
@@ -291,7 +295,7 @@ enum {
291 INTICI4, INTICI5, INTICI6, INTICI7, 295 INTICI4, INTICI5, INTICI6, INTICI7,
292 296
293 /* interrupt groups */ 297 /* interrupt groups */
294 PCII56789, SCIF0, SCIF1, SCIF2, SCIF3, 298 IRL, PCII56789, SCIF0, SCIF1, SCIF2, SCIF3,
295 DMAC0, DMAC1, 299 DMAC0, DMAC1,
296}; 300};
297 301
@@ -344,6 +348,10 @@ static struct intc_vect vectors[] __initdata = {
344}; 348};
345 349
346static struct intc_group groups[] __initdata = { 350static struct intc_group groups[] __initdata = {
351 INTC_GROUP(IRL, IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
352 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
353 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
354 IRL_HHLL, IRL_HHLH, IRL_HHHL),
347 INTC_GROUP(PCII56789, PCII5, PCII6, PCII7, PCII8, PCII9), 355 INTC_GROUP(PCII56789, PCII5, PCII6, PCII7, PCII8, PCII9),
348 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI), 356 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
349 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI), 357 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
@@ -419,14 +427,14 @@ static DECLARE_INTC_DESC(intc_desc_irq, "shx3-irq", vectors_irq, groups,
419 427
420/* External interrupt pins in IRL mode */ 428/* External interrupt pins in IRL mode */
421static struct intc_vect vectors_irl[] __initdata = { 429static struct intc_vect vectors_irl[] __initdata = {
422 INTC_VECT(IRL, 0x200), INTC_VECT(IRL, 0x220), 430 INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
423 INTC_VECT(IRL, 0x240), INTC_VECT(IRL, 0x260), 431 INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
424 INTC_VECT(IRL, 0x280), INTC_VECT(IRL, 0x2a0), 432 INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
425 INTC_VECT(IRL, 0x2c0), INTC_VECT(IRL, 0x2e0), 433 INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
426 INTC_VECT(IRL, 0x300), INTC_VECT(IRL, 0x320), 434 INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
427 INTC_VECT(IRL, 0x340), INTC_VECT(IRL, 0x360), 435 INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
428 INTC_VECT(IRL, 0x380), INTC_VECT(IRL, 0x3a0), 436 INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
429 INTC_VECT(IRL, 0x3c0), 437 INTC_VECT(IRL_HHHL, 0x3c0),
430}; 438};
431 439
432static DECLARE_INTC_DESC(intc_desc_irl, "shx3-irl", vectors_irl, groups, 440static DECLARE_INTC_DESC(intc_desc_irl, "shx3-irl", vectors_irl, groups,