Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/torvalds/linux-2.6 into common/serial-rework

Conflicts:
	arch/sh/kernel/cpu/sh2/setup-sh7619.c
	arch/sh/kernel/cpu/sh2a/setup-mxg.c
	arch/sh/kernel/cpu/sh2a/setup-sh7201.c
	arch/sh/kernel/cpu/sh2a/setup-sh7203.c
	arch/sh/kernel/cpu/sh2a/setup-sh7206.c
	arch/sh/kernel/cpu/sh3/setup-sh7705.c
	arch/sh/kernel/cpu/sh3/setup-sh770x.c
	arch/sh/kernel/cpu/sh3/setup-sh7710.c
	arch/sh/kernel/cpu/sh3/setup-sh7720.c
	arch/sh/kernel/cpu/sh4/setup-sh4-202.c
	arch/sh/kernel/cpu/sh4/setup-sh7750.c
	arch/sh/kernel/cpu/sh4/setup-sh7760.c
	arch/sh/kernel/cpu/sh4a/setup-sh7343.c
	arch/sh/kernel/cpu/sh4a/setup-sh7366.c
	arch/sh/kernel/cpu/sh4a/setup-sh7722.c
	arch/sh/kernel/cpu/sh4a/setup-sh7723.c
	arch/sh/kernel/cpu/sh4a/setup-sh7724.c
	arch/sh/kernel/cpu/sh4a/setup-sh7763.c
	arch/sh/kernel/cpu/sh4a/setup-sh7770.c
	arch/sh/kernel/cpu/sh4a/setup-sh7780.c
	arch/sh/kernel/cpu/sh4a/setup-sh7785.c
	arch/sh/kernel/cpu/sh4a/setup-sh7786.c
	arch/sh/kernel/cpu/sh4a/setup-shx3.c
	arch/sh/kernel/cpu/sh5/setup-sh5.c
	drivers/serial/sh-sci.c
	drivers/serial/sh-sci.h
	include/linux/serial_sci.h

1 files changed, 106 insertions, 90 deletions

diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
index 4a26cc304139..bb208806dc1a 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
@@ -1,7 +1,7 @@
 /*
  * SH-X3 Prototype Setup
  *
- *  Copyright (C) 2007 - 2009  Paul Mundt
+ *  Copyright (C) 2007 - 2010  Paul Mundt
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -12,62 +12,79 @@
 #include <linux/serial.h>
 #include <linux/serial_sci.h>
 #include <linux/io.h>
+#include <linux/gpio.h>
 #include <linux/sh_timer.h>
+#include <cpu/shx3.h>
 #include <asm/mmzone.h>
 
-static struct plat_sci_port sci_platform_data[] = {
-        {
-                .mapbase        = 0xffc30000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 40, 41, 43, 42 },
-        }, {
-                .mapbase        = 0xffc40000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 44, 45, 47, 46 },
-        }, {
-                .mapbase        = 0xffc50000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 48, 49, 51, 50 },
-        }, {
-                .mapbase        = 0xffc60000,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
-                .scbrr_algo_id  = SCBRR_ALGO_2,
-                .type           = PORT_SCIF,
-                .irqs           = { 52, 53, 55, 54 },
-        }, {
-                .flags = 0,
-        }
+/*
+ * This intentionally only registers SCIF ports 0, 1, and 3. SCIF 2
+ * INTEVT values overlap with the FPU EXPEVT ones, requiring special
+ * demuxing in the exception dispatch path.
+ *
+ * As this overlap is something that never should have made it in to
+ * silicon in the first place, we just refuse to deal with the port at
+ * all rather than adding infrastructure to hack around it.
+ */
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xffc30000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 40, 41, 43, 42 },
+};
+
+static struct platform_device scif0_device = {
+        .name           = "sh-sci",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xffc40000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 44, 45, 47, 46 },
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &scif1_platform_data,
+        },
+};
+
+static struct plat_sci_port scif2_platform_data = {
+        .mapbase        = 0xffc60000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           = { 52, 53, 55, 54 },
 };
 
-static struct platform_device sci_device = {
+static struct platform_device scif2_device = {
         .name           = "sh-sci",
-        .id             = -1,
+        .id             = 2,
         .dev            = {
-                .platform_data  = sci_platform_data,
+                .platform_data  = &scif2_platform_data,
         },
 };
 
 static struct sh_timer_config tmu0_platform_data = {
-        .name = "TMU0",
         .channel_offset = 0x04,
         .timer_bit = 0,
-        .clk = "peripheral_clk",
         .clockevent_rating = 200,
 };
 
 static struct resource tmu0_resources[] = {
         [0] = {
-                .name   = "TMU0",
                 .start  = 0xffc10008,
                 .end    = 0xffc10013,
                 .flags  = IORESOURCE_MEM,
@@ -89,16 +106,13 @@ static struct platform_device tmu0_device = {
 };
 
 static struct sh_timer_config tmu1_platform_data = {
-        .name = "TMU1",
         .channel_offset = 0x10,
         .timer_bit = 1,
-        .clk = "peripheral_clk",
         .clocksource_rating = 200,
 };
 
 static struct resource tmu1_resources[] = {
         [0] = {
-                .name   = "TMU1",
                 .start  = 0xffc10014,
                 .end    = 0xffc1001f,
                 .flags  = IORESOURCE_MEM,
@@ -120,15 +134,12 @@ static struct platform_device tmu1_device = {
 };
 
 static struct sh_timer_config tmu2_platform_data = {
-        .name = "TMU2",
         .channel_offset = 0x1c,
         .timer_bit = 2,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu2_resources[] = {
         [0] = {
-                .name   = "TMU2",
                 .start  = 0xffc10020,
                 .end    = 0xffc1002f,
                 .flags  = IORESOURCE_MEM,
@@ -150,15 +161,12 @@ static struct platform_device tmu2_device = {
 };
 
 static struct sh_timer_config tmu3_platform_data = {
-        .name = "TMU3",
         .channel_offset = 0x04,
         .timer_bit = 0,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu3_resources[] = {
         [0] = {
-                .name   = "TMU3",
                 .start  = 0xffc20008,
                 .end    = 0xffc20013,
                 .flags  = IORESOURCE_MEM,
@@ -180,15 +188,12 @@ static struct platform_device tmu3_device = {
 };
 
 static struct sh_timer_config tmu4_platform_data = {
-        .name = "TMU4",
         .channel_offset = 0x10,
         .timer_bit = 1,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu4_resources[] = {
         [0] = {
-                .name   = "TMU4",
                 .start  = 0xffc20014,
                 .end    = 0xffc2001f,
                 .flags  = IORESOURCE_MEM,
@@ -210,15 +215,12 @@ static struct platform_device tmu4_device = {
 };
 
 static struct sh_timer_config tmu5_platform_data = {
-        .name = "TMU5",
         .channel_offset = 0x1c,
         .timer_bit = 2,
-        .clk = "peripheral_clk",
 };
 
 static struct resource tmu5_resources[] = {
         [0] = {
-                .name   = "TMU5",
                 .start  = 0xffc20020,
                 .end    = 0xffc2002b,
                 .flags  = IORESOURCE_MEM,
@@ -240,6 +242,9 @@ static struct platform_device tmu5_device = {
 };
 
 static struct platform_device *shx3_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
@@ -248,23 +253,12 @@ static struct platform_device *shx3_early_devices[] __initdata = {
         &tmu5_device,
 };
 
-static struct platform_device *shx3_devices[] __initdata = {
-        &sci_device,
-};
-
 static int __init shx3_devices_setup(void)
 {
-        int ret;
-
-        ret = platform_add_devices(shx3_early_devices,
+        return platform_add_devices(shx3_early_devices,
                                    ARRAY_SIZE(shx3_early_devices));
-        if (unlikely(ret != 0))
-                return ret;
-
-        return platform_add_devices(shx3_devices,
-                                    ARRAY_SIZE(shx3_devices));
 }
-__initcall(shx3_devices_setup);
+arch_initcall(shx3_devices_setup);
 
 void __init plat_early_device_setup(void)
 {
@@ -295,10 +289,7 @@ enum {
         DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8, DMAC1_DMINT9,
         DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE,
         IIC, VIN0, VIN1, VCORE0, ATAPI,
-        DTU0_TEND, DTU0_AE, DTU0_TMISS,
-        DTU1_TEND, DTU1_AE, DTU1_TMISS,
-        DTU2_TEND, DTU2_AE, DTU2_TMISS,
-        DTU3_TEND, DTU3_AE, DTU3_TMISS,
+        DTU0, DTU1, DTU2, DTU3,
         FE0, FE1,
         GPIO0, GPIO1, GPIO2, GPIO3,
         PAM, IRM,
@@ -307,7 +298,7 @@ enum {
 
         /* interrupt groups */
         IRL, PCII56789, SCIF0, SCIF1, SCIF2, SCIF3,
-        DMAC0, DMAC1, DTU0, DTU1, DTU2, DTU3,
+        DMAC0, DMAC1,
 };
 
 static struct intc_vect vectors[] __initdata = {
@@ -324,8 +315,6 @@ static struct intc_vect vectors[] __initdata = {
         INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760),
         INTC_VECT(SCIF1_ERI, 0x780), INTC_VECT(SCIF1_RXI, 0x7a0),
         INTC_VECT(SCIF1_BRI, 0x7c0), INTC_VECT(SCIF1_TXI, 0x7e0),
-        INTC_VECT(SCIF2_ERI, 0x800), INTC_VECT(SCIF2_RXI, 0x820),
-        INTC_VECT(SCIF2_BRI, 0x840), INTC_VECT(SCIF2_TXI, 0x860),
         INTC_VECT(SCIF3_ERI, 0x880), INTC_VECT(SCIF3_RXI, 0x8a0),
         INTC_VECT(SCIF3_BRI, 0x8c0), INTC_VECT(SCIF3_TXI, 0x8e0),
         INTC_VECT(DMAC0_DMINT0, 0x900), INTC_VECT(DMAC0_DMINT1, 0x920),
@@ -340,14 +329,14 @@ static struct intc_vect vectors[] __initdata = {
         INTC_VECT(IIC, 0xae0),
         INTC_VECT(VIN0, 0xb00), INTC_VECT(VIN1, 0xb20),
         INTC_VECT(VCORE0, 0xb00), INTC_VECT(ATAPI, 0xb60),
-        INTC_VECT(DTU0_TEND, 0xc00), INTC_VECT(DTU0_AE, 0xc20),
-        INTC_VECT(DTU0_TMISS, 0xc40),
-        INTC_VECT(DTU1_TEND, 0xc60), INTC_VECT(DTU1_AE, 0xc80),
-        INTC_VECT(DTU1_TMISS, 0xca0),
-        INTC_VECT(DTU2_TEND, 0xcc0), INTC_VECT(DTU2_AE, 0xce0),
-        INTC_VECT(DTU2_TMISS, 0xd00),
-        INTC_VECT(DTU3_TEND, 0xd20), INTC_VECT(DTU3_AE, 0xd40),
-        INTC_VECT(DTU3_TMISS, 0xd60),
+        INTC_VECT(DTU0, 0xc00), INTC_VECT(DTU0, 0xc20),
+        INTC_VECT(DTU0, 0xc40),
+        INTC_VECT(DTU1, 0xc60), INTC_VECT(DTU1, 0xc80),
+        INTC_VECT(DTU1, 0xca0),
+        INTC_VECT(DTU2, 0xcc0), INTC_VECT(DTU2, 0xce0),
+        INTC_VECT(DTU2, 0xd00),
+        INTC_VECT(DTU3, 0xd20), INTC_VECT(DTU3, 0xd40),
+        INTC_VECT(DTU3, 0xd60),
         INTC_VECT(FE0, 0xe00), INTC_VECT(FE1, 0xe20),
         INTC_VECT(GPIO0, 0xe40), INTC_VECT(GPIO1, 0xe60),
         INTC_VECT(GPIO2, 0xe80), INTC_VECT(GPIO3, 0xea0),
@@ -366,18 +355,17 @@ static struct intc_group groups[] __initdata = {
         INTC_GROUP(PCII56789, PCII5, PCII6, PCII7, PCII8, PCII9),
         INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
         INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
-        INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
         INTC_GROUP(SCIF3, SCIF3_ERI, SCIF3_RXI, SCIF3_BRI, SCIF3_TXI),
         INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
                    DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
         INTC_GROUP(DMAC1, DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8,
                    DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11),
-        INTC_GROUP(DTU0, DTU0_TEND, DTU0_AE, DTU0_TMISS),
-        INTC_GROUP(DTU1, DTU1_TEND, DTU1_AE, DTU1_TMISS),
-        INTC_GROUP(DTU2, DTU2_TEND, DTU2_AE, DTU2_TMISS),
-        INTC_GROUP(DTU3, DTU3_TEND, DTU3_AE, DTU3_TMISS),
 };
 
+#define INT2DISTCR0     0xfe4108a0
+#define INT2DISTCR1     0xfe4108a4
+#define INT2DISTCR2     0xfe4108a8
+
 static struct intc_mask_reg mask_registers[] __initdata = {
         { 0xfe410030, 0xfe410050, 32, /* CnINTMSK0 / CnINTMSKCLR0 */
           { IRQ0, IRQ1, IRQ2, IRQ3 } },
@@ -387,20 +375,23 @@ static struct intc_mask_reg mask_registers[] __initdata = {
           { FE1, FE0, 0, ATAPI, VCORE0, VIN1, VIN0, IIC,
             DU, GPIO3, GPIO2, GPIO1, GPIO0, PAM, 0, 0,
             0, 0, 0, 0, 0, 0, 0, 0, /* HUDI bits ignored */
-            0, TMU5, TMU4, TMU3, TMU2, TMU1, TMU0, 0, } },
+            0, TMU5, TMU4, TMU3, TMU2, TMU1, TMU0, 0, },
+            INTC_SMP_BALANCING(INT2DISTCR0) },
         { 0xfe410830, 0xfe410860, 32, /* CnINT2MSK1 / CnINT2MSKCLR1 */
           { 0, 0, 0, 0, DTU3, DTU2, DTU1, DTU0, /* IRM bits ignored */
             PCII9, PCII8, PCII7, PCII6, PCII5, PCII4, PCII3, PCII2,
             PCII1, PCII0, DMAC1_DMAE, DMAC1_DMINT11,
             DMAC1_DMINT10, DMAC1_DMINT9, DMAC1_DMINT8, DMAC1_DMINT7,
             DMAC1_DMINT6, DMAC0_DMAE, DMAC0_DMINT5, DMAC0_DMINT4,
-            DMAC0_DMINT3, DMAC0_DMINT2, DMAC0_DMINT1, DMAC0_DMINT0 } },
+            DMAC0_DMINT3, DMAC0_DMINT2, DMAC0_DMINT1, DMAC0_DMINT0 },
+            INTC_SMP_BALANCING(INT2DISTCR1) },
         { 0xfe410840, 0xfe410870, 32, /* CnINT2MSK2 / CnINT2MSKCLR2 */
           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
             SCIF3_TXI, SCIF3_BRI, SCIF3_RXI, SCIF3_ERI,
             SCIF2_TXI, SCIF2_BRI, SCIF2_RXI, SCIF2_ERI,
             SCIF1_TXI, SCIF1_BRI, SCIF1_RXI, SCIF1_ERI,
-            SCIF0_TXI, SCIF0_BRI, SCIF0_RXI, SCIF0_ERI } },
+            SCIF0_TXI, SCIF0_BRI, SCIF0_RXI, SCIF0_ERI },
+            INTC_SMP_BALANCING(INT2DISTCR2) },
 };
 
 static struct intc_prio_reg prio_registers[] __initdata = {
@@ -457,11 +448,33 @@ static DECLARE_INTC_DESC(intc_desc_irl, "shx3-irl", vectors_irl, groups,
 
 void __init plat_irq_setup_pins(int mode)
 {
+        int ret = 0;
+
         switch (mode) {
         case IRQ_MODE_IRQ:
+                ret |= gpio_request(GPIO_FN_IRQ3, intc_desc_irq.name);
+                ret |= gpio_request(GPIO_FN_IRQ2, intc_desc_irq.name);
+                ret |= gpio_request(GPIO_FN_IRQ1, intc_desc_irq.name);
+                ret |= gpio_request(GPIO_FN_IRQ0, intc_desc_irq.name);
+
+                if (unlikely(ret)) {
+                        pr_err("Failed to set IRQ mode\n");
+                        return;
+                }
+
                 register_intc_controller(&intc_desc_irq);
                 break;
         case IRQ_MODE_IRL3210:
+                ret |= gpio_request(GPIO_FN_IRL3, intc_desc_irl.name);
+                ret |= gpio_request(GPIO_FN_IRL2, intc_desc_irl.name);
+                ret |= gpio_request(GPIO_FN_IRL1, intc_desc_irl.name);
+                ret |= gpio_request(GPIO_FN_IRL0, intc_desc_irl.name);
+
+                if (unlikely(ret)) {
+                        pr_err("Failed to set IRL mode\n");
+                        return;
+                }
+
                 register_intc_controller(&intc_desc_irl);
                 break;
         default:
@@ -471,6 +484,9 @@ void __init plat_irq_setup_pins(int mode)
 
 void __init plat_irq_setup(void)
 {
+        reserve_intc_vectors(vectors_irq, ARRAY_SIZE(vectors_irq));
+        reserve_intc_vectors(vectors_irl, ARRAY_SIZE(vectors_irl));
+
         register_intc_controller(&intc_desc);
 }