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authorMagnus Damm <damm@igel.co.jp>2009-05-28 09:13:56 -0400
committerPaul Mundt <lethal@linux-sh.org>2009-06-01 05:07:50 -0400
commit43909a938063f9b6f98c05a2e28b072dd972ece7 (patch)
tree74ce513c49b2467e30b36c8fd730a3d05503bbe3 /arch/sh/kernel/cpu/sh4a/clock-sh7785.c
parenta1153e27eec25e9963f5843ba8932952bd9847ac (diff)
sh: hook up shared div4 clock code to sh7785
Hook up the shared 4-bit divisor clock code to sh7785. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/cpu/sh4a/clock-sh7785.c')
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7785.c207
1 files changed, 48 insertions, 159 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
index 7d557068f4a3..dae20aca536d 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
@@ -18,65 +18,14 @@
18#include <asm/freq.h> 18#include <asm/freq.h>
19#include <cpu/sh7785.h> 19#include <cpu/sh7785.h>
20 20
21static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18, 21/*
22 24, 32, 36, 48 }; 22 * Default rate for the root input clock, reset this with clk_set_rate()
23 23 * from the platform code.
24static struct clk_div_mult_table cpg_div = { 24 */
25 .divisors = div2, 25static struct clk extal_clk = {
26 .nr_divisors = ARRAY_SIZE(div2), 26 .name = "extal",
27}; 27 .id = -1,
28 28 .rate = 33333333,
29struct clk_priv {
30 unsigned int shift;
31
32 /* allowable divisor bitmap */
33 unsigned long div_bitmap;
34
35 /* Supportable frequencies + termination entry */
36 struct cpufreq_frequency_table freq_table[ARRAY_SIZE(div2)+1];
37};
38
39#define FRQMR_CLK_DATA(_name, _shift, _div_bitmap) \
40static struct clk_priv _name##_data = { \
41 .shift = _shift, \
42 .div_bitmap = _div_bitmap, \
43 \
44 .freq_table[0] = { \
45 .index = 0, \
46 .frequency = CPUFREQ_TABLE_END, \
47 }, \
48}
49
50FRQMR_CLK_DATA(pfc, 0, 0x0f80);
51FRQMR_CLK_DATA(s3fc, 4, 0x0ff0);
52FRQMR_CLK_DATA(s2fc, 8, 0x0030);
53FRQMR_CLK_DATA(mfc, 12, 0x000c);
54FRQMR_CLK_DATA(bfc, 16, 0x0fe0);
55FRQMR_CLK_DATA(sfc, 20, 0x000c);
56FRQMR_CLK_DATA(ufc, 24, 0x000c);
57FRQMR_CLK_DATA(ifc, 28, 0x000e);
58
59static unsigned long frqmr_recalc(struct clk *clk)
60{
61 struct clk_priv *data = clk->priv;
62 unsigned int idx = (__raw_readl(FRQMR1) >> data->shift) & 0x000f;
63
64 clk_rate_table_build(clk, data->freq_table, ARRAY_SIZE(div2),
65 &cpg_div, &data->div_bitmap);
66
67 return data->freq_table[idx].frequency;
68}
69
70static long frqmr_round_rate(struct clk *clk, unsigned long rate)
71{
72 struct clk_priv *data = clk->priv;
73
74 return clk_rate_table_round(clk, data->freq_table, rate);
75}
76
77static struct clk_ops frqmr_clk_ops = {
78 .recalc = frqmr_recalc,
79 .round_rate = frqmr_round_rate,
80}; 29};
81 30
82static unsigned long pll_recalc(struct clk *clk) 31static unsigned long pll_recalc(struct clk *clk)
@@ -92,16 +41,6 @@ static struct clk_ops pll_clk_ops = {
92 .recalc = pll_recalc, 41 .recalc = pll_recalc,
93}; 42};
94 43
95/*
96 * Default rate for the root input clock, reset this with clk_set_rate()
97 * from the platform code.
98 */
99static struct clk extal_clk = {
100 .name = "extal",
101 .id = -1,
102 .rate = 33333333,
103};
104
105static struct clk pll_clk = { 44static struct clk pll_clk = {
106 .name = "pll_clk", 45 .name = "pll_clk",
107 .id = -1, 46 .id = -1,
@@ -110,87 +49,34 @@ static struct clk pll_clk = {
110 .flags = CLK_ENABLE_ON_INIT, 49 .flags = CLK_ENABLE_ON_INIT,
111}; 50};
112 51
113static struct clk cpu_clk = { 52static struct clk *clks[] = {
114 .name = "cpu_clk", /* Ick */ 53 &extal_clk,
115 .id = -1, 54 &pll_clk,
116 .ops = &frqmr_clk_ops,
117 .parent = &pll_clk,
118 .flags = CLK_ENABLE_ON_INIT,
119 .priv = &ifc_data,
120};
121
122static struct clk shyway_clk = {
123 .name = "shyway_clk", /* SHck */
124 .id = -1,
125 .ops = &frqmr_clk_ops,
126 .parent = &pll_clk,
127 .flags = CLK_ENABLE_ON_INIT,
128 .priv = &sfc_data,
129};
130
131static struct clk peripheral_clk = {
132 .name = "peripheral_clk", /* Pck */
133 .id = -1,
134 .ops = &frqmr_clk_ops,
135 .parent = &pll_clk,
136 .flags = CLK_ENABLE_ON_INIT,
137 .priv = &pfc_data,
138};
139
140static struct clk ddr_clk = {
141 .name = "ddr_clk", /* DDRck */
142 .id = -1,
143 .ops = &frqmr_clk_ops,
144 .parent = &pll_clk,
145 .flags = CLK_ENABLE_ON_INIT,
146 .priv = &mfc_data,
147}; 55};
148 56
149static struct clk bus_clk = { 57static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,
150 .name = "bus_clk", /* Bck */ 58 24, 32, 36, 48 };
151 .id = -1,
152 .ops = &frqmr_clk_ops,
153 .parent = &pll_clk,
154 .flags = CLK_ENABLE_ON_INIT,
155 .priv = &bfc_data,
156};
157 59
158static struct clk ga_clk = { 60static struct clk_div_mult_table div4_table = {
159 .name = "ga_clk", /* GAck */ 61 .divisors = div2,
160 .id = -1, 62 .nr_divisors = ARRAY_SIZE(div2),
161 .ops = &frqmr_clk_ops,
162 .parent = &pll_clk,
163 .priv = &s2fc_data,
164}; 63};
165 64
166static struct clk du_clk = { 65enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_GA,
167 .name = "du_clk", /* DUck */ 66 DIV4_DU, DIV4_P, DIV4_NR };
168 .id = -1,
169 .ops = &frqmr_clk_ops,
170 .parent = &pll_clk,
171 .priv = &s3fc_data,
172};
173 67
174static struct clk umem_clk = { 68#define DIV4(_str, _bit, _mask, _flags) \
175 .name = "umem_clk", /* uck */ 69 SH_CLK_DIV4(_str, &pll_clk, FRQMR1, _bit, _mask, _flags)
176 .id = -1,
177 .ops = &frqmr_clk_ops,
178 .parent = &pll_clk,
179 .flags = CLK_ENABLE_ON_INIT,
180 .priv = &ufc_data,
181};
182 70
183static struct clk *clks[] = { 71struct clk div4_clks[DIV4_NR] = {
184 &extal_clk, 72 [DIV4_P] = DIV4("peripheral_clk", 0, 0x0f80, 0),
185 &pll_clk, 73 [DIV4_DU] = DIV4("du_clk", 4, 0x0ff0, 0),
186 &cpu_clk, 74 [DIV4_GA] = DIV4("ga_clk", 8, 0x0030, 0),
187 &shyway_clk, 75 [DIV4_DDR] = DIV4("ddr_clk", 12, 0x000c, CLK_ENABLE_ON_INIT),
188 &peripheral_clk, 76 [DIV4_B] = DIV4("bus_clk", 16, 0x0fe0, CLK_ENABLE_ON_INIT),
189 &ddr_clk, 77 [DIV4_SH] = DIV4("shyway_clk", 20, 0x000c, CLK_ENABLE_ON_INIT),
190 &bus_clk, 78 [DIV4_U] = DIV4("umem_clk", 24, 0x000c, CLK_ENABLE_ON_INIT),
191 &ga_clk, 79 [DIV4_I] = DIV4("cpu_clk", 28, 0x000e, CLK_ENABLE_ON_INIT),
192 &du_clk,
193 &umem_clk,
194}; 80};
195 81
196#define MSTPCR0 0xffc80030 82#define MSTPCR0 0xffc80030
@@ -198,22 +84,22 @@ static struct clk *clks[] = {
198 84
199static struct clk mstp_clks[] = { 85static struct clk mstp_clks[] = {
200 /* MSTPCR0 */ 86 /* MSTPCR0 */
201 SH_CLK_MSTP32("scif_fck", 5, &peripheral_clk, MSTPCR0, 29, 0), 87 SH_CLK_MSTP32("scif_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0),
202 SH_CLK_MSTP32("scif_fck", 4, &peripheral_clk, MSTPCR0, 28, 0), 88 SH_CLK_MSTP32("scif_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0),
203 SH_CLK_MSTP32("scif_fck", 3, &peripheral_clk, MSTPCR0, 27, 0), 89 SH_CLK_MSTP32("scif_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0),
204 SH_CLK_MSTP32("scif_fck", 2, &peripheral_clk, MSTPCR0, 26, 0), 90 SH_CLK_MSTP32("scif_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0),
205 SH_CLK_MSTP32("scif_fck", 1, &peripheral_clk, MSTPCR0, 25, 0), 91 SH_CLK_MSTP32("scif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0),
206 SH_CLK_MSTP32("scif_fck", 0, &peripheral_clk, MSTPCR0, 24, 0), 92 SH_CLK_MSTP32("scif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0),
207 SH_CLK_MSTP32("ssi_fck", 1, &peripheral_clk, MSTPCR0, 21, 0), 93 SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0),
208 SH_CLK_MSTP32("ssi_fck", 0, &peripheral_clk, MSTPCR0, 20, 0), 94 SH_CLK_MSTP32("ssi_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 20, 0),
209 SH_CLK_MSTP32("hac_fck", 1, &peripheral_clk, MSTPCR0, 17, 0), 95 SH_CLK_MSTP32("hac_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 17, 0),
210 SH_CLK_MSTP32("hac_fck", 0, &peripheral_clk, MSTPCR0, 16, 0), 96 SH_CLK_MSTP32("hac_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 16, 0),
211 SH_CLK_MSTP32("mmcif_fck", -1, &peripheral_clk, MSTPCR0, 13, 0), 97 SH_CLK_MSTP32("mmcif_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 13, 0),
212 SH_CLK_MSTP32("flctl_fck", -1, &peripheral_clk, MSTPCR0, 12, 0), 98 SH_CLK_MSTP32("flctl_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 12, 0),
213 SH_CLK_MSTP32("tmu345_fck", -1, &peripheral_clk, MSTPCR0, 9, 0), 99 SH_CLK_MSTP32("tmu345_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 9, 0),
214 SH_CLK_MSTP32("tmu012_fck", -1, &peripheral_clk, MSTPCR0, 8, 0), 100 SH_CLK_MSTP32("tmu012_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 8, 0),
215 SH_CLK_MSTP32("siof_fck", -1, &peripheral_clk, MSTPCR0, 3, 0), 101 SH_CLK_MSTP32("siof_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 3, 0),
216 SH_CLK_MSTP32("hspi_fck", -1, &peripheral_clk, MSTPCR0, 2, 0), 102 SH_CLK_MSTP32("hspi_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 2, 0),
217 103
218 /* MSTPCR1 */ 104 /* MSTPCR1 */
219 SH_CLK_MSTP32("hudi_fck", -1, NULL, MSTPCR1, 19, 0), 105 SH_CLK_MSTP32("hudi_fck", -1, NULL, MSTPCR1, 19, 0),
@@ -231,6 +117,9 @@ int __init arch_clk_init(void)
231 ret |= clk_register(clks[i]); 117 ret |= clk_register(clks[i]);
232 118
233 if (!ret) 119 if (!ret)
120 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
121 &div4_table);
122 if (!ret)
234 ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); 123 ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
235 124
236 return ret; 125 return ret;
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-15 23:19:13 -0500