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authorMagnus Damm <magnus.damm@gmail.com>2008-04-24 08:36:34 -0400
committerPaul Mundt <lethal@linux-sh.org>2008-05-08 06:52:03 -0400
commitd58876e289b0153bf86162aa1a43249e0f0aa03d (patch)
treebcba99bfb89b61142a81a651958c10e4c9828778 /arch/sh/kernel/cpu/sh3/setup-sh3.c
parenta276e588a92737889c21e736f2bbed8aecda25fb (diff)
sh: add interrupt ack code to sh3
This patch adds interrupt acknowledge code for external interrupt sources on sh3 processors. Only really required for edge triggered interrupts, but we ack regardless of sense configuration. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/cpu/sh3/setup-sh3.c')
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh3.c15
1 files changed, 11 insertions, 4 deletions
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh3.c b/arch/sh/kernel/cpu/sh3/setup-sh3.c
index 28e7d6553091..c98846857855 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh3.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh3.c
@@ -35,15 +35,22 @@ static struct intc_prio_reg prio_registers[] __initdata = {
35 { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } }, 35 { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
36}; 36};
37 37
38static struct intc_mask_reg ack_registers[] __initdata = {
39 { 0xa4000004, 0, 8, /* IRR0 */
40 { 0, 0, IRQ5, IRQ4, IRQ3, IRQ2, IRQ1, IRQ0 } },
41};
42
38static struct intc_sense_reg sense_registers[] __initdata = { 43static struct intc_sense_reg sense_registers[] __initdata = {
39 { 0xa4000010, 16, 2, { 0, 0, IRQ5, IRQ4, IRQ3, IRQ2, IRQ1, IRQ0 } }, 44 { 0xa4000010, 16, 2, { 0, 0, IRQ5, IRQ4, IRQ3, IRQ2, IRQ1, IRQ0 } },
40}; 45};
41 46
42static DECLARE_INTC_DESC(intc_desc_irq0123, "sh3-irq0123", vectors_irq0123, 47static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh3-irq0123",
43 NULL, NULL, prio_registers, sense_registers); 48 vectors_irq0123, NULL, NULL,
49 prio_registers, sense_registers, ack_registers);
44 50
45static DECLARE_INTC_DESC(intc_desc_irq45, "sh3-irq45", vectors_irq45, 51static DECLARE_INTC_DESC_ACK(intc_desc_irq45, "sh3-irq45",
46 NULL, NULL, prio_registers, sense_registers); 52 vectors_irq45, NULL, NULL,
53 prio_registers, sense_registers, ack_registers);
47 54
48#define INTC_ICR1 0xa4000010UL 55#define INTC_ICR1 0xa4000010UL
49#define INTC_ICR1_IRQLVL (1<<14) 56#define INTC_ICR1_IRQLVL (1<<14)