Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6

* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (266 commits)
  sh: Tie sparseirq in to Kconfig.
  sh: Wire up sys_rt_tgsigqueueinfo.
  sh: Fix sys_pwritev() syscall table entry for sh32.
  sh: Fix sh4a llsc-based cmpxchg()
  sh: sh7724: Add JPU support
  sh: sh7724: INTC setting update
  sh: sh7722 clock framework rewrite
  sh: sh7366 clock framework rewrite
  sh: sh7343 clock framework rewrite
  sh: sh7724 clock framework rewrite V3
  sh: sh7723 clock framework rewrite V2
  sh: add enable()/disable()/set_rate() to div6 code
  sh: add AP325RXA mode pin configuration
  sh: add Migo-R mode pin configuration
  sh: sh7722 mode pin definitions
  sh: sh7724 mode pin comments
  sh: sh7723 mode pin V2
  sh: rework mode pin code
  sh: clock div6 helper code
  sh: clock div4 frequency table offset fix
  ...

38 files changed, 796 insertions, 362 deletions

diff --git a/arch/sh/include/asm/atomic-llsc.h b/arch/sh/include/asm/atomic-llsc.h
index 4b00b78e3f4f..b040e1e08610 100644
--- a/arch/sh/include/asm/atomic-llsc.h
+++ b/arch/sh/include/asm/atomic-llsc.h
@@ -104,4 +104,31 @@ static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
         : "t");
 }
 
+#define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
+
+/**
+ * atomic_add_unless - add unless the number is a given value
+ * @v: pointer of type atomic_t
+ * @a: the amount to add to v...
+ * @u: ...unless v is equal to u.
+ *
+ * Atomically adds @a to @v, so long as it was not @u.
+ * Returns non-zero if @v was not @u, and zero otherwise.
+ */
+static inline int atomic_add_unless(atomic_t *v, int a, int u)
+{
+        int c, old;
+        c = atomic_read(v);
+        for (;;) {
+                if (unlikely(c == (u)))
+                        break;
+                old = atomic_cmpxchg((v), c, c + (a));
+                if (likely(old == c))
+                        break;
+                c = old;
+        }
+
+        return c != (u);
+}
+
 #endif /* __ASM_SH_ATOMIC_LLSC_H */
diff --git a/arch/sh/include/asm/atomic.h b/arch/sh/include/asm/atomic.h
index 6327ffbb1992..978b58efb1e9 100644
--- a/arch/sh/include/asm/atomic.h
+++ b/arch/sh/include/asm/atomic.h
@@ -45,7 +45,7 @@
 #define atomic_inc(v) atomic_add(1,(v))
 #define atomic_dec(v) atomic_sub(1,(v))
 
-#ifndef CONFIG_GUSA_RB
+#if !defined(CONFIG_GUSA_RB) && !defined(CONFIG_CPU_SH4A)
 static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
 {
         int ret;
@@ -73,7 +73,7 @@ static inline int atomic_add_unless(atomic_t *v, int a, int u)
 
         return ret != u;
 }
-#endif
+#endif /* !CONFIG_GUSA_RB && !CONFIG_CPU_SH4A */
 
 #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
 #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
diff --git a/arch/sh/include/asm/cacheflush.h b/arch/sh/include/asm/cacheflush.h
index 09acbc32d6c7..4c5462daa74c 100644
--- a/arch/sh/include/asm/cacheflush.h
+++ b/arch/sh/include/asm/cacheflush.h
@@ -75,7 +75,5 @@ extern void copy_from_user_page(struct vm_area_struct *vma,
 #define flush_cache_vmap(start, end)            flush_cache_all()
 #define flush_cache_vunmap(start, end)          flush_cache_all()
 
-#define HAVE_ARCH_UNMAPPED_AREA
-
 #endif /* __KERNEL__ */
 #endif /* __ASM_SH_CACHEFLUSH_H */
diff --git a/arch/sh/include/asm/clock.h b/arch/sh/include/asm/clock.h
index 2f6c9627bc1f..9fe7d7f8af40 100644
--- a/arch/sh/include/asm/clock.h
+++ b/arch/sh/include/asm/clock.h
@@ -1,9 +1,9 @@
 #ifndef __ASM_SH_CLOCK_H
 #define __ASM_SH_CLOCK_H
 
-#include <linux/kref.h>
 #include <linux/list.h>
 #include <linux/seq_file.h>
+#include <linux/cpufreq.h>
 #include <linux/clk.h>
 #include <linux/err.h>
 
@@ -11,9 +11,9 @@ struct clk;
 
 struct clk_ops {
         void (*init)(struct clk *clk);
-        void (*enable)(struct clk *clk);
+        int (*enable)(struct clk *clk);
         void (*disable)(struct clk *clk);
-        void (*recalc)(struct clk *clk);
+        unsigned long (*recalc)(struct clk *clk);
         int (*set_rate)(struct clk *clk, unsigned long rate, int algo_id);
         int (*set_parent)(struct clk *clk, struct clk *parent);
         long (*round_rate)(struct clk *clk, unsigned long rate);
@@ -28,43 +28,47 @@ struct clk {
         struct clk              *parent;
         struct clk_ops          *ops;
 
-        struct kref             kref;
+        struct list_head        children;
+        struct list_head        sibling;        /* node for children */
+
+        int                     usecount;
 
         unsigned long           rate;
         unsigned long           flags;
+
+        void __iomem            *enable_reg;
+        unsigned int            enable_bit;
+
         unsigned long           arch_flags;
+        void                    *priv;
+        struct dentry           *dentry;
+        struct cpufreq_frequency_table *freq_table;
+};
+
+struct clk_lookup {
+        struct list_head        node;
+        const char              *dev_id;
+        const char              *con_id;
+        struct clk              *clk;
 };
 
-#define CLK_ALWAYS_ENABLED      (1 << 0)
-#define CLK_RATE_PROPAGATES     (1 << 1)
+#define CLK_ENABLE_ON_INIT      (1 << 0)
 
 /* Should be defined by processor-specific code */
-void arch_init_clk_ops(struct clk_ops **, int type);
+void __deprecated arch_init_clk_ops(struct clk_ops **, int type);
 int __init arch_clk_init(void);
 
 /* arch/sh/kernel/cpu/clock.c */
 int clk_init(void);
-
-void clk_recalc_rate(struct clk *);
-
+unsigned long followparent_recalc(struct clk *);
+void recalculate_root_clocks(void);
+void propagate_rate(struct clk *);
+int clk_reparent(struct clk *child, struct clk *parent);
 int clk_register(struct clk *);
 void clk_unregister(struct clk *);
 
-static inline int clk_always_enable(const char *id)
-{
-        struct clk *clk;
-        int ret;
-
-        clk = clk_get(NULL, id);
-        if (IS_ERR(clk))
-                return PTR_ERR(clk);
-
-        ret = clk_enable(clk);
-        if (ret)
-                clk_put(clk);
-
-        return ret;
-}
+/* arch/sh/kernel/cpu/clock-cpg.c */
+int __init __deprecated cpg_clk_init(void);
 
 /* the exported API, in addition to clk_set_rate */
 /**
@@ -96,4 +100,63 @@ enum clk_sh_algo_id {
 
         IP_N1,
 };
+
+struct clk_div_mult_table {
+        unsigned int *divisors;
+        unsigned int nr_divisors;
+        unsigned int *multipliers;
+        unsigned int nr_multipliers;
+};
+
+struct cpufreq_frequency_table;
+void clk_rate_table_build(struct clk *clk,
+                          struct cpufreq_frequency_table *freq_table,
+                          int nr_freqs,
+                          struct clk_div_mult_table *src_table,
+                          unsigned long *bitmap);
+
+long clk_rate_table_round(struct clk *clk,
+                          struct cpufreq_frequency_table *freq_table,
+                          unsigned long rate);
+
+int clk_rate_table_find(struct clk *clk,
+                        struct cpufreq_frequency_table *freq_table,
+                        unsigned long rate);
+
+#define SH_CLK_MSTP32(_name, _id, _parent, _enable_reg, \
+            _enable_bit, _flags)                        \
+{                                                       \
+        .name           = _name,                        \
+        .id             = _id,                          \
+        .parent         = _parent,                      \
+        .enable_reg     = (void __iomem *)_enable_reg,  \
+        .enable_bit     = _enable_bit,                  \
+        .flags          = _flags,                       \
+}
+
+int sh_clk_mstp32_register(struct clk *clks, int nr);
+
+#define SH_CLK_DIV4(_name, _parent, _reg, _shift, _div_bitmap, _flags)  \
+{                                                                       \
+        .name = _name,                                                  \
+        .parent = _parent,                                              \
+        .enable_reg = (void __iomem *)_reg,                             \
+        .enable_bit = _shift,                                           \
+        .arch_flags = _div_bitmap,                                      \
+        .flags = _flags,                                                \
+}
+
+int sh_clk_div4_register(struct clk *clks, int nr,
+                         struct clk_div_mult_table *table);
+
+#define SH_CLK_DIV6(_name, _parent, _reg, _flags)       \
+{                                                       \
+        .name = _name,                                  \
+        .parent = _parent,                              \
+        .enable_reg = (void __iomem *)_reg,             \
+        .flags = _flags,                                \
+}
+
+int sh_clk_div6_register(struct clk *clks, int nr);
+
 #endif /* __ASM_SH_CLOCK_H */
diff --git a/arch/sh/include/asm/cmpxchg-llsc.h b/arch/sh/include/asm/cmpxchg-llsc.h
index 0fac3da536ca..47136661a203 100644
--- a/arch/sh/include/asm/cmpxchg-llsc.h
+++ b/arch/sh/include/asm/cmpxchg-llsc.h
@@ -55,7 +55,7 @@ __cmpxchg_u32(volatile int *m, unsigned long old, unsigned long new)
                 "mov            %0, %1                          \n\t"
                 "cmp/eq         %1, %3                          \n\t"
                 "bf             2f                              \n\t"
-                "mov            %3, %0                          \n\t"
+                "mov            %4, %0                          \n\t"
                 "2:                                             \n\t"
                 "movco.l        %0, @%2                         \n\t"
                 "bf             1b                              \n\t"
diff --git a/arch/sh/include/asm/device.h b/arch/sh/include/asm/device.h
index efd511d0803a..8688a88303ee 100644
--- a/arch/sh/include/asm/device.h
+++ b/arch/sh/include/asm/device.h
@@ -10,3 +10,5 @@ struct platform_device;
 int platform_resource_setup_memory(struct platform_device *pdev,
                                    char *name, unsigned long memsize);
 
+void plat_early_device_setup(void);
+
diff --git a/arch/sh/include/asm/hd64461.h b/arch/sh/include/asm/hd64461.h
index 52b4b6238277..977355f0a483 100644
--- a/arch/sh/include/asm/hd64461.h
+++ b/arch/sh/include/asm/hd64461.h
@@ -13,18 +13,20 @@
 #define HD64461_PCC_WINDOW      0x01000000
 
 /* Area 6 - Slot 0 - memory and/or IO card */
-#define HD64461_PCC0_BASE       (CONFIG_HD64461_IOBASE + 0x8000000)
+#define HD64461_IOBASE          0xb0000000
+#define HD64461_IO_OFFSET(x)    (HD64461_IOBASE + (x))
+#define HD64461_PCC0_BASE       HD64461_IO_OFFSET(0x8000000)
 #define HD64461_PCC0_ATTR       (HD64461_PCC0_BASE)                             /* 0xb80000000 */
 #define HD64461_PCC0_COMM       (HD64461_PCC0_BASE+HD64461_PCC_WINDOW)          /* 0xb90000000 */
 #define HD64461_PCC0_IO         (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW)        /* 0xba0000000 */
 
 /* Area 5 - Slot 1 - memory card only */
-#define HD64461_PCC1_BASE       (CONFIG_HD64461_IOBASE + 0x4000000)
+#define HD64461_PCC1_BASE       HD64461_IO_OFFSET(0x4000000)
 #define HD64461_PCC1_ATTR       (HD64461_PCC1_BASE)                             /* 0xb4000000 */
 #define HD64461_PCC1_COMM       (HD64461_PCC1_BASE+HD64461_PCC_WINDOW)          /* 0xb5000000 */
 
 /* Standby Control Register for HD64461 */
-#define HD64461_STBCR                   CONFIG_HD64461_IOBASE
+#define HD64461_STBCR                   HD64461_IO_OFFSET(0x00000000)
 #define HD64461_STBCR_CKIO_STBY         0x2000
 #define HD64461_STBCR_SAFECKE_IST       0x1000
 #define HD64461_STBCR_SLCKE_IST         0x0800
@@ -41,19 +43,19 @@
 #define HD64461_STBCR_SURTST            0x0001
 
 /* System Configuration Register */
-#define HD64461_SYSCR           (CONFIG_HD64461_IOBASE + 0x02)
+#define HD64461_SYSCR           HD64461_IO_OFFSET(0x02)
 
 /* CPU Data Bus Control Register */
-#define HD64461_SCPUCR          (CONFIG_HD64461_IOBASE + 0x04)
+#define HD64461_SCPUCR          HD64461_IO_OFFSET(0x04)
 
 /* Base Address Register */
-#define HD64461_LCDCBAR         (CONFIG_HD64461_IOBASE + 0x1000)
+#define HD64461_LCDCBAR         HD64461_IO_OFFSET(0x1000)
 
 /* Line increment address */
-#define HD64461_LCDCLOR         (CONFIG_HD64461_IOBASE + 0x1002)
+#define HD64461_LCDCLOR         HD64461_IO_OFFSET(0x1002)
 
 /* Controls LCD controller */
-#define HD64461_LCDCCR          (CONFIG_HD64461_IOBASE + 0x1004)
+#define HD64461_LCDCCR          HD64461_IO_OFFSET(0x1004)
 
 /* LCCDR control bits */
 #define HD64461_LCDCCR_STBACK   0x0400  /* Standby Back */
@@ -64,30 +66,30 @@
 #define HD64461_LCDCCR_SPON     0x0010  /* Start Power On */
 
 /* Controls LCD (1) */
-#define HD64461_LDR1            (CONFIG_HD64461_IOBASE + 0x1010)
+#define HD64461_LDR1            HD64461_IO_OFFSET(0x1010)
 #define HD64461_LDR1_DON        0x01    /* Display On */
 #define HD64461_LDR1_DINV       0x80    /* Display Invert */
 
 /* Controls LCD (2) */
-#define HD64461_LDR2            (CONFIG_HD64461_IOBASE + 0x1012)
-#define HD64461_LDHNCR          (CONFIG_HD64461_IOBASE + 0x1014)        /* Number of horizontal characters */
-#define HD64461_LDHNSR          (CONFIG_HD64461_IOBASE + 0x1016)        /* Specify output start position + width of CL1 */
-#define HD64461_LDVNTR          (CONFIG_HD64461_IOBASE + 0x1018)        /* Specify total vertical lines */
-#define HD64461_LDVNDR          (CONFIG_HD64461_IOBASE + 0x101a)        /* specify number of display vertical lines */
-#define HD64461_LDVSPR          (CONFIG_HD64461_IOBASE + 0x101c)        /* specify vertical synchronization pos and AC nr */
+#define HD64461_LDR2            HD64461_IO_OFFSET(0x1012)
+#define HD64461_LDHNCR          HD64461_IO_OFFSET(0x1014)       /* Number of horizontal characters */
+#define HD64461_LDHNSR          HD64461_IO_OFFSET(0x1016)       /* Specify output start position + width of CL1 */
+#define HD64461_LDVNTR          HD64461_IO_OFFSET(0x1018)       /* Specify total vertical lines */
+#define HD64461_LDVNDR          HD64461_IO_OFFSET(0x101a)       /* specify number of display vertical lines */
+#define HD64461_LDVSPR          HD64461_IO_OFFSET(0x101c)       /* specify vertical synchronization pos and AC nr */
 
 /* Controls LCD (3) */
-#define HD64461_LDR3            (CONFIG_HD64461_IOBASE + 0x101e)
+#define HD64461_LDR3            HD64461_IO_OFFSET(0x101e)
 
 /* Palette Registers */
-#define HD64461_CPTWAR          (CONFIG_HD64461_IOBASE + 0x1030)        /* Color Palette Write Address Register */
-#define HD64461_CPTWDR          (CONFIG_HD64461_IOBASE + 0x1032)        /* Color Palette Write Data Register */
-#define HD64461_CPTRAR          (CONFIG_HD64461_IOBASE + 0x1034)        /* Color Palette Read Address Register */
-#define HD64461_CPTRDR          (CONFIG_HD64461_IOBASE + 0x1036)        /* Color Palette Read Data Register */
+#define HD64461_CPTWAR          HD64461_IO_OFFSET(0x1030)       /* Color Palette Write Address Register */
+#define HD64461_CPTWDR          HD64461_IO_OFFSET(0x1032)       /* Color Palette Write Data Register */
+#define HD64461_CPTRAR          HD64461_IO_OFFSET(0x1034)       /* Color Palette Read Address Register */
+#define HD64461_CPTRDR          HD64461_IO_OFFSET(0x1036)       /* Color Palette Read Data Register */
 
-#define HD64461_GRDOR           (CONFIG_HD64461_IOBASE + 0x1040)        /* Display Resolution Offset Register */
-#define HD64461_GRSCR           (CONFIG_HD64461_IOBASE + 0x1042)        /* Solid Color Register */
-#define HD64461_GRCFGR          (CONFIG_HD64461_IOBASE + 0x1044)        /* Accelerator Configuration Register */
+#define HD64461_GRDOR           HD64461_IO_OFFSET(0x1040)       /* Display Resolution Offset Register */
+#define HD64461_GRSCR           HD64461_IO_OFFSET(0x1042)       /* Solid Color Register */
+#define HD64461_GRCFGR          HD64461_IO_OFFSET(0x1044)       /* Accelerator Configuration Register */
 
 #define HD64461_GRCFGR_ACCSTATUS        0x10    /* Accelerator Status */
 #define HD64461_GRCFGR_ACCRESET         0x08    /* Accelerator Reset */
@@ -97,41 +99,41 @@
 #define HD64461_GRCFGR_COLORDEPTH8      0x01    /* Sets Colordepth 8 for Accelerator */
 
 /* Line Drawing Registers */
-#define HD64461_LNSARH          (CONFIG_HD64461_IOBASE + 0x1046)        /* Line Start Address Register (H) */
-#define HD64461_LNSARL          (CONFIG_HD64461_IOBASE + 0x1048)        /* Line Start Address Register (L) */
-#define HD64461_LNAXLR          (CONFIG_HD64461_IOBASE + 0x104a)        /* Axis Pixel Length Register */
-#define HD64461_LNDGR           (CONFIG_HD64461_IOBASE + 0x104c)        /* Diagonal Register */
-#define HD64461_LNAXR           (CONFIG_HD64461_IOBASE + 0x104e)        /* Axial Register */
-#define HD64461_LNERTR          (CONFIG_HD64461_IOBASE + 0x1050)        /* Start Error Term Register */
-#define HD64461_LNMDR           (CONFIG_HD64461_IOBASE + 0x1052)        /* Line Mode Register */
+#define HD64461_LNSARH          HD64461_IO_OFFSET(0x1046)       /* Line Start Address Register (H) */
+#define HD64461_LNSARL          HD64461_IO_OFFSET(0x1048)       /* Line Start Address Register (L) */
+#define HD64461_LNAXLR          HD64461_IO_OFFSET(0x104a)       /* Axis Pixel Length Register */
+#define HD64461_LNDGR           HD64461_IO_OFFSET(0x104c)       /* Diagonal Register */
+#define HD64461_LNAXR           HD64461_IO_OFFSET(0x104e)       /* Axial Register */
+#define HD64461_LNERTR          HD64461_IO_OFFSET(0x1050)       /* Start Error Term Register */
+#define HD64461_LNMDR           HD64461_IO_OFFSET(0x1052)       /* Line Mode Register */
 
 /* BitBLT Registers */
-#define HD64461_BBTSSARH        (CONFIG_HD64461_IOBASE + 0x1054)        /* Source Start Address Register (H) */
-#define HD64461_BBTSSARL        (CONFIG_HD64461_IOBASE + 0x1056)        /* Source Start Address Register (L) */
-#define HD64461_BBTDSARH        (CONFIG_HD64461_IOBASE + 0x1058)        /* Destination Start Address Register (H) */
-#define HD64461_BBTDSARL        (CONFIG_HD64461_IOBASE + 0x105a)        /* Destination Start Address Register (L) */
-#define HD64461_BBTDWR          (CONFIG_HD64461_IOBASE + 0x105c)        /* Destination Block Width Register */
-#define HD64461_BBTDHR          (CONFIG_HD64461_IOBASE + 0x105e)        /* Destination Block Height Register */
-#define HD64461_BBTPARH         (CONFIG_HD64461_IOBASE + 0x1060)        /* Pattern Start Address Register (H) */
-#define HD64461_BBTPARL         (CONFIG_HD64461_IOBASE + 0x1062)        /* Pattern Start Address Register (L) */
-#define HD64461_BBTMARH         (CONFIG_HD64461_IOBASE + 0x1064)        /* Mask Start Address Register (H) */
-#define HD64461_BBTMARL         (CONFIG_HD64461_IOBASE + 0x1066)        /* Mask Start Address Register (L) */
-#define HD64461_BBTROPR         (CONFIG_HD64461_IOBASE + 0x1068)        /* ROP Register */
-#define HD64461_BBTMDR          (CONFIG_HD64461_IOBASE + 0x106a)        /* BitBLT Mode Register */
+#define HD64461_BBTSSARH        HD64461_IO_OFFSET(0x1054)       /* Source Start Address Register (H) */
+#define HD64461_BBTSSARL        HD64461_IO_OFFSET(0x1056)       /* Source Start Address Register (L) */
+#define HD64461_BBTDSARH        HD64461_IO_OFFSET(0x1058)       /* Destination Start Address Register (H) */
+#define HD64461_BBTDSARL        HD64461_IO_OFFSET(0x105a)       /* Destination Start Address Register (L) */
+#define HD64461_BBTDWR          HD64461_IO_OFFSET(0x105c)       /* Destination Block Width Register */
+#define HD64461_BBTDHR          HD64461_IO_OFFSET(0x105e)       /* Destination Block Height Register */
+#define HD64461_BBTPARH         HD64461_IO_OFFSET(0x1060)       /* Pattern Start Address Register (H) */
+#define HD64461_BBTPARL         HD64461_IO_OFFSET(0x1062)       /* Pattern Start Address Register (L) */
+#define HD64461_BBTMARH         HD64461_IO_OFFSET(0x1064)       /* Mask Start Address Register (H) */
+#define HD64461_BBTMARL         HD64461_IO_OFFSET(0x1066)       /* Mask Start Address Register (L) */
+#define HD64461_BBTROPR         HD64461_IO_OFFSET(0x1068)       /* ROP Register */
+#define HD64461_BBTMDR          HD64461_IO_OFFSET(0x106a)       /* BitBLT Mode Register */
 
 /* PC Card Controller Registers */
 /* Maps to Physical Area 6 */
-#define HD64461_PCC0ISR         (CONFIG_HD64461_IOBASE + 0x2000)        /* socket 0 interface status */
-#define HD64461_PCC0GCR         (CONFIG_HD64461_IOBASE + 0x2002)        /* socket 0 general control */
-#define HD64461_PCC0CSCR        (CONFIG_HD64461_IOBASE + 0x2004)        /* socket 0 card status change */
-#define HD64461_PCC0CSCIER      (CONFIG_HD64461_IOBASE + 0x2006)        /* socket 0 card status change interrupt enable */
-#define HD64461_PCC0SCR         (CONFIG_HD64461_IOBASE + 0x2008)        /* socket 0 software control */
+#define HD64461_PCC0ISR         HD64461_IO_OFFSET(0x2000)       /* socket 0 interface status */
+#define HD64461_PCC0GCR         HD64461_IO_OFFSET(0x2002)       /* socket 0 general control */
+#define HD64461_PCC0CSCR        HD64461_IO_OFFSET(0x2004)       /* socket 0 card status change */
+#define HD64461_PCC0CSCIER      HD64461_IO_OFFSET(0x2006)       /* socket 0 card status change interrupt enable */
+#define HD64461_PCC0SCR         HD64461_IO_OFFSET(0x2008)       /* socket 0 software control */
 /* Maps to Physical Area 5 */
-#define HD64461_PCC1ISR         (CONFIG_HD64461_IOBASE + 0x2010)        /* socket 1 interface status */
-#define HD64461_PCC1GCR         (CONFIG_HD64461_IOBASE + 0x2012)        /* socket 1 general control */
-#define HD64461_PCC1CSCR        (CONFIG_HD64461_IOBASE + 0x2014)        /* socket 1 card status change */
-#define HD64461_PCC1CSCIER      (CONFIG_HD64461_IOBASE + 0x2016)        /* socket 1 card status change interrupt enable */
-#define HD64461_PCC1SCR         (CONFIG_HD64461_IOBASE + 0x2018)        /* socket 1 software control */
+#define HD64461_PCC1ISR         HD64461_IO_OFFSET(0x2010)       /* socket 1 interface status */
+#define HD64461_PCC1GCR         HD64461_IO_OFFSET(0x2012)       /* socket 1 general control */
+#define HD64461_PCC1CSCR        HD64461_IO_OFFSET(0x2014)       /* socket 1 card status change */
+#define HD64461_PCC1CSCIER      HD64461_IO_OFFSET(0x2016)       /* socket 1 card status change interrupt enable */
+#define HD64461_PCC1SCR         HD64461_IO_OFFSET(0x2018)       /* socket 1 software control */
 
 /* PCC Interface Status Register */
 #define HD64461_PCCISR_READY            0x80    /* card ready */
@@ -189,41 +191,41 @@
 #define HD64461_PCCSCR_SWP              0x01    /* write protect */
 
 /* PCC0 Output Pins Control Register */
-#define HD64461_P0OCR           (CONFIG_HD64461_IOBASE + 0x202a)
+#define HD64461_P0OCR           HD64461_IO_OFFSET(0x202a)
 
 /* PCC1 Output Pins Control Register */
-#define HD64461_P1OCR           (CONFIG_HD64461_IOBASE + 0x202c)
+#define HD64461_P1OCR           HD64461_IO_OFFSET(0x202c)
 
 /* PC Card General Control Register */
-#define HD64461_PGCR            (CONFIG_HD64461_IOBASE + 0x202e)
+#define HD64461_PGCR            HD64461_IO_OFFSET(0x202e)
 
 /* Port Control Registers */
-#define HD64461_GPACR           (CONFIG_HD64461_IOBASE + 0x4000)        /* Port A - Handles IRDA/TIMER */
-#define HD64461_GPBCR           (CONFIG_HD64461_IOBASE + 0x4002)        /* Port B - Handles UART */
-#define HD64461_GPCCR           (CONFIG_HD64461_IOBASE + 0x4004)        /* Port C - Handles PCMCIA 1 */
-#define HD64461_GPDCR           (CONFIG_HD64461_IOBASE + 0x4006)        /* Port D - Handles PCMCIA 1 */
+#define HD64461_GPACR           HD64461_IO_OFFSET(0x4000)       /* Port A - Handles IRDA/TIMER */
+#define HD64461_GPBCR           HD64461_IO_OFFSET(0x4002)       /* Port B - Handles UART */
+#define HD64461_GPCCR           HD64461_IO_OFFSET(0x4004)       /* Port C - Handles PCMCIA 1 */
+#define HD64461_GPDCR           HD64461_IO_OFFSET(0x4006)       /* Port D - Handles PCMCIA 1 */
 
 /* Port Control Data Registers */
-#define HD64461_GPADR           (CONFIG_HD64461_IOBASE + 0x4010)        /* A */
-#define HD64461_GPBDR           (CONFIG_HD64461_IOBASE + 0x4012)        /* B */
-#define HD64461_GPCDR           (CONFIG_HD64461_IOBASE + 0x4014)        /* C */
-#define HD64461_GPDDR           (CONFIG_HD64461_IOBASE + 0x4016)        /* D */
+#define HD64461_GPADR           HD64461_IO_OFFSET(0x4010)       /* A */
+#define HD64461_GPBDR           HD64461_IO_OFFSET(0x4012)       /* B */
+#define HD64461_GPCDR           HD64461_IO_OFFSET(0x4014)       /* C */
+#define HD64461_GPDDR           HD64461_IO_OFFSET(0x4016)       /* D */
 
 /* Interrupt Control Registers */
-#define HD64461_GPAICR          (CONFIG_HD64461_IOBASE + 0x4020)        /* A */
-#define HD64461_GPBICR          (CONFIG_HD64461_IOBASE + 0x4022)        /* B */
-#define HD64461_GPCICR          (CONFIG_HD64461_IOBASE + 0x4024)        /* C */
-#define HD64461_GPDICR          (CONFIG_HD64461_IOBASE + 0x4026)        /* D */
+#define HD64461_GPAICR          HD64461_IO_OFFSET(0x4020)       /* A */
+#define HD64461_GPBICR          HD64461_IO_OFFSET(0x4022)       /* B */
+#define HD64461_GPCICR          HD64461_IO_OFFSET(0x4024)       /* C */
+#define HD64461_GPDICR          HD64461_IO_OFFSET(0x4026)       /* D */
 
 /* Interrupt Status Registers */
-#define HD64461_GPAISR          (CONFIG_HD64461_IOBASE + 0x4040)        /* A */
-#define HD64461_GPBISR          (CONFIG_HD64461_IOBASE + 0x4042)        /* B */
-#define HD64461_GPCISR          (CONFIG_HD64461_IOBASE + 0x4044)        /* C */
-#define HD64461_GPDISR          (CONFIG_HD64461_IOBASE + 0x4046)        /* D */
+#define HD64461_GPAISR          HD64461_IO_OFFSET(0x4040)       /* A */
+#define HD64461_GPBISR          HD64461_IO_OFFSET(0x4042)       /* B */
+#define HD64461_GPCISR          HD64461_IO_OFFSET(0x4044)       /* C */
+#define HD64461_GPDISR          HD64461_IO_OFFSET(0x4046)       /* D */
 
 /* Interrupt Request Register & Interrupt Mask Register */
-#define HD64461_NIRR            (CONFIG_HD64461_IOBASE + 0x5000)
-#define HD64461_NIMR            (CONFIG_HD64461_IOBASE + 0x5002)
+#define HD64461_NIRR            HD64461_IO_OFFSET(0x5000)
+#define HD64461_NIMR            HD64461_IO_OFFSET(0x5002)
 
 #define HD64461_IRQBASE         OFFCHIP_IRQ_BASE
 #define OFFCHIP_IRQ_BASE        64
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
index 0454f8d68059..25348141674b 100644
--- a/arch/sh/include/asm/io.h
+++ b/arch/sh/include/asm/io.h
@@ -123,10 +123,15 @@ static inline void __raw_reads##bwlq(volatile void __iomem *mem,	\
 
 __BUILD_MEMORY_STRING(b, u8)
 __BUILD_MEMORY_STRING(w, u16)
-__BUILD_MEMORY_STRING(q, u64)
 
+#ifdef CONFIG_SUPERH32
 void __raw_writesl(void __iomem *addr, const void *data, int longlen);
 void __raw_readsl(const void __iomem *addr, void *data, int longlen);
+#else
+__BUILD_MEMORY_STRING(l, u32)
+#endif
+
+__BUILD_MEMORY_STRING(q, u64)
 
 #define writesb                 __raw_writesb
 #define writesw                 __raw_writesw
@@ -224,17 +229,6 @@ void __iomem *__ioremap(unsigned long offset, unsigned long size,
                         unsigned long flags);
 void __iounmap(void __iomem *addr);
 
-/* arch/sh/mm/ioremap_64.c */
-unsigned long onchip_remap(unsigned long addr, unsigned long size,
-                           const char *name);
-extern void onchip_unmap(unsigned long vaddr);
-#else
-#define __ioremap(offset, size, flags)  ((void __iomem *)(offset))
-#define __iounmap(addr)                 do { } while (0)
-#define onchip_remap(addr, size, name)  (addr)
-#define onchip_unmap(addr)              do { } while (0)
-#endif /* CONFIG_MMU */
-
 static inline void __iomem *
 __ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags)
 {
@@ -268,6 +262,10 @@ __ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags)
 
         return __ioremap(offset, size, flags);
 }
+#else
+#define __ioremap_mode(offset, size, flags)     ((void __iomem *)(offset))
+#define __iounmap(addr)                         do { } while (0)
+#endif /* CONFIG_MMU */
 
 #define ioremap(offset, size)                           \
         __ioremap_mode((offset), (size), 0)
diff --git a/arch/sh/include/asm/irq.h b/arch/sh/include/asm/irq.h
index d319baaf4fbd..a2b8c99cc06f 100644
--- a/arch/sh/include/asm/irq.h
+++ b/arch/sh/include/asm/irq.h
@@ -8,7 +8,8 @@
  * advised to cap this at the hard limit that they're interested in
  * through the machvec.
  */
-#define NR_IRQS 256
+#define NR_IRQS                 256
+#define NR_IRQS_LEGACY          8       /* Legacy external IRQ0-7 */
 
 /*
  * Convert back and forth between INTEVT and IRQ values.
diff --git a/arch/sh/include/asm/kprobes.h b/arch/sh/include/asm/kprobes.h
index 613644a758e8..036c3311233c 100644
--- a/arch/sh/include/asm/kprobes.h
+++ b/arch/sh/include/asm/kprobes.h
@@ -6,7 +6,7 @@
 #include <linux/types.h>
 #include <linux/ptrace.h>
 
-typedef u16 kprobe_opcode_t;
+typedef insn_size_t kprobe_opcode_t;
 #define BREAKPOINT_INSTRUCTION  0xc33a
 
 #define MAX_INSN_SIZE 16
diff --git a/arch/sh/include/asm/machvec.h b/arch/sh/include/asm/machvec.h
index 64b1c16a0f03..84dd37761f56 100644
--- a/arch/sh/include/asm/machvec.h
+++ b/arch/sh/include/asm/machvec.h
@@ -46,6 +46,9 @@ struct sh_machine_vector {
 
         void __iomem *(*mv_ioport_map)(unsigned long port, unsigned int size);
         void (*mv_ioport_unmap)(void __iomem *);
+
+        int (*mv_clk_init)(void);
+        int (*mv_mode_pins)(void);
 };
 
 extern struct sh_machine_vector sh_mv;
diff --git a/arch/sh/include/asm/pci.h b/arch/sh/include/asm/pci.h
index df1d383e18a5..ae0da6f48b6d 100644
--- a/arch/sh/include/asm/pci.h
+++ b/arch/sh/include/asm/pci.h
@@ -17,54 +17,29 @@
  * external) PCI controllers.
  */
 struct pci_channel {
-        struct pci_ops *pci_ops;
-        struct resource *io_resource;
-        struct resource *mem_resource;
-        int first_devfn;
-        int last_devfn;
-};
+        struct pci_channel      *next;
 
-/*
- * Each board initializes this array and terminates it with a NULL entry.
- */
-extern struct pci_channel board_pci_channels[];
+        struct pci_ops          *pci_ops;
+        struct resource         *io_resource;
+        struct resource         *mem_resource;
 
-#define PCIBIOS_MIN_IO          board_pci_channels->io_resource->start
-#define PCIBIOS_MIN_MEM         board_pci_channels->mem_resource->start
+        unsigned long           io_offset;
+        unsigned long           mem_offset;
 
-/*
- * I/O routine helpers
- */
-#if defined(CONFIG_CPU_SUBTYPE_SH7780) || defined(CONFIG_CPU_SUBTYPE_SH7785)
-#define PCI_IO_AREA             0xFE400000
-#define PCI_IO_SIZE             0x00400000
-#elif defined(CONFIG_CPU_SH5)
-extern unsigned long PCI_IO_AREA;
-#define PCI_IO_SIZE             0x00010000
-#else
-#define PCI_IO_AREA             0xFE240000
-#define PCI_IO_SIZE             0x00040000
-#endif
+        unsigned long           reg_base;
 
-#define PCI_MEM_SIZE            0x01000000
+        unsigned long           io_map_base;
+};
 
-#define SH4_PCIIOBR_MASK        0xFFFC0000
-#define pci_ioaddr(addr)        (PCI_IO_AREA + (addr & ~SH4_PCIIOBR_MASK))
+extern void register_pci_controller(struct pci_channel *hose);
 
-#if defined(CONFIG_PCI)
-#define is_pci_ioaddr(port)             \
-        (((port) >= PCIBIOS_MIN_IO) &&  \
-         ((port) < (PCIBIOS_MIN_IO + PCI_IO_SIZE)))
-#define is_pci_memaddr(port)            \
-        (((port) >= PCIBIOS_MIN_MEM) && \
-         ((port) < (PCIBIOS_MIN_MEM + PCI_MEM_SIZE)))
-#else
-#define is_pci_ioaddr(port)     (0)
-#define is_pci_memaddr(port)    (0)
-#endif
+extern unsigned long PCIBIOS_MIN_IO, PCIBIOS_MIN_MEM;
 
 struct pci_dev;
 
+#define HAVE_PCI_MMAP
+extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
+        enum pci_mmap_state mmap_state, int write_combine);
 extern void pcibios_set_master(struct pci_dev *dev);
 
 static inline void pcibios_penalize_isa_irq(int irq, int active)
@@ -114,31 +89,76 @@ static inline void pcibios_penalize_isa_irq(int irq, int active)
 #endif
 
 #ifdef CONFIG_PCI
+/*
+ * None of the SH PCI controllers support MWI, it is always treated as a
+ * direct memory write.
+ */
+#define PCI_DISABLE_MWI
+
 static inline void pci_dma_burst_advice(struct pci_dev *pdev,
                                         enum pci_dma_burst_strategy *strat,
                                         unsigned long *strategy_parameter)
 {
-        *strat = PCI_DMA_BURST_INFINITY;
-        *strategy_parameter = ~0UL;
+        unsigned long cacheline_size;
+        u8 byte;
+
+        pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
+
+        if (byte == 0)
+                cacheline_size = L1_CACHE_BYTES;
+        else
+                cacheline_size = byte << 2;
+
+        *strat = PCI_DMA_BURST_MULTIPLE;
+        *strategy_parameter = cacheline_size;
 }
 #endif
 
+#ifdef CONFIG_SUPERH32
+/*
+ * If we're on an SH7751 or SH7780 PCI controller, PCI memory is mapped
+ * at the end of the address space in a special non-translatable area.
+ */
+#define PCI_MEM_FIXED_START     0xfd000000
+#define PCI_MEM_FIXED_END       (PCI_MEM_FIXED_START + 0x01000000)
+
+#define is_pci_memory_fixed_range(s, e) \
+        ((s) >= PCI_MEM_FIXED_START && (e) < PCI_MEM_FIXED_END)
+#else
+#define is_pci_memory_fixed_range(s, e) (0)
+#endif
+
 /* Board-specific fixup routines. */
-void pcibios_fixup(void);
-int pcibios_init_platform(void);
 int pcibios_map_platform_irq(struct pci_dev *dev, u8 slot, u8 pin);
 
-#ifdef CONFIG_PCI_AUTO
-int pciauto_assign_resources(int busno, struct pci_channel *hose);
-#endif
+extern void pcibios_resource_to_bus(struct pci_dev *dev,
+        struct pci_bus_region *region, struct resource *res);
 
-#endif /* __KERNEL__ */
+extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
+                                    struct pci_bus_region *region);
 
-/* generic pci stuff */
-#include <asm-generic/pci.h>
+static inline struct resource *
+pcibios_select_root(struct pci_dev *pdev, struct resource *res)
+{
+        struct resource *root = NULL;
+
+        if (res->flags & IORESOURCE_IO)
+                root = &ioport_resource;
+        if (res->flags & IORESOURCE_MEM)
+                root = &iomem_resource;
+
+        return root;
+}
+
+/* Chances are this interrupt is wired PC-style ...  */
+static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
+{
+        return channel ? 15 : 14;
+}
 
 /* generic DMA-mapping stuff */
 #include <asm-generic/pci-dma-compat.h>
 
+#endif /* __KERNEL__ */
 #endif /* __ASM_SH_PCI_H */
 
diff --git a/arch/sh/include/asm/pgtable.h b/arch/sh/include/asm/pgtable.h
index b517ae08b9c0..2a011b18090b 100644
--- a/arch/sh/include/asm/pgtable.h
+++ b/arch/sh/include/asm/pgtable.h
@@ -154,6 +154,10 @@ extern void kmap_coherent_init(void);
 #define kmap_coherent_init()    do { } while (0)
 #endif
 
+/* arch/sh/mm/mmap.c */
+#define HAVE_ARCH_UNMAPPED_AREA
+#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
+
 #include <asm-generic/pgtable.h>
 
 #endif /* __ASM_SH_PGTABLE_H */
diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h
index 1fd58b421438..ff7daaf9a620 100644
--- a/arch/sh/include/asm/processor.h
+++ b/arch/sh/include/asm/processor.h
@@ -32,7 +32,7 @@ enum cpu_type {
 
         /* SH-4A types */
         CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786,
-        CPU_SH7723, CPU_SHX3,
+        CPU_SH7723, CPU_SH7724, CPU_SHX3,
 
         /* SH4AL-DSP types */
         CPU_SH7343, CPU_SH7722, CPU_SH7366,
@@ -94,6 +94,27 @@ extern struct pt_regs fake_swapper_regs;
 const char *get_cpu_subtype(struct sh_cpuinfo *c);
 extern const struct seq_operations cpuinfo_op;
 
+/* processor boot mode configuration */
+#define MODE_PIN0 (1 << 0)
+#define MODE_PIN1 (1 << 1)
+#define MODE_PIN2 (1 << 2)
+#define MODE_PIN3 (1 << 3)
+#define MODE_PIN4 (1 << 4)
+#define MODE_PIN5 (1 << 5)
+#define MODE_PIN6 (1 << 6)
+#define MODE_PIN7 (1 << 7)
+#define MODE_PIN8 (1 << 8)
+#define MODE_PIN9 (1 << 9)
+#define MODE_PIN10 (1 << 10)
+#define MODE_PIN11 (1 << 11)
+#define MODE_PIN12 (1 << 12)
+#define MODE_PIN13 (1 << 13)
+#define MODE_PIN14 (1 << 14)
+#define MODE_PIN15 (1 << 15)
+
+int generic_mode_pins(void);
+int test_mode_pin(int pin);
+
 #ifdef CONFIG_VSYSCALL
 int vsyscall_init(void);
 #else
diff --git a/arch/sh/include/asm/ptrace.h b/arch/sh/include/asm/ptrace.h
index 68e20ff9aa9b..1dc12cb44a2d 100644
--- a/arch/sh/include/asm/ptrace.h
+++ b/arch/sh/include/asm/ptrace.h
@@ -102,6 +102,11 @@ struct pt_dspregs {
 #define PTRACE_GETDSPREGS       55      /* DSP registers */
 #define PTRACE_SETDSPREGS       56
 
+#define PT_TEXT_END_ADDR        240
+#define PT_TEXT_ADDR            244     /* &(struct user)->start_code */
+#define PT_DATA_ADDR            248     /* &(struct user)->start_data */
+#define PT_TEXT_LEN             252
+
 #ifdef __KERNEL__
 #include <asm/addrspace.h>
 
diff --git a/arch/sh/include/asm/rtc.h b/arch/sh/include/asm/rtc.h
index f7b010d48af7..52b0c2dba979 100644
--- a/arch/sh/include/asm/rtc.h
+++ b/arch/sh/include/asm/rtc.h
@@ -6,6 +6,17 @@ extern void (*board_time_init)(void);
 extern void (*rtc_sh_get_time)(struct timespec *);
 extern int (*rtc_sh_set_time)(const time_t);
 
+/* some dummy definitions */
+#define RTC_BATT_BAD 0x100      /* battery bad */
+#define RTC_SQWE 0x08           /* enable square-wave output */
+#define RTC_DM_BINARY 0x04      /* all time/date values are BCD if clear */
+#define RTC_24H 0x02            /* 24 hour mode - else hours bit 7 means pm */
+#define RTC_DST_EN 0x01         /* auto switch DST - works f. USA only */
+
+struct rtc_time;
+unsigned int get_rtc_time(struct rtc_time *);
+int set_rtc_time(struct rtc_time *);
+
 #define RTC_CAP_4_DIGIT_YEAR    (1 << 0)
 
 struct sh_rtc_platform_info {
diff --git a/arch/sh/include/asm/spinlock.h b/arch/sh/include/asm/spinlock.h
index 60283565f89b..a28c9f0053fd 100644
--- a/arch/sh/include/asm/spinlock.h
+++ b/arch/sh/include/asm/spinlock.h
@@ -26,7 +26,7 @@
 #define __raw_spin_is_locked(x)         ((x)->lock <= 0)
 #define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
 #define __raw_spin_unlock_wait(x) \
-        do { cpu_relax(); } while ((x)->lock)
+        do { while (__raw_spin_is_locked(x)) cpu_relax(); } while (0)
 
 /*
  * Simple spin lock operations.  There are two variants, one clears IRQ's
diff --git a/arch/sh/include/asm/swab.h b/arch/sh/include/asm/swab.h
index e69315935107..0e08fe54ad71 100644
--- a/arch/sh/include/asm/swab.h
+++ b/arch/sh/include/asm/swab.h
@@ -14,15 +14,15 @@ static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
 {
         __asm__(
 #ifdef __SH5__
-                "byterev        %0, %0\n\t"
+                "byterev        %1, %0\n\t"
                 "shari          %0, 32, %0"
 #else
-                "swap.b         %0, %0\n\t"
+                "swap.b         %1, %0\n\t"
                 "swap.w         %0, %0\n\t"
                 "swap.b         %0, %0"
 #endif
                 : "=r" (x)
-                : "0" (x));
+                : "r" (x));
 
         return x;
 }
@@ -32,13 +32,13 @@ static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
 {
         __asm__(
 #ifdef __SH5__
-                "byterev        %0, %0\n\t"
+                "byterev        %1, %0\n\t"
                 "shari          %0, 32, %0"
 #else
-                "swap.b         %0, %0"
+                "swap.b         %1, %0"
 #endif
                 : "=r" (x)
-                :  "0" (x));
+                :  "r" (x));
 
         return x;
 }
diff --git a/arch/sh/include/asm/system_32.h b/arch/sh/include/asm/system_32.h
index 240b31e1142c..6c68a51f1cc5 100644
--- a/arch/sh/include/asm/system_32.h
+++ b/arch/sh/include/asm/system_32.h
@@ -198,7 +198,7 @@ do {							\
 })
 #endif
 
-int handle_unaligned_access(opcode_t instruction, struct pt_regs *regs,
+int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
                             struct mem_access *ma);
 
 asmlinkage void do_address_error(struct pt_regs *regs,
diff --git a/arch/sh/include/asm/timer.h b/arch/sh/include/asm/timer.h
deleted file mode 100644
index 4c3b66e30af2..000000000000
--- a/arch/sh/include/asm/timer.h
+++ /dev/null
@@ -1,44 +0,0 @@
-#ifndef __ASM_SH_TIMER_H
-#define __ASM_SH_TIMER_H
-
-#include <linux/sysdev.h>
-#include <linux/clocksource.h>
-#include <cpu/timer.h>
-
-struct sys_timer_ops {
-        int (*init)(void);
-        int (*start)(void);
-        int (*stop)(void);
-#ifndef CONFIG_GENERIC_TIME
-        unsigned long (*get_offset)(void);
-#endif
-};
-
-struct sys_timer {
-        const char              *name;
-
-        struct sys_device       dev;
-        struct sys_timer_ops    *ops;
-};
-
-#define TICK_SIZE (tick_nsec / 1000)
-
-extern struct sys_timer tmu_timer, cmt_timer, mtu2_timer;
-extern struct sys_timer *sys_timer;
-
-#ifndef CONFIG_GENERIC_TIME
-static inline unsigned long get_timer_offset(void)
-{
-        return sys_timer->ops->get_offset();
-}
-#endif
-
-/* arch/sh/kernel/timers/timer.c */
-struct sys_timer *get_sys_timer(void);
-
-/* arch/sh/kernel/time.c */
-void handle_timer_tick(void);
-
-extern struct clocksource clocksource_sh;
-
-#endif /* __ASM_SH_TIMER_H */
diff --git a/arch/sh/include/asm/types.h b/arch/sh/include/asm/types.h
index beea4e6f8dfd..b13caca62a76 100644
--- a/arch/sh/include/asm/types.h
+++ b/arch/sh/include/asm/types.h
@@ -23,9 +23,9 @@ typedef unsigned short umode_t;
 typedef u32 dma_addr_t;
 
 #ifdef CONFIG_SUPERH32
-typedef u16 opcode_t;
+typedef u16 insn_size_t;
 #else
-typedef u32 opcode_t;
+typedef u32 insn_size_t;
 #endif
 
 #endif /* __ASSEMBLY__ */
diff --git a/arch/sh/include/asm/ubc.h b/arch/sh/include/asm/ubc.h
index a7b9028bbfbb..4ca4b7717371 100644
--- a/arch/sh/include/asm/ubc.h
+++ b/arch/sh/include/asm/ubc.h
@@ -42,12 +42,23 @@
 
 #define BRCR_CMFA               (1 << 15)
 #define BRCR_CMFB               (1 << 14)
+
+#if defined CONFIG_CPU_SH2A
+#define BRCR_CMFCA              (1 << 15)
+#define BRCR_CMFCB              (1 << 14)
+#define BRCR_CMFDA              (1 << 13)
+#define BRCR_CMFDB              (1 << 12)
+#define BRCR_PCBB               (1 << 6)        /* 1: after execution */
+#define BRCR_PCBA               (1 << 5)        /* 1: after execution */
+#define BRCR_PCTE               0
+#else
 #define BRCR_PCTE               (1 << 11)
 #define BRCR_PCBA               (1 << 10)       /* 1: after execution */
 #define BRCR_DBEB               (1 << 7)
 #define BRCR_PCBB               (1 << 6)
 #define BRCR_SEQ                (1 << 3)
 #define BRCR_UBDE               (1 << 0)
+#endif
 
 #ifndef __ASSEMBLY__
 /* arch/sh/kernel/cpu/ubc.S */
diff --git a/arch/sh/include/asm/unaligned-sh4a.h b/arch/sh/include/asm/unaligned-sh4a.h
index d8f89770275b..9f4dd252c981 100644
--- a/arch/sh/include/asm/unaligned-sh4a.h
+++ b/arch/sh/include/asm/unaligned-sh4a.h
@@ -3,9 +3,9 @@
 
 /*
  * SH-4A has support for unaligned 32-bit loads, and 32-bit loads only.
- * Support for 16 and 64-bit accesses are done through shifting and
- * masking relative to the endianness. Unaligned stores are not supported
- * by the instruction encoding, so these continue to use the packed
+ * Support for 64-bit accesses are done through shifting and masking
+ * relative to the endianness. Unaligned stores are not supported by the
+ * instruction encoding, so these continue to use the packed
  * struct.
  *
  * The same note as with the movli.l/movco.l pair applies here, as long
@@ -41,9 +41,9 @@ struct __una_u64 { u64 x __attribute__((packed)); };
 static inline u16 __get_unaligned_cpu16(const u8 *p)
 {
 #ifdef __LITTLE_ENDIAN
-        return __get_unaligned_cpu32(p) & 0xffff;
+        return p[0] | p[1] << 8;
 #else
-        return __get_unaligned_cpu32(p) >> 16;
+        return p[0] << 8 | p[1];
 #endif
 }
 
diff --git a/arch/sh/include/asm/unistd_32.h b/arch/sh/include/asm/unistd_32.h
index 2efb819e2db3..65197086a1c5 100644
--- a/arch/sh/include/asm/unistd_32.h
+++ b/arch/sh/include/asm/unistd_32.h
@@ -343,8 +343,9 @@
 #define __NR_inotify_init1      332
 #define __NR_preadv             333
 #define __NR_pwritev            334
+#define __NR_rt_tgsigqueueinfo  335
 
-#define NR_syscalls 335
+#define NR_syscalls 336
 
 #ifdef __KERNEL__
 
diff --git a/arch/sh/include/asm/unistd_64.h b/arch/sh/include/asm/unistd_64.h
index 6eb9d2934c0f..8014aea88ec3 100644
--- a/arch/sh/include/asm/unistd_64.h
+++ b/arch/sh/include/asm/unistd_64.h
@@ -383,10 +383,11 @@
 #define __NR_inotify_init1      360
 #define __NR_preadv             361
 #define __NR_pwritev            362
+#define __NR_rt_tgsigqueueinfo  363
 
 #ifdef __KERNEL__
 
-#define NR_syscalls 363
+#define NR_syscalls 364
 
 #define __ARCH_WANT_IPC_PARSE_VERSION
 #define __ARCH_WANT_OLD_READDIR
diff --git a/arch/sh/include/cpu-sh2a/cpu/ubc.h b/arch/sh/include/cpu-sh2a/cpu/ubc.h
index 8ce2fc1cf625..1192e1c761a7 100644
--- a/arch/sh/include/cpu-sh2a/cpu/ubc.h
+++ b/arch/sh/include/cpu-sh2a/cpu/ubc.h
@@ -1 +1,28 @@
-#include <cpu-sh2/cpu/ubc.h>
+/*
+ * SH-2A UBC definitions
+ *
+ * Copyright (C) 2008 Kieran Bingham
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_CPU_SH2A_UBC_H
+#define __ASM_CPU_SH2A_UBC_H
+
+#define UBC_BARA                0xfffc0400
+#define UBC_BAMRA               0xfffc0404
+#define UBC_BBRA                0xfffc04a0      /* 16 bit access */
+#define UBC_BDRA                0xfffc0408
+#define UBC_BDMRA               0xfffc040c
+
+#define UBC_BARB                0xfffc0410
+#define UBC_BAMRB               0xfffc0414
+#define UBC_BBRB                0xfffc04b0      /* 16 bit access */
+#define UBC_BDRB                0xfffc0418
+#define UBC_BDMRB               0xfffc041c
+
+#define UBC_BRCR                0xfffc04c0
+
+#endif /* __ASM_CPU_SH2A_UBC_H */
diff --git a/arch/sh/include/cpu-sh3/cpu/timer.h b/arch/sh/include/cpu-sh3/cpu/timer.h
deleted file mode 100644
index 793acf12aa08..000000000000
--- a/arch/sh/include/cpu-sh3/cpu/timer.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * include/asm-sh/cpu-sh3/timer.h
- *
- * Copyright (C) 2004 Lineo Solutions, Inc.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#ifndef __ASM_CPU_SH3_TIMER_H
-#define __ASM_CPU_SH3_TIMER_H
-
-/*
- * ---------------------------------------------------------------------------
- * TMU Common definitions for SH3 processors
- *      SH7706
- *      SH7709S
- *      SH7727
- *      SH7729R
- *      SH7710
- *      SH7720
- *      SH7710
- * ---------------------------------------------------------------------------
- */
-
-#if  !defined(CONFIG_CPU_SUBTYPE_SH7720) && !defined(CONFIG_CPU_SUBTYPE_SH7721)
-#define TMU_TOCR        0xfffffe90      /* Byte access */
-#endif
-
-#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \
-    defined(CONFIG_CPU_SUBTYPE_SH7720) || \
-    defined(CONFIG_CPU_SUBTYPE_SH7721)
-#define TMU_012_TSTR    0xa412fe92      /* Byte access */
-
-#define TMU0_TCOR       0xa412fe94      /* Long access */
-#define TMU0_TCNT       0xa412fe98      /* Long access */
-#define TMU0_TCR        0xa412fe9c      /* Word access */
-
-#define TMU1_TCOR       0xa412fea0      /* Long access */
-#define TMU1_TCNT       0xa412fea4      /* Long access */
-#define TMU1_TCR        0xa412fea8      /* Word access */
-
-#define TMU2_TCOR       0xa412feac      /* Long access */
-#define TMU2_TCNT       0xa412feb0      /* Long access */
-#define TMU2_TCR        0xa412feb4      /* Word access */
-
-#else
-#define TMU_012_TSTR    0xfffffe92      /* Byte access */
-
-#define TMU0_TCOR       0xfffffe94      /* Long access */
-#define TMU0_TCNT       0xfffffe98      /* Long access */
-#define TMU0_TCR        0xfffffe9c      /* Word access */
-
-#define TMU1_TCOR       0xfffffea0      /* Long access */
-#define TMU1_TCNT       0xfffffea4      /* Long access */
-#define TMU1_TCR        0xfffffea8      /* Word access */
-
-#define TMU2_TCOR       0xfffffeac      /* Long access */
-#define TMU2_TCNT       0xfffffeb0      /* Long access */
-#define TMU2_TCR        0xfffffeb4      /* Word access */
-#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && !defined(CONFIG_CPU_SUBTYPE_SH7721)
-#define TMU2_TCPR2      0xfffffeb8      /* Long access */
-#endif
-#endif
-
-#endif /* __ASM_CPU_SH3_TIMER_H */
-
diff --git a/arch/sh/include/cpu-sh4/cpu/cache.h b/arch/sh/include/cpu-sh4/cpu/cache.h
index 1c61ebf5c8e3..7bfb9e8b069c 100644
--- a/arch/sh/include/cpu-sh4/cpu/cache.h
+++ b/arch/sh/include/cpu-sh4/cpu/cache.h
@@ -38,5 +38,7 @@
 #define CACHE_IC_ADDRESS_ARRAY  0xf0000000
 #define CACHE_OC_ADDRESS_ARRAY  0xf4000000
 
+#define RAMCR                   0xFF000074
+
 #endif /* __ASM_CPU_SH4_CACHE_H */
 
diff --git a/arch/sh/include/cpu-sh4/cpu/freq.h b/arch/sh/include/cpu-sh4/cpu/freq.h
index 749d1c434337..ccf1d999db6d 100644
--- a/arch/sh/include/cpu-sh4/cpu/freq.h
+++ b/arch/sh/include/cpu-sh4/cpu/freq.h
@@ -25,6 +25,24 @@
 #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
       defined(CONFIG_CPU_SUBTYPE_SH7780)
 #define FRQCR                   0xffc80000
+#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
+#define FRQCRA                  0xa4150000
+#define FRQCRB                  0xa4150004
+#define VCLKCR                  0xa4150048
+
+#define FCLKACR                 0xa4150008
+#define FCLKBCR                 0xa415000c
+#define FRQCR                   FRQCRA
+#define SCLKACR                 FCLKACR
+#define SCLKBCR                 FCLKBCR
+#define FCLKACR                 0xa4150008
+#define FCLKBCR                 0xa415000c
+#define IrDACLKCR               0xa4150018
+
+#define MSTPCR0                 0xa4150030
+#define MSTPCR1                 0xa4150034
+#define MSTPCR2                 0xa4150038
+
 #elif defined(CONFIG_CPU_SUBTYPE_SH7785)
 #define FRQCR0                  0xffc80000
 #define FRQCR1                  0xffc80004
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7722.h b/arch/sh/include/cpu-sh4/cpu/sh7722.h
index 4b3096f5307b..738ea43c5038 100644
--- a/arch/sh/include/cpu-sh4/cpu/sh7722.h
+++ b/arch/sh/include/cpu-sh4/cpu/sh7722.h
@@ -1,6 +1,20 @@
 #ifndef __ASM_SH7722_H__
 #define __ASM_SH7722_H__
 
+/* Boot Mode Pins:
+ *
+ * MD0: CPG - Clock Mode 0->3
+ * MD1: CPG - Clock Mode 0->3
+ * MD2: CPG - Reserved (L: Normal operation)
+ * MD3: BSC - Area0 Bus Width (16/32-bit) [CS0BCR.9,10]
+ * MD5: BSC - Endian Mode (L: Big, H: Little) [CMNCR.3]
+ * MD8: Test Mode
+ */
+
+/* Pin Function Controller:
+ * GPIO_FN_xx - GPIO used to select pin function
+ * GPIO_Pxx - GPIO mapped to real I/O pin on CPU
+ */
 enum {
         /* PTA */
         GPIO_PTA7, GPIO_PTA6, GPIO_PTA5, GPIO_PTA4,
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7723.h b/arch/sh/include/cpu-sh4/cpu/sh7723.h
index 9d2f6d7aa938..14c8ca936781 100644
--- a/arch/sh/include/cpu-sh4/cpu/sh7723.h
+++ b/arch/sh/include/cpu-sh4/cpu/sh7723.h
@@ -1,6 +1,20 @@
 #ifndef __ASM_SH7723_H__
 #define __ASM_SH7723_H__
 
+/* Boot Mode Pins:
+ *
+ * MD0: CPG - Clock Mode 0->3
+ * MD1: CPG - Clock Mode 0->3
+ * MD2: CPG - Reserved (L: Normal operation)
+ * MD3: BSC - Area0 Bus Width (16/32-bit) [CS0BCR.9,10]
+ * MD5: BSC - Endian Mode (L: Big, H: Little) [CMNCR.3]
+ * MD8: Test Mode
+ */
+
+/* Pin Function Controller:
+ * GPIO_FN_xx - GPIO used to select pin function
+ * GPIO_Pxx - GPIO mapped to real I/O pin on CPU
+ */
 enum {
         /* PTA */
         GPIO_PTA7, GPIO_PTA6, GPIO_PTA5, GPIO_PTA4,
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7724.h b/arch/sh/include/cpu-sh4/cpu/sh7724.h
new file mode 100644
index 000000000000..66fd1184359e
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/sh7724.h
@@ -0,0 +1,269 @@
+#ifndef __ASM_SH7724_H__
+#define __ASM_SH7724_H__
+
+/* Boot Mode Pins:
+ *
+ * MD0: CPG - Clock Mode 0->7
+ * MD1: CPG - Clock Mode 0->7
+ * MD2: CPG - Clock Mode 0->7
+ * MD3: BSC - Area0 Bus Width (16/32-bit) [CS0BCR.9,10]
+ * MD5: BSC - Endian Mode (L: Big, H: Little) [CMNCR.3]
+ * MD8: Test Mode
+ */
+
+/* Pin Function Controller:
+ * GPIO_FN_xx - GPIO used to select pin function
+ * GPIO_Pxx - GPIO mapped to real I/O pin on CPU
+ */
+enum {
+        /* PTA */
+        GPIO_PTA7, GPIO_PTA6, GPIO_PTA5, GPIO_PTA4,
+        GPIO_PTA3, GPIO_PTA2, GPIO_PTA1, GPIO_PTA0,
+
+        /* PTB */
+        GPIO_PTB7, GPIO_PTB6, GPIO_PTB5, GPIO_PTB4,
+        GPIO_PTB3, GPIO_PTB2, GPIO_PTB1, GPIO_PTB0,
+
+        /* PTC */
+        GPIO_PTC7, GPIO_PTC6, GPIO_PTC5, GPIO_PTC4,
+        GPIO_PTC3, GPIO_PTC2, GPIO_PTC1, GPIO_PTC0,
+
+        /* PTD */
+        GPIO_PTD7, GPIO_PTD6, GPIO_PTD5, GPIO_PTD4,
+        GPIO_PTD3, GPIO_PTD2, GPIO_PTD1, GPIO_PTD0,
+
+        /* PTE */
+        GPIO_PTE7, GPIO_PTE6, GPIO_PTE5, GPIO_PTE4,
+        GPIO_PTE3, GPIO_PTE2, GPIO_PTE1, GPIO_PTE0,
+
+        /* PTF */
+        GPIO_PTF7, GPIO_PTF6, GPIO_PTF5, GPIO_PTF4,
+        GPIO_PTF3, GPIO_PTF2, GPIO_PTF1, GPIO_PTF0,
+
+        /* PTG */
+                              GPIO_PTG5, GPIO_PTG4,
+        GPIO_PTG3, GPIO_PTG2, GPIO_PTG1, GPIO_PTG0,
+
+        /* PTH */
+        GPIO_PTH7, GPIO_PTH6, GPIO_PTH5, GPIO_PTH4,
+        GPIO_PTH3, GPIO_PTH2, GPIO_PTH1, GPIO_PTH0,
+
+        /* PTJ */
+        GPIO_PTJ7, GPIO_PTJ6, GPIO_PTJ5,
+        GPIO_PTJ3, GPIO_PTJ2, GPIO_PTJ1, GPIO_PTJ0,
+
+        /* PTK */
+        GPIO_PTK7, GPIO_PTK6, GPIO_PTK5, GPIO_PTK4,
+        GPIO_PTK3, GPIO_PTK2, GPIO_PTK1, GPIO_PTK0,
+
+        /* PTL */
+        GPIO_PTL7, GPIO_PTL6, GPIO_PTL5, GPIO_PTL4,
+        GPIO_PTL3, GPIO_PTL2, GPIO_PTL1, GPIO_PTL0,
+
+        /* PTM */
+        GPIO_PTM7, GPIO_PTM6, GPIO_PTM5, GPIO_PTM4,
+        GPIO_PTM3, GPIO_PTM2, GPIO_PTM1, GPIO_PTM0,
+
+        /* PTN */
+        GPIO_PTN7, GPIO_PTN6, GPIO_PTN5, GPIO_PTN4,
+        GPIO_PTN3, GPIO_PTN2, GPIO_PTN1, GPIO_PTN0,
+
+        /* PTQ */
+        GPIO_PTQ7, GPIO_PTQ6, GPIO_PTQ5, GPIO_PTQ4,
+        GPIO_PTQ3, GPIO_PTQ2, GPIO_PTQ1, GPIO_PTQ0,
+
+        /* PTR */
+        GPIO_PTR7, GPIO_PTR6, GPIO_PTR5, GPIO_PTR4,
+        GPIO_PTR3, GPIO_PTR2, GPIO_PTR1, GPIO_PTR0,
+
+        /* PTS */
+                   GPIO_PTS6, GPIO_PTS5, GPIO_PTS4,
+        GPIO_PTS3, GPIO_PTS2, GPIO_PTS1, GPIO_PTS0,
+
+        /* PTT */
+        GPIO_PTT7, GPIO_PTT6, GPIO_PTT5, GPIO_PTT4,
+        GPIO_PTT3, GPIO_PTT2, GPIO_PTT1, GPIO_PTT0,
+
+        /* PTU */
+        GPIO_PTU7, GPIO_PTU6, GPIO_PTU5, GPIO_PTU4,
+        GPIO_PTU3, GPIO_PTU2, GPIO_PTU1, GPIO_PTU0,
+
+        /* PTV */
+        GPIO_PTV7, GPIO_PTV6, GPIO_PTV5, GPIO_PTV4,
+        GPIO_PTV3, GPIO_PTV2, GPIO_PTV1, GPIO_PTV0,
+
+        /* PTW */
+        GPIO_PTW7, GPIO_PTW6, GPIO_PTW5, GPIO_PTW4,
+        GPIO_PTW3, GPIO_PTW2, GPIO_PTW1, GPIO_PTW0,
+
+        /* PTX */
+        GPIO_PTX7, GPIO_PTX6, GPIO_PTX5, GPIO_PTX4,
+        GPIO_PTX3, GPIO_PTX2, GPIO_PTX1, GPIO_PTX0,
+
+        /* PTY */
+        GPIO_PTY7, GPIO_PTY6, GPIO_PTY5, GPIO_PTY4,
+        GPIO_PTY3, GPIO_PTY2, GPIO_PTY1, GPIO_PTY0,
+
+        /* PTZ */
+        GPIO_PTZ7, GPIO_PTZ6, GPIO_PTZ5, GPIO_PTZ4,
+        GPIO_PTZ3, GPIO_PTZ2, GPIO_PTZ1, GPIO_PTZ0,
+
+        /* BSC (PTA/PTB/PTJ/PTQ/PTR/PTT) */
+        GPIO_FN_D31, GPIO_FN_D30, GPIO_FN_D29, GPIO_FN_D28,
+        GPIO_FN_D27, GPIO_FN_D26, GPIO_FN_D25, GPIO_FN_D24,
+        GPIO_FN_D23, GPIO_FN_D22, GPIO_FN_D21, GPIO_FN_D20,
+        GPIO_FN_D19, GPIO_FN_D18, GPIO_FN_D17, GPIO_FN_D16,
+        GPIO_FN_D15, GPIO_FN_D14, GPIO_FN_D13, GPIO_FN_D12,
+        GPIO_FN_D11, GPIO_FN_D10, GPIO_FN_D9,  GPIO_FN_D8,
+        GPIO_FN_D7,  GPIO_FN_D6,  GPIO_FN_D5,  GPIO_FN_D4,
+        GPIO_FN_D3,  GPIO_FN_D2,  GPIO_FN_D1,  GPIO_FN_D0,
+        GPIO_FN_A25, GPIO_FN_A24, GPIO_FN_A23, GPIO_FN_A22,
+        GPIO_FN_CS6B_CE1B,  GPIO_FN_CS6A_CE2B,
+        GPIO_FN_CS5B_CE1A,  GPIO_FN_CS5A_CE2A,
+        GPIO_FN_WE3_ICIOWR, GPIO_FN_WE2_ICIORD,
+        GPIO_FN_IOIS16,     GPIO_FN_WAIT,
+        GPIO_FN_BS,
+
+        /* KEYSC (PTA/PTB)*/
+        GPIO_FN_KEYOUT5_IN5, GPIO_FN_KEYOUT4_IN6, GPIO_FN_KEYIN4,
+        GPIO_FN_KEYIN3,  GPIO_FN_KEYIN2,  GPIO_FN_KEYIN1,  GPIO_FN_KEYIN0,
+        GPIO_FN_KEYOUT3, GPIO_FN_KEYOUT2, GPIO_FN_KEYOUT1, GPIO_FN_KEYOUT0,
+
+        /* ATAPI (PTA/PTB/PTK/PTR/PTS/PTW) */
+        GPIO_FN_IDED15, GPIO_FN_IDED14, GPIO_FN_IDED13, GPIO_FN_IDED12,
+        GPIO_FN_IDED11, GPIO_FN_IDED10, GPIO_FN_IDED9,  GPIO_FN_IDED8,
+        GPIO_FN_IDED7,  GPIO_FN_IDED6,  GPIO_FN_IDED5,  GPIO_FN_IDED4,
+        GPIO_FN_IDED3,  GPIO_FN_IDED2,  GPIO_FN_IDED1,  GPIO_FN_IDED0,
+        GPIO_FN_IDEA2,     GPIO_FN_IDEA1,     GPIO_FN_IDEA0,  GPIO_FN_IDEIOWR,
+        GPIO_FN_IODREQ,    GPIO_FN_IDECS0,    GPIO_FN_IDECS1, GPIO_FN_IDEIORD,
+        GPIO_FN_DIRECTION, GPIO_FN_EXBUF_ENB, GPIO_FN_IDERST, GPIO_FN_IODACK,
+        GPIO_FN_IDEINT,    GPIO_FN_IDEIORDY,
+
+        /* TPU (PTB/PTR/PTS) */
+        GPIO_FN_TPUTO3, GPIO_FN_TPUTO2, GPIO_FN_TPUTO1, GPIO_FN_TPUTO0,
+        GPIO_FN_TPUTI3, GPIO_FN_TPUTI2,
+
+        /* LCDC (PTC/PTD/PTE/PTF/PTM/PTR) */
+        GPIO_FN_LCDD23, GPIO_FN_LCDD22, GPIO_FN_LCDD21, GPIO_FN_LCDD20,
+        GPIO_FN_LCDD19, GPIO_FN_LCDD18, GPIO_FN_LCDD17, GPIO_FN_LCDD16,
+        GPIO_FN_LCDD15, GPIO_FN_LCDD14, GPIO_FN_LCDD13, GPIO_FN_LCDD12,
+        GPIO_FN_LCDD11, GPIO_FN_LCDD10, GPIO_FN_LCDD9,  GPIO_FN_LCDD8,
+        GPIO_FN_LCDD7,  GPIO_FN_LCDD6,  GPIO_FN_LCDD5,  GPIO_FN_LCDD4,
+        GPIO_FN_LCDD3,  GPIO_FN_LCDD2,  GPIO_FN_LCDD1,  GPIO_FN_LCDD0,
+        GPIO_FN_LCDVSYN,  GPIO_FN_LCDDISP,  GPIO_FN_LCDRS,  GPIO_FN_LCDHSYN,
+        GPIO_FN_LCDCS,    GPIO_FN_LCDDON,   GPIO_FN_LCDDCK, GPIO_FN_LCDWR,
+        GPIO_FN_LCDVEPWC, GPIO_FN_LCDVCPWC, GPIO_FN_LCDRD,  GPIO_FN_LCDLCLK,
+
+        /* SCIF0 (PTF/PTM) */
+        GPIO_FN_SCIF0_TXD, GPIO_FN_SCIF0_RXD, GPIO_FN_SCIF0_SCK,
+
+        /* SCIF1 (PTL) */
+        GPIO_FN_SCIF1_SCK, GPIO_FN_SCIF1_RXD, GPIO_FN_SCIF1_TXD,
+
+        /* SCIF2 (PTE/PTF/PTN) with LCDC, VOU */
+        GPIO_FN_SCIF2_L_TXD, GPIO_FN_SCIF2_L_SCK, GPIO_FN_SCIF2_L_RXD,
+        GPIO_FN_SCIF2_V_TXD, GPIO_FN_SCIF2_V_SCK, GPIO_FN_SCIF2_V_RXD,
+
+        /* SCIF3 (PTL/PTN/PTZ) with VOU, IRQ */
+        GPIO_FN_SCIF3_V_SCK, GPIO_FN_SCIF3_V_RXD, GPIO_FN_SCIF3_V_TXD,
+        GPIO_FN_SCIF3_V_CTS, GPIO_FN_SCIF3_V_RTS,
+        GPIO_FN_SCIF3_I_SCK, GPIO_FN_SCIF3_I_RXD, GPIO_FN_SCIF3_I_TXD,
+        GPIO_FN_SCIF3_I_CTS, GPIO_FN_SCIF3_I_RTS,
+
+        /* SCIF4 (PTE) */
+        GPIO_FN_SCIF4_SCK, GPIO_FN_SCIF4_RXD, GPIO_FN_SCIF4_TXD,
+
+        /* SCIF5 (PTS) */
+        GPIO_FN_SCIF5_SCK, GPIO_FN_SCIF5_RXD, GPIO_FN_SCIF5_TXD,
+
+        /* FSI (PTE/PTU/PTV) */
+        GPIO_FN_FSIMCKB,   GPIO_FN_FSIMCKA,    GPIO_FN_FSIOASD,
+        GPIO_FN_FSIIABCK,  GPIO_FN_FSIIALRCK,  GPIO_FN_FSIOABCK,
+        GPIO_FN_FSIOALRCK, GPIO_FN_CLKAUDIOAO, GPIO_FN_FSIIBSD,
+        GPIO_FN_FSIOBSD,   GPIO_FN_FSIIBBCK,   GPIO_FN_FSIIBLRCK,
+        GPIO_FN_FSIOBBCK,  GPIO_FN_FSIOBLRCK,  GPIO_FN_CLKAUDIOBO,
+        GPIO_FN_FSIIASD,
+
+        /* AUD (PTG) */
+        GPIO_FN_AUDCK,   GPIO_FN_AUDSYNC, GPIO_FN_AUDATA3,
+        GPIO_FN_AUDATA2, GPIO_FN_AUDATA1, GPIO_FN_AUDATA0,
+
+        /* VIO (PTS) (common?) */
+        GPIO_FN_VIO_CKO,
+
+        /* VIO0 (PTH/PTK) */
+        GPIO_FN_VIO0_D15, GPIO_FN_VIO0_D14, GPIO_FN_VIO0_D13, GPIO_FN_VIO0_D12,
+        GPIO_FN_VIO0_D11, GPIO_FN_VIO0_D10, GPIO_FN_VIO0_D9,  GPIO_FN_VIO0_D8,
+        GPIO_FN_VIO0_D7,  GPIO_FN_VIO0_D6,  GPIO_FN_VIO0_D5,  GPIO_FN_VIO0_D4,
+        GPIO_FN_VIO0_D3,  GPIO_FN_VIO0_D2,  GPIO_FN_VIO0_D1,  GPIO_FN_VIO0_D0,
+        GPIO_FN_VIO0_VD,  GPIO_FN_VIO0_CLK,
+        GPIO_FN_VIO0_FLD, GPIO_FN_VIO0_HD,
+
+        /* VIO1 (PTK/PTS) */
+        GPIO_FN_VIO1_D7,  GPIO_FN_VIO1_D6, GPIO_FN_VIO1_D5, GPIO_FN_VIO1_D4,
+        GPIO_FN_VIO1_D3,  GPIO_FN_VIO1_D2, GPIO_FN_VIO1_D1, GPIO_FN_VIO1_D0,
+        GPIO_FN_VIO1_FLD, GPIO_FN_VIO1_HD, GPIO_FN_VIO1_VD, GPIO_FN_VIO1_CLK,
+
+        /* Eth  (PTL/PTN/PTX) */
+        GPIO_FN_RMII_RXD0,    GPIO_FN_RMII_RXD1,
+        GPIO_FN_RMII_TXD0,    GPIO_FN_RMII_TXD1,
+        GPIO_FN_RMII_REF_CLK, GPIO_FN_RMII_TX_EN,
+        GPIO_FN_RMII_RX_ER,   GPIO_FN_RMII_CRS_DV,
+        GPIO_FN_LNKSTA,       GPIO_FN_MDIO,
+        GPIO_FN_MDC,
+
+        /* System (PTJ) */
+        GPIO_FN_PDSTATUS, GPIO_FN_STATUS2, GPIO_FN_STATUS0,
+
+        /* VOU (PTL/PTM/PTN*/
+        GPIO_FN_DV_D15,  GPIO_FN_DV_D14, GPIO_FN_DV_D13,   GPIO_FN_DV_D12,
+        GPIO_FN_DV_D11,  GPIO_FN_DV_D10, GPIO_FN_DV_D9,    GPIO_FN_DV_D8,
+        GPIO_FN_DV_D7,   GPIO_FN_DV_D6,  GPIO_FN_DV_D5,    GPIO_FN_DV_D4,
+        GPIO_FN_DV_D3,   GPIO_FN_DV_D2,  GPIO_FN_DV_D1,    GPIO_FN_DV_D0,
+        GPIO_FN_DV_CLKI, GPIO_FN_DV_CLK, GPIO_FN_DV_VSYNC, GPIO_FN_DV_HSYNC,
+
+        /* MSIOF0 (PTL/PTM) */
+        GPIO_FN_MSIOF0_RXD,   GPIO_FN_MSIOF0_TXD,
+        GPIO_FN_MSIOF0_MCK,   GPIO_FN_MSIOF0_TSCK,
+        GPIO_FN_MSIOF0_SS1,   GPIO_FN_MSIOF0_SS2,
+        GPIO_FN_MSIOF0_TSYNC, GPIO_FN_MSIOF0_RSCK,
+        GPIO_FN_MSIOF0_RSYNC,
+
+        /* MSIOF1 (PTV) */
+        GPIO_FN_MSIOF1_RXD,   GPIO_FN_MSIOF1_TXD,
+        GPIO_FN_MSIOF1_MCK,   GPIO_FN_MSIOF1_TSCK,
+        GPIO_FN_MSIOF1_SS1,   GPIO_FN_MSIOF1_SS2,
+        GPIO_FN_MSIOF1_TSYNC, GPIO_FN_MSIOF1_RSCK,
+        GPIO_FN_MSIOF1_RSYNC,
+
+        /* DMAC (PTU/PTX) */
+        GPIO_FN_DMAC_DACK0, GPIO_FN_DMAC_DREQ0,
+        GPIO_FN_DMAC_DACK1, GPIO_FN_DMAC_DREQ1,
+
+        /* SDHI0 (PTY) */
+        GPIO_FN_SDHI0CD, GPIO_FN_SDHI0WP, GPIO_FN_SDHI0CMD, GPIO_FN_SDHI0CLK,
+        GPIO_FN_SDHI0D3, GPIO_FN_SDHI0D2, GPIO_FN_SDHI0D1,  GPIO_FN_SDHI0D0,
+
+        /* SDHI1 (PTW) */
+        GPIO_FN_SDHI1CD, GPIO_FN_SDHI1WP, GPIO_FN_SDHI1CMD, GPIO_FN_SDHI1CLK,
+        GPIO_FN_SDHI1D3, GPIO_FN_SDHI1D2, GPIO_FN_SDHI1D1,  GPIO_FN_SDHI1D0,
+
+        /* MMC (PTW/PTX)*/
+        GPIO_FN_MMC_D7,  GPIO_FN_MMC_D6,  GPIO_FN_MMC_D5, GPIO_FN_MMC_D4,
+        GPIO_FN_MMC_D3,  GPIO_FN_MMC_D2,  GPIO_FN_MMC_D1, GPIO_FN_MMC_D0,
+        GPIO_FN_MMC_CLK, GPIO_FN_MMC_CMD,
+
+        /* IrDA (PTX) */
+        GPIO_FN_IRDA_OUT, GPIO_FN_IRDA_IN,
+
+        /* TSIF (PTX) */
+        GPIO_FN_TSIF_TS0_SDAT, GPIO_FN_TSIF_TS0_SCK,
+        GPIO_FN_TSIF_TS0_SDEN, GPIO_FN_TSIF_TS0_SPSYNC,
+
+        /* IRQ (PTZ) */
+        GPIO_FN_INTC_IRQ7, GPIO_FN_INTC_IRQ6, GPIO_FN_INTC_IRQ5,
+        GPIO_FN_INTC_IRQ4, GPIO_FN_INTC_IRQ3, GPIO_FN_INTC_IRQ2,
+        GPIO_FN_INTC_IRQ1, GPIO_FN_INTC_IRQ0,
+};
+
+#endif /* __ASM_SH7724_H__ */
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7785.h b/arch/sh/include/cpu-sh4/cpu/sh7785.h
index e4006afb735e..9dc9d91e0a8e 100644
--- a/arch/sh/include/cpu-sh4/cpu/sh7785.h
+++ b/arch/sh/include/cpu-sh4/cpu/sh7785.h
@@ -1,6 +1,31 @@
 #ifndef __ASM_SH7785_H__
 #define __ASM_SH7785_H__
 
+/* Boot Mode Pins:
+ *
+ * MODE0: CPG - Initial Pck/Bck Frequency [FRQMR1]
+ * MODE1: CPG - Initial Uck/SHck/DDRck Frequency [FRQMR1]
+ * MODE2: CPG - Reserved (L: Normal operation)
+ * MODE3: CPG - Reserved (L: Normal operation)
+ * MODE4: CPG - Initial PLL setting (72x/36x)
+ * MODE5: LBSC - Area0 Memory Type / Bus Width [CS0BCR.8]
+ * MODE6: LBSC - Area0 Memory Type / Bus Width [CS0BCR.9]
+ * MODE7: LBSC - Area0 Memory Type / Bus Width [CS0BCR.3]
+ * MODE8: LBSC - Endian Mode (L: Big, H: Little) [BCR.31]
+ * MODE9: LBSC - Master/Slave Mode (L: Slave) [BCR.30]
+ * MODE10: CPG - Clock Input (L: Ext Clk, H: Crystal)
+ * MODE11: PCI - Pin Mode (LL: PCI host, LH: PCI slave)
+ * MODE12: PCI - Pin Mode (HL: Local bus, HH: DU)
+ * MODE13: Boot Address Mode (L: 29-bit, H: 32-bit)
+ * MODE14: Reserved (H: Normal operation)
+ *
+ * More information in sh7785 manual Rev.1.00, page 1628.
+ */
+
+/* Pin Function Controller:
+ * GPIO_FN_xx - GPIO used to select pin function
+ * GPIO_Pxx - GPIO mapped to real I/O pin on CPU
+ */
 enum {
         /* PA */
         GPIO_PA7, GPIO_PA6, GPIO_PA5, GPIO_PA4,
diff --git a/arch/sh/include/cpu-sh4/cpu/timer.h b/arch/sh/include/cpu-sh4/cpu/timer.h
deleted file mode 100644
index d1e796b96888..000000000000
--- a/arch/sh/include/cpu-sh4/cpu/timer.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * include/asm-sh/cpu-sh4/timer.h
- *
- * Copyright (C) 2004 Lineo Solutions, Inc.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#ifndef __ASM_CPU_SH4_TIMER_H
-#define __ASM_CPU_SH4_TIMER_H
-
-/*
- * ---------------------------------------------------------------------------
- * TMU Common definitions for SH4 processors
- *      SH7750S/SH7750R
- *      SH7751/SH7751R
- *      SH7760
- *      SH-X3
- * ---------------------------------------------------------------------------
- */
-#ifdef CONFIG_CPU_SUBTYPE_SHX3
-#define TMU_012_BASE    0xffc10000
-#define TMU_345_BASE    0xffc20000
-#else
-#define TMU_012_BASE    0xffd80000
-#define TMU_345_BASE    0xfe100000
-#endif
-
-#define TMU_TOCR        TMU_012_BASE    /* Not supported on all CPUs */
-
-#define TMU_012_TSTR    (TMU_012_BASE + 0x04)
-#define TMU_345_TSTR    (TMU_345_BASE + 0x04)
-
-#define TMU0_TCOR       (TMU_012_BASE + 0x08)
-#define TMU0_TCNT       (TMU_012_BASE + 0x0c)
-#define TMU0_TCR        (TMU_012_BASE + 0x10)
-
-#define TMU1_TCOR       (TMU_012_BASE + 0x14)
-#define TMU1_TCNT       (TMU_012_BASE + 0x18)
-#define TMU1_TCR        (TMU_012_BASE + 0x1c)
-
-#define TMU2_TCOR       (TMU_012_BASE + 0x20)
-#define TMU2_TCNT       (TMU_012_BASE + 0x24)
-#define TMU2_TCR        (TMU_012_BASE + 0x28)
-#define TMU2_TCPR       (TMU_012_BASE + 0x2c)
-
-#define TMU3_TCOR       (TMU_345_BASE + 0x08)
-#define TMU3_TCNT       (TMU_345_BASE + 0x0c)
-#define TMU3_TCR        (TMU_345_BASE + 0x10)
-
-#define TMU4_TCOR       (TMU_345_BASE + 0x14)
-#define TMU4_TCNT       (TMU_345_BASE + 0x18)
-#define TMU4_TCR        (TMU_345_BASE + 0x1c)
-
-#define TMU5_TCOR       (TMU_345_BASE + 0x20)
-#define TMU5_TCNT       (TMU_345_BASE + 0x24)
-#define TMU5_TCR        (TMU_345_BASE + 0x28)
-
-#endif /* __ASM_CPU_SH4_TIMER_H */
diff --git a/arch/sh/include/cpu-sh5/cpu/irq.h b/arch/sh/include/cpu-sh5/cpu/irq.h
index f0f0756e6e84..0ccf257a72d1 100644
--- a/arch/sh/include/cpu-sh5/cpu/irq.h
+++ b/arch/sh/include/cpu-sh5/cpu/irq.h
@@ -111,7 +111,6 @@
 #define TOP_PRIORITY    15
 
 extern int intc_evt_to_irq[(0xE20/0x20)+1];
-int intc_irq_describe(char* p, int irq);
 extern int platform_int_priority[NR_INTC_IRQS];
 
 #endif /* __ASM_SH_CPU_SH5_IRQ_H */
diff --git a/arch/sh/include/mach-common/mach/sh7785lcr.h b/arch/sh/include/mach-common/mach/sh7785lcr.h
index 1ce27d5c7491..90011d435f30 100644
--- a/arch/sh/include/mach-common/mach/sh7785lcr.h
+++ b/arch/sh/include/mach-common/mach/sh7785lcr.h
@@ -9,11 +9,11 @@
  * -----------------------------+---------------+---------------
  * 0x00000000 - 0x03ffffff(CS0) | NOR Flash     | NOR Flash
  * 0x04000000 - 0x05ffffff(CS1) | PLD           | PLD
- * 0x06000000 - 0x07ffffff(CS1) | reserved      | I2C
+ * 0x06000000 - 0x07ffffff(CS1) | I2C           | I2C
  * 0x08000000 - 0x0bffffff(CS2) | USB           | DDR SDRAM
  * 0x0c000000 - 0x0fffffff(CS3) | SD            | DDR SDRAM
  * 0x10000000 - 0x13ffffff(CS4) | SM107         | SM107
- * 0x14000000 - 0x17ffffff(CS5) | I2C           | USB
+ * 0x14000000 - 0x17ffffff(CS5) | reserved      | USB
  * 0x18000000 - 0x1bffffff(CS6) | reserved      | SD
  * 0x40000000 - 0x5fffffff      | DDR SDRAM     | (cannot use)
  *
@@ -32,6 +32,9 @@
 #define PLD_VERSR               (PLD_BASE_ADDR + 0x0c)
 #define PLD_MMSR                (PLD_BASE_ADDR + 0x0e)
 
+#define PCA9564_ADDR            0x06000000      /* I2C */
+#define PCA9564_SIZE            0x00000100
+
 #define SM107_MEM_ADDR          0x10000000
 #define SM107_MEM_SIZE          0x00e00000
 #define SM107_REG_ADDR          0x13e00000
@@ -40,16 +43,13 @@
 #if defined(CONFIG_SH_SH7785LCR_29BIT_PHYSMAPS)
 #define R8A66597_ADDR           0x14000000      /* USB */
 #define CG200_ADDR              0x18000000      /* SD */
-#define PCA9564_ADDR            0x06000000      /* I2C */
 #else
 #define R8A66597_ADDR           0x08000000
 #define CG200_ADDR              0x0c000000
-#define PCA9564_ADDR            0x14000000
 #endif
 
 #define R8A66597_SIZE           0x00000100
 #define CG200_SIZE              0x00010000
-#define PCA9564_SIZE            0x00000100
 
 #endif  /* __ASM_SH_RENESAS_SH7785LCR_H */
 
diff --git a/arch/sh/include/mach-dreamcast/mach/pci.h b/arch/sh/include/mach-dreamcast/mach/pci.h
index 75fc9009e092..0314d975e626 100644
--- a/arch/sh/include/mach-dreamcast/mach/pci.h
+++ b/arch/sh/include/mach-dreamcast/mach/pci.h
@@ -21,5 +21,7 @@
 
 #define GAPSPCI_IRQ             HW_EVENT_EXTERNAL
 
+extern struct pci_ops gapspci_pci_ops;
+
 #endif /* __ASM_SH_DREAMCAST_PCI_H */
 
diff --git a/arch/sh/include/mach-se/mach/se7724.h b/arch/sh/include/mach-se/mach/se7724.h
new file mode 100644
index 000000000000..74164b60d0db
--- /dev/null
+++ b/arch/sh/include/mach-se/mach/se7724.h
@@ -0,0 +1,67 @@
+#ifndef __ASM_SH_SE7724_H
+#define __ASM_SH_SE7724_H
+
+/*
+ * linux/include/asm-sh/se7724.h
+ *
+ * Copyright (C) 2009 Renesas Solutions Corp.
+ *
+ * Kuninori Morimoto <morimoto.kuninori@renesas.com>
+ *
+ * Hitachi UL SolutionEngine 7724 Support.
+ *
+ * Based on se7722.h
+ * Copyright (C) 2007  Nobuhiro Iwamatsu
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+#include <asm/addrspace.h>
+
+#define PA_LED          (0xba203000)    /* 8bit LED */
+#define IRQ_MODE        (0xba200010)
+#define IRQ0_SR         (0xba200014)
+#define IRQ1_SR         (0xba200018)
+#define IRQ2_SR         (0xba20001c)
+#define IRQ0_MR         (0xba200020)
+#define IRQ1_MR         (0xba200024)
+#define IRQ2_MR         (0xba200028)
+
+/* IRQ */
+#define IRQ0_IRQ        32
+#define IRQ1_IRQ        33
+#define IRQ2_IRQ        34
+
+/* Bits in IRQ012 registers */
+#define SE7724_FPGA_IRQ_BASE    220
+
+/* IRQ0 */
+#define IRQ0_BASE       SE7724_FPGA_IRQ_BASE
+#define IRQ0_KEY        (IRQ0_BASE + 12)
+#define IRQ0_RMII       (IRQ0_BASE + 13)
+#define IRQ0_SMC        (IRQ0_BASE + 14)
+#define IRQ0_MASK       0x7fff
+#define IRQ0_END        IRQ0_SMC
+/* IRQ1 */
+#define IRQ1_BASE       (IRQ0_END + 1)
+#define IRQ1_TS         (IRQ1_BASE + 0)
+#define IRQ1_MASK       0x0001
+#define IRQ1_END        IRQ1_TS
+/* IRQ2 */
+#define IRQ2_BASE       (IRQ1_END + 1)
+#define IRQ2_USB0       (IRQ1_BASE + 0)
+#define IRQ2_USB1       (IRQ1_BASE + 1)
+#define IRQ2_MASK       0x0003
+#define IRQ2_END        IRQ2_USB1
+
+#define SE7724_FPGA_IRQ_NR      (IRQ2_END - IRQ0_BASE)
+
+/* arch/sh/boards/se/7724/irq.c */
+void init_se7724_IRQ(void);
+
+#define __IO_PREFIX             se7724
+#include <asm/io_generic.h>
+
+#endif  /* __ASM_SH_SE7724_H */