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authorDavid S. Miller <davem@davemloft.net>2009-06-15 06:02:23 -0400
committerDavid S. Miller <davem@davemloft.net>2009-06-15 06:02:23 -0400
commit9cbc1cb8cd46ce1f7645b9de249b2ce8460129bb (patch)
tree8d104ec2a459346b99413b0b77421ca7b9936c1a /arch/sh/include/mach-common/mach/sh7785lcr.h
parentca44d6e60f9de26281fda203f58b570e1748c015 (diff)
parent45e3e1935e2857c54783291107d33323b3ef33c8 (diff)
Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/torvalds/linux-2.6
Conflicts: Documentation/feature-removal-schedule.txt drivers/scsi/fcoe/fcoe.c net/core/drop_monitor.c net/core/net-traces.c
Diffstat (limited to 'arch/sh/include/mach-common/mach/sh7785lcr.h')
-rw-r--r--arch/sh/include/mach-common/mach/sh7785lcr.h10
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/sh/include/mach-common/mach/sh7785lcr.h b/arch/sh/include/mach-common/mach/sh7785lcr.h
index 1ce27d5c7491..90011d435f30 100644
--- a/arch/sh/include/mach-common/mach/sh7785lcr.h
+++ b/arch/sh/include/mach-common/mach/sh7785lcr.h
@@ -9,11 +9,11 @@
9 * -----------------------------+---------------+--------------- 9 * -----------------------------+---------------+---------------
10 * 0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash 10 * 0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash
11 * 0x04000000 - 0x05ffffff(CS1) | PLD | PLD 11 * 0x04000000 - 0x05ffffff(CS1) | PLD | PLD
12 * 0x06000000 - 0x07ffffff(CS1) | reserved | I2C 12 * 0x06000000 - 0x07ffffff(CS1) | I2C | I2C
13 * 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM 13 * 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM
14 * 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM 14 * 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM
15 * 0x10000000 - 0x13ffffff(CS4) | SM107 | SM107 15 * 0x10000000 - 0x13ffffff(CS4) | SM107 | SM107
16 * 0x14000000 - 0x17ffffff(CS5) | I2C | USB 16 * 0x14000000 - 0x17ffffff(CS5) | reserved | USB
17 * 0x18000000 - 0x1bffffff(CS6) | reserved | SD 17 * 0x18000000 - 0x1bffffff(CS6) | reserved | SD
18 * 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use) 18 * 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use)
19 * 19 *
@@ -32,6 +32,9 @@
32#define PLD_VERSR (PLD_BASE_ADDR + 0x0c) 32#define PLD_VERSR (PLD_BASE_ADDR + 0x0c)
33#define PLD_MMSR (PLD_BASE_ADDR + 0x0e) 33#define PLD_MMSR (PLD_BASE_ADDR + 0x0e)
34 34
35#define PCA9564_ADDR 0x06000000 /* I2C */
36#define PCA9564_SIZE 0x00000100
37
35#define SM107_MEM_ADDR 0x10000000 38#define SM107_MEM_ADDR 0x10000000
36#define SM107_MEM_SIZE 0x00e00000 39#define SM107_MEM_SIZE 0x00e00000
37#define SM107_REG_ADDR 0x13e00000 40#define SM107_REG_ADDR 0x13e00000
@@ -40,16 +43,13 @@
40#if defined(CONFIG_SH_SH7785LCR_29BIT_PHYSMAPS) 43#if defined(CONFIG_SH_SH7785LCR_29BIT_PHYSMAPS)
41#define R8A66597_ADDR 0x14000000 /* USB */ 44#define R8A66597_ADDR 0x14000000 /* USB */
42#define CG200_ADDR 0x18000000 /* SD */ 45#define CG200_ADDR 0x18000000 /* SD */
43#define PCA9564_ADDR 0x06000000 /* I2C */
44#else 46#else
45#define R8A66597_ADDR 0x08000000 47#define R8A66597_ADDR 0x08000000
46#define CG200_ADDR 0x0c000000 48#define CG200_ADDR 0x0c000000
47#define PCA9564_ADDR 0x14000000
48#endif 49#endif
49 50
50#define R8A66597_SIZE 0x00000100 51#define R8A66597_SIZE 0x00000100
51#define CG200_SIZE 0x00010000 52#define CG200_SIZE 0x00010000
52#define PCA9564_SIZE 0x00000100
53 53
54#endif /* __ASM_SH_RENESAS_SH7785LCR_H */ 54#endif /* __ASM_SH_RENESAS_SH7785LCR_H */
55 55