sh: migrate to arch/sh/include/

This follows the sparc changes a439fe51a1f8eb087c22dd24d69cebae4a3addac.

Most of the moving about was done with Sam's directions at:

http://marc.info/?l=linux-sh&m=121724823706062&w=2

with subsequent hacking and fixups entirely my fault.

Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

9 files changed, 403 insertions, 0 deletions

diff --git a/arch/sh/include/cpu-sh5/cpu/addrspace.h b/arch/sh/include/cpu-sh5/cpu/addrspace.h
new file mode 100644
index 000000000000..dc36b9a03af6
--- /dev/null
+++ b/arch/sh/include/cpu-sh5/cpu/addrspace.h
@@ -0,0 +1,11 @@
+#ifndef __ASM_SH_CPU_SH5_ADDRSPACE_H
+#define __ASM_SH_CPU_SH5_ADDRSPACE_H
+
+#define PHYS_PERIPHERAL_BLOCK   0x09000000
+#define PHYS_DMAC_BLOCK         0x0e000000
+#define PHYS_PCI_BLOCK          0x60000000
+#define PHYS_EMI_BLOCK          0xff000000
+
+/* No segmentation.. */
+
+#endif /* __ASM_SH_CPU_SH5_ADDRSPACE_H */
diff --git a/arch/sh/include/cpu-sh5/cpu/cache.h b/arch/sh/include/cpu-sh5/cpu/cache.h
new file mode 100644
index 000000000000..ed050ab526f2
--- /dev/null
+++ b/arch/sh/include/cpu-sh5/cpu/cache.h
@@ -0,0 +1,97 @@
+#ifndef __ASM_SH_CPU_SH5_CACHE_H
+#define __ASM_SH_CPU_SH5_CACHE_H
+
+/*
+ * include/asm-sh/cpu-sh5/cache.h
+ *
+ * Copyright (C) 2000, 2001  Paolo Alberelli
+ * Copyright (C) 2003, 2004  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#define L1_CACHE_SHIFT          5
+
+/* Valid and Dirty bits */
+#define SH_CACHE_VALID          (1LL<<0)
+#define SH_CACHE_UPDATED        (1LL<<57)
+
+/* Unimplemented compat bits.. */
+#define SH_CACHE_COMBINED       0
+#define SH_CACHE_ASSOC          0
+
+/* Cache flags */
+#define SH_CACHE_MODE_WT        (1LL<<0)
+#define SH_CACHE_MODE_WB        (1LL<<1)
+
+/*
+ * Control Registers.
+ */
+#define ICCR_BASE       0x01600000      /* Instruction Cache Control Register */
+#define ICCR_REG0       0               /* Register 0 offset */
+#define ICCR_REG1       1               /* Register 1 offset */
+#define ICCR0           ICCR_BASE+ICCR_REG0
+#define ICCR1           ICCR_BASE+ICCR_REG1
+
+#define ICCR0_OFF       0x0             /* Set ICACHE off */
+#define ICCR0_ON        0x1             /* Set ICACHE on */
+#define ICCR0_ICI       0x2             /* Invalidate all in IC */
+
+#define ICCR1_NOLOCK    0x0             /* Set No Locking */
+
+#define OCCR_BASE       0x01E00000      /* Operand Cache Control Register */
+#define OCCR_REG0       0               /* Register 0 offset */
+#define OCCR_REG1       1               /* Register 1 offset */
+#define OCCR0           OCCR_BASE+OCCR_REG0
+#define OCCR1           OCCR_BASE+OCCR_REG1
+
+#define OCCR0_OFF       0x0             /* Set OCACHE off */
+#define OCCR0_ON        0x1             /* Set OCACHE on */
+#define OCCR0_OCI       0x2             /* Invalidate all in OC */
+#define OCCR0_WT        0x4             /* Set OCACHE in WT Mode */
+#define OCCR0_WB        0x0             /* Set OCACHE in WB Mode */
+
+#define OCCR1_NOLOCK    0x0             /* Set No Locking */
+
+/*
+ * SH-5
+ * A bit of description here, for neff=32.
+ *
+ *                               |<--- tag  (19 bits) --->|
+ * +-----------------------------+-----------------+------+----------+------+
+ * |                             |                 | ways |set index |offset|
+ * +-----------------------------+-----------------+------+----------+------+
+ *                                ^                 2 bits   8 bits   5 bits
+ *                                +- Bit 31
+ *
+ * Cacheline size is based on offset: 5 bits = 32 bytes per line
+ * A cache line is identified by a tag + set but OCACHETAG/ICACHETAG
+ * have a broader space for registers. These are outlined by
+ * CACHE_?C_*_STEP below.
+ *
+ */
+
+/* Instruction cache */
+#define CACHE_IC_ADDRESS_ARRAY 0x01000000
+
+/* Operand Cache */
+#define CACHE_OC_ADDRESS_ARRAY 0x01800000
+
+/* These declarations relate to cache 'synonyms' in the operand cache.  A
+   'synonym' occurs where effective address bits overlap between those used for
+   indexing the cache sets and those passed to the MMU for translation.  In the
+   case of SH5-101 & SH5-103, only bit 12 is affected for 4k pages. */
+
+#define CACHE_OC_N_SYNBITS  1               /* Number of synonym bits */
+#define CACHE_OC_SYN_SHIFT  12
+/* Mask to select synonym bit(s) */
+#define CACHE_OC_SYN_MASK   (((1UL<<CACHE_OC_N_SYNBITS)-1)<<CACHE_OC_SYN_SHIFT)
+
+/*
+ * Instruction cache can't be invalidated based on physical addresses.
+ * No Instruction Cache defines required, then.
+ */
+
+#endif /* __ASM_SH_CPU_SH5_CACHE_H */
diff --git a/arch/sh/include/cpu-sh5/cpu/cacheflush.h b/arch/sh/include/cpu-sh5/cpu/cacheflush.h
new file mode 100644
index 000000000000..5a11f0b7e66a
--- /dev/null
+++ b/arch/sh/include/cpu-sh5/cpu/cacheflush.h
@@ -0,0 +1,33 @@
+#ifndef __ASM_SH_CPU_SH5_CACHEFLUSH_H
+#define __ASM_SH_CPU_SH5_CACHEFLUSH_H
+
+#ifndef __ASSEMBLY__
+
+struct vm_area_struct;
+struct page;
+struct mm_struct;
+
+extern void flush_cache_all(void);
+extern void flush_cache_mm(struct mm_struct *mm);
+extern void flush_cache_sigtramp(unsigned long vaddr);
+extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
+                              unsigned long end);
+extern void flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn);
+extern void flush_dcache_page(struct page *pg);
+extern void flush_icache_range(unsigned long start, unsigned long end);
+extern void flush_icache_user_range(struct vm_area_struct *vma,
+                                    struct page *page, unsigned long addr,
+                                    int len);
+
+#define flush_cache_dup_mm(mm)  flush_cache_mm(mm)
+
+#define flush_dcache_mmap_lock(mapping)         do { } while (0)
+#define flush_dcache_mmap_unlock(mapping)       do { } while (0)
+
+#define flush_icache_page(vma, page)    do { } while (0)
+void p3_cache_init(void);
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_SH_CPU_SH5_CACHEFLUSH_H */
+
diff --git a/arch/sh/include/cpu-sh5/cpu/dma.h b/arch/sh/include/cpu-sh5/cpu/dma.h
new file mode 100644
index 000000000000..7bf6bb3d35ed
--- /dev/null
+++ b/arch/sh/include/cpu-sh5/cpu/dma.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_SH_CPU_SH5_DMA_H
+#define __ASM_SH_CPU_SH5_DMA_H
+
+/* Nothing yet */
+
+#endif /* __ASM_SH_CPU_SH5_DMA_H */
diff --git a/arch/sh/include/cpu-sh5/cpu/irq.h b/arch/sh/include/cpu-sh5/cpu/irq.h
new file mode 100644
index 000000000000..f0f0756e6e84
--- /dev/null
+++ b/arch/sh/include/cpu-sh5/cpu/irq.h
@@ -0,0 +1,117 @@
+#ifndef __ASM_SH_CPU_SH5_IRQ_H
+#define __ASM_SH_CPU_SH5_IRQ_H
+
+/*
+ * include/asm-sh/cpu-sh5/irq.h
+ *
+ * Copyright (C) 2000, 2001  Paolo Alberelli
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+
+/*
+ * Encoded IRQs are not considered worth to be supported.
+ * Main reason is that there's no per-encoded-interrupt
+ * enable/disable mechanism (as there was in SH3/4).
+ * An all enabled/all disabled is worth only if there's
+ * a cascaded IC to disable/enable/ack on. Until such
+ * IC is available there's no such support.
+ *
+ * Presumably Encoded IRQs may use extra IRQs beyond 64,
+ * below. Some logic must be added to cope with IRQ_IRL?
+ * in an exclusive way.
+ *
+ * Priorities are set at Platform level, when IRQ_IRL0-3
+ * are set to 0 Encoding is allowed. Otherwise it's not
+ * allowed.
+ */
+
+/* Independent IRQs */
+#define IRQ_IRL0        0
+#define IRQ_IRL1        1
+#define IRQ_IRL2        2
+#define IRQ_IRL3        3
+
+#define IRQ_INTA        4
+#define IRQ_INTB        5
+#define IRQ_INTC        6
+#define IRQ_INTD        7
+
+#define IRQ_SERR        12
+#define IRQ_ERR         13
+#define IRQ_PWR3        14
+#define IRQ_PWR2        15
+#define IRQ_PWR1        16
+#define IRQ_PWR0        17
+
+#define IRQ_DMTE0       18
+#define IRQ_DMTE1       19
+#define IRQ_DMTE2       20
+#define IRQ_DMTE3       21
+#define IRQ_DAERR       22
+
+#define IRQ_TUNI0       32
+#define IRQ_TUNI1       33
+#define IRQ_TUNI2       34
+#define IRQ_TICPI2      35
+
+#define IRQ_ATI         36
+#define IRQ_PRI         37
+#define IRQ_CUI         38
+
+#define IRQ_ERI         39
+#define IRQ_RXI         40
+#define IRQ_BRI         41
+#define IRQ_TXI         42
+
+#define IRQ_ITI         63
+
+#define NR_INTC_IRQS    64
+
+#ifdef CONFIG_SH_CAYMAN
+#define NR_EXT_IRQS     32
+#define START_EXT_IRQS  64
+
+/* PCI bus 2 uses encoded external interrupts on the Cayman board */
+#define IRQ_P2INTA      (START_EXT_IRQS + (3*8) + 0)
+#define IRQ_P2INTB      (START_EXT_IRQS + (3*8) + 1)
+#define IRQ_P2INTC      (START_EXT_IRQS + (3*8) + 2)
+#define IRQ_P2INTD      (START_EXT_IRQS + (3*8) + 3)
+
+#define I8042_KBD_IRQ   (START_EXT_IRQS + 2)
+#define I8042_AUX_IRQ   (START_EXT_IRQS + 6)
+
+#define IRQ_CFCARD      (START_EXT_IRQS + 7)
+#define IRQ_PCMCIA      (0)
+
+#else
+#define NR_EXT_IRQS     0
+#endif
+
+/* Default IRQs, fixed */
+#define TIMER_IRQ       IRQ_TUNI0
+#define RTC_IRQ         IRQ_CUI
+
+/* Default Priorities, Platform may choose differently */
+#define NO_PRIORITY     0       /* Disabled */
+#define TIMER_PRIORITY  2
+#define RTC_PRIORITY    TIMER_PRIORITY
+#define SCIF_PRIORITY   3
+#define INTD_PRIORITY   3
+#define IRL3_PRIORITY   4
+#define INTC_PRIORITY   6
+#define IRL2_PRIORITY   7
+#define INTB_PRIORITY   9
+#define IRL1_PRIORITY   10
+#define INTA_PRIORITY   12
+#define IRL0_PRIORITY   13
+#define TOP_PRIORITY    15
+
+extern int intc_evt_to_irq[(0xE20/0x20)+1];
+int intc_irq_describe(char* p, int irq);
+extern int platform_int_priority[NR_INTC_IRQS];
+
+#endif /* __ASM_SH_CPU_SH5_IRQ_H */
diff --git a/arch/sh/include/cpu-sh5/cpu/mmu_context.h b/arch/sh/include/cpu-sh5/cpu/mmu_context.h
new file mode 100644
index 000000000000..68a1d2cff457
--- /dev/null
+++ b/arch/sh/include/cpu-sh5/cpu/mmu_context.h
@@ -0,0 +1,21 @@
+#ifndef __ASM_SH_CPU_SH5_MMU_CONTEXT_H
+#define __ASM_SH_CPU_SH5_MMU_CONTEXT_H
+
+/* Common defines */
+#define TLB_STEP        0x00000010
+#define TLB_PTEH        0x00000000
+#define TLB_PTEL        0x00000008
+
+/* PTEH defines */
+#define PTEH_ASID_SHIFT 2
+#define PTEH_VALID      0x0000000000000001
+#define PTEH_SHARED     0x0000000000000002
+#define PTEH_MATCH_ASID 0x00000000000003ff
+
+#ifndef __ASSEMBLY__
+/* This has to be a common function because the next location to fill
+ * information is shared. */
+extern void __do_tlb_refill(unsigned long address, unsigned long long is_text_not_data, pte_t *pte);
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_SH_CPU_SH5_MMU_CONTEXT_H */
diff --git a/arch/sh/include/cpu-sh5/cpu/registers.h b/arch/sh/include/cpu-sh5/cpu/registers.h
new file mode 100644
index 000000000000..6664ea6f1566
--- /dev/null
+++ b/arch/sh/include/cpu-sh5/cpu/registers.h
@@ -0,0 +1,106 @@
+#ifndef __ASM_SH_CPU_SH5_REGISTERS_H
+#define __ASM_SH_CPU_SH5_REGISTERS_H
+
+/*
+ * include/asm-sh/cpu-sh5/registers.h
+ *
+ * Copyright (C) 2000, 2001  Paolo Alberelli
+ * Copyright (C) 2004  Richard Curnow
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifdef __ASSEMBLY__
+/* =====================================================================
+**
+** Section 1: acts on assembly sources pre-processed by GPP ( <source.S>).
+**            Assigns symbolic names to control & target registers.
+*/
+
+/*
+ * Define some useful aliases for control registers.
+ */
+#define SR      cr0
+#define SSR     cr1
+#define PSSR    cr2
+                        /* cr3 UNDEFINED */
+#define INTEVT  cr4
+#define EXPEVT  cr5
+#define PEXPEVT cr6
+#define TRA     cr7
+#define SPC     cr8
+#define PSPC    cr9
+#define RESVEC  cr10
+#define VBR     cr11
+                        /* cr12 UNDEFINED */
+#define TEA     cr13
+                        /* cr14-cr15 UNDEFINED */
+#define DCR     cr16
+#define KCR0    cr17
+#define KCR1    cr18
+                        /* cr19-cr31 UNDEFINED */
+                        /* cr32-cr61 RESERVED */
+#define CTC     cr62
+#define USR     cr63
+
+/*
+ * ABI dependent registers (general purpose set)
+ */
+#define RET     r2
+#define ARG1    r2
+#define ARG2    r3
+#define ARG3    r4
+#define ARG4    r5
+#define ARG5    r6
+#define ARG6    r7
+#define SP      r15
+#define LINK    r18
+#define ZERO    r63
+
+/*
+ * Status register defines: used only by assembly sources (and
+ *                          syntax independednt)
+ */
+#define SR_RESET_VAL    0x0000000050008000
+#define SR_HARMLESS     0x00000000500080f0      /* Write ignores for most */
+#define SR_ENABLE_FPU   0xffffffffffff7fff      /* AND with this */
+
+#if defined (CONFIG_SH64_SR_WATCH)
+#define SR_ENABLE_MMU   0x0000000084000000      /* OR with this */
+#else
+#define SR_ENABLE_MMU   0x0000000080000000      /* OR with this */
+#endif
+
+#define SR_UNBLOCK_EXC  0xffffffffefffffff      /* AND with this */
+#define SR_BLOCK_EXC    0x0000000010000000      /* OR with this */
+
+#else   /* Not __ASSEMBLY__ syntax */
+
+/*
+** Stringify reg. name
+*/
+#define __str(x)  #x
+
+/* Stringify control register names for use in inline assembly */
+#define __SR __str(SR)
+#define __SSR __str(SSR)
+#define __PSSR __str(PSSR)
+#define __INTEVT __str(INTEVT)
+#define __EXPEVT __str(EXPEVT)
+#define __PEXPEVT __str(PEXPEVT)
+#define __TRA __str(TRA)
+#define __SPC __str(SPC)
+#define __PSPC __str(PSPC)
+#define __RESVEC __str(RESVEC)
+#define __VBR __str(VBR)
+#define __TEA __str(TEA)
+#define __DCR __str(DCR)
+#define __KCR0 __str(KCR0)
+#define __KCR1 __str(KCR1)
+#define __CTC __str(CTC)
+#define __USR __str(USR)
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_SH_CPU_SH5_REGISTERS_H */
diff --git a/arch/sh/include/cpu-sh5/cpu/rtc.h b/arch/sh/include/cpu-sh5/cpu/rtc.h
new file mode 100644
index 000000000000..12ea0ed144e1
--- /dev/null
+++ b/arch/sh/include/cpu-sh5/cpu/rtc.h
@@ -0,0 +1,8 @@
+#ifndef __ASM_SH_CPU_SH5_RTC_H
+#define __ASM_SH_CPU_SH5_RTC_H
+
+#define rtc_reg_size            sizeof(u32)
+#define RTC_BIT_INVERTED        0       /* The SH-5 RTC is surprisingly sane! */
+#define RTC_DEF_CAPABILITIES    RTC_CAP_4_DIGIT_YEAR
+
+#endif /* __ASM_SH_CPU_SH5_RTC_H */
diff --git a/arch/sh/include/cpu-sh5/cpu/timer.h b/arch/sh/include/cpu-sh5/cpu/timer.h
new file mode 100644
index 000000000000..88da9b341a36
--- /dev/null
+++ b/arch/sh/include/cpu-sh5/cpu/timer.h
@@ -0,0 +1,4 @@
+#ifndef __ASM_SH_CPU_SH5_TIMER_H
+#define __ASM_SH_CPU_SH5_TIMER_H
+
+#endif /* __ASM_SH_CPU_SH5_TIMER_H */