diff options
| author | Guennadi Liakhovetski <g.liakhovetski@gmx.de> | 2010-02-03 09:46:41 -0500 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2010-02-07 19:40:26 -0500 |
| commit | cfefe99795251d76d92e8457f4152f532a961ec5 (patch) | |
| tree | 531a4677401afb0e9816441ac1366dfa46f5ca7b /arch/sh/include/cpu-sh4 | |
| parent | 623b4ac4bf9e767991c66e29b47dd4b19458fb42 (diff) | |
sh: implement DMA_SLAVE capability in SH dmaengine driver
Tested to work with a SIU ASoC driver on sh7722 (migor).
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Acked-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/include/cpu-sh4')
| -rw-r--r-- | arch/sh/include/cpu-sh4/cpu/dma-sh4a.h | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h b/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h index cc1cf3e8f163..e734ea47d8a0 100644 --- a/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h +++ b/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h | |||
| @@ -7,7 +7,7 @@ | |||
| 7 | #define DMTE4_IRQ 76 | 7 | #define DMTE4_IRQ 76 |
| 8 | #define DMAE0_IRQ 78 /* DMA Error IRQ*/ | 8 | #define DMAE0_IRQ 78 /* DMA Error IRQ*/ |
| 9 | #define SH_DMAC_BASE0 0xFE008020 | 9 | #define SH_DMAC_BASE0 0xFE008020 |
| 10 | #define SH_DMARS_BASE 0xFE009000 | 10 | #define SH_DMARS_BASE0 0xFE009000 |
| 11 | #define CHCR_TS_LOW_MASK 0x00000018 | 11 | #define CHCR_TS_LOW_MASK 0x00000018 |
| 12 | #define CHCR_TS_LOW_SHIFT 3 | 12 | #define CHCR_TS_LOW_SHIFT 3 |
| 13 | #define CHCR_TS_HIGH_MASK 0 | 13 | #define CHCR_TS_HIGH_MASK 0 |
| @@ -17,7 +17,7 @@ | |||
| 17 | #define DMTE4_IRQ 76 | 17 | #define DMTE4_IRQ 76 |
| 18 | #define DMAE0_IRQ 78 /* DMA Error IRQ*/ | 18 | #define DMAE0_IRQ 78 /* DMA Error IRQ*/ |
| 19 | #define SH_DMAC_BASE0 0xFE008020 | 19 | #define SH_DMAC_BASE0 0xFE008020 |
| 20 | #define SH_DMARS_BASE 0xFE009000 | 20 | #define SH_DMARS_BASE0 0xFE009000 |
| 21 | #define CHCR_TS_LOW_MASK 0x00000018 | 21 | #define CHCR_TS_LOW_MASK 0x00000018 |
| 22 | #define CHCR_TS_LOW_SHIFT 3 | 22 | #define CHCR_TS_LOW_SHIFT 3 |
| 23 | #define CHCR_TS_HIGH_MASK 0x00300000 | 23 | #define CHCR_TS_HIGH_MASK 0x00300000 |
| @@ -28,7 +28,7 @@ | |||
| 28 | #define DMTE4_IRQ 44 | 28 | #define DMTE4_IRQ 44 |
| 29 | #define DMAE0_IRQ 38 | 29 | #define DMAE0_IRQ 38 |
| 30 | #define SH_DMAC_BASE0 0xFF608020 | 30 | #define SH_DMAC_BASE0 0xFF608020 |
| 31 | #define SH_DMARS_BASE 0xFF609000 | 31 | #define SH_DMARS_BASE0 0xFF609000 |
| 32 | #define CHCR_TS_LOW_MASK 0x00000018 | 32 | #define CHCR_TS_LOW_MASK 0x00000018 |
| 33 | #define CHCR_TS_LOW_SHIFT 3 | 33 | #define CHCR_TS_LOW_SHIFT 3 |
| 34 | #define CHCR_TS_HIGH_MASK 0 | 34 | #define CHCR_TS_HIGH_MASK 0 |
| @@ -45,7 +45,7 @@ | |||
| 45 | #define DMAE1_IRQ 74 /* DMA Error IRQ*/ | 45 | #define DMAE1_IRQ 74 /* DMA Error IRQ*/ |
| 46 | #define SH_DMAC_BASE0 0xFE008020 | 46 | #define SH_DMAC_BASE0 0xFE008020 |
| 47 | #define SH_DMAC_BASE1 0xFDC08020 | 47 | #define SH_DMAC_BASE1 0xFDC08020 |
| 48 | #define SH_DMARS_BASE 0xFDC09000 | 48 | #define SH_DMARS_BASE0 0xFDC09000 |
| 49 | #define CHCR_TS_LOW_MASK 0x00000018 | 49 | #define CHCR_TS_LOW_MASK 0x00000018 |
| 50 | #define CHCR_TS_LOW_SHIFT 3 | 50 | #define CHCR_TS_LOW_SHIFT 3 |
| 51 | #define CHCR_TS_HIGH_MASK 0 | 51 | #define CHCR_TS_HIGH_MASK 0 |
| @@ -62,7 +62,8 @@ | |||
| 62 | #define DMAE1_IRQ 74 /* DMA Error IRQ*/ | 62 | #define DMAE1_IRQ 74 /* DMA Error IRQ*/ |
| 63 | #define SH_DMAC_BASE0 0xFE008020 | 63 | #define SH_DMAC_BASE0 0xFE008020 |
| 64 | #define SH_DMAC_BASE1 0xFDC08020 | 64 | #define SH_DMAC_BASE1 0xFDC08020 |
| 65 | #define SH_DMARS_BASE 0xFDC09000 | 65 | #define SH_DMARS_BASE0 0xFE009000 |
| 66 | #define SH_DMARS_BASE1 0xFDC09000 | ||
| 66 | #define CHCR_TS_LOW_MASK 0x00000018 | 67 | #define CHCR_TS_LOW_MASK 0x00000018 |
| 67 | #define CHCR_TS_LOW_SHIFT 3 | 68 | #define CHCR_TS_LOW_SHIFT 3 |
| 68 | #define CHCR_TS_HIGH_MASK 0x00600000 | 69 | #define CHCR_TS_HIGH_MASK 0x00600000 |
| @@ -78,7 +79,7 @@ | |||
| 78 | #define DMAE0_IRQ 38 /* DMA Error IRQ */ | 79 | #define DMAE0_IRQ 38 /* DMA Error IRQ */ |
| 79 | #define SH_DMAC_BASE0 0xFC808020 | 80 | #define SH_DMAC_BASE0 0xFC808020 |
| 80 | #define SH_DMAC_BASE1 0xFC818020 | 81 | #define SH_DMAC_BASE1 0xFC818020 |
| 81 | #define SH_DMARS_BASE 0xFC809000 | 82 | #define SH_DMARS_BASE0 0xFC809000 |
| 82 | #define CHCR_TS_LOW_MASK 0x00000018 | 83 | #define CHCR_TS_LOW_MASK 0x00000018 |
| 83 | #define CHCR_TS_LOW_SHIFT 3 | 84 | #define CHCR_TS_LOW_SHIFT 3 |
| 84 | #define CHCR_TS_HIGH_MASK 0 | 85 | #define CHCR_TS_HIGH_MASK 0 |
| @@ -95,7 +96,7 @@ | |||
| 95 | #define DMAE1_IRQ 58 /* DMA Error IRQ1 */ | 96 | #define DMAE1_IRQ 58 /* DMA Error IRQ1 */ |
| 96 | #define SH_DMAC_BASE0 0xFC808020 | 97 | #define SH_DMAC_BASE0 0xFC808020 |
| 97 | #define SH_DMAC_BASE1 0xFCC08020 | 98 | #define SH_DMAC_BASE1 0xFCC08020 |
| 98 | #define SH_DMARS_BASE 0xFC809000 | 99 | #define SH_DMARS_BASE0 0xFC809000 |
| 99 | #define CHCR_TS_LOW_MASK 0x00000018 | 100 | #define CHCR_TS_LOW_MASK 0x00000018 |
| 100 | #define CHCR_TS_LOW_SHIFT 3 | 101 | #define CHCR_TS_LOW_SHIFT 3 |
| 101 | #define CHCR_TS_HIGH_MASK 0 | 102 | #define CHCR_TS_HIGH_MASK 0 |