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authorAndrea Bastoni <bastoni@cs.unc.edu>2010-05-30 19:16:45 -0400
committerAndrea Bastoni <bastoni@cs.unc.edu>2010-05-30 19:16:45 -0400
commitada47b5fe13d89735805b566185f4885f5a3f750 (patch)
tree644b88f8a71896307d71438e9b3af49126ffb22b /arch/sh/include/cpu-sh4/cpu
parent43e98717ad40a4ae64545b5ba047c7b86aa44f4f (diff)
parent3280f21d43ee541f97f8cda5792150d2dbec20d5 (diff)
Merge branch 'wip-2.6.34' into old-private-masterarchived-private-master
Diffstat (limited to 'arch/sh/include/cpu-sh4/cpu')
-rw-r--r--arch/sh/include/cpu-sh4/cpu/addrspace.h9
-rw-r--r--arch/sh/include/cpu-sh4/cpu/dma-register.h112
-rw-r--r--arch/sh/include/cpu-sh4/cpu/dma-sh4a.h80
-rw-r--r--arch/sh/include/cpu-sh4/cpu/dma.h33
-rw-r--r--arch/sh/include/cpu-sh4/cpu/mmu_context.h8
-rw-r--r--arch/sh/include/cpu-sh4/cpu/sq.h3
-rw-r--r--arch/sh/include/cpu-sh4/cpu/ubc.h64
-rw-r--r--arch/sh/include/cpu-sh4/cpu/watchdog.h19
8 files changed, 185 insertions, 143 deletions
diff --git a/arch/sh/include/cpu-sh4/cpu/addrspace.h b/arch/sh/include/cpu-sh4/cpu/addrspace.h
index a3fa733c1c7d..d51da25da72c 100644
--- a/arch/sh/include/cpu-sh4/cpu/addrspace.h
+++ b/arch/sh/include/cpu-sh4/cpu/addrspace.h
@@ -28,6 +28,15 @@
28#define P4SEG_TLB_DATA 0xf7000000 28#define P4SEG_TLB_DATA 0xf7000000
29#define P4SEG_REG_BASE 0xff000000 29#define P4SEG_REG_BASE 0xff000000
30 30
31#define PA_AREA0 0x00000000
32#define PA_AREA1 0x04000000
33#define PA_AREA2 0x08000000
34#define PA_AREA3 0x0c000000
35#define PA_AREA4 0x10000000
36#define PA_AREA5 0x14000000
37#define PA_AREA6 0x18000000
38#define PA_AREA7 0x1c000000
39
31#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */ 40#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */
32#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */ 41#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */
33 42
diff --git a/arch/sh/include/cpu-sh4/cpu/dma-register.h b/arch/sh/include/cpu-sh4/cpu/dma-register.h
new file mode 100644
index 000000000000..de2359533994
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/dma-register.h
@@ -0,0 +1,112 @@
1/*
2 * SH4 CPU-specific DMA definitions, used by both DMA drivers
3 *
4 * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef CPU_DMA_REGISTER_H
11#define CPU_DMA_REGISTER_H
12
13/* SH7751/7760/7780 DMA IRQ sources */
14
15#ifdef CONFIG_CPU_SH4A
16
17#define DMAOR_INIT DMAOR_DME
18
19#if defined(CONFIG_CPU_SUBTYPE_SH7343) || \
20 defined(CONFIG_CPU_SUBTYPE_SH7730)
21#define CHCR_TS_LOW_MASK 0x00000018
22#define CHCR_TS_LOW_SHIFT 3
23#define CHCR_TS_HIGH_MASK 0
24#define CHCR_TS_HIGH_SHIFT 0
25#elif defined(CONFIG_CPU_SUBTYPE_SH7722) || \
26 defined(CONFIG_CPU_SUBTYPE_SH7724)
27#define CHCR_TS_LOW_MASK 0x00000018
28#define CHCR_TS_LOW_SHIFT 3
29#define CHCR_TS_HIGH_MASK 0x00300000
30#define CHCR_TS_HIGH_SHIFT (20 - 2) /* 2 bits for shifted low TS */
31#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
32 defined(CONFIG_CPU_SUBTYPE_SH7764)
33#define CHCR_TS_LOW_MASK 0x00000018
34#define CHCR_TS_LOW_SHIFT 3
35#define CHCR_TS_HIGH_MASK 0
36#define CHCR_TS_HIGH_SHIFT 0
37#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
38#define CHCR_TS_LOW_MASK 0x00000018
39#define CHCR_TS_LOW_SHIFT 3
40#define CHCR_TS_HIGH_MASK 0
41#define CHCR_TS_HIGH_SHIFT 0
42#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
43#define CHCR_TS_LOW_MASK 0x00000018
44#define CHCR_TS_LOW_SHIFT 3
45#define CHCR_TS_HIGH_MASK 0
46#define CHCR_TS_HIGH_SHIFT 0
47#else /* SH7785 */
48#define CHCR_TS_LOW_MASK 0x00000018
49#define CHCR_TS_LOW_SHIFT 3
50#define CHCR_TS_HIGH_MASK 0
51#define CHCR_TS_HIGH_SHIFT 0
52#endif
53
54/* Transmit sizes and respective CHCR register values */
55enum {
56 XMIT_SZ_8BIT = 0,
57 XMIT_SZ_16BIT = 1,
58 XMIT_SZ_32BIT = 2,
59 XMIT_SZ_64BIT = 7,
60 XMIT_SZ_128BIT = 3,
61 XMIT_SZ_256BIT = 4,
62 XMIT_SZ_128BIT_BLK = 0xb,
63 XMIT_SZ_256BIT_BLK = 0xc,
64};
65
66/* log2(size / 8) - used to calculate number of transfers */
67#define TS_SHIFT { \
68 [XMIT_SZ_8BIT] = 0, \
69 [XMIT_SZ_16BIT] = 1, \
70 [XMIT_SZ_32BIT] = 2, \
71 [XMIT_SZ_64BIT] = 3, \
72 [XMIT_SZ_128BIT] = 4, \
73 [XMIT_SZ_256BIT] = 5, \
74 [XMIT_SZ_128BIT_BLK] = 4, \
75 [XMIT_SZ_256BIT_BLK] = 5, \
76}
77
78#define TS_INDEX2VAL(i) ((((i) & 3) << CHCR_TS_LOW_SHIFT) | \
79 (((i) & 0xc) << CHCR_TS_HIGH_SHIFT))
80
81#else /* CONFIG_CPU_SH4A */
82
83#define DMAOR_INIT (0x8000 | DMAOR_DME)
84
85#define CHCR_TS_LOW_MASK 0x70
86#define CHCR_TS_LOW_SHIFT 4
87#define CHCR_TS_HIGH_MASK 0
88#define CHCR_TS_HIGH_SHIFT 0
89
90/* Transmit sizes and respective CHCR register values */
91enum {
92 XMIT_SZ_8BIT = 1,
93 XMIT_SZ_16BIT = 2,
94 XMIT_SZ_32BIT = 3,
95 XMIT_SZ_64BIT = 0,
96 XMIT_SZ_256BIT = 4,
97};
98
99/* log2(size / 8) - used to calculate number of transfers */
100#define TS_SHIFT { \
101 [XMIT_SZ_8BIT] = 0, \
102 [XMIT_SZ_16BIT] = 1, \
103 [XMIT_SZ_32BIT] = 2, \
104 [XMIT_SZ_64BIT] = 3, \
105 [XMIT_SZ_256BIT] = 5, \
106}
107
108#define TS_INDEX2VAL(i) (((i) & 7) << CHCR_TS_LOW_SHIFT)
109
110#endif /* CONFIG_CPU_SH4A */
111
112#endif
diff --git a/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h b/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
index f0886bc880e0..9647e681fd27 100644
--- a/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
+++ b/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
@@ -2,34 +2,52 @@
2#define __ASM_SH_CPU_SH4_DMA_SH7780_H 2#define __ASM_SH_CPU_SH4_DMA_SH7780_H
3 3
4#if defined(CONFIG_CPU_SUBTYPE_SH7343) || \ 4#if defined(CONFIG_CPU_SUBTYPE_SH7343) || \
5 defined(CONFIG_CPU_SUBTYPE_SH7722) || \
6 defined(CONFIG_CPU_SUBTYPE_SH7730) 5 defined(CONFIG_CPU_SUBTYPE_SH7730)
7#define DMTE0_IRQ 48 6#define DMTE0_IRQ 48
8#define DMTE4_IRQ 76 7#define DMTE4_IRQ 76
9#define DMAE0_IRQ 78 /* DMA Error IRQ*/ 8#define DMAE0_IRQ 78 /* DMA Error IRQ*/
10#define SH_DMAC_BASE0 0xFE008020 9#define SH_DMAC_BASE0 0xFE008020
11#define SH_DMARS_BASE 0xFE009000 10#define SH_DMARS_BASE0 0xFE009000
11#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
12#define DMTE0_IRQ 48
13#define DMTE4_IRQ 76
14#define DMAE0_IRQ 78 /* DMA Error IRQ*/
15#define SH_DMAC_BASE0 0xFE008020
16#define SH_DMARS_BASE0 0xFE009000
12#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \ 17#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
13 defined(CONFIG_CPU_SUBTYPE_SH7764) 18 defined(CONFIG_CPU_SUBTYPE_SH7764)
14#define DMTE0_IRQ 34 19#define DMTE0_IRQ 34
15#define DMTE4_IRQ 44 20#define DMTE4_IRQ 44
16#define DMAE0_IRQ 38 21#define DMAE0_IRQ 38
17#define SH_DMAC_BASE0 0xFF608020 22#define SH_DMAC_BASE0 0xFF608020
18#define SH_DMARS_BASE 0xFF609000 23#define SH_DMARS_BASE0 0xFF609000
19#elif defined(CONFIG_CPU_SUBTYPE_SH7723) || \ 24#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
20 defined(CONFIG_CPU_SUBTYPE_SH7724)
21#define DMTE0_IRQ 48 /* DMAC0A*/ 25#define DMTE0_IRQ 48 /* DMAC0A*/
22#define DMTE4_IRQ 40 /* DMAC0B */ 26#define DMTE4_IRQ 76 /* DMAC0B */
23#define DMTE6_IRQ 42 27#define DMTE6_IRQ 40
24#define DMTE8_IRQ 76 /* DMAC1A */ 28#define DMTE8_IRQ 42 /* DMAC1A */
25#define DMTE9_IRQ 77 29#define DMTE9_IRQ 43
26#define DMTE10_IRQ 72 /* DMAC1B */ 30#define DMTE10_IRQ 72 /* DMAC1B */
27#define DMTE11_IRQ 73 31#define DMTE11_IRQ 73
28#define DMAE0_IRQ 78 /* DMA Error IRQ*/ 32#define DMAE0_IRQ 78 /* DMA Error IRQ*/
29#define DMAE1_IRQ 74 /* DMA Error IRQ*/ 33#define DMAE1_IRQ 74 /* DMA Error IRQ*/
30#define SH_DMAC_BASE0 0xFE008020 34#define SH_DMAC_BASE0 0xFE008020
31#define SH_DMAC_BASE1 0xFDC08020 35#define SH_DMAC_BASE1 0xFDC08020
32#define SH_DMARS_BASE 0xFDC09000 36#define SH_DMARS_BASE0 0xFDC09000
37#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
38#define DMTE0_IRQ 48 /* DMAC0A*/
39#define DMTE4_IRQ 76 /* DMAC0B */
40#define DMTE6_IRQ 40
41#define DMTE8_IRQ 42 /* DMAC1A */
42#define DMTE9_IRQ 43
43#define DMTE10_IRQ 72 /* DMAC1B */
44#define DMTE11_IRQ 73
45#define DMAE0_IRQ 78 /* DMA Error IRQ*/
46#define DMAE1_IRQ 74 /* DMA Error IRQ*/
47#define SH_DMAC_BASE0 0xFE008020
48#define SH_DMAC_BASE1 0xFDC08020
49#define SH_DMARS_BASE0 0xFE009000
50#define SH_DMARS_BASE1 0xFDC09000
33#elif defined(CONFIG_CPU_SUBTYPE_SH7780) 51#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
34#define DMTE0_IRQ 34 52#define DMTE0_IRQ 34
35#define DMTE4_IRQ 44 53#define DMTE4_IRQ 44
@@ -41,7 +59,7 @@
41#define DMAE0_IRQ 38 /* DMA Error IRQ */ 59#define DMAE0_IRQ 38 /* DMA Error IRQ */
42#define SH_DMAC_BASE0 0xFC808020 60#define SH_DMAC_BASE0 0xFC808020
43#define SH_DMAC_BASE1 0xFC818020 61#define SH_DMAC_BASE1 0xFC818020
44#define SH_DMARS_BASE 0xFC809000 62#define SH_DMARS_BASE0 0xFC809000
45#else /* SH7785 */ 63#else /* SH7785 */
46#define DMTE0_IRQ 33 64#define DMTE0_IRQ 33
47#define DMTE4_IRQ 37 65#define DMTE4_IRQ 37
@@ -54,42 +72,12 @@
54#define DMAE1_IRQ 58 /* DMA Error IRQ1 */ 72#define DMAE1_IRQ 58 /* DMA Error IRQ1 */
55#define SH_DMAC_BASE0 0xFC808020 73#define SH_DMAC_BASE0 0xFC808020
56#define SH_DMAC_BASE1 0xFCC08020 74#define SH_DMAC_BASE1 0xFCC08020
57#define SH_DMARS_BASE 0xFC809000 75#define SH_DMARS_BASE0 0xFC809000
58#endif 76#endif
59 77
60#define REQ_HE 0x000000C0 78#define REQ_HE 0x000000C0
61#define REQ_H 0x00000080 79#define REQ_H 0x00000080
62#define REQ_LE 0x00000040 80#define REQ_LE 0x00000040
63#define TM_BURST 0x0000020 81#define TM_BURST 0x00000020
64#define TS_8 0x00000000
65#define TS_16 0x00000008
66#define TS_32 0x00000010
67#define TS_16BLK 0x00000018
68#define TS_32BLK 0x00100000
69
70/*
71 * The SuperH DMAC supports a number of transmit sizes, we list them here,
72 * with their respective values as they appear in the CHCR registers.
73 *
74 * Defaults to a 64-bit transfer size.
75 */
76enum {
77 XMIT_SZ_8BIT,
78 XMIT_SZ_16BIT,
79 XMIT_SZ_32BIT,
80 XMIT_SZ_128BIT,
81 XMIT_SZ_256BIT,
82};
83
84/*
85 * The DMA count is defined as the number of bytes to transfer.
86 */
87static unsigned int ts_shift[] __maybe_unused = {
88 [XMIT_SZ_8BIT] = 0,
89 [XMIT_SZ_16BIT] = 1,
90 [XMIT_SZ_32BIT] = 2,
91 [XMIT_SZ_128BIT] = 4,
92 [XMIT_SZ_256BIT] = 5,
93};
94 82
95#endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */ 83#endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */
diff --git a/arch/sh/include/cpu-sh4/cpu/dma.h b/arch/sh/include/cpu-sh4/cpu/dma.h
index bcb30246e85c..ca747e93c2ed 100644
--- a/arch/sh/include/cpu-sh4/cpu/dma.h
+++ b/arch/sh/include/cpu-sh4/cpu/dma.h
@@ -5,11 +5,8 @@
5 5
6#ifdef CONFIG_CPU_SH4A 6#ifdef CONFIG_CPU_SH4A
7 7
8#define DMAOR_INIT (DMAOR_DME)
9#define CHCR_TS_MASK 0x18
10#define CHCR_TS_SHIFT 3
11
12#include <cpu/dma-sh4a.h> 8#include <cpu/dma-sh4a.h>
9
13#else /* CONFIG_CPU_SH4A */ 10#else /* CONFIG_CPU_SH4A */
14/* 11/*
15 * SH7750/SH7751/SH7760 12 * SH7750/SH7751/SH7760
@@ -19,7 +16,6 @@
19#define DMTE6_IRQ 46 16#define DMTE6_IRQ 46
20#define DMAE0_IRQ 38 17#define DMAE0_IRQ 38
21 18
22#define DMAOR_INIT (0x8000|DMAOR_DME)
23#define SH_DMAC_BASE0 0xffa00000 19#define SH_DMAC_BASE0 0xffa00000
24#define SH_DMAC_BASE1 0xffa00070 20#define SH_DMAC_BASE1 0xffa00070
25/* Definitions for the SuperH DMAC */ 21/* Definitions for the SuperH DMAC */
@@ -29,35 +25,8 @@
29#define TS_32 0x00000030 25#define TS_32 0x00000030
30#define TS_64 0x00000000 26#define TS_64 0x00000000
31 27
32#define CHCR_TS_MASK 0x70
33#define CHCR_TS_SHIFT 4
34
35#define DMAOR_COD 0x00000008 28#define DMAOR_COD 0x00000008
36 29
37/*
38 * The SuperH DMAC supports a number of transmit sizes, we list them here,
39 * with their respective values as they appear in the CHCR registers.
40 *
41 * Defaults to a 64-bit transfer size.
42 */
43enum {
44 XMIT_SZ_64BIT,
45 XMIT_SZ_8BIT,
46 XMIT_SZ_16BIT,
47 XMIT_SZ_32BIT,
48 XMIT_SZ_256BIT,
49};
50
51/*
52 * The DMA count is defined as the number of bytes to transfer.
53 */
54static unsigned int ts_shift[] __maybe_unused = {
55 [XMIT_SZ_64BIT] = 3,
56 [XMIT_SZ_8BIT] = 0,
57 [XMIT_SZ_16BIT] = 1,
58 [XMIT_SZ_32BIT] = 2,
59 [XMIT_SZ_256BIT] = 5,
60};
61#endif 30#endif
62 31
63#endif /* __ASM_CPU_SH4_DMA_H */ 32#endif /* __ASM_CPU_SH4_DMA_H */
diff --git a/arch/sh/include/cpu-sh4/cpu/mmu_context.h b/arch/sh/include/cpu-sh4/cpu/mmu_context.h
index 3ce7ef6c2978..5963124c1d4a 100644
--- a/arch/sh/include/cpu-sh4/cpu/mmu_context.h
+++ b/arch/sh/include/cpu-sh4/cpu/mmu_context.h
@@ -19,12 +19,20 @@
19 19
20#define MMUCR 0xFF000010 /* MMU Control Register */ 20#define MMUCR 0xFF000010 /* MMU Control Register */
21 21
22#define MMU_ITLB_ADDRESS_ARRAY 0xF2000000
23#define MMU_ITLB_ADDRESS_ARRAY2 0xF2800000
22#define MMU_UTLB_ADDRESS_ARRAY 0xF6000000 24#define MMU_UTLB_ADDRESS_ARRAY 0xF6000000
23#define MMU_UTLB_ADDRESS_ARRAY2 0xF6800000 25#define MMU_UTLB_ADDRESS_ARRAY2 0xF6800000
24#define MMU_PAGE_ASSOC_BIT 0x80 26#define MMU_PAGE_ASSOC_BIT 0x80
25 27
26#define MMUCR_TI (1<<2) 28#define MMUCR_TI (1<<2)
27 29
30#define MMUCR_URB 0x00FC0000
31#define MMUCR_URB_SHIFT 18
32#define MMUCR_URB_NENTRIES 64
33#define MMUCR_URC 0x0000FC00
34#define MMUCR_URC_SHIFT 10
35
28#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_SUBTYPE_ST40) 36#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_SUBTYPE_ST40)
29#define MMUCR_SE (1 << 4) 37#define MMUCR_SE (1 << 4)
30#else 38#else
diff --git a/arch/sh/include/cpu-sh4/cpu/sq.h b/arch/sh/include/cpu-sh4/cpu/sq.h
index 586d6491816a..74716ba2dc3c 100644
--- a/arch/sh/include/cpu-sh4/cpu/sq.h
+++ b/arch/sh/include/cpu-sh4/cpu/sq.h
@@ -12,6 +12,7 @@
12#define __ASM_CPU_SH4_SQ_H 12#define __ASM_CPU_SH4_SQ_H
13 13
14#include <asm/addrspace.h> 14#include <asm/addrspace.h>
15#include <asm/page.h>
15 16
16/* 17/*
17 * Store queues range from e0000000-e3fffffc, allowing approx. 64MB to be 18 * Store queues range from e0000000-e3fffffc, allowing approx. 64MB to be
@@ -28,7 +29,7 @@
28 29
29/* arch/sh/kernel/cpu/sh4/sq.c */ 30/* arch/sh/kernel/cpu/sh4/sq.c */
30unsigned long sq_remap(unsigned long phys, unsigned int size, 31unsigned long sq_remap(unsigned long phys, unsigned int size,
31 const char *name, unsigned long flags); 32 const char *name, pgprot_t prot);
32void sq_unmap(unsigned long vaddr); 33void sq_unmap(unsigned long vaddr);
33void sq_flush_range(unsigned long start, unsigned int len); 34void sq_flush_range(unsigned long start, unsigned int len);
34 35
diff --git a/arch/sh/include/cpu-sh4/cpu/ubc.h b/arch/sh/include/cpu-sh4/cpu/ubc.h
deleted file mode 100644
index c86e17050935..000000000000
--- a/arch/sh/include/cpu-sh4/cpu/ubc.h
+++ /dev/null
@@ -1,64 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh4/ubc.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 * Copyright (C) 2003 Paul Mundt
6 * Copyright (C) 2006 Lineo Solutions Inc. support SH4A UBC
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#ifndef __ASM_CPU_SH4_UBC_H
13#define __ASM_CPU_SH4_UBC_H
14
15#if defined(CONFIG_CPU_SH4A)
16#define UBC_CBR0 0xff200000
17#define UBC_CRR0 0xff200004
18#define UBC_CAR0 0xff200008
19#define UBC_CAMR0 0xff20000c
20#define UBC_CBR1 0xff200020
21#define UBC_CRR1 0xff200024
22#define UBC_CAR1 0xff200028
23#define UBC_CAMR1 0xff20002c
24#define UBC_CDR1 0xff200030
25#define UBC_CDMR1 0xff200034
26#define UBC_CETR1 0xff200038
27#define UBC_CCMFR 0xff200600
28#define UBC_CBCR 0xff200620
29
30/* CBR */
31#define UBC_CBR_AIE (0x01<<30)
32#define UBC_CBR_ID_INST (0x01<<4)
33#define UBC_CBR_RW_READ (0x01<<1)
34#define UBC_CBR_CE (0x01)
35
36#define UBC_CBR_AIV_MASK (0x00FF0000)
37#define UBC_CBR_AIV_SHIFT (16)
38#define UBC_CBR_AIV_SET(asid) (((asid)<<UBC_CBR_AIV_SHIFT) & UBC_CBR_AIV_MASK)
39
40#define UBC_CBR_INIT 0x20000000
41
42/* CRR */
43#define UBC_CRR_RES (0x01<<13)
44#define UBC_CRR_PCB (0x01<<1)
45#define UBC_CRR_BIE (0x01)
46
47#define UBC_CRR_INIT 0x00002000
48
49#else /* CONFIG_CPU_SH4 */
50#define UBC_BARA 0xff200000
51#define UBC_BAMRA 0xff200004
52#define UBC_BBRA 0xff200008
53#define UBC_BASRA 0xff000014
54#define UBC_BARB 0xff20000c
55#define UBC_BAMRB 0xff200010
56#define UBC_BBRB 0xff200014
57#define UBC_BASRB 0xff000018
58#define UBC_BDRB 0xff200018
59#define UBC_BDMRB 0xff20001c
60#define UBC_BRCR 0xff200020
61#endif /* CONFIG_CPU_SH4 */
62
63#endif /* __ASM_CPU_SH4_UBC_H */
64
diff --git a/arch/sh/include/cpu-sh4/cpu/watchdog.h b/arch/sh/include/cpu-sh4/cpu/watchdog.h
index 259f6a0ce23d..7f62b9380938 100644
--- a/arch/sh/include/cpu-sh4/cpu/watchdog.h
+++ b/arch/sh/include/cpu-sh4/cpu/watchdog.h
@@ -2,6 +2,8 @@
2 * include/asm-sh/cpu-sh4/watchdog.h 2 * include/asm-sh/cpu-sh4/watchdog.h
3 * 3 *
4 * Copyright (C) 2002, 2003 Paul Mundt 4 * Copyright (C) 2002, 2003 Paul Mundt
5 * Copyright (C) 2009 Siemens AG
6 * Copyright (C) 2009 Sitdikov Valentin
5 * 7 *
6 * This file is subject to the terms and conditions of the GNU General Public 8 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive 9 * License. See the file "COPYING" in the main directory of this archive
@@ -10,9 +12,26 @@
10#ifndef __ASM_CPU_SH4_WATCHDOG_H 12#ifndef __ASM_CPU_SH4_WATCHDOG_H
11#define __ASM_CPU_SH4_WATCHDOG_H 13#define __ASM_CPU_SH4_WATCHDOG_H
12 14
15#if defined(CONFIG_CPU_SUBTYPE_SH7785) || defined(CONFIG_CPU_SUBTYPE_SH7780)
16/* Prefix definition */
17#define WTBST_HIGH 0x55
18/* Register definitions */
19#define WTCNT_R 0xffcc0010 /*WDTCNT*/
20#define WTCSR 0xffcc0004 /*WDTCSR*/
21#define WTCNT 0xffcc0000 /*WDTST*/
22#define WTST WTCNT
23#define WTBST 0xffcc0008 /*WDTBST*/
24/* Register definitions */
25#elif defined(CONFIG_CPU_SUBTYPE_SH7722) || \
26 defined(CONFIG_CPU_SUBTYPE_SH7723) || \
27 defined(CONFIG_CPU_SUBTYPE_SH7724)
28#define WTCNT 0xa4520000
29#define WTCSR 0xa4520004
30#else
13/* Register definitions */ 31/* Register definitions */
14#define WTCNT 0xffc00008 32#define WTCNT 0xffc00008
15#define WTCSR 0xffc0000c 33#define WTCSR 0xffc0000c
34#endif
16 35
17/* Bit definitions */ 36/* Bit definitions */
18#define WTCSR_TME 0x80 37#define WTCSR_TME 0x80
generated by cgit v1.2.2 (git 2.25.0) at 2025-07-31 14:32:54 -0400