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authorPaul Mundt <lethal@linux-sh.org>2009-04-17 01:09:09 -0400
committerPaul Mundt <lethal@linux-sh.org>2009-04-17 01:09:09 -0400
commit0bbc9bc3189f24de946777af43c9033c8c4871e4 (patch)
tree996a03383430848a62746d8ffb9c5035d0d9a4ca /arch/sh/drivers
parent7e4ba0d77c96d328ba968ddff4a464d4d2fa7abc (diff)
sh: pci: Set class/sub-class code correctly for SH7780 PCIC.
The SH7780 PCI host controller implements a configuration header that requires a fair bit of hand-holding to initialize properly. By default it appears as a pre-2.0 host controller given the zeroed out class code, so fix this up properly. Some boards that happened to be using the R7780RP version of the PCIC fixups had set this correctly, but this belongs in the standard initialization, and is by no means board specific. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/drivers')
-rw-r--r--arch/sh/drivers/pci/fixups-sdk7780.c4
-rw-r--r--arch/sh/drivers/pci/pci-sh7780.c7
2 files changed, 3 insertions, 8 deletions
diff --git a/arch/sh/drivers/pci/fixups-sdk7780.c b/arch/sh/drivers/pci/fixups-sdk7780.c
index c2957312b30b..004efd486ee3 100644
--- a/arch/sh/drivers/pci/fixups-sdk7780.c
+++ b/arch/sh/drivers/pci/fixups-sdk7780.c
@@ -16,8 +16,6 @@
16 16
17int pci_fixup_pcic(struct pci_channel *chan) 17int pci_fixup_pcic(struct pci_channel *chan)
18{ 18{
19 ctrl_outl(0x00000001, SH7780_PCI_VCR2);
20
21 /* Enable all interrupts, so we know what to fix */ 19 /* Enable all interrupts, so we know what to fix */
22 pci_write_reg(chan, 0x0000C3FF, SH7780_PCIIMR); 20 pci_write_reg(chan, 0x0000C3FF, SH7780_PCIIMR);
23 pci_write_reg(chan, 0x0000380F, SH7780_PCIAINTM); 21 pci_write_reg(chan, 0x0000380F, SH7780_PCIAINTM);
@@ -26,8 +24,6 @@ int pci_fixup_pcic(struct pci_channel *chan)
26 pci_write_reg(chan, 0xFB00, SH7780_PCISTATUS); 24 pci_write_reg(chan, 0xFB00, SH7780_PCISTATUS);
27 pci_write_reg(chan, 0x0047, SH7780_PCICMD); 25 pci_write_reg(chan, 0x0047, SH7780_PCICMD);
28 pci_write_reg(chan, 0x00, SH7780_PCIPIF); 26 pci_write_reg(chan, 0x00, SH7780_PCIPIF);
29 pci_write_reg(chan, 0x00, SH7780_PCISUB);
30 pci_write_reg(chan, 0x06, SH7780_PCIBCC);
31 pci_write_reg(chan, 0x1912, SH7780_PCISVID); 27 pci_write_reg(chan, 0x1912, SH7780_PCISVID);
32 pci_write_reg(chan, 0x0001, SH7780_PCISID); 28 pci_write_reg(chan, 0x0001, SH7780_PCISID);
33 29
diff --git a/arch/sh/drivers/pci/pci-sh7780.c b/arch/sh/drivers/pci/pci-sh7780.c
index 45fa423f2e53..7f4f59037544 100644
--- a/arch/sh/drivers/pci/pci-sh7780.c
+++ b/arch/sh/drivers/pci/pci-sh7780.c
@@ -72,16 +72,15 @@ int __init sh7780_pcic_init(struct pci_channel *chan,
72{ 72{
73 u32 word; 73 u32 word;
74 74
75 pci_write_reg(chan, PCI_CLASS_BRIDGE_HOST >> 8, SH7780_PCIBCC);
76 pci_write_reg(chan, PCI_CLASS_BRIDGE_HOST & 0xff, SH7780_PCISUB);
77
75 /* set the command/status bits to: 78 /* set the command/status bits to:
76 * Wait Cycle Control + Parity Enable + Bus Master + 79 * Wait Cycle Control + Parity Enable + Bus Master +
77 * Mem space enable 80 * Mem space enable
78 */ 81 */
79 pci_write_reg(chan, 0x00000046, SH7780_PCICMD); 82 pci_write_reg(chan, 0x00000046, SH7780_PCICMD);
80 83
81 /* define this host as the host bridge */
82 word = PCI_BASE_CLASS_BRIDGE << 24;
83 pci_write_reg(chan, word, SH7780_PCIRID);
84
85 /* Set IO and Mem windows to local address 84 /* Set IO and Mem windows to local address
86 * Make PCI and local address the same for easy 1 to 1 mapping 85 * Make PCI and local address the same for easy 1 to 1 mapping
87 */ 86 */