sh: Renesas R0P7785LC0011RL board support

This adds initial support for the Renesas R0P7785LC0011RL board.
This patch supports 29bit address mode only.

Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

3 files changed, 113 insertions, 0 deletions

diff --git a/arch/sh/drivers/pci/Makefile b/arch/sh/drivers/pci/Makefile
index 0718805774e8..847e90894d1b 100644
--- a/arch/sh/drivers/pci/Makefile
+++ b/arch/sh/drivers/pci/Makefile
@@ -23,3 +23,4 @@ obj-$(CONFIG_SH_LANDISK)		+= ops-landisk.o
 obj-$(CONFIG_SH_LBOX_RE2)               += ops-lboxre2.o fixups-lboxre2.o
 obj-$(CONFIG_SH_7780_SOLUTION_ENGINE)   += ops-se7780.o fixups-se7780.o
 obj-$(CONFIG_SH_CAYMAN)                 += ops-cayman.o
+obj-$(CONFIG_SH_SH7785LCR)              += ops-sh7785lcr.o fixups-sh7785lcr.o
diff --git a/arch/sh/drivers/pci/fixups-sh7785lcr.c b/arch/sh/drivers/pci/fixups-sh7785lcr.c
new file mode 100644
index 000000000000..4949e601387a
--- /dev/null
+++ b/arch/sh/drivers/pci/fixups-sh7785lcr.c
@@ -0,0 +1,46 @@
+/*
+ * arch/sh/drivers/pci/fixups-sh7785lcr.c
+ *
+ * R0P7785LC0011RL PCI fixups
+ * Copyright (C) 2008  Yoshihiro Shimoda
+ *
+ * Based on arch/sh/drivers/pci/fixups-r7780rp.c
+ * Copyright (C) 2003  Lineo uSolutions, Inc.
+ * Copyright (C) 2004 - 2006  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/pci.h>
+#include "pci-sh4.h"
+
+int pci_fixup_pcic(void)
+{
+        pci_write_reg(0x000043ff, SH4_PCIINTM);
+        pci_write_reg(0x0000380f, SH4_PCIAINTM);
+
+        pci_write_reg(0xfbb00047, SH7780_PCICMD);
+        pci_write_reg(0x00000000, SH7780_PCIIBAR);
+
+        pci_write_reg(0x00011912, SH7780_PCISVID);
+        pci_write_reg(0x08000000, SH7780_PCICSCR0);
+        pci_write_reg(0x0000001b, SH7780_PCICSAR0);
+        pci_write_reg(0xfd000000, SH7780_PCICSCR1);
+        pci_write_reg(0x0000000f, SH7780_PCICSAR1);
+
+        pci_write_reg(0xfd000000, SH7780_PCIMBR0);
+        pci_write_reg(0x00fc0000, SH7780_PCIMBMR0);
+
+#ifdef CONFIG_32BIT
+        pci_write_reg(0xc0000000, SH7780_PCIMBR2);
+        pci_write_reg(0x20000000 - SH7780_PCI_IO_SIZE, SH7780_PCIMBMR2);
+#endif
+
+        /* Set IOBR for windows containing area specified in pci.h */
+        pci_write_reg((PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE - 1)),
+                      SH7780_PCIIOBR);
+        pci_write_reg(((SH7780_PCI_IO_SIZE - 1) & (7 << 18)), SH7780_PCIIOBMR);
+
+        return 0;
+}
diff --git a/arch/sh/drivers/pci/ops-sh7785lcr.c b/arch/sh/drivers/pci/ops-sh7785lcr.c
new file mode 100644
index 000000000000..b3bd68702059
--- /dev/null
+++ b/arch/sh/drivers/pci/ops-sh7785lcr.c
@@ -0,0 +1,66 @@
+/*
+ * Author:  Ian DaSilva (idasilva@mvista.com)
+ *
+ * Highly leveraged from pci-bigsur.c, written by Dustin McIntire.
+ *
+ * May be copied or modified under the terms of the GNU General Public
+ * License.  See linux/COPYING for more information.
+ *
+ * PCI initialization for the Renesas R0P7785LC0011RL board
+ * Based on arch/sh/drivers/pci/ops-r7780rp.c
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pci.h>
+#include "pci-sh4.h"
+
+static char irq_tab[] __initdata = {
+        65, 66, 67, 68,
+};
+
+int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
+{
+        return irq_tab[slot];
+}
+
+static struct resource sh7785_io_resource = {
+        .name   = "SH7785_IO",
+        .start  = SH7780_PCI_IO_BASE,
+        .end    = SH7780_PCI_IO_BASE + SH7780_PCI_IO_SIZE - 1,
+        .flags  = IORESOURCE_IO
+};
+
+static struct resource sh7785_mem_resource = {
+        .name   = "SH7785_mem",
+        .start  = SH7780_PCI_MEMORY_BASE,
+        .end    = SH7780_PCI_MEMORY_BASE + SH7780_PCI_MEM_SIZE - 1,
+        .flags  = IORESOURCE_MEM
+};
+
+struct pci_channel board_pci_channels[] = {
+        { &sh4_pci_ops, &sh7785_io_resource, &sh7785_mem_resource, 0, 0xff },
+        { NULL, NULL, NULL, 0, 0 },
+};
+EXPORT_SYMBOL(board_pci_channels);
+
+static struct sh4_pci_address_map sh7785_pci_map = {
+        .window0        = {
+                .base   = SH7780_CS2_BASE_ADDR,
+                .size   = 0x04000000,
+        },
+
+        .window1        = {
+                .base   = SH7780_CS3_BASE_ADDR,
+                .size   = 0x04000000,
+        },
+
+        .flags  = SH4_PCIC_NO_RESET,
+};
+
+int __init pcibios_init_platform(void)
+{
+        return sh7780_pcic_init(&sh7785_pci_map);
+}