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authorMagnus Damm <damm@igel.co.jp>2007-08-12 02:26:12 -0400
committerPaul Mundt <lethal@linux-sh.org>2007-09-20 22:57:50 -0400
commit73505b445dbb8ad12df468404c4dd5cde9c40c65 (patch)
treec248710475090f01dc874e2c878efc769b24d2af /arch/sh/cchips
parent6ef5fb2cfcedaab4a43493c8f2305a67c0ce1af6 (diff)
sh: intc - rework core code
This patch reworks the intc core, implementing the following features: - Support dual priority registers - one set and one clear register - All 8/16/32 bit register combinations are now supported - Both single mask and single enable bitmap register are supported - Add code to set interrupt priority - Speedup sense and priority configuration code - Allocate data using bootmem, allows intc data structures to be __initdata - Save memory - allocated memory footprint is smaller than intc structures Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/cchips')
-rw-r--r--arch/sh/cchips/voyagergx/irq.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/sh/cchips/voyagergx/irq.c b/arch/sh/cchips/voyagergx/irq.c
index 0ca405a46a5b..2d3620cc92be 100644
--- a/arch/sh/cchips/voyagergx/irq.c
+++ b/arch/sh/cchips/voyagergx/irq.c
@@ -50,7 +50,7 @@ static struct intc_vect vectors[] = {
50}; 50};
51 51
52static struct intc_mask_reg mask_registers[] = { 52static struct intc_mask_reg mask_registers[] = {
53 { VOYAGER_INT_MASK, 1, 32, /* "Interrupt Mask", MMIO_base + 0x30 */ 53 { VOYAGER_INT_MASK, 0, 32, /* "Interrupt Mask", MMIO_base + 0x30 */
54 { UP, G54, G53, G52, G51, G50, G49, G48, 54 { UP, G54, G53, G52, G51, G50, G49, G48,
55 I2C, PW, 0, DMA, PCI, I2S, AC, US, 55 I2C, PW, 0, DMA, PCI, I2S, AC, US,
56 0, 0, U1, U0, CV, MC, S1, S0, 56 0, 0, U1, U0, CV, MC, S1, S0,