Linux-2.6.12-rc2v2.6.12-rc2

Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.

Let it rip!

5 files changed, 958 insertions, 0 deletions

diff --git a/arch/sh/boards/superh/microdev/Makefile b/arch/sh/boards/superh/microdev/Makefile
new file mode 100644
index 000000000000..1387dd6c85eb
--- /dev/null
+++ b/arch/sh/boards/superh/microdev/Makefile
@@ -0,0 +1,8 @@
+#
+# Makefile for the SuperH MicroDev specific parts of the kernel
+#
+
+obj-y    := setup.o irq.o io.o
+
+obj-$(CONFIG_HEARTBEAT) += led.o
+
diff --git a/arch/sh/boards/superh/microdev/io.c b/arch/sh/boards/superh/microdev/io.c
new file mode 100644
index 000000000000..fe83b2c03076
--- /dev/null
+++ b/arch/sh/boards/superh/microdev/io.c
@@ -0,0 +1,370 @@
+/*
+ * linux/arch/sh/kernel/io_microdev.c
+ *
+ * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com)
+ * Copyright (C) 2003, 2004 SuperH, Inc.
+ * Copyright (C) 2004 Paul Mundt
+ *
+ * SuperH SH4-202 MicroDev board support.
+ *
+ * May be copied or modified under the terms of the GNU General Public
+ * License.  See linux/COPYING for more information.
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/wait.h>
+#include <asm/io.h>
+#include <asm/mach/io.h>
+
+        /*
+         *      we need to have a 'safe' address to re-direct all I/O requests
+         *      that we do not explicitly wish to handle. This safe address
+         *      must have the following properies:
+         *
+         *              * writes are ignored (no exception)
+         *              * reads are benign (no side-effects)
+         *              * accesses of width 1, 2 and 4-bytes are all valid.
+         *
+         *      The Processor Version Register (PVR) has these properties.
+         */
+#define PVR     0xff000030      /* Processor Version Register */
+
+
+#define IO_IDE2_BASE            0x170ul /* I/O base for SMSC FDC37C93xAPM IDE #2 */
+#define IO_IDE1_BASE            0x1f0ul /* I/O base for SMSC FDC37C93xAPM IDE #1 */
+#define IO_ISP1161_BASE         0x290ul /* I/O port for Philips ISP1161x USB chip */
+#define IO_SERIAL2_BASE         0x2f8ul /* I/O base for SMSC FDC37C93xAPM Serial #2 */
+#define IO_LAN91C111_BASE       0x300ul /* I/O base for SMSC LAN91C111 Ethernet chip */
+#define IO_IDE2_MISC            0x376ul /* I/O misc for SMSC FDC37C93xAPM IDE #2 */
+#define IO_SUPERIO_BASE         0x3f0ul /* I/O base for SMSC FDC37C93xAPM SuperIO chip */
+#define IO_IDE1_MISC            0x3f6ul /* I/O misc for SMSC FDC37C93xAPM IDE #1 */
+#define IO_SERIAL1_BASE         0x3f8ul /* I/O base for SMSC FDC37C93xAPM Serial #1 */
+
+#define IO_ISP1161_EXTENT       0x04ul  /* I/O extent for Philips ISP1161x USB chip */
+#define IO_LAN91C111_EXTENT     0x10ul  /* I/O extent for SMSC LAN91C111 Ethernet chip */
+#define IO_SUPERIO_EXTENT       0x02ul  /* I/O extent for SMSC FDC37C93xAPM SuperIO chip */
+#define IO_IDE_EXTENT           0x08ul  /* I/O extent for IDE Task Register set */
+#define IO_SERIAL_EXTENT        0x10ul
+
+#define IO_LAN91C111_PHYS       0xa7500000ul    /* Physical address of SMSC LAN91C111 Ethernet chip */
+#define IO_ISP1161_PHYS         0xa7700000ul    /* Physical address of Philips ISP1161x USB chip */
+#define IO_SUPERIO_PHYS         0xa7800000ul    /* Physical address of SMSC FDC37C93xAPM SuperIO chip */
+
+#define PORT2ADDR(x) (microdev_isa_port2addr(x))
+
+
+static inline void delay(void)
+{
+#if defined(CONFIG_PCI)
+        /* System board present, just make a dummy SRAM access.  (CS0 will be
+           mapped to PCI memory, probably good to avoid it.) */
+        ctrl_inw(0xa6800000);
+#else
+        /* CS0 will be mapped to flash, ROM etc so safe to access it. */
+        ctrl_inw(0xa0000000);
+#endif
+}
+
+unsigned char microdev_inb(unsigned long port)
+{
+#ifdef CONFIG_PCI
+        if (port >= PCIBIOS_MIN_IO)
+                return microdev_pci_inb(port);
+#endif
+        return *(volatile unsigned char*)PORT2ADDR(port);
+}
+
+unsigned short microdev_inw(unsigned long port)
+{
+#ifdef CONFIG_PCI
+        if (port >= PCIBIOS_MIN_IO)
+                return microdev_pci_inw(port);
+#endif
+        return *(volatile unsigned short*)PORT2ADDR(port);
+}
+
+unsigned int microdev_inl(unsigned long port)
+{
+#ifdef CONFIG_PCI
+        if (port >= PCIBIOS_MIN_IO)
+                return microdev_pci_inl(port);
+#endif
+        return *(volatile unsigned int*)PORT2ADDR(port);
+}
+
+void microdev_outb(unsigned char b, unsigned long port)
+{
+#ifdef CONFIG_PCI
+        if (port >= PCIBIOS_MIN_IO) {
+                microdev_pci_outb(b, port);
+                return;
+        }
+#endif
+
+        /*
+         *      There is a board feature with the current SH4-202 MicroDev in
+         *      that the 2 byte enables (nBE0 and nBE1) are tied together (and
+         *      to the Chip Select Line (Ethernet_CS)). Due to this conectivity,
+         *      it is not possible to safely perform 8-bit writes to the
+         *      Ethernet registers, as 16-bits will be consumed from the Data
+         *      lines (corrupting the other byte).  Hence, this function is
+         *      written to impliment 16-bit read/modify/write for all byte-wide
+         *      acceses.
+         *
+         *      Note: there is no problem with byte READS (even or odd).
+         *
+         *                      Sean McGoogan - 16th June 2003.
+         */
+        if ((port >= IO_LAN91C111_BASE) &&
+            (port <  IO_LAN91C111_BASE + IO_LAN91C111_EXTENT)) {
+                        /*
+                         * Then are trying to perform a byte-write to the
+                         * LAN91C111.  This needs special care.
+                         */
+                if (port % 2 == 1) {    /* is the port odd ? */
+                        /* unset bit-0, i.e. make even */
+                        const unsigned long evenPort = port-1;
+                        unsigned short word;
+
+                        /*
+                         * do a 16-bit read/write to write to 'port',
+                         * preserving even byte.
+                         *
+                         *      Even addresses are bits 0-7
+                         *      Odd  addresses are bits 8-15
+                         */
+                        word = microdev_inw(evenPort);
+                        word = (word & 0xffu) | (b << 8);
+                        microdev_outw(word, evenPort);
+                } else {
+                        /* else, we are trying to do an even byte write */
+                        unsigned short word;
+
+                        /*
+                         * do a 16-bit read/write to write to 'port',
+                         * preserving odd byte.
+                         *
+                         *      Even addresses are bits 0-7
+                         *      Odd  addresses are bits 8-15
+                         */
+                        word = microdev_inw(port);
+                        word = (word & 0xff00u) | (b);
+                        microdev_outw(word, port);
+                }
+        } else {
+                *(volatile unsigned char*)PORT2ADDR(port) = b;
+        }
+}
+
+void microdev_outw(unsigned short b, unsigned long port)
+{
+#ifdef CONFIG_PCI
+        if (port >= PCIBIOS_MIN_IO) {
+                microdev_pci_outw(b, port);
+                return;
+        }
+#endif
+        *(volatile unsigned short*)PORT2ADDR(port) = b;
+}
+
+void microdev_outl(unsigned int b, unsigned long port)
+{
+#ifdef CONFIG_PCI
+        if (port >= PCIBIOS_MIN_IO) {
+                microdev_pci_outl(b, port);
+                return;
+        }
+#endif
+        *(volatile unsigned int*)PORT2ADDR(port) = b;
+}
+
+unsigned char microdev_inb_p(unsigned long port)
+{
+        unsigned char v = microdev_inb(port);
+        delay();
+        return v;
+}
+
+unsigned short microdev_inw_p(unsigned long port)
+{
+        unsigned short v = microdev_inw(port);
+        delay();
+        return v;
+}
+
+unsigned int microdev_inl_p(unsigned long port)
+{
+        unsigned int v = microdev_inl(port);
+        delay();
+        return v;
+}
+
+void microdev_outb_p(unsigned char b, unsigned long port)
+{
+        microdev_outb(b, port);
+        delay();
+}
+
+void microdev_outw_p(unsigned short b, unsigned long port)
+{
+        microdev_outw(b, port);
+        delay();
+}
+
+void microdev_outl_p(unsigned int b, unsigned long port)
+{
+        microdev_outl(b, port);
+        delay();
+}
+
+void microdev_insb(unsigned long port, void *buffer, unsigned long count)
+{
+        volatile unsigned char *port_addr;
+        unsigned char *buf = buffer;
+
+        port_addr = (volatile unsigned char *)PORT2ADDR(port);
+
+        while (count--)
+                *buf++ = *port_addr;
+}
+
+void microdev_insw(unsigned long port, void *buffer, unsigned long count)
+{
+        volatile unsigned short *port_addr;
+        unsigned short *buf = buffer;
+
+        port_addr = (volatile unsigned short *)PORT2ADDR(port);
+
+        while (count--)
+                *buf++ = *port_addr;
+}
+
+void microdev_insl(unsigned long port, void *buffer, unsigned long count)
+{
+        volatile unsigned long *port_addr;
+        unsigned int *buf = buffer;
+
+        port_addr = (volatile unsigned long *)PORT2ADDR(port);
+
+        while (count--)
+                *buf++ = *port_addr;
+}
+
+void microdev_outsb(unsigned long port, const void *buffer, unsigned long count)
+{
+        volatile unsigned char *port_addr;
+        const unsigned char *buf = buffer;
+
+        port_addr = (volatile unsigned char *)PORT2ADDR(port);
+
+        while (count--)
+                *port_addr = *buf++;
+}
+
+void microdev_outsw(unsigned long port, const void *buffer, unsigned long count)
+{
+        volatile unsigned short *port_addr;
+        const unsigned short *buf = buffer;
+
+        port_addr = (volatile unsigned short *)PORT2ADDR(port);
+
+        while (count--)
+                *port_addr = *buf++;
+}
+
+void microdev_outsl(unsigned long port, const void *buffer, unsigned long count)
+{
+        volatile unsigned long *port_addr;
+        const unsigned int *buf = buffer;
+
+        port_addr = (volatile unsigned long *)PORT2ADDR(port);
+
+        while (count--)
+                *port_addr = *buf++;
+}
+
+/*
+ * map I/O ports to memory-mapped addresses
+ */
+unsigned long microdev_isa_port2addr(unsigned long offset)
+{
+        unsigned long result;
+
+        if ((offset >= IO_LAN91C111_BASE) &&
+            (offset <  IO_LAN91C111_BASE + IO_LAN91C111_EXTENT)) {
+                        /*
+                         *      SMSC LAN91C111 Ethernet chip
+                         */
+                result = IO_LAN91C111_PHYS + offset - IO_LAN91C111_BASE;
+        } else if ((offset >= IO_SUPERIO_BASE) &&
+                   (offset <  IO_SUPERIO_BASE + IO_SUPERIO_EXTENT)) {
+                        /*
+                         *      SMSC FDC37C93xAPM SuperIO chip
+                         *
+                         *      Configuration Registers
+                         */
+                result = IO_SUPERIO_PHYS + (offset << 1);
+#if 0
+        } else if (offset == KBD_DATA_REG || offset == KBD_CNTL_REG ||
+                   offset == KBD_STATUS_REG) {
+                        /*
+                         *      SMSC FDC37C93xAPM SuperIO chip
+                         *
+                         *      PS/2 Keyboard + Mouse (ports 0x60 and 0x64).
+                         */
+                result = IO_SUPERIO_PHYS + (offset << 1);
+#endif
+        } else if (((offset >= IO_IDE1_BASE) &&
+                    (offset <  IO_IDE1_BASE + IO_IDE_EXTENT)) ||
+                    (offset == IO_IDE1_MISC)) {
+                        /*
+                         *      SMSC FDC37C93xAPM SuperIO chip
+                         *
+                         *      IDE #1
+                         */
+                result = IO_SUPERIO_PHYS + (offset << 1);
+        } else if (((offset >= IO_IDE2_BASE) &&
+                    (offset <  IO_IDE2_BASE + IO_IDE_EXTENT)) ||
+                    (offset == IO_IDE2_MISC)) {
+                        /*
+                         *      SMSC FDC37C93xAPM SuperIO chip
+                         *
+                         *      IDE #2
+                         */
+                result = IO_SUPERIO_PHYS + (offset << 1);
+        } else if ((offset >= IO_SERIAL1_BASE) &&
+                   (offset <  IO_SERIAL1_BASE + IO_SERIAL_EXTENT)) {
+                        /*
+                         *      SMSC FDC37C93xAPM SuperIO chip
+                         *
+                         *      Serial #1
+                         */
+                result = IO_SUPERIO_PHYS + (offset << 1);
+        } else if ((offset >= IO_SERIAL2_BASE) &&
+                   (offset <  IO_SERIAL2_BASE + IO_SERIAL_EXTENT)) {
+                        /*
+                         *      SMSC FDC37C93xAPM SuperIO chip
+                         *
+                         *      Serial #2
+                         */
+                result = IO_SUPERIO_PHYS + (offset << 1);
+        } else if ((offset >= IO_ISP1161_BASE) &&
+                   (offset < IO_ISP1161_BASE + IO_ISP1161_EXTENT)) {
+                        /*
+                         *      Philips USB ISP1161x chip
+                         */
+                result = IO_ISP1161_PHYS + offset - IO_ISP1161_BASE;
+        } else {
+                        /*
+                         *      safe default.
+                         */
+                printk("Warning: unexpected port in %s( offset = 0x%lx )\n",
+                       __FUNCTION__, offset);
+                result = PVR;
+        }
+
+        return result;
+}
+
diff --git a/arch/sh/boards/superh/microdev/irq.c b/arch/sh/boards/superh/microdev/irq.c
new file mode 100644
index 000000000000..1298883eca4b
--- /dev/null
+++ b/arch/sh/boards/superh/microdev/irq.c
@@ -0,0 +1,200 @@
+/*
+ * arch/sh/boards/superh/microdev/irq.c
+ *
+ * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com)
+ *
+ * SuperH SH4-202 MicroDev board support.
+ *
+ * May be copied or modified under the terms of the GNU General Public
+ * License.  See linux/COPYING for more information.
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/mach/irq.h>
+
+#define NUM_EXTERNAL_IRQS 16    /* IRL0 .. IRL15 */
+
+
+static const struct {
+        unsigned char fpgaIrq;
+        unsigned char mapped;
+        const char *name;
+} fpgaIrqTable[NUM_EXTERNAL_IRQS] = {
+        { 0,                            0,      "unused"   },           /* IRQ #0       IRL=15  0x200  */
+        { MICRODEV_FPGA_IRQ_KEYBOARD,   1,      "keyboard" },           /* IRQ #1       IRL=14  0x220  */
+        { MICRODEV_FPGA_IRQ_SERIAL1,    1,      "Serial #1"},           /* IRQ #2       IRL=13  0x240  */
+        { MICRODEV_FPGA_IRQ_ETHERNET,   1,      "Ethernet" },           /* IRQ #3       IRL=12  0x260  */
+        { MICRODEV_FPGA_IRQ_SERIAL2,    0,      "Serial #2"},           /* IRQ #4       IRL=11  0x280  */
+        { 0,                            0,      "unused"   },           /* IRQ #5       IRL=10  0x2a0  */
+        { 0,                            0,      "unused"   },           /* IRQ #6       IRL=9   0x2c0  */
+        { MICRODEV_FPGA_IRQ_USB_HC,     1,      "USB"      },           /* IRQ #7       IRL=8   0x2e0  */
+        { MICRODEV_IRQ_PCI_INTA,        1,      "PCI INTA" },           /* IRQ #8       IRL=7   0x300  */
+        { MICRODEV_IRQ_PCI_INTB,        1,      "PCI INTB" },           /* IRQ #9       IRL=6   0x320  */
+        { MICRODEV_IRQ_PCI_INTC,        1,      "PCI INTC" },           /* IRQ #10      IRL=5   0x340  */
+        { MICRODEV_IRQ_PCI_INTD,        1,      "PCI INTD" },           /* IRQ #11      IRL=4   0x360  */
+        { MICRODEV_FPGA_IRQ_MOUSE,      1,      "mouse"    },           /* IRQ #12      IRL=3   0x380  */
+        { MICRODEV_FPGA_IRQ_IDE2,       1,      "IDE #2"   },           /* IRQ #13      IRL=2   0x3a0  */
+        { MICRODEV_FPGA_IRQ_IDE1,       1,      "IDE #1"   },           /* IRQ #14      IRL=1   0x3c0  */
+        { 0,                            0,      "unused"   },           /* IRQ #15      IRL=0   0x3e0  */
+};
+
+#if (MICRODEV_LINUX_IRQ_KEYBOARD != 1)
+#  error Inconsistancy in defining the IRQ# for Keyboard!
+#endif
+
+#if (MICRODEV_LINUX_IRQ_ETHERNET != 3)
+#  error Inconsistancy in defining the IRQ# for Ethernet!
+#endif
+
+#if (MICRODEV_LINUX_IRQ_USB_HC != 7)
+#  error Inconsistancy in defining the IRQ# for USB!
+#endif
+
+#if (MICRODEV_LINUX_IRQ_MOUSE != 12)
+#  error Inconsistancy in defining the IRQ# for PS/2 Mouse!
+#endif
+
+#if (MICRODEV_LINUX_IRQ_IDE2 != 13)
+#  error Inconsistancy in defining the IRQ# for secondary IDE!
+#endif
+
+#if (MICRODEV_LINUX_IRQ_IDE1 != 14)
+#  error Inconsistancy in defining the IRQ# for primary IDE!
+#endif
+
+static void enable_microdev_irq(unsigned int irq);
+static void disable_microdev_irq(unsigned int irq);
+
+        /* shutdown is same as "disable" */
+#define shutdown_microdev_irq disable_microdev_irq
+
+static void mask_and_ack_microdev(unsigned int);
+static void end_microdev_irq(unsigned int irq);
+
+static unsigned int startup_microdev_irq(unsigned int irq)
+{
+        enable_microdev_irq(irq);
+        return 0;               /* never anything pending */
+}
+
+static struct hw_interrupt_type microdev_irq_type = {
+        "MicroDev-IRQ",
+        startup_microdev_irq,
+        shutdown_microdev_irq,
+        enable_microdev_irq,
+        disable_microdev_irq,
+        mask_and_ack_microdev,
+        end_microdev_irq
+};
+
+static void disable_microdev_irq(unsigned int irq)
+{
+        unsigned int flags;
+        unsigned int fpgaIrq;
+
+        if (irq >= NUM_EXTERNAL_IRQS) return;
+        if (!fpgaIrqTable[irq].mapped) return;
+
+        fpgaIrq = fpgaIrqTable[irq].fpgaIrq;
+
+                /* disable interrupts */
+        local_irq_save(flags);
+
+                /* disable interupts on the FPGA INTC register */
+        ctrl_outl(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTDSB_REG);
+
+                /* restore interrupts */
+        local_irq_restore(flags);
+}
+
+static void enable_microdev_irq(unsigned int irq)
+{
+        unsigned long priorityReg, priorities, pri;
+        unsigned int flags;
+        unsigned int fpgaIrq;
+
+
+        if (irq >= NUM_EXTERNAL_IRQS) return;
+        if (!fpgaIrqTable[irq].mapped) return;
+
+        pri = 15 - irq;
+
+        fpgaIrq = fpgaIrqTable[irq].fpgaIrq;
+        priorityReg = MICRODEV_FPGA_INTPRI_REG(fpgaIrq);
+
+                /* disable interrupts */
+        local_irq_save(flags);
+
+                /* set priority for the interrupt */
+        priorities = ctrl_inl(priorityReg);
+        priorities &= ~MICRODEV_FPGA_INTPRI_MASK(fpgaIrq);
+        priorities |= MICRODEV_FPGA_INTPRI_LEVEL(fpgaIrq, pri);
+        ctrl_outl(priorities, priorityReg);
+
+                /* enable interupts on the FPGA INTC register */
+        ctrl_outl(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTENB_REG);
+
+                /* restore interrupts */
+        local_irq_restore(flags);
+}
+
+        /* This functions sets the desired irq handler to be a MicroDev type */
+static void __init make_microdev_irq(unsigned int irq)
+{
+        disable_irq_nosync(irq);
+        irq_desc[irq].handler = &microdev_irq_type;
+        disable_microdev_irq(irq);
+}
+
+static void mask_and_ack_microdev(unsigned int irq)
+{
+        disable_microdev_irq(irq);
+}
+
+static void end_microdev_irq(unsigned int irq)
+{
+        if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
+        {
+                enable_microdev_irq(irq);
+        }
+}
+
+extern void __init init_microdev_irq(void)
+{
+        int i;
+
+                /* disable interupts on the FPGA INTC register */
+        ctrl_outl(~0ul, MICRODEV_FPGA_INTDSB_REG);
+
+        for (i = 0; i < NUM_EXTERNAL_IRQS; i++)
+        {
+                make_microdev_irq(i);
+        }
+}
+
+extern void microdev_print_fpga_intc_status(void)
+{
+        volatile unsigned int * const intenb = (unsigned int*)MICRODEV_FPGA_INTENB_REG;
+        volatile unsigned int * const intdsb = (unsigned int*)MICRODEV_FPGA_INTDSB_REG;
+        volatile unsigned int * const intpria = (unsigned int*)MICRODEV_FPGA_INTPRI_REG(0);
+        volatile unsigned int * const intprib = (unsigned int*)MICRODEV_FPGA_INTPRI_REG(8);
+        volatile unsigned int * const intpric = (unsigned int*)MICRODEV_FPGA_INTPRI_REG(16);
+        volatile unsigned int * const intprid = (unsigned int*)MICRODEV_FPGA_INTPRI_REG(24);
+        volatile unsigned int * const intsrc = (unsigned int*)MICRODEV_FPGA_INTSRC_REG;
+        volatile unsigned int * const intreq = (unsigned int*)MICRODEV_FPGA_INTREQ_REG;
+
+        printk("-------------------------- microdev_print_fpga_intc_status() ------------------\n");
+        printk("FPGA_INTENB = 0x%08x\n", *intenb);
+        printk("FPGA_INTDSB = 0x%08x\n", *intdsb);
+        printk("FPGA_INTSRC = 0x%08x\n", *intsrc);
+        printk("FPGA_INTREQ = 0x%08x\n", *intreq);
+        printk("FPGA_INTPRI[3..0] = %08x:%08x:%08x:%08x\n", *intprid, *intpric, *intprib, *intpria);
+        printk("-------------------------------------------------------------------------------\n");
+}
+
+
diff --git a/arch/sh/boards/superh/microdev/led.c b/arch/sh/boards/superh/microdev/led.c
new file mode 100644
index 000000000000..52a98e69d3f0
--- /dev/null
+++ b/arch/sh/boards/superh/microdev/led.c
@@ -0,0 +1,102 @@
+/*
+ * linux/arch/sh/kernel/led_microdev.c
+ *
+ * Copyright (C) 2002 Stuart Menefy <stuart.menefy@st.com>
+ * Copyright (C) 2003 Richard Curnow (Richard.Curnow@superh.com)
+ *
+ * May be copied or modified under the terms of the GNU General Public
+ * License.  See linux/COPYING for more information.
+ *
+ */
+
+#include <linux/config.h>
+#include <asm/io.h>
+
+#define LED_REGISTER 0xa6104d20
+
+static void mach_led_d9(int value)
+{
+        unsigned long reg;
+        reg = ctrl_inl(LED_REGISTER);
+        reg &= ~1;
+        reg |= (value & 1);
+        ctrl_outl(reg, LED_REGISTER);
+        return;
+}
+
+static void mach_led_d10(int value)
+{
+        unsigned long reg;
+        reg = ctrl_inl(LED_REGISTER);
+        reg &= ~2;
+        reg |= ((value & 1) << 1);
+        ctrl_outl(reg, LED_REGISTER);
+        return;
+}
+
+
+#ifdef CONFIG_HEARTBEAT
+#include <linux/sched.h>
+
+static unsigned char banner_table[] = {
+        0x11, 0x01, 0x11, 0x01, 0x11, 0x03,
+        0x11, 0x01, 0x11, 0x01, 0x13, 0x03,
+        0x11, 0x01, 0x13, 0x01, 0x13, 0x01, 0x11, 0x03,
+        0x11, 0x03,
+        0x11, 0x01, 0x13, 0x01, 0x11, 0x03,
+        0x11, 0x01, 0x11, 0x01, 0x11, 0x01, 0x11, 0x07,
+        0x13, 0x01, 0x13, 0x03,
+        0x11, 0x01, 0x11, 0x03,
+        0x13, 0x01, 0x11, 0x01, 0x13, 0x01, 0x11, 0x03,
+        0x11, 0x01, 0x13, 0x01, 0x11, 0x03,
+        0x13, 0x01, 0x13, 0x01, 0x13, 0x03,
+        0x13, 0x01, 0x11, 0x01, 0x11, 0x03,
+        0x11, 0x03,
+        0x11, 0x01, 0x11, 0x01, 0x11, 0x01, 0x13, 0x07,
+        0xff
+};
+
+static void banner(void)
+{
+        static int pos = 0;
+        static int count = 0;
+
+        if (count) {
+                count--;
+        } else {
+                int val = banner_table[pos];
+                if (val == 0xff) {
+                        pos = 0;
+                        val = banner_table[pos];
+                }
+                pos++;
+                mach_led_d10((val >> 4) & 1);
+                count = 10 * (val & 0xf);
+        }
+}
+
+/* From heartbeat_harp in the stboards directory */
+/* acts like an actual heart beat -- ie thump-thump-pause... */
+void microdev_heartbeat(void)
+{
+        static unsigned cnt = 0, period = 0, dist = 0;
+
+        if (cnt == 0 || cnt == dist)
+                mach_led_d9(1);
+        else if (cnt == 7 || cnt == dist+7)
+                mach_led_d9(0);
+
+        if (++cnt > period) {
+                cnt = 0;
+                /* The hyperbolic function below modifies the heartbeat period
+                 * length in dependency of the current (5min) load. It goes
+                 * through the points f(0)=126, f(1)=86, f(5)=51,
+                 * f(inf)->30. */
+                period = ((672<<FSHIFT)/(5*avenrun[0]+(7<<FSHIFT))) + 30;
+                dist = period / 4;
+        }
+
+        banner();
+}
+
+#endif
diff --git a/arch/sh/boards/superh/microdev/setup.c b/arch/sh/boards/superh/microdev/setup.c
new file mode 100644
index 000000000000..c18919941ec0
--- /dev/null
+++ b/arch/sh/boards/superh/microdev/setup.c
@@ -0,0 +1,278 @@
+/*
+ * arch/sh/boards/superh/microdev/setup.c
+ *
+ * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com)
+ * Copyright (C) 2003, 2004 SuperH, Inc.
+ * Copyright (C) 2004 Paul Mundt
+ *
+ * SuperH SH4-202 MicroDev board support.
+ *
+ * May be copied or modified under the terms of the GNU General Public
+ * License.  See linux/COPYING for more information.
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/ioport.h>
+#include <asm/io.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/io.h>
+#include <asm/machvec.h>
+#include <asm/machvec_init.h>
+
+extern void microdev_heartbeat(void);
+
+/*
+ * The Machine Vector
+ */
+
+struct sh_machine_vector mv_sh4202_microdev __initmv = {
+        .mv_nr_irqs             = 72,           /* QQQ need to check this - use the MACRO */
+
+        .mv_inb                 = microdev_inb,
+        .mv_inw                 = microdev_inw,
+        .mv_inl                 = microdev_inl,
+        .mv_outb                = microdev_outb,
+        .mv_outw                = microdev_outw,
+        .mv_outl                = microdev_outl,
+
+        .mv_inb_p               = microdev_inb_p,
+        .mv_inw_p               = microdev_inw_p,
+        .mv_inl_p               = microdev_inl_p,
+        .mv_outb_p              = microdev_outb_p,
+        .mv_outw_p              = microdev_outw_p,
+        .mv_outl_p              = microdev_outl_p,
+
+        .mv_insb                = microdev_insb,
+        .mv_insw                = microdev_insw,
+        .mv_insl                = microdev_insl,
+        .mv_outsb               = microdev_outsb,
+        .mv_outsw               = microdev_outsw,
+        .mv_outsl               = microdev_outsl,
+
+        .mv_isa_port2addr       = microdev_isa_port2addr,
+
+        .mv_init_irq            = init_microdev_irq,
+
+#ifdef CONFIG_HEARTBEAT
+        .mv_heartbeat           = microdev_heartbeat,
+#endif
+};
+ALIAS_MV(sh4202_microdev)
+
+/****************************************************************************/
+
+
+        /*
+         * Setup for the SMSC FDC37C93xAPM
+         */
+#define SMSC_CONFIG_PORT_ADDR    (0x3F0)
+#define SMSC_INDEX_PORT_ADDR     SMSC_CONFIG_PORT_ADDR
+#define SMSC_DATA_PORT_ADDR      (SMSC_INDEX_PORT_ADDR + 1)
+
+#define SMSC_ENTER_CONFIG_KEY    0x55
+#define SMSC_EXIT_CONFIG_KEY     0xaa
+
+#define SMCS_LOGICAL_DEV_INDEX   0x07   /* Logical Device Number */
+#define SMSC_DEVICE_ID_INDEX     0x20   /* Device ID */
+#define SMSC_DEVICE_REV_INDEX    0x21   /* Device Revision */
+#define SMSC_ACTIVATE_INDEX      0x30   /* Activate */
+#define SMSC_PRIMARY_BASE_INDEX  0x60   /* Primary Base Address */
+#define SMSC_SECONDARY_BASE_INDEX 0x62  /* Secondary Base Address */
+#define SMSC_PRIMARY_INT_INDEX   0x70   /* Primary Interrupt Select */
+#define SMSC_SECONDARY_INT_INDEX 0x72   /* Secondary Interrupt Select */
+#define SMSC_HDCS0_INDEX         0xf0   /* HDCS0 Address Decoder */
+#define SMSC_HDCS1_INDEX         0xf1   /* HDCS1 Address Decoder */
+
+#define SMSC_IDE1_DEVICE        1       /* IDE #1 logical device */
+#define SMSC_IDE2_DEVICE        2       /* IDE #2 logical device */
+#define SMSC_PARALLEL_DEVICE    3       /* Parallel Port logical device */
+#define SMSC_SERIAL1_DEVICE     4       /* Serial #1 logical device */
+#define SMSC_SERIAL2_DEVICE     5       /* Serial #2 logical device */
+#define SMSC_KEYBOARD_DEVICE    7       /* Keyboard logical device */
+#define SMSC_CONFIG_REGISTERS   8       /* Configuration Registers (Aux I/O) */
+
+#define SMSC_READ_INDEXED(index) ({ \
+        outb((index), SMSC_INDEX_PORT_ADDR); \
+        inb(SMSC_DATA_PORT_ADDR); })
+#define SMSC_WRITE_INDEXED(val, index) ({ \
+        outb((index), SMSC_INDEX_PORT_ADDR); \
+        outb((val),   SMSC_DATA_PORT_ADDR); })
+
+#define IDE1_PRIMARY_BASE       0x01f0  /* Task File Registe base for IDE #1 */
+#define IDE1_SECONDARY_BASE     0x03f6  /* Miscellaneous AT registers for IDE #1 */
+#define IDE2_PRIMARY_BASE       0x0170  /* Task File Registe base for IDE #2 */
+#define IDE2_SECONDARY_BASE     0x0376  /* Miscellaneous AT registers for IDE #2 */
+
+#define SERIAL1_PRIMARY_BASE    0x03f8
+#define SERIAL2_PRIMARY_BASE    0x02f8
+
+#define MSB(x)          ( (x) >> 8 )
+#define LSB(x)          ( (x) & 0xff )
+
+        /* General-Purpose base address on CPU-board FPGA */
+#define MICRODEV_FPGA_GP_BASE           0xa6100000ul
+
+        /* assume a Keyboard Controller is present */
+int microdev_kbd_controller_present = 1;
+
+const char *get_system_type(void)
+{
+        return "SH4-202 MicroDev";
+}
+
+static struct resource smc91x_resources[] = {
+        [0] = {
+                .start          = 0x300,
+                .end            = 0x300 + 0x0001000 - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start          = MICRODEV_LINUX_IRQ_ETHERNET,
+                .end            = MICRODEV_LINUX_IRQ_ETHERNET,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device smc91x_device = {
+        .name           = "smc91x",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(smc91x_resources),
+        .resource       = smc91x_resources,
+};
+
+static int __init smc91x_setup(void)
+{
+        return platform_device_register(&smc91x_device);
+}
+
+__initcall(smc91x_setup);
+
+        /*
+         * Initialize the board
+         */
+void __init platform_setup(void)
+{
+        int * const fpgaRevisionRegister = (int*)(MICRODEV_FPGA_GP_BASE + 0x8ul);
+        const int fpgaRevision = *fpgaRevisionRegister;
+        int * const CacheControlRegister = (int*)CCR;
+
+        printk("SuperH %s board (FPGA rev: 0x%0x, CCR: 0x%0x)\n",
+                get_system_type(), fpgaRevision, *CacheControlRegister);
+}
+
+
+/****************************************************************************/
+
+
+        /*
+         * Setup for the SMSC FDC37C93xAPM
+         */
+static int __init smsc_superio_setup(void)
+{
+
+        unsigned char devid, devrev;
+
+                /* Initially the chip is in run state */
+                /* Put it into configuration state */
+        outb(SMSC_ENTER_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
+
+                /* Read device ID info */
+        devid  = SMSC_READ_INDEXED(SMSC_DEVICE_ID_INDEX);
+        devrev = SMSC_READ_INDEXED(SMSC_DEVICE_REV_INDEX);
+        if ( (devid==0x30) && (devrev==0x01) )
+        {
+                printk("SMSC FDC37C93xAPM SuperIO device detected\n");
+        }
+        else
+        {               /* not the device identity we expected */
+                printk("Not detected a SMSC FDC37C93xAPM SuperIO device (devid=0x%02x, rev=0x%02x)\n",
+                        devid, devrev);
+                        /* inform the keyboard driver that we have no keyboard controller */
+                microdev_kbd_controller_present = 0;
+                        /* little point in doing anything else in this functon */
+                return 0;
+        }
+
+                /* Select the keyboard device */
+        SMSC_WRITE_INDEXED(SMSC_KEYBOARD_DEVICE, SMCS_LOGICAL_DEV_INDEX);
+                /* enable it */
+        SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
+                /* enable the interrupts */
+        SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_KEYBOARD, SMSC_PRIMARY_INT_INDEX);
+        SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_MOUSE, SMSC_SECONDARY_INT_INDEX);
+
+                /* Select the Serial #1 device */
+        SMSC_WRITE_INDEXED(SMSC_SERIAL1_DEVICE, SMCS_LOGICAL_DEV_INDEX);
+                /* enable it */
+        SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
+                /* program with port addresses */
+        SMSC_WRITE_INDEXED(MSB(SERIAL1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
+        SMSC_WRITE_INDEXED(LSB(SERIAL1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
+        SMSC_WRITE_INDEXED(0x00, SMSC_HDCS0_INDEX);
+                /* enable the interrupts */
+        SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_SERIAL1, SMSC_PRIMARY_INT_INDEX);
+
+                /* Select the Serial #2 device */
+        SMSC_WRITE_INDEXED(SMSC_SERIAL2_DEVICE, SMCS_LOGICAL_DEV_INDEX);
+                /* enable it */
+        SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
+                /* program with port addresses */
+        SMSC_WRITE_INDEXED(MSB(SERIAL2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
+        SMSC_WRITE_INDEXED(LSB(SERIAL2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
+        SMSC_WRITE_INDEXED(0x00, SMSC_HDCS0_INDEX);
+                /* enable the interrupts */
+        SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_SERIAL2, SMSC_PRIMARY_INT_INDEX);
+
+                /* Select the IDE#1 device */
+        SMSC_WRITE_INDEXED(SMSC_IDE1_DEVICE, SMCS_LOGICAL_DEV_INDEX);
+                /* enable it */
+        SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
+                /* program with port addresses */
+        SMSC_WRITE_INDEXED(MSB(IDE1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
+        SMSC_WRITE_INDEXED(LSB(IDE1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
+        SMSC_WRITE_INDEXED(MSB(IDE1_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+0);
+        SMSC_WRITE_INDEXED(LSB(IDE1_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+1);
+        SMSC_WRITE_INDEXED(0x0c, SMSC_HDCS0_INDEX);
+        SMSC_WRITE_INDEXED(0x00, SMSC_HDCS1_INDEX);
+                /* select the interrupt */
+        SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_IDE1, SMSC_PRIMARY_INT_INDEX);
+
+                /* Select the IDE#2 device */
+        SMSC_WRITE_INDEXED(SMSC_IDE2_DEVICE, SMCS_LOGICAL_DEV_INDEX);
+                /* enable it */
+        SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
+                /* program with port addresses */
+        SMSC_WRITE_INDEXED(MSB(IDE2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
+        SMSC_WRITE_INDEXED(LSB(IDE2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
+        SMSC_WRITE_INDEXED(MSB(IDE2_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+0);
+        SMSC_WRITE_INDEXED(LSB(IDE2_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+1);
+                /* select the interrupt */
+        SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_IDE2, SMSC_PRIMARY_INT_INDEX);
+
+                /* Select the configuration registers */
+        SMSC_WRITE_INDEXED(SMSC_CONFIG_REGISTERS, SMCS_LOGICAL_DEV_INDEX);
+                /* enable the appropriate GPIO pins for IDE functionality:
+                 * bit[0]   In/Out              1==input;  0==output
+                 * bit[1]   Polarity            1==invert; 0==no invert
+                 * bit[2]   Int Enb #1          1==Enable Combined IRQ #1; 0==disable
+                 * bit[3:4] Function Select     00==original; 01==Alternate Function #1
+                 */
+        SMSC_WRITE_INDEXED(0x00, 0xc2); /* GP42 = nIDE1_OE */
+        SMSC_WRITE_INDEXED(0x01, 0xc5); /* GP45 = IDE1_IRQ */
+        SMSC_WRITE_INDEXED(0x00, 0xc6); /* GP46 = nIOROP */
+        SMSC_WRITE_INDEXED(0x00, 0xc7); /* GP47 = nIOWOP */
+        SMSC_WRITE_INDEXED(0x08, 0xe8); /* GP20 = nIDE2_OE */
+
+                /* Exit the configuraton state */
+        outb(SMSC_EXIT_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
+
+        return 0;
+}
+
+
+/* This is grotty, but, because kernel is always referenced on the link line
+ * before any devices, this is safe.
+ */
+__initcall(smsc_superio_setup);