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authorIngo Molnar <mingo@elte.hu>2008-07-28 17:32:00 -0400
committerIngo Molnar <mingo@elte.hu>2008-07-28 17:32:00 -0400
commit9e3ee1c39c0cc71222f9980ccbf87fe072897eef (patch)
tree99462000e6f0d4f907cb2fc690f19d4d441ba0f3 /arch/sh/boards/se
parente56b3bc7942982ac2589c942fb345e38bc7a341a (diff)
parentf934fb19ef34730263e6afc01e8ec27a8a71470f (diff)
Merge branch 'linus' into cpus4096
Conflicts: kernel/stop_machine.c Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/sh/boards/se')
-rw-r--r--arch/sh/boards/se/7343/irq.c232
-rw-r--r--arch/sh/boards/se/7343/setup.c70
-rw-r--r--arch/sh/boards/se/770x/io.c59
-rw-r--r--arch/sh/boards/se/770x/setup.c53
-rw-r--r--arch/sh/boards/se/7722/setup.c8
5 files changed, 186 insertions, 236 deletions
diff --git a/arch/sh/boards/se/7343/irq.c b/arch/sh/boards/se/7343/irq.c
index 763f6deba814..1112e86aa93a 100644
--- a/arch/sh/boards/se/7343/irq.c
+++ b/arch/sh/boards/se/7343/irq.c
@@ -1,202 +1,80 @@
1/* 1/*
2 * arch/sh/boards/se/7343/irq.c 2 * linux/arch/sh/boards/se/7343/irq.c
3 * 3 *
4 * Copyright (C) 2008 Yoshihiro Shimoda
5 *
6 * Based on linux/arch/sh/boards/se/7722/irq.c
7 * Copyright (C) 2007 Nobuhiro Iwamatsu
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
4 */ 12 */
5#include <linux/init.h> 13#include <linux/init.h>
6#include <linux/interrupt.h>
7#include <linux/irq.h> 14#include <linux/irq.h>
15#include <linux/interrupt.h>
8#include <asm/irq.h> 16#include <asm/irq.h>
9#include <asm/io.h> 17#include <asm/io.h>
10#include <asm/mach/se7343.h> 18#include <asm/se7343.h>
11 19
12static void 20static void disable_se7343_irq(unsigned int irq)
13disable_intreq_irq(unsigned int irq)
14{ 21{
15 int bit = irq - OFFCHIP_IRQ_BASE; 22 unsigned int bit = irq - SE7343_FPGA_IRQ_BASE;
16 u16 val; 23 ctrl_outw(ctrl_inw(PA_CPLD_IMSK) | 1 << bit, PA_CPLD_IMSK);
17
18 val = ctrl_inw(PA_CPLD_IMSK);
19 val |= 1 << bit;
20 ctrl_outw(val, PA_CPLD_IMSK);
21} 24}
22 25
23static void 26static void enable_se7343_irq(unsigned int irq)
24enable_intreq_irq(unsigned int irq)
25{ 27{
26 int bit = irq - OFFCHIP_IRQ_BASE; 28 unsigned int bit = irq - SE7343_FPGA_IRQ_BASE;
27 u16 val; 29 ctrl_outw(ctrl_inw(PA_CPLD_IMSK) & ~(1 << bit), PA_CPLD_IMSK);
28
29 val = ctrl_inw(PA_CPLD_IMSK);
30 val &= ~(1 << bit);
31 ctrl_outw(val, PA_CPLD_IMSK);
32} 30}
33 31
34static void 32static struct irq_chip se7343_irq_chip __read_mostly = {
35mask_and_ack_intreq_irq(unsigned int irq) 33 .name = "SE7343-FPGA",
36{ 34 .mask = disable_se7343_irq,
37 disable_intreq_irq(irq); 35 .unmask = enable_se7343_irq,
38} 36 .mask_ack = disable_se7343_irq,
39
40static unsigned int
41startup_intreq_irq(unsigned int irq)
42{
43 enable_intreq_irq(irq);
44 return 0;
45}
46
47static void
48shutdown_intreq_irq(unsigned int irq)
49{
50 disable_intreq_irq(irq);
51}
52
53static void
54end_intreq_irq(unsigned int irq)
55{
56 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
57 enable_intreq_irq(irq);
58}
59
60static struct hw_interrupt_type intreq_irq_type = {
61 .typename = "FPGA-IRQ",
62 .startup = startup_intreq_irq,
63 .shutdown = shutdown_intreq_irq,
64 .enable = enable_intreq_irq,
65 .disable = disable_intreq_irq,
66 .ack = mask_and_ack_intreq_irq,
67 .end = end_intreq_irq
68}; 37};
69 38
70static void 39static void se7343_irq_demux(unsigned int irq, struct irq_desc *desc)
71make_intreq_irq(unsigned int irq)
72{
73 disable_irq_nosync(irq);
74 irq_desc[irq].chip = &intreq_irq_type;
75 disable_intreq_irq(irq);
76}
77
78int
79shmse_irq_demux(int irq)
80{ 40{
81 int bit; 41 unsigned short intv = ctrl_inw(PA_CPLD_ST);
82 volatile u16 val; 42 struct irq_desc *ext_desc;
83 43 unsigned int ext_irq = SE7343_FPGA_IRQ_BASE;
84 if (irq == IRQ5_IRQ) { 44
85 /* Read status Register */ 45 intv &= (1 << SE7343_FPGA_IRQ_NR) - 1;
86 val = ctrl_inw(PA_CPLD_ST); 46
87 bit = ffs(val); 47 while (intv) {
88 if (bit != 0) 48 if (intv & 1) {
89 return OFFCHIP_IRQ_BASE + bit - 1; 49 ext_desc = irq_desc + ext_irq;
50 handle_level_irq(ext_irq, ext_desc);
51 }
52 intv >>= 1;
53 ext_irq++;
90 } 54 }
91 return irq;
92} 55}
93 56
94/* IRQ5 is multiplexed between the following sources:
95 * 1. PC Card socket
96 * 2. Extension slot
97 * 3. USB Controller
98 * 4. Serial Controller
99 *
100 * We configure IRQ5 as a cascade IRQ.
101 */
102static struct irqaction irq5 = {
103 .handler = no_action,
104 .mask = CPU_MASK_NONE,
105 .name = "IRQ5-cascade",
106};
107
108static struct ipr_data se7343_irq5_ipr_map[] = {
109 { IRQ5_IRQ, IRQ5_IPR_ADDR+2, IRQ5_IPR_POS, IRQ5_PRIORITY },
110};
111static struct ipr_data se7343_siof0_vpu_ipr_map[] = {
112 { SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY },
113 { VPU_IRQ, VPU_IPR_ADDR, VPU_IPR_POS, 8 },
114};
115static struct ipr_data se7343_other_ipr_map[] = {
116 { DMTE0_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
117 { DMTE1_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
118 { DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
119 { DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
120 { DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY },
121 { DMTE5_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY },
122
123 /* I2C block */
124 { IIC0_ALI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
125 { IIC0_TACKI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
126 { IIC0_WAITI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
127 { IIC0_DTEI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
128
129 { IIC1_ALI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY },
130 { IIC1_TACKI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY },
131 { IIC1_WAITI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY },
132 { IIC1_DTEI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY },
133
134 /* SIOF */
135 { SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY },
136
137 /* SIU */
138 { SIU_IRQ, SIU_IPR_ADDR, SIU_IPR_POS, SIU_PRIORITY },
139
140 /* VIO interrupt */
141 { CEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
142 { BEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
143 { VEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
144
145 /*MFI interrupt*/
146
147 { MFI_IRQ, MFI_IPR_ADDR, MFI_IPR_POS, MFI_PRIORITY },
148
149 /* LCD controller */
150 { LCDC_IRQ, LCDC_IPR_ADDR, LCDC_IPR_POS, LCDC_PRIORITY },
151};
152
153/* 57/*
154 * Initialize IRQ setting 58 * Initialize IRQ setting
155 */ 59 */
156void __init 60void __init init_7343se_IRQ(void)
157init_7343se_IRQ(void)
158{ 61{
159 /* Setup Multiplexed interrupts */ 62 int i;
160 ctrl_outw(8, PA_CPLD_MODESET); /* Set all CPLD interrupts to active 63
161 * low. 64 ctrl_outw(0, PA_CPLD_IMSK); /* disable all irqs */
162 */ 65 ctrl_outw(0x2000, 0xb03fffec); /* mrshpc irq enable */
163 /* Mask all CPLD controller interrupts */ 66
164 ctrl_outw(0x0fff, PA_CPLD_IMSK); 67 for (i = 0; i < SE7343_FPGA_IRQ_NR; i++)
165 68 set_irq_chip_and_handler_name(SE7343_FPGA_IRQ_BASE + i,
166 /* PC Card interrupts */ 69 &se7343_irq_chip,
167 make_intreq_irq(PC_IRQ0); 70 handle_level_irq, "level");
168 make_intreq_irq(PC_IRQ1); 71
169 make_intreq_irq(PC_IRQ2); 72 set_irq_chained_handler(IRQ0_IRQ, se7343_irq_demux);
170 make_intreq_irq(PC_IRQ3); 73 set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
171 74 set_irq_chained_handler(IRQ1_IRQ, se7343_irq_demux);
172 /* Extension Slot Interrupts */ 75 set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
173 make_intreq_irq(EXT_IRQ0); 76 set_irq_chained_handler(IRQ4_IRQ, se7343_irq_demux);
174 make_intreq_irq(EXT_IRQ1); 77 set_irq_type(IRQ4_IRQ, IRQ_TYPE_LEVEL_LOW);
175 make_intreq_irq(EXT_IRQ2); 78 set_irq_chained_handler(IRQ5_IRQ, se7343_irq_demux);
176 make_intreq_irq(EXT_IRQ3); 79 set_irq_type(IRQ5_IRQ, IRQ_TYPE_LEVEL_LOW);
177
178 /* USB Controller interrupts */
179 make_intreq_irq(USB_IRQ0);
180 make_intreq_irq(USB_IRQ1);
181
182 /* Serial Controller interrupts */
183 make_intreq_irq(UART_IRQ0);
184 make_intreq_irq(UART_IRQ1);
185
186 /* Setup all external interrupts to be active low */
187 ctrl_outw(0xaaaa, INTC_ICR1);
188
189 make_ipr_irq(se7343_irq5_ipr_map, ARRAY_SIZE(se7343_irq5_ipr_map));
190
191 setup_irq(IRQ5_IRQ, &irq5);
192 /* Set port control to use IRQ5 */
193 *(u16 *)0xA4050108 &= ~0xc;
194
195 make_ipr_irq(se7343_siof0_vpu_ipr_map, ARRAY_SIZE(se7343_siof0_vpu_ipr_map));
196
197 ctrl_outb(0x0f, INTC_IMCR5); /* enable SCIF IRQ */
198
199 make_ipr_irq(se7343_other_ipr_map, ARRAY_SIZE(se7343_other_ipr_map));
200
201 ctrl_outw(0x2000, PA_MRSHPC + 0x0c); /* mrshpc irq enable */
202} 80}
diff --git a/arch/sh/boards/se/7343/setup.c b/arch/sh/boards/se/7343/setup.c
index c9431b3a051b..8ae718d6c710 100644
--- a/arch/sh/boards/se/7343/setup.c
+++ b/arch/sh/boards/se/7343/setup.c
@@ -1,10 +1,11 @@
1#include <linux/init.h> 1#include <linux/init.h>
2#include <linux/platform_device.h> 2#include <linux/platform_device.h>
3#include <linux/mtd/physmap.h>
3#include <asm/machvec.h> 4#include <asm/machvec.h>
4#include <asm/mach/se7343.h> 5#include <asm/mach/se7343.h>
6#include <asm/heartbeat.h>
5#include <asm/irq.h> 7#include <asm/irq.h>
6 8#include <asm/io.h>
7void init_7343se_IRQ(void);
8 9
9static struct resource smc91x_resources[] = { 10static struct resource smc91x_resources[] = {
10 [0] = { 11 [0] = {
@@ -17,8 +18,8 @@ static struct resource smc91x_resources[] = {
17 * shared with other devices via externel 18 * shared with other devices via externel
18 * interrupt controller in FPGA... 19 * interrupt controller in FPGA...
19 */ 20 */
20 .start = EXT_IRQ2, 21 .start = SMC_IRQ,
21 .end = EXT_IRQ2, 22 .end = SMC_IRQ,
22 .flags = IORESOURCE_IRQ, 23 .flags = IORESOURCE_IRQ,
23 }, 24 },
24}; 25};
@@ -38,16 +39,65 @@ static struct resource heartbeat_resources[] = {
38 }, 39 },
39}; 40};
40 41
42static struct heartbeat_data heartbeat_data = {
43 .regsize = 16,
44};
45
41static struct platform_device heartbeat_device = { 46static struct platform_device heartbeat_device = {
42 .name = "heartbeat", 47 .name = "heartbeat",
43 .id = -1, 48 .id = -1,
49 .dev = {
50 .platform_data = &heartbeat_data,
51 },
44 .num_resources = ARRAY_SIZE(heartbeat_resources), 52 .num_resources = ARRAY_SIZE(heartbeat_resources),
45 .resource = heartbeat_resources, 53 .resource = heartbeat_resources,
46}; 54};
47 55
56static struct mtd_partition nor_flash_partitions[] = {
57 {
58 .name = "loader",
59 .offset = 0x00000000,
60 .size = 128 * 1024,
61 },
62 {
63 .name = "rootfs",
64 .offset = MTDPART_OFS_APPEND,
65 .size = 31 * 1024 * 1024,
66 },
67 {
68 .name = "data",
69 .offset = MTDPART_OFS_APPEND,
70 .size = MTDPART_SIZ_FULL,
71 },
72};
73
74static struct physmap_flash_data nor_flash_data = {
75 .width = 2,
76 .parts = nor_flash_partitions,
77 .nr_parts = ARRAY_SIZE(nor_flash_partitions),
78};
79
80static struct resource nor_flash_resources[] = {
81 [0] = {
82 .start = 0x00000000,
83 .end = 0x01ffffff,
84 .flags = IORESOURCE_MEM,
85 }
86};
87
88static struct platform_device nor_flash_device = {
89 .name = "physmap-flash",
90 .dev = {
91 .platform_data = &nor_flash_data,
92 },
93 .num_resources = ARRAY_SIZE(nor_flash_resources),
94 .resource = nor_flash_resources,
95};
96
48static struct platform_device *sh7343se_platform_devices[] __initdata = { 97static struct platform_device *sh7343se_platform_devices[] __initdata = {
49 &smc91x_device, 98 &smc91x_device,
50 &heartbeat_device, 99 &heartbeat_device,
100 &nor_flash_device,
51}; 101};
52 102
53static int __init sh7343se_devices_setup(void) 103static int __init sh7343se_devices_setup(void)
@@ -55,10 +105,19 @@ static int __init sh7343se_devices_setup(void)
55 return platform_add_devices(sh7343se_platform_devices, 105 return platform_add_devices(sh7343se_platform_devices,
56 ARRAY_SIZE(sh7343se_platform_devices)); 106 ARRAY_SIZE(sh7343se_platform_devices));
57} 107}
108device_initcall(sh7343se_devices_setup);
58 109
110/*
111 * Initialize the board
112 */
59static void __init sh7343se_setup(char **cmdline_p) 113static void __init sh7343se_setup(char **cmdline_p)
60{ 114{
61 device_initcall(sh7343se_devices_setup); 115 ctrl_outw(0xf900, FPGA_OUT); /* FPGA */
116
117 ctrl_outw(0x0002, PORT_PECR); /* PORT E 1 = IRQ5 */
118 ctrl_outw(0x0020, PORT_PSELD);
119
120 printk(KERN_INFO "MS7343CP01 Setup...done\n");
62} 121}
63 122
64/* 123/*
@@ -90,5 +149,4 @@ static struct sh_machine_vector mv_7343se __initmv = {
90 .mv_outsl = sh7343se_outsl, 149 .mv_outsl = sh7343se_outsl,
91 150
92 .mv_init_irq = init_7343se_IRQ, 151 .mv_init_irq = init_7343se_IRQ,
93 .mv_irq_demux = shmse_irq_demux,
94}; 152};
diff --git a/arch/sh/boards/se/770x/io.c b/arch/sh/boards/se/770x/io.c
index c4550473d4c3..b1ec085b8673 100644
--- a/arch/sh/boards/se/770x/io.c
+++ b/arch/sh/boards/se/770x/io.c
@@ -1,25 +1,13 @@
1/* $Id: io.c,v 1.7 2006/02/05 21:55:29 lethal Exp $ 1/*
2 *
3 * linux/arch/sh/kernel/io_se.c
4 *
5 * Copyright (C) 2000 Kazumoto Kojima 2 * Copyright (C) 2000 Kazumoto Kojima
6 * 3 *
7 * I/O routine for Hitachi SolutionEngine. 4 * I/O routine for Hitachi SolutionEngine.
8 *
9 */ 5 */
10
11#include <linux/kernel.h> 6#include <linux/kernel.h>
12#include <linux/types.h> 7#include <linux/types.h>
13#include <asm/io.h> 8#include <asm/io.h>
14#include <asm/se.h> 9#include <asm/se.h>
15 10
16/* SH pcmcia io window base, start and end. */
17int sh_pcic_io_wbase = 0xb8400000;
18int sh_pcic_io_start;
19int sh_pcic_io_stop;
20int sh_pcic_io_type;
21int sh_pcic_io_dummy;
22
23/* MS7750 requires special versions of in*, out* routines, since 11/* MS7750 requires special versions of in*, out* routines, since
24 PC-like io ports are located at upper half byte of 16-bit word which 12 PC-like io ports are located at upper half byte of 16-bit word which
25 can be accessed only with 16-bit wide. */ 13 can be accessed only with 16-bit wide. */
@@ -33,8 +21,6 @@ port2adr(unsigned int port)
33 return (volatile __u16 *) (PA_MRSHPC + (port - 0x2000)); 21 return (volatile __u16 *) (PA_MRSHPC + (port - 0x2000));
34 else if (port >= 0x1000) 22 else if (port >= 0x1000)
35 return (volatile __u16 *) (PA_83902 + (port << 1)); 23 return (volatile __u16 *) (PA_83902 + (port << 1));
36 else if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop)
37 return (volatile __u16 *) (sh_pcic_io_wbase + (port &~ 1));
38 else 24 else
39 return (volatile __u16 *) (PA_SUPERIO + (port << 1)); 25 return (volatile __u16 *) (PA_SUPERIO + (port << 1));
40} 26}
@@ -51,32 +37,27 @@ shifted_port(unsigned long port)
51 37
52unsigned char se_inb(unsigned long port) 38unsigned char se_inb(unsigned long port)
53{ 39{
54 if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop) 40 if (shifted_port(port))
55 return *(__u8 *) (sh_pcic_io_wbase + 0x40000 + port); 41 return (*port2adr(port) >> 8);
56 else if (shifted_port(port))
57 return (*port2adr(port) >> 8);
58 else 42 else
59 return (*port2adr(port))&0xff; 43 return (*port2adr(port))&0xff;
60} 44}
61 45
62unsigned char se_inb_p(unsigned long port) 46unsigned char se_inb_p(unsigned long port)
63{ 47{
64 unsigned long v; 48 unsigned long v;
65 49
66 if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop) 50 if (shifted_port(port))
67 v = *(__u8 *) (sh_pcic_io_wbase + 0x40000 + port); 51 v = (*port2adr(port) >> 8);
68 else if (shifted_port(port))
69 v = (*port2adr(port) >> 8);
70 else 52 else
71 v = (*port2adr(port))&0xff; 53 v = (*port2adr(port))&0xff;
72 ctrl_delay(); 54 ctrl_delay();
73 return v; 55 return v;
74} 56}
75 57
76unsigned short se_inw(unsigned long port) 58unsigned short se_inw(unsigned long port)
77{ 59{
78 if (port >= 0x2000 || 60 if (port >= 0x2000)
79 (sh_pcic_io_start <= port && port <= sh_pcic_io_stop))
80 return *port2adr(port); 61 return *port2adr(port);
81 else 62 else
82 maybebadio(port); 63 maybebadio(port);
@@ -91,9 +72,7 @@ unsigned int se_inl(unsigned long port)
91 72
92void se_outb(unsigned char value, unsigned long port) 73void se_outb(unsigned char value, unsigned long port)
93{ 74{
94 if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop) 75 if (shifted_port(port))
95 *(__u8 *)(sh_pcic_io_wbase + port) = value;
96 else if (shifted_port(port))
97 *(port2adr(port)) = value << 8; 76 *(port2adr(port)) = value << 8;
98 else 77 else
99 *(port2adr(port)) = value; 78 *(port2adr(port)) = value;
@@ -101,9 +80,7 @@ void se_outb(unsigned char value, unsigned long port)
101 80
102void se_outb_p(unsigned char value, unsigned long port) 81void se_outb_p(unsigned char value, unsigned long port)
103{ 82{
104 if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop) 83 if (shifted_port(port))
105 *(__u8 *)(sh_pcic_io_wbase + port) = value;
106 else if (shifted_port(port))
107 *(port2adr(port)) = value << 8; 84 *(port2adr(port)) = value << 8;
108 else 85 else
109 *(port2adr(port)) = value; 86 *(port2adr(port)) = value;
@@ -112,8 +89,7 @@ void se_outb_p(unsigned char value, unsigned long port)
112 89
113void se_outw(unsigned short value, unsigned long port) 90void se_outw(unsigned short value, unsigned long port)
114{ 91{
115 if (port >= 0x2000 || 92 if (port >= 0x2000)
116 (sh_pcic_io_start <= port && port <= sh_pcic_io_stop))
117 *port2adr(port) = value; 93 *port2adr(port) = value;
118 else 94 else
119 maybebadio(port); 95 maybebadio(port);
@@ -129,11 +105,7 @@ void se_insb(unsigned long port, void *addr, unsigned long count)
129 volatile __u16 *p = port2adr(port); 105 volatile __u16 *p = port2adr(port);
130 __u8 *ap = addr; 106 __u8 *ap = addr;
131 107
132 if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop) { 108 if (shifted_port(port)) {
133 volatile __u8 *bp = (__u8 *) (sh_pcic_io_wbase + 0x40000 + port);
134 while (count--)
135 *ap++ = *bp;
136 } else if (shifted_port(port)) {
137 while (count--) 109 while (count--)
138 *ap++ = *p >> 8; 110 *ap++ = *p >> 8;
139 } else { 111 } else {
@@ -160,11 +132,7 @@ void se_outsb(unsigned long port, const void *addr, unsigned long count)
160 volatile __u16 *p = port2adr(port); 132 volatile __u16 *p = port2adr(port);
161 const __u8 *ap = addr; 133 const __u8 *ap = addr;
162 134
163 if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop) { 135 if (shifted_port(port)) {
164 volatile __u8 *bp = (__u8 *) (sh_pcic_io_wbase + port);
165 while (count--)
166 *bp = *ap++;
167 } else if (shifted_port(port)) {
168 while (count--) 136 while (count--)
169 *p = *ap++ << 8; 137 *p = *ap++ << 8;
170 } else { 138 } else {
@@ -177,6 +145,7 @@ void se_outsw(unsigned long port, const void *addr, unsigned long count)
177{ 145{
178 volatile __u16 *p = port2adr(port); 146 volatile __u16 *p = port2adr(port);
179 const __u16 *ap = addr; 147 const __u16 *ap = addr;
148
180 while (count--) 149 while (count--)
181 *p = *ap++; 150 *p = *ap++;
182} 151}
diff --git a/arch/sh/boards/se/770x/setup.c b/arch/sh/boards/se/770x/setup.c
index 318bc8a3969c..cf4a5ba12df4 100644
--- a/arch/sh/boards/se/770x/setup.c
+++ b/arch/sh/boards/se/770x/setup.c
@@ -14,8 +14,6 @@
14#include <asm/smc37c93x.h> 14#include <asm/smc37c93x.h>
15#include <asm/heartbeat.h> 15#include <asm/heartbeat.h>
16 16
17void init_se_IRQ(void);
18
19/* 17/*
20 * Configure the Super I/O chip 18 * Configure the Super I/O chip
21 */ 19 */
@@ -73,7 +71,7 @@ static struct resource cf_ide_resources[] = {
73 }, 71 },
74 [1] = { 72 [1] = {
75 .start = PA_MRSHPC_IO + 0x1f0 + 0x206, 73 .start = PA_MRSHPC_IO + 0x1f0 + 0x206,
76 .end = PA_MRSHPC_IO + 0x1f0 +8 + 0x206 + 8, 74 .end = PA_MRSHPC_IO + 0x1f0 + 8 + 0x206 + 8,
77 .flags = IORESOURCE_MEM, 75 .flags = IORESOURCE_MEM,
78 }, 76 },
79 [2] = { 77 [2] = {
@@ -115,9 +113,58 @@ static struct platform_device heartbeat_device = {
115 .resource = heartbeat_resources, 113 .resource = heartbeat_resources,
116}; 114};
117 115
116/* SH771X Ethernet driver */
117static struct resource sh_eth0_resources[] = {
118 [0] = {
119 .start = SH_ETH0_BASE,
120 .end = SH_ETH0_BASE + 0x1B8,
121 .flags = IORESOURCE_MEM,
122 },
123 [1] = {
124 .start = SH_ETH0_IRQ,
125 .end = SH_ETH0_IRQ,
126 .flags = IORESOURCE_IRQ,
127 },
128};
129
130static struct platform_device sh_eth0_device = {
131 .name = "sh-eth",
132 .id = 0,
133 .dev = {
134 .platform_data = PHY_ID,
135 },
136 .num_resources = ARRAY_SIZE(sh_eth0_resources),
137 .resource = sh_eth0_resources,
138};
139
140static struct resource sh_eth1_resources[] = {
141 [0] = {
142 .start = SH_ETH1_BASE,
143 .end = SH_ETH1_BASE + 0x1B8,
144 .flags = IORESOURCE_MEM,
145 },
146 [1] = {
147 .start = SH_ETH1_IRQ,
148 .end = SH_ETH1_IRQ,
149 .flags = IORESOURCE_IRQ,
150 },
151};
152
153static struct platform_device sh_eth1_device = {
154 .name = "sh-eth",
155 .id = 1,
156 .dev = {
157 .platform_data = PHY_ID,
158 },
159 .num_resources = ARRAY_SIZE(sh_eth1_resources),
160 .resource = sh_eth1_resources,
161};
162
118static struct platform_device *se_devices[] __initdata = { 163static struct platform_device *se_devices[] __initdata = {
119 &heartbeat_device, 164 &heartbeat_device,
120 &cf_ide_device, 165 &cf_ide_device,
166 &sh_eth0_device,
167 &sh_eth1_device,
121}; 168};
122 169
123static int __init se_devices_setup(void) 170static int __init se_devices_setup(void)
diff --git a/arch/sh/boards/se/7722/setup.c b/arch/sh/boards/se/7722/setup.c
index ede3957fc14a..6e228ea59788 100644
--- a/arch/sh/boards/se/7722/setup.c
+++ b/arch/sh/boards/se/7722/setup.c
@@ -16,6 +16,7 @@
16#include <linux/input.h> 16#include <linux/input.h>
17#include <linux/smc91x.h> 17#include <linux/smc91x.h>
18#include <asm/machvec.h> 18#include <asm/machvec.h>
19#include <asm/clock.h>
19#include <asm/se7722.h> 20#include <asm/se7722.h>
20#include <asm/io.h> 21#include <asm/io.h>
21#include <asm/heartbeat.h> 22#include <asm/heartbeat.h>
@@ -145,6 +146,8 @@ static struct platform_device *se7722_devices[] __initdata = {
145 146
146static int __init se7722_devices_setup(void) 147static int __init se7722_devices_setup(void)
147{ 148{
149 clk_always_enable("mstp214"); /* KEYSC */
150
148 return platform_add_devices(se7722_devices, 151 return platform_add_devices(se7722_devices,
149 ARRAY_SIZE(se7722_devices)); 152 ARRAY_SIZE(se7722_devices));
150} 153}
@@ -154,11 +157,6 @@ static void __init se7722_setup(char **cmdline_p)
154{ 157{
155 ctrl_outw(0x010D, FPGA_OUT); /* FPGA */ 158 ctrl_outw(0x010D, FPGA_OUT); /* FPGA */
156 159
157 ctrl_outl(0x00051001, MSTPCR0);
158 ctrl_outl(0x00000000, MSTPCR1);
159 /* KEYSC, VOU, BEU, CEU, VEU, VPU, LCDC, USB */
160 ctrl_outl(0xffffb7c0, MSTPCR2);
161
162 ctrl_outw(0x0000, PORT_PECR); /* PORT E 1 = IRQ5 ,E 0 = BS */ 160 ctrl_outw(0x0000, PORT_PECR); /* PORT E 1 = IRQ5 ,E 0 = BS */
163 ctrl_outw(0x1000, PORT_PJCR); /* PORT J 1 = IRQ1,J 0 =IRQ0 */ 161 ctrl_outw(0x1000, PORT_PJCR); /* PORT J 1 = IRQ1,J 0 =IRQ0 */
164 162
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-21 05:35:20 -0400