sh: intc - shared IPR and INTC2 controller

This is the second version of the shared interrupt controller patch
for the sh architecture, fixing up handling of intc_reg_fns[].

The three main advantages with this controller over the existing
ones are:

	- Both priority (ipr) and bitmap (intc2) registers are
	  supported
	- External pin sense configuration is supported, ie edge
	  vs level triggered
	- CPU/Board specific code maps 1:1 with datasheet for
	  easy verification

This controller can easily coexist with the current IPR and INTC2
controllers, but the idea is that CPUs/Boards should be moved over
to this controller over time so we have a single code base to
maintain.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

1 files changed, 3 insertions, 0 deletions

diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index d8ed6676ae86..3ac6db263ed8 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -178,6 +178,9 @@ config CPU_HAS_PINT_IRQ
 config CPU_HAS_MASKREG_IRQ
         bool
 
+config CPU_HAS_INTC_IRQ
+        bool
+
 config CPU_HAS_INTC2_IRQ
         bool