Merge branch 'for-2.6.24' of master.kernel.org:/pub/scm/linux/kernel/git/jwboyer/powerpc-4xx into merge

10 files changed, 68 insertions, 23 deletions

diff --git a/arch/ppc/kernel/entry.S b/arch/ppc/kernel/entry.S
index fba7ca17a67e..b19bfef2034d 100644
--- a/arch/ppc/kernel/entry.S
+++ b/arch/ppc/kernel/entry.S
@@ -244,6 +244,13 @@ syscall_exit_cont:
         andis.  r10,r0,DBCR0_IC@h
         bnel-   load_dbcr0
 #endif
+#ifdef CONFIG_44x
+        lis     r4,icache_44x_need_flush@ha
+        lwz     r5,icache_44x_need_flush@l(r4)
+        cmplwi  cr0,r5,0
+        bne-    2f
+1:
+#endif /* CONFIG_44x */
         stwcx.  r0,0,r1                 /* to clear the reservation */
         lwz     r4,_LINK(r1)
         lwz     r5,_CCR(r1)
@@ -258,6 +265,12 @@ syscall_exit_cont:
         mtspr   SPRN_SRR1,r8
         SYNC
         RFI
+#ifdef CONFIG_44x
+2:      li      r7,0
+        iccci   r0,r0
+        stw     r7,icache_44x_need_flush@l(r4)
+        b       1b
+#endif  /* CONFIG_44x */
 
 66:     li      r3,-ENOSYS
         b       ret_from_syscall
@@ -679,6 +692,16 @@ resume_kernel:
 
         /* interrupts are hard-disabled at this point */
 restore:
+#ifdef CONFIG_44x
+        lis     r4,icache_44x_need_flush@ha
+        lwz     r5,icache_44x_need_flush@l(r4)
+        cmplwi  cr0,r5,0
+        beq+    1f
+        li      r6,0
+        iccci   r0,r0
+        stw     r6,icache_44x_need_flush@l(r4)
+1:
+#endif  /* CONFIG_44x */
         lwz     r0,GPR0(r1)
         lwz     r2,GPR2(r1)
         REST_4GPRS(3, r1)
diff --git a/arch/ppc/kernel/misc.S b/arch/ppc/kernel/misc.S
index a22e1f4d94c8..e0c850d85c53 100644
--- a/arch/ppc/kernel/misc.S
+++ b/arch/ppc/kernel/misc.S
@@ -224,7 +224,16 @@ _GLOBAL(_tlbia)
  */
 _GLOBAL(_tlbie)
 #if defined(CONFIG_40x)
+        /* We run the search with interrupts disabled because we have to change
+         * the PID and I don't want to preempt when that happens.
+         */
+        mfmsr   r5
+        mfspr   r6,SPRN_PID
+        wrteei  0
+        mtspr   SPRN_PID,r4
         tlbsx.  r3, 0, r3
+        mtspr   SPRN_PID,r6
+        wrtee   r5
         bne     10f
         sync
         /* There are only 64 TLB entries, so r3 < 64, which means bit 25 is clear.
@@ -234,22 +243,21 @@ _GLOBAL(_tlbie)
         isync
 10:
 #elif defined(CONFIG_44x)
-        mfspr   r4,SPRN_MMUCR
-        mfspr   r5,SPRN_PID                     /* Get PID */
-        rlwimi  r4,r5,0,24,31                   /* Set TID */
+        mfspr   r5,SPRN_MMUCR
+        rlwimi  r5,r4,0,24,31                   /* Set TID */
 
         /* We have to run the search with interrupts disabled, even critical
          * and debug interrupts (in fact the only critical exceptions we have
          * are debug and machine check).  Otherwise  an interrupt which causes
          * a TLB miss can clobber the MMUCR between the mtspr and the tlbsx. */
-        mfmsr   r5
+        mfmsr   r4
         lis     r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@ha
         addi    r6,r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@l
-        andc    r6,r5,r6
+        andc    r6,r4,r6
         mtmsr   r6
-        mtspr   SPRN_MMUCR,r4
+        mtspr   SPRN_MMUCR,r5
         tlbsx.  r3, 0, r3
-        mtmsr   r5
+        mtmsr   r4
         bne     10f
         sync
         /* There are only 64 TLB entries, so r3 < 64,
@@ -491,12 +499,21 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
         addi    r3,r3,L1_CACHE_BYTES
         bdnz    0b
         sync
+#ifndef CONFIG_44x
+        /* We don't flush the icache on 44x. Those have a virtual icache
+         * and we don't have access to the virtual address here (it's
+         * not the page vaddr but where it's mapped in user space). The
+         * flushing of the icache on these is handled elsewhere, when
+         * a change in the address space occurs, before returning to
+         * user space
+         */
         mtctr   r4
 1:      icbi    0,r6
         addi    r6,r6,L1_CACHE_BYTES
         bdnz    1b
         sync
         isync
+#endif /* CONFIG_44x */
         blr
 
 /*
diff --git a/arch/ppc/mm/44x_mmu.c b/arch/ppc/mm/44x_mmu.c
index 0a0a0487b334..6536a25cfcb8 100644
--- a/arch/ppc/mm/44x_mmu.c
+++ b/arch/ppc/mm/44x_mmu.c
@@ -61,6 +61,7 @@ extern char etext[], _stext[];
  */
 unsigned int tlb_44x_index = 0;
 unsigned int tlb_44x_hwater = 62;
+int icache_44x_need_flush;
 
 /*
  * "Pins" a 256MB TLB entry in AS0 for kernel lowmem
diff --git a/arch/ppc/mm/4xx_mmu.c b/arch/ppc/mm/4xx_mmu.c
index 838e09db71d9..ea785dbaac7c 100644
--- a/arch/ppc/mm/4xx_mmu.c
+++ b/arch/ppc/mm/4xx_mmu.c
@@ -99,13 +99,12 @@ unsigned long __init mmu_mapin_ram(void)
 
         v = KERNELBASE;
         p = PPC_MEMSTART;
-        s = 0;
+        s = total_lowmem;
 
-        if (__map_without_ltlbs) {
-                return s;
-        }
+        if (__map_without_ltlbs)
+                return 0;
 
-        while (s <= (total_lowmem - LARGE_PAGE_SIZE_16M)) {
+        while (s >= LARGE_PAGE_SIZE_16M) {
                 pmd_t *pmdp;
                 unsigned long val = p | _PMD_SIZE_16M | _PAGE_HWEXEC | _PAGE_HWWRITE;
 
@@ -117,10 +116,10 @@ unsigned long __init mmu_mapin_ram(void)
 
                 v += LARGE_PAGE_SIZE_16M;
                 p += LARGE_PAGE_SIZE_16M;
-                s += LARGE_PAGE_SIZE_16M;
+                s -= LARGE_PAGE_SIZE_16M;
         }
 
-        while (s <= (total_lowmem - LARGE_PAGE_SIZE_4M)) {
+        while (s >= LARGE_PAGE_SIZE_4M) {
                 pmd_t *pmdp;
                 unsigned long val = p | _PMD_SIZE_4M | _PAGE_HWEXEC | _PAGE_HWWRITE;
 
@@ -129,8 +128,8 @@ unsigned long __init mmu_mapin_ram(void)
 
                 v += LARGE_PAGE_SIZE_4M;
                 p += LARGE_PAGE_SIZE_4M;
-                s += LARGE_PAGE_SIZE_4M;
+                s -= LARGE_PAGE_SIZE_4M;
         }
 
-        return s;
+        return total_lowmem - s;
 }
diff --git a/arch/ppc/mm/fault.c b/arch/ppc/mm/fault.c
index 254c23b755e6..36c0e7529edb 100644
--- a/arch/ppc/mm/fault.c
+++ b/arch/ppc/mm/fault.c
@@ -227,7 +227,7 @@ good_area:
                                         set_bit(PG_arch_1, &page->flags);
                                 }
                                 pte_update(ptep, 0, _PAGE_HWEXEC);
-                                _tlbie(address);
+                                _tlbie(address, mm->context.id);
                                 pte_unmap_unlock(ptep, ptl);
                                 up_read(&mm->mmap_sem);
                                 return 0;
diff --git a/arch/ppc/mm/mmu_decl.h b/arch/ppc/mm/mmu_decl.h
index 540f3292b229..f1d4f2109a99 100644
--- a/arch/ppc/mm/mmu_decl.h
+++ b/arch/ppc/mm/mmu_decl.h
@@ -54,12 +54,12 @@ extern unsigned int num_tlbcam_entries;
 #define mmu_mapin_ram()         (0UL)
 
 #elif defined(CONFIG_4xx)
-#define flush_HPTE(X, va, pg)   _tlbie(va)
+#define flush_HPTE(pid, va, pg) _tlbie(va, pid)
 extern void MMU_init_hw(void);
 extern unsigned long mmu_mapin_ram(void);
 
 #elif defined(CONFIG_FSL_BOOKE)
-#define flush_HPTE(X, va, pg)   _tlbie(va)
+#define flush_HPTE(pid, va, pg) _tlbie(va, pid)
 extern void MMU_init_hw(void);
 extern unsigned long mmu_mapin_ram(void);
 extern void adjust_total_lowmem(void);
diff --git a/arch/ppc/platforms/4xx/ebony.c b/arch/ppc/platforms/4xx/ebony.c
index 05d7184d7e14..453643a0eeea 100644
--- a/arch/ppc/platforms/4xx/ebony.c
+++ b/arch/ppc/platforms/4xx/ebony.c
@@ -236,7 +236,7 @@ ebony_early_serial_map(void)
         gen550_init(0, &port);
 
         /* Purge TLB entry added in head_44x.S for early serial access */
-        _tlbie(UART0_IO_BASE);
+        _tlbie(UART0_IO_BASE, 0);
 #endif
 
         port.membase = ioremap64(PPC440GP_UART1_ADDR, 8);
diff --git a/arch/ppc/platforms/4xx/luan.c b/arch/ppc/platforms/4xx/luan.c
index 4b169610f154..b79ebb8a3e6c 100644
--- a/arch/ppc/platforms/4xx/luan.c
+++ b/arch/ppc/platforms/4xx/luan.c
@@ -230,9 +230,14 @@ luan_setup_hoses(void)
 
         /* Allocate hoses for PCIX1 and PCIX2 */
         hose1 = pcibios_alloc_controller();
+        if (!hose1)
+                return;
+
         hose2 = pcibios_alloc_controller();
-        if (!hose1 || !hose2)
+        if (!hose2) {
+                pcibios_free_controller(hose1);
                 return;
+        }
 
         /* Setup PCIX1 */
         hose1->first_busno = 0;
diff --git a/arch/ppc/platforms/4xx/ocotea.c b/arch/ppc/platforms/4xx/ocotea.c
index fd0f971881d6..28a712cd4800 100644
--- a/arch/ppc/platforms/4xx/ocotea.c
+++ b/arch/ppc/platforms/4xx/ocotea.c
@@ -259,7 +259,7 @@ ocotea_early_serial_map(void)
         gen550_init(0, &port);
 
         /* Purge TLB entry added in head_44x.S for early serial access */
-        _tlbie(UART0_IO_BASE);
+        _tlbie(UART0_IO_BASE, 0);
 #endif
 
         port.membase = ioremap64(PPC440GX_UART1_ADDR, 8);
diff --git a/arch/ppc/platforms/4xx/taishan.c b/arch/ppc/platforms/4xx/taishan.c
index 888c492b4a45..f6a0c6650f33 100644
--- a/arch/ppc/platforms/4xx/taishan.c
+++ b/arch/ppc/platforms/4xx/taishan.c
@@ -316,7 +316,7 @@ taishan_early_serial_map(void)
         gen550_init(0, &port);
 
         /* Purge TLB entry added in head_44x.S for early serial access */
-        _tlbie(UART0_IO_BASE);
+        _tlbie(UART0_IO_BASE, 0);
 #endif
 
         port.membase = ioremap64(PPC440GX_UART1_ADDR, 8);