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authorKumar Gala <galak@freescale.com>2005-09-03 18:55:50 -0400
committerLinus Torvalds <torvalds@evo.osdl.org>2005-09-05 03:05:59 -0400
commit66d2cc95d14b5d750a9c58209fddb62eb139eaab (patch)
tree7397b11eeb20801423e88975ecc1a79a81cf70e4 /arch/ppc
parentcc9c540b6c4c883d7ff250c17647dedfa4184ca6 (diff)
[PATCH] ppc32: Added PCI support MPC83xx
Adds support for the two PCI busses on MPC83xx and the MPC834x SYS/PIBS reference board. The code initializes PCI inbound/outbound windows, allocates and registers PCI memory/io space. Be aware that setup of the PCI buses on the PIBs board is expected to be done by the firmware. Signed-off-by: Tony Li <tony.li@freescale.com> Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/ppc')
-rw-r--r--arch/ppc/Kconfig10
-rw-r--r--arch/ppc/platforms/83xx/mpc834x_sys.c35
-rw-r--r--arch/ppc/platforms/83xx/mpc834x_sys.h40
-rw-r--r--arch/ppc/syslib/ppc83xx_pci.h151
-rw-r--r--arch/ppc/syslib/ppc83xx_setup.c250
-rw-r--r--arch/ppc/syslib/ppc83xx_setup.h19
6 files changed, 474 insertions, 31 deletions
diff --git a/arch/ppc/Kconfig b/arch/ppc/Kconfig
index 9b849e281b45..36dee0ff5ca0 100644
--- a/arch/ppc/Kconfig
+++ b/arch/ppc/Kconfig
@@ -495,6 +495,11 @@ config WINCEPT
495 MPC821 PowerPC, introduced in 1998 and designed to be used in 495 MPC821 PowerPC, introduced in 1998 and designed to be used in
496 thin-client machines. Say Y to support it directly. 496 thin-client machines. Say Y to support it directly.
497 497
498 Be aware that PCI buses can only function when SYS board is plugged
499 into the PIB (Platform IO Board) board from Freescale which provide
500 3 PCI slots. The PIBs PCI initialization is the bootloader's
501 responsiblilty.
502
498endchoice 503endchoice
499 504
500choice 505choice
@@ -1153,6 +1158,11 @@ config PCI_DOMAINS
1153 bool 1158 bool
1154 default PCI 1159 default PCI
1155 1160
1161config MPC83xx_PCI2
1162 bool " Supprt for 2nd PCI host controller"
1163 depends on PCI && MPC834x
1164 default y if MPC834x_SYS
1165
1156config PCI_QSPAN 1166config PCI_QSPAN
1157 bool "QSpan PCI" 1167 bool "QSpan PCI"
1158 depends on !4xx && !CPM2 && 8xx 1168 depends on !4xx && !CPM2 && 8xx
diff --git a/arch/ppc/platforms/83xx/mpc834x_sys.c b/arch/ppc/platforms/83xx/mpc834x_sys.c
index ddd04d4c1ea9..b38a851a64ec 100644
--- a/arch/ppc/platforms/83xx/mpc834x_sys.c
+++ b/arch/ppc/platforms/83xx/mpc834x_sys.c
@@ -62,9 +62,29 @@ extern unsigned long total_memory; /* in mm/init */
62unsigned char __res[sizeof (bd_t)]; 62unsigned char __res[sizeof (bd_t)];
63 63
64#ifdef CONFIG_PCI 64#ifdef CONFIG_PCI
65#error "PCI is not supported" 65int
66/* NEED mpc83xx_map_irq & mpc83xx_exclude_device 66mpc83xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
67 see platforms/85xx/mpc85xx_ads_common.c */ 67{
68 static char pci_irq_table[][4] =
69 /*
70 * PCI IDSEL/INTPIN->INTLINE
71 * A B C D
72 */
73 {
74 {PIRQA, PIRQB, PIRQC, PIRQD}, /* idsel 0x11 */
75 {PIRQC, PIRQD, PIRQA, PIRQB}, /* idsel 0x12 */
76 {PIRQD, PIRQA, PIRQB, PIRQC} /* idsel 0x13 */
77 };
78
79 const long min_idsel = 0x11, max_idsel = 0x13, irqs_per_slot = 4;
80 return PCI_IRQ_TABLE_LOOKUP;
81}
82
83int
84mpc83xx_exclude_device(u_char bus, u_char devfn)
85{
86 return PCIBIOS_SUCCESSFUL;
87}
68#endif /* CONFIG_PCI */ 88#endif /* CONFIG_PCI */
69 89
70/* ************************************************************************ 90/* ************************************************************************
@@ -88,7 +108,7 @@ mpc834x_sys_setup_arch(void)
88 108
89#ifdef CONFIG_PCI 109#ifdef CONFIG_PCI
90 /* setup PCI host bridges */ 110 /* setup PCI host bridges */
91 mpc83xx_sys_setup_hose(); 111 mpc83xx_setup_hose();
92#endif 112#endif
93 mpc83xx_early_serial_map(); 113 mpc83xx_early_serial_map();
94 114
@@ -175,10 +195,17 @@ mpc834x_sys_init_IRQ(void)
175 IRQ_SENSE_LEVEL, /* EXT 1 */ 195 IRQ_SENSE_LEVEL, /* EXT 1 */
176 IRQ_SENSE_LEVEL, /* EXT 2 */ 196 IRQ_SENSE_LEVEL, /* EXT 2 */
177 0, /* EXT 3 */ 197 0, /* EXT 3 */
198#ifdef CONFIG_PCI
199 IRQ_SENSE_LEVEL, /* EXT 4 */
200 IRQ_SENSE_LEVEL, /* EXT 5 */
201 IRQ_SENSE_LEVEL, /* EXT 6 */
202 IRQ_SENSE_LEVEL, /* EXT 7 */
203#else
178 0, /* EXT 4 */ 204 0, /* EXT 4 */
179 0, /* EXT 5 */ 205 0, /* EXT 5 */
180 0, /* EXT 6 */ 206 0, /* EXT 6 */
181 0, /* EXT 7 */ 207 0, /* EXT 7 */
208#endif
182 }; 209 };
183 210
184 ipic_init(binfo->bi_immr_base + 0x00700, 0, MPC83xx_IPIC_IRQ_OFFSET, senses, 8); 211 ipic_init(binfo->bi_immr_base + 0x00700, 0, MPC83xx_IPIC_IRQ_OFFSET, senses, 8);
diff --git a/arch/ppc/platforms/83xx/mpc834x_sys.h b/arch/ppc/platforms/83xx/mpc834x_sys.h
index a2f6e49d7151..1584cd77a9ef 100644
--- a/arch/ppc/platforms/83xx/mpc834x_sys.h
+++ b/arch/ppc/platforms/83xx/mpc834x_sys.h
@@ -26,7 +26,7 @@
26#define VIRT_IMMRBAR ((uint)0xfe000000) 26#define VIRT_IMMRBAR ((uint)0xfe000000)
27 27
28#define BCSR_PHYS_ADDR ((uint)0xf8000000) 28#define BCSR_PHYS_ADDR ((uint)0xf8000000)
29#define BCSR_SIZE ((uint)(32 * 1024)) 29#define BCSR_SIZE ((uint)(128 * 1024))
30 30
31#define BCSR_MISC_REG2_OFF 0x07 31#define BCSR_MISC_REG2_OFF 0x07
32#define BCSR_MISC_REG2_PORESET 0x01 32#define BCSR_MISC_REG2_PORESET 0x01
@@ -34,23 +34,25 @@
34#define BCSR_MISC_REG3_OFF 0x08 34#define BCSR_MISC_REG3_OFF 0x08
35#define BCSR_MISC_REG3_CNFLOCK 0x80 35#define BCSR_MISC_REG3_CNFLOCK 0x80
36 36
37#ifdef CONFIG_PCI 37#define PIRQA MPC83xx_IRQ_EXT4
38/* PCI interrupt controller */ 38#define PIRQB MPC83xx_IRQ_EXT5
39#define PIRQA MPC83xx_IRQ_IRQ4 39#define PIRQC MPC83xx_IRQ_EXT6
40#define PIRQB MPC83xx_IRQ_IRQ5 40#define PIRQD MPC83xx_IRQ_EXT7
41#define PIRQC MPC83xx_IRQ_IRQ6 41
42#define PIRQD MPC83xx_IRQ_IRQ7 42#define MPC83xx_PCI1_LOWER_IO 0x00000000
43 43#define MPC83xx_PCI1_UPPER_IO 0x00ffffff
44#define MPC834x_SYS_PCI1_LOWER_IO 0x00000000 44#define MPC83xx_PCI1_LOWER_MEM 0x80000000
45#define MPC834x_SYS_PCI1_UPPER_IO 0x00ffffff 45#define MPC83xx_PCI1_UPPER_MEM 0x9fffffff
46 46#define MPC83xx_PCI1_IO_BASE 0xe2000000
47#define MPC834x_SYS_PCI1_LOWER_MEM 0x80000000 47#define MPC83xx_PCI1_MEM_OFFSET 0x00000000
48#define MPC834x_SYS_PCI1_UPPER_MEM 0x9fffffff 48#define MPC83xx_PCI1_IO_SIZE 0x01000000
49 49
50#define MPC834x_SYS_PCI1_IO_BASE 0xe2000000 50#define MPC83xx_PCI2_LOWER_IO 0x00000000
51#define MPC834x_SYS_PCI1_MEM_OFFSET 0x00000000 51#define MPC83xx_PCI2_UPPER_IO 0x00ffffff
52 52#define MPC83xx_PCI2_LOWER_MEM 0xa0000000
53#define MPC834x_SYS_PCI1_IO_SIZE 0x01000000 53#define MPC83xx_PCI2_UPPER_MEM 0xbfffffff
54#endif /* CONFIG_PCI */ 54#define MPC83xx_PCI2_IO_BASE 0xe3000000
55#define MPC83xx_PCI2_MEM_OFFSET 0x00000000
56#define MPC83xx_PCI2_IO_SIZE 0x01000000
55 57
56#endif /* __MACH_MPC83XX_SYS_H__ */ 58#endif /* __MACH_MPC83XX_SYS_H__ */
diff --git a/arch/ppc/syslib/ppc83xx_pci.h b/arch/ppc/syslib/ppc83xx_pci.h
new file mode 100644
index 000000000000..ec691640f6be
--- /dev/null
+++ b/arch/ppc/syslib/ppc83xx_pci.h
@@ -0,0 +1,151 @@
1/* Created by Tony Li <tony.li@freescale.com>
2 * Copyright (c) 2005 freescale semiconductor
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19#ifndef __PPC_SYSLIB_PPC83XX_PCI_H
20#define __PPC_SYSLIB_PPC83XX_PCI_H
21
22typedef struct immr_clk {
23 u32 spmr; /* system PLL mode Register */
24 u32 occr; /* output clock control Register */
25 u32 sccr; /* system clock control Register */
26 u8 res0[0xF4];
27} immr_clk_t;
28
29/*
30 * Sequencer
31 */
32typedef struct immr_ios {
33 u32 potar0;
34 u8 res0[4];
35 u32 pobar0;
36 u8 res1[4];
37 u32 pocmr0;
38 u8 res2[4];
39 u32 potar1;
40 u8 res3[4];
41 u32 pobar1;
42 u8 res4[4];
43 u32 pocmr1;
44 u8 res5[4];
45 u32 potar2;
46 u8 res6[4];
47 u32 pobar2;
48 u8 res7[4];
49 u32 pocmr2;
50 u8 res8[4];
51 u32 potar3;
52 u8 res9[4];
53 u32 pobar3;
54 u8 res10[4];
55 u32 pocmr3;
56 u8 res11[4];
57 u32 potar4;
58 u8 res12[4];
59 u32 pobar4;
60 u8 res13[4];
61 u32 pocmr4;
62 u8 res14[4];
63 u32 potar5;
64 u8 res15[4];
65 u32 pobar5;
66 u8 res16[4];
67 u32 pocmr5;
68 u8 res17[4];
69 u8 res18[0x60];
70 u32 pmcr;
71 u8 res19[4];
72 u32 dtcr;
73 u8 res20[4];
74} immr_ios_t;
75#define POTAR_TA_MASK 0x000fffff
76#define POBAR_BA_MASK 0x000fffff
77#define POCMR_EN 0x80000000
78#define POCMR_IO 0x40000000 /* 0--memory space 1--I/O space */
79#define POCMR_SE 0x20000000 /* streaming enable */
80#define POCMR_DST 0x10000000 /* 0--PCI1 1--PCI2 */
81#define POCMR_CM_MASK 0x000fffff
82
83/*
84 * PCI Controller Control and Status Registers
85 */
86typedef struct immr_pcictrl {
87 u32 esr;
88 u32 ecdr;
89 u32 eer;
90 u32 eatcr;
91 u32 eacr;
92 u32 eeacr;
93 u32 edlcr;
94 u32 edhcr;
95 u32 gcr;
96 u32 ecr;
97 u32 gsr;
98 u8 res0[12];
99 u32 pitar2;
100 u8 res1[4];
101 u32 pibar2;
102 u32 piebar2;
103 u32 piwar2;
104 u8 res2[4];
105 u32 pitar1;
106 u8 res3[4];
107 u32 pibar1;
108 u32 piebar1;
109 u32 piwar1;
110 u8 res4[4];
111 u32 pitar0;
112 u8 res5[4];
113 u32 pibar0;
114 u8 res6[4];
115 u32 piwar0;
116 u8 res7[132];
117} immr_pcictrl_t;
118#define PITAR_TA_MASK 0x000fffff
119#define PIBAR_MASK 0xffffffff
120#define PIEBAR_EBA_MASK 0x000fffff
121#define PIWAR_EN 0x80000000
122#define PIWAR_PF 0x20000000
123#define PIWAR_RTT_MASK 0x000f0000
124#define PIWAR_RTT_NO_SNOOP 0x00040000
125#define PIWAR_RTT_SNOOP 0x00050000
126#define PIWAR_WTT_MASK 0x0000f000
127#define PIWAR_WTT_NO_SNOOP 0x00004000
128#define PIWAR_WTT_SNOOP 0x00005000
129#define PIWAR_IWS_MASK 0x0000003F
130#define PIWAR_IWS_4K 0x0000000B
131#define PIWAR_IWS_8K 0x0000000C
132#define PIWAR_IWS_16K 0x0000000D
133#define PIWAR_IWS_32K 0x0000000E
134#define PIWAR_IWS_64K 0x0000000F
135#define PIWAR_IWS_128K 0x00000010
136#define PIWAR_IWS_256K 0x00000011
137#define PIWAR_IWS_512K 0x00000012
138#define PIWAR_IWS_1M 0x00000013
139#define PIWAR_IWS_2M 0x00000014
140#define PIWAR_IWS_4M 0x00000015
141#define PIWAR_IWS_8M 0x00000016
142#define PIWAR_IWS_16M 0x00000017
143#define PIWAR_IWS_32M 0x00000018
144#define PIWAR_IWS_64M 0x00000019
145#define PIWAR_IWS_128M 0x0000001A
146#define PIWAR_IWS_256M 0x0000001B
147#define PIWAR_IWS_512M 0x0000001C
148#define PIWAR_IWS_1G 0x0000001D
149#define PIWAR_IWS_2G 0x0000001E
150
151#endif /* __PPC_SYSLIB_PPC83XX_PCI_H */
diff --git a/arch/ppc/syslib/ppc83xx_setup.c b/arch/ppc/syslib/ppc83xx_setup.c
index 602a86891f7f..890484e576e7 100644
--- a/arch/ppc/syslib/ppc83xx_setup.c
+++ b/arch/ppc/syslib/ppc83xx_setup.c
@@ -11,6 +11,17 @@
11 * under the terms of the GNU General Public License as published by the 11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your 12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version. 13 * option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 675 Mass Ave, Cambridge, MA 02139, USA.
23 *
24 * Added PCI support -- Tony Li <tony.li@freescale.com>
14 */ 25 */
15 26
16#include <linux/config.h> 27#include <linux/config.h>
@@ -31,6 +42,10 @@
31#include <asm/delay.h> 42#include <asm/delay.h>
32 43
33#include <syslib/ppc83xx_setup.h> 44#include <syslib/ppc83xx_setup.h>
45#if defined(CONFIG_PCI)
46#include <asm/delay.h>
47#include <syslib/ppc83xx_pci.h>
48#endif
34 49
35phys_addr_t immrbar; 50phys_addr_t immrbar;
36 51
@@ -162,4 +177,237 @@ mpc83xx_halt(void)
162 for(;;); 177 for(;;);
163} 178}
164 179
165/* PCI SUPPORT DOES NOT EXIT, MODEL after ppc85xx_setup.c */ 180#if defined(CONFIG_PCI)
181void __init
182mpc83xx_setup_pci1(struct pci_controller *hose)
183{
184 u16 reg16;
185 volatile immr_pcictrl_t * pci_ctrl;
186 volatile immr_ios_t * ios;
187 bd_t *binfo = (bd_t *) __res;
188
189 pci_ctrl = ioremap(binfo->bi_immr_base + 0x8500, sizeof(immr_pcictrl_t));
190 ios = ioremap(binfo->bi_immr_base + 0x8400, sizeof(immr_ios_t));
191
192 /*
193 * Configure PCI Outbound Translation Windows
194 */
195 ios->potar0 = (MPC83xx_PCI1_LOWER_MEM >> 12) & POTAR_TA_MASK;
196 ios->pobar0 = (MPC83xx_PCI1_LOWER_MEM >> 12) & POBAR_BA_MASK;
197 ios->pocmr0 = POCMR_EN |
198 (((0xffffffff - (MPC83xx_PCI1_UPPER_MEM -
199 MPC83xx_PCI1_LOWER_MEM)) >> 12) & POCMR_CM_MASK);
200
201 /* mapped to PCI1 IO space */
202 ios->potar1 = (MPC83xx_PCI1_LOWER_IO >> 12) & POTAR_TA_MASK;
203 ios->pobar1 = (MPC83xx_PCI1_IO_BASE >> 12) & POBAR_BA_MASK;
204 ios->pocmr1 = POCMR_EN | POCMR_IO |
205 (((0xffffffff - (MPC83xx_PCI1_UPPER_IO -
206 MPC83xx_PCI1_LOWER_IO)) >> 12) & POCMR_CM_MASK);
207
208 /*
209 * Configure PCI Inbound Translation Windows
210 */
211 pci_ctrl->pitar1 = 0x0;
212 pci_ctrl->pibar1 = 0x0;
213 pci_ctrl->piebar1 = 0x0;
214 pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G;
215
216 /*
217 * Release PCI RST signal
218 */
219 pci_ctrl->gcr = 0;
220 udelay(2000);
221 pci_ctrl->gcr = 1;
222 udelay(2000);
223
224 reg16 = 0xff;
225 early_read_config_word(hose, hose->first_busno, 0, PCI_COMMAND, &reg16);
226 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
227 early_write_config_word(hose, hose->first_busno, 0, PCI_COMMAND, reg16);
228
229 /*
230 * Clear non-reserved bits in status register.
231 */
232 early_write_config_word(hose, hose->first_busno, 0, PCI_STATUS, 0xffff);
233 early_write_config_byte(hose, hose->first_busno, 0, PCI_LATENCY_TIMER, 0x80);
234
235 iounmap(pci_ctrl);
236 iounmap(ios);
237}
238
239void __init
240mpc83xx_setup_pci2(struct pci_controller *hose)
241{
242 u16 reg16;
243 volatile immr_pcictrl_t * pci_ctrl;
244 volatile immr_ios_t * ios;
245 bd_t *binfo = (bd_t *) __res;
246
247 pci_ctrl = ioremap(binfo->bi_immr_base + 0x8600, sizeof(immr_pcictrl_t));
248 ios = ioremap(binfo->bi_immr_base + 0x8400, sizeof(immr_ios_t));
249
250 /*
251 * Configure PCI Outbound Translation Windows
252 */
253 ios->potar3 = (MPC83xx_PCI2_LOWER_MEM >> 12) & POTAR_TA_MASK;
254 ios->pobar3 = (MPC83xx_PCI2_LOWER_MEM >> 12) & POBAR_BA_MASK;
255 ios->pocmr3 = POCMR_EN | POCMR_DST |
256 (((0xffffffff - (MPC83xx_PCI2_UPPER_MEM -
257 MPC83xx_PCI2_LOWER_MEM)) >> 12) & POCMR_CM_MASK);
258
259 /* mapped to PCI2 IO space */
260 ios->potar4 = (MPC83xx_PCI2_LOWER_IO >> 12) & POTAR_TA_MASK;
261 ios->pobar4 = (MPC83xx_PCI2_IO_BASE >> 12) & POBAR_BA_MASK;
262 ios->pocmr4 = POCMR_EN | POCMR_DST | POCMR_IO |
263 (((0xffffffff - (MPC83xx_PCI2_UPPER_IO -
264 MPC83xx_PCI2_LOWER_IO)) >> 12) & POCMR_CM_MASK);
265
266 /*
267 * Configure PCI Inbound Translation Windows
268 */
269 pci_ctrl->pitar1 = 0x0;
270 pci_ctrl->pibar1 = 0x0;
271 pci_ctrl->piebar1 = 0x0;
272 pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G;
273
274 /*
275 * Release PCI RST signal
276 */
277 pci_ctrl->gcr = 0;
278 udelay(2000);
279 pci_ctrl->gcr = 1;
280 udelay(2000);
281
282 reg16 = 0xff;
283 early_read_config_word(hose, hose->first_busno, 0, PCI_COMMAND, &reg16);
284 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
285 early_write_config_word(hose, hose->first_busno, 0, PCI_COMMAND, reg16);
286
287 /*
288 * Clear non-reserved bits in status register.
289 */
290 early_write_config_word(hose, hose->first_busno, 0, PCI_STATUS, 0xffff);
291 early_write_config_byte(hose, hose->first_busno, 0, PCI_LATENCY_TIMER, 0x80);
292
293 iounmap(pci_ctrl);
294 iounmap(ios);
295}
296
297/*
298 * PCI buses can be enabled only if SYS board combinates with PIB
299 * (Platform IO Board) board which provide 3 PCI slots. There is 2 PCI buses
300 * and 3 PCI slots, so people must configure the routes between them before
301 * enable PCI bus. This routes are under the control of PCA9555PW device which
302 * can be accessed via I2C bus 2 and are configured by firmware. Refer to
303 * Freescale to get more information about firmware configuration.
304 */
305
306extern int mpc83xx_exclude_device(u_char bus, u_char devfn);
307extern int mpc83xx_map_irq(struct pci_dev *dev, unsigned char idsel,
308 unsigned char pin);
309void __init
310mpc83xx_setup_hose(void)
311{
312 u32 val32;
313 volatile immr_clk_t * clk;
314 struct pci_controller * hose1;
315#ifdef CONFIG_MPC83xx_PCI2
316 struct pci_controller * hose2;
317#endif
318 bd_t * binfo = (bd_t *)__res;
319
320 clk = ioremap(binfo->bi_immr_base + 0xA00,
321 sizeof(immr_clk_t));
322
323 /*
324 * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
325 */
326 val32 = clk->occr;
327 udelay(2000);
328 clk->occr = 0xff000000;
329 udelay(2000);
330
331 iounmap(clk);
332
333 hose1 = pcibios_alloc_controller();
334 if(!hose1)
335 return;
336
337 ppc_md.pci_swizzle = common_swizzle;
338 ppc_md.pci_map_irq = mpc83xx_map_irq;
339
340 hose1->bus_offset = 0;
341 hose1->first_busno = 0;
342 hose1->last_busno = 0xff;
343
344 setup_indirect_pci(hose1, binfo->bi_immr_base + PCI1_CFG_ADDR_OFFSET,
345 binfo->bi_immr_base + PCI1_CFG_DATA_OFFSET);
346 hose1->set_cfg_type = 1;
347
348 mpc83xx_setup_pci1(hose1);
349
350 hose1->pci_mem_offset = MPC83xx_PCI1_MEM_OFFSET;
351 hose1->mem_space.start = MPC83xx_PCI1_LOWER_MEM;
352 hose1->mem_space.end = MPC83xx_PCI1_UPPER_MEM;
353
354 hose1->io_base_phys = MPC83xx_PCI1_IO_BASE;
355 hose1->io_space.start = MPC83xx_PCI1_LOWER_IO;
356 hose1->io_space.end = MPC83xx_PCI1_UPPER_IO;
357#ifdef CONFIG_MPC83xx_PCI2
358 isa_io_base = (unsigned long)ioremap(MPC83xx_PCI1_IO_BASE,
359 MPC83xx_PCI1_IO_SIZE + MPC83xx_PCI2_IO_SIZE);
360#else
361 isa_io_base = (unsigned long)ioremap(MPC83xx_PCI1_IO_BASE,
362 MPC83xx_PCI1_IO_SIZE);
363#endif /* CONFIG_MPC83xx_PCI2 */
364 hose1->io_base_virt = (void *)isa_io_base;
365 /* setup resources */
366 pci_init_resource(&hose1->io_resource,
367 MPC83xx_PCI1_LOWER_IO,
368 MPC83xx_PCI1_UPPER_IO,
369 IORESOURCE_IO, "PCI host bridge 1");
370 pci_init_resource(&hose1->mem_resources[0],
371 MPC83xx_PCI1_LOWER_MEM,
372 MPC83xx_PCI1_UPPER_MEM,
373 IORESOURCE_MEM, "PCI host bridge 1");
374
375 ppc_md.pci_exclude_device = mpc83xx_exclude_device;
376 hose1->last_busno = pciauto_bus_scan(hose1, hose1->first_busno);
377
378#ifdef CONFIG_MPC83xx_PCI2
379 hose2 = pcibios_alloc_controller();
380 if(!hose2)
381 return;
382
383 hose2->bus_offset = hose1->last_busno + 1;
384 hose2->first_busno = hose1->last_busno + 1;
385 hose2->last_busno = 0xff;
386 setup_indirect_pci(hose2, binfo->bi_immr_base + PCI2_CFG_ADDR_OFFSET,
387 binfo->bi_immr_base + PCI2_CFG_DATA_OFFSET);
388 hose2->set_cfg_type = 1;
389
390 mpc83xx_setup_pci2(hose2);
391
392 hose2->pci_mem_offset = MPC83xx_PCI2_MEM_OFFSET;
393 hose2->mem_space.start = MPC83xx_PCI2_LOWER_MEM;
394 hose2->mem_space.end = MPC83xx_PCI2_UPPER_MEM;
395
396 hose2->io_base_phys = MPC83xx_PCI2_IO_BASE;
397 hose2->io_space.start = MPC83xx_PCI2_LOWER_IO;
398 hose2->io_space.end = MPC83xx_PCI2_UPPER_IO;
399 hose2->io_base_virt = (void *)(isa_io_base + MPC83xx_PCI1_IO_SIZE);
400 /* setup resources */
401 pci_init_resource(&hose2->io_resource,
402 MPC83xx_PCI2_LOWER_IO,
403 MPC83xx_PCI2_UPPER_IO,
404 IORESOURCE_IO, "PCI host bridge 2");
405 pci_init_resource(&hose2->mem_resources[0],
406 MPC83xx_PCI2_LOWER_MEM,
407 MPC83xx_PCI2_UPPER_MEM,
408 IORESOURCE_MEM, "PCI host bridge 2");
409
410 hose2->last_busno = pciauto_bus_scan(hose2, hose2->first_busno);
411#endif /* CONFIG_MPC83xx_PCI2 */
412}
413#endif /*CONFIG_PCI*/
diff --git a/arch/ppc/syslib/ppc83xx_setup.h b/arch/ppc/syslib/ppc83xx_setup.h
index 683f179b746c..c766c1a5f786 100644
--- a/arch/ppc/syslib/ppc83xx_setup.h
+++ b/arch/ppc/syslib/ppc83xx_setup.h
@@ -12,6 +12,14 @@
12 * Free Software Foundation; either version 2 of the License, or (at your 12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version. 13 * option) any later version.
14 * 14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 675 Mass Ave, Cambridge, MA 02139, USA.
15 */ 23 */
16 24
17#ifndef __PPC_SYSLIB_PPC83XX_SETUP_H 25#ifndef __PPC_SYSLIB_PPC83XX_SETUP_H
@@ -19,7 +27,6 @@
19 27
20#include <linux/config.h> 28#include <linux/config.h>
21#include <linux/init.h> 29#include <linux/init.h>
22#include <asm/ppcboot.h>
23 30
24extern unsigned long mpc83xx_find_end_of_memory(void) __init; 31extern unsigned long mpc83xx_find_end_of_memory(void) __init;
25extern long mpc83xx_time_init(void) __init; 32extern long mpc83xx_time_init(void) __init;
@@ -31,13 +38,11 @@ extern void mpc83xx_halt(void);
31extern void mpc83xx_setup_hose(void) __init; 38extern void mpc83xx_setup_hose(void) __init;
32 39
33/* PCI config */ 40/* PCI config */
34#if 0 41#define PCI1_CFG_ADDR_OFFSET (0x8300)
35#define PCI1_CFG_ADDR_OFFSET (FIXME) 42#define PCI1_CFG_DATA_OFFSET (0x8304)
36#define PCI1_CFG_DATA_OFFSET (FIXME)
37 43
38#define PCI2_CFG_ADDR_OFFSET (FIXME) 44#define PCI2_CFG_ADDR_OFFSET (0x8380)
39#define PCI2_CFG_DATA_OFFSET (FIXME) 45#define PCI2_CFG_DATA_OFFSET (0x8384)
40#endif
41 46
42/* Serial Config */ 47/* Serial Config */
43#ifdef CONFIG_SERIAL_MANY_PORTS 48#ifdef CONFIG_SERIAL_MANY_PORTS