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authorDavid Woodhouse <dwmw2@shinybook.infradead.org>2005-06-18 03:36:46 -0400
committerDavid Woodhouse <dwmw2@shinybook.infradead.org>2005-06-18 03:36:46 -0400
commit0107b3cf3225aed6ddde4fa8dbcd4ed643b34f4d (patch)
tree9b9337ae627fc56a0eda43c60860765f25efaa0b /arch/ppc
parent1c3f45ab2f7f879ea482501c83899505c31f7539 (diff)
parent9ee1c939d1cb936b1f98e8d81aeffab57bae46ab (diff)
Merge with master.kernel.org:/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
Diffstat (limited to 'arch/ppc')
-rw-r--r--arch/ppc/kernel/cputable.c11
-rw-r--r--arch/ppc/kernel/misc.S6
-rw-r--r--arch/ppc/platforms/pmac_cpufreq.c7
3 files changed, 19 insertions, 5 deletions
diff --git a/arch/ppc/kernel/cputable.c b/arch/ppc/kernel/cputable.c
index 8aa5e8c69009..d44b7dc5390a 100644
--- a/arch/ppc/kernel/cputable.c
+++ b/arch/ppc/kernel/cputable.c
@@ -838,6 +838,17 @@ struct cpu_spec cpu_specs[] = {
838 .icache_bsize = 32, 838 .icache_bsize = 32,
839 .dcache_bsize = 32, 839 .dcache_bsize = 32,
840 }, 840 },
841 { /* 405EP */
842 .pvr_mask = 0xffff0000,
843 .pvr_value = 0x51210000,
844 .cpu_name = "405EP",
845 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
846 CPU_FTR_USE_TB,
847 .cpu_user_features = PPC_FEATURE_32 |
848 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
849 .icache_bsize = 32,
850 .dcache_bsize = 32,
851 },
841 852
842#endif /* CONFIG_40x */ 853#endif /* CONFIG_40x */
843#ifdef CONFIG_44x 854#ifdef CONFIG_44x
diff --git a/arch/ppc/kernel/misc.S b/arch/ppc/kernel/misc.S
index e4f1615ec13f..7329ef177a18 100644
--- a/arch/ppc/kernel/misc.S
+++ b/arch/ppc/kernel/misc.S
@@ -619,7 +619,7 @@ _GLOBAL(flush_instruction_cache)
619_GLOBAL(flush_icache_range) 619_GLOBAL(flush_icache_range)
620BEGIN_FTR_SECTION 620BEGIN_FTR_SECTION
621 blr /* for 601, do nothing */ 621 blr /* for 601, do nothing */
622END_FTR_SECTION_IFSET(PPC_FEATURE_UNIFIED_CACHE) 622END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
623 li r5,L1_CACHE_LINE_SIZE-1 623 li r5,L1_CACHE_LINE_SIZE-1
624 andc r3,r3,r5 624 andc r3,r3,r5
625 subf r4,r3,r4 625 subf r4,r3,r4
@@ -736,7 +736,7 @@ _GLOBAL(flush_dcache_all)
736_GLOBAL(__flush_dcache_icache) 736_GLOBAL(__flush_dcache_icache)
737BEGIN_FTR_SECTION 737BEGIN_FTR_SECTION
738 blr /* for 601, do nothing */ 738 blr /* for 601, do nothing */
739END_FTR_SECTION_IFSET(PPC_FEATURE_UNIFIED_CACHE) 739END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
740 rlwinm r3,r3,0,0,19 /* Get page base address */ 740 rlwinm r3,r3,0,0,19 /* Get page base address */
741 li r4,4096/L1_CACHE_LINE_SIZE /* Number of lines in a page */ 741 li r4,4096/L1_CACHE_LINE_SIZE /* Number of lines in a page */
742 mtctr r4 742 mtctr r4
@@ -764,7 +764,7 @@ END_FTR_SECTION_IFSET(PPC_FEATURE_UNIFIED_CACHE)
764_GLOBAL(__flush_dcache_icache_phys) 764_GLOBAL(__flush_dcache_icache_phys)
765BEGIN_FTR_SECTION 765BEGIN_FTR_SECTION
766 blr /* for 601, do nothing */ 766 blr /* for 601, do nothing */
767END_FTR_SECTION_IFSET(PPC_FEATURE_UNIFIED_CACHE) 767END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
768 mfmsr r10 768 mfmsr r10
769 rlwinm r0,r10,0,28,26 /* clear DR */ 769 rlwinm r0,r10,0,28,26 /* clear DR */
770 mtmsr r0 770 mtmsr r0
diff --git a/arch/ppc/platforms/pmac_cpufreq.c b/arch/ppc/platforms/pmac_cpufreq.c
index 937f46df711e..5fdd4f607a40 100644
--- a/arch/ppc/platforms/pmac_cpufreq.c
+++ b/arch/ppc/platforms/pmac_cpufreq.c
@@ -83,7 +83,7 @@ static u32 frequency_gpio;
83static u32 slew_done_gpio; 83static u32 slew_done_gpio;
84static int no_schedule; 84static int no_schedule;
85static int has_cpu_l2lve; 85static int has_cpu_l2lve;
86 86static int is_pmu_based;
87 87
88/* There are only two frequency states for each processor. Values 88/* There are only two frequency states for each processor. Values
89 * are in kHz for the time being. 89 * are in kHz for the time being.
@@ -463,7 +463,7 @@ static int __pmac pmac_cpufreq_suspend(struct cpufreq_policy *policy, u32 state)
463 */ 463 */
464 no_schedule = 1; 464 no_schedule = 1;
465 sleep_freq = cur_freq; 465 sleep_freq = cur_freq;
466 if (cur_freq == low_freq) 466 if (cur_freq == low_freq && !is_pmu_based)
467 do_set_cpu_speed(CPUFREQ_HIGH, 0); 467 do_set_cpu_speed(CPUFREQ_HIGH, 0);
468 return 0; 468 return 0;
469} 469}
@@ -588,6 +588,7 @@ static int __pmac pmac_cpufreq_init_MacRISC3(struct device_node *cpunode)
588 return 1; 588 return 1;
589 hi_freq = (*value) / 1000; 589 hi_freq = (*value) / 1000;
590 set_speed_proc = pmu_set_cpu_speed; 590 set_speed_proc = pmu_set_cpu_speed;
591 is_pmu_based = 1;
591 592
592 return 0; 593 return 0;
593} 594}
@@ -692,6 +693,7 @@ static int __init pmac_cpufreq_setup(void)
692 hi_freq = cur_freq; 693 hi_freq = cur_freq;
693 low_freq = 400000; 694 low_freq = 400000;
694 set_speed_proc = pmu_set_cpu_speed; 695 set_speed_proc = pmu_set_cpu_speed;
696 is_pmu_based = 1;
695 } 697 }
696 /* Else check for TiPb 400 & 500 */ 698 /* Else check for TiPb 400 & 500 */
697 else if (machine_is_compatible("PowerBook3,2")) { 699 else if (machine_is_compatible("PowerBook3,2")) {
@@ -703,6 +705,7 @@ static int __init pmac_cpufreq_setup(void)
703 hi_freq = cur_freq; 705 hi_freq = cur_freq;
704 low_freq = 300000; 706 low_freq = 300000;
705 set_speed_proc = pmu_set_cpu_speed; 707 set_speed_proc = pmu_set_cpu_speed;
708 is_pmu_based = 1;
706 } 709 }
707 /* Else check for 750FX */ 710 /* Else check for 750FX */
708 else if (PVR_VER(mfspr(SPRN_PVR)) == 0x7000) 711 else if (PVR_VER(mfspr(SPRN_PVR)) == 0x7000)