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authorJeff Garzik <jgarzik@pretzel.yyz.us>2005-06-22 13:07:28 -0400
committerJeff Garzik <jgarzik@pobox.com>2005-06-22 13:07:28 -0400
commitff40c6d3d1437ecdf295b8e39adcb06c3d6021ef (patch)
tree3666d029b4bd4df2909dbefd9c7a09e6042b7d32 /arch/ppc/syslib
parent8bf62ecee58360749c5f0e68bc97d5e02a6816b1 (diff)
parent2a5a68b840cbab31baab2d9b2e1e6de3b289ae1e (diff)
Merge upstream kernel changes into 'C/H/S support' branch of libata.
Diffstat (limited to 'arch/ppc/syslib')
-rw-r--r--arch/ppc/syslib/Makefile7
-rw-r--r--arch/ppc/syslib/ipic.c2
-rw-r--r--arch/ppc/syslib/m8260_pci.c193
-rw-r--r--arch/ppc/syslib/m8260_pci.h76
-rw-r--r--arch/ppc/syslib/m8260_pci_erratum9.c10
-rw-r--r--arch/ppc/syslib/m8260_setup.c11
-rw-r--r--arch/ppc/syslib/m82xx_pci.c383
-rw-r--r--arch/ppc/syslib/m82xx_pci.h92
-rw-r--r--arch/ppc/syslib/mpc10x_common.c203
-rw-r--r--arch/ppc/syslib/mpc83xx_devices.c1
-rw-r--r--arch/ppc/syslib/mpc85xx_devices.c188
-rw-r--r--arch/ppc/syslib/mpc85xx_sys.c105
-rw-r--r--arch/ppc/syslib/ocp.c2
-rw-r--r--arch/ppc/syslib/of_device.c2
-rw-r--r--arch/ppc/syslib/open_pic.c7
-rw-r--r--arch/ppc/syslib/open_pic2.c1
-rw-r--r--arch/ppc/syslib/ppc4xx_kgdb.c124
-rw-r--r--arch/ppc/syslib/ppc83xx_setup.c29
-rw-r--r--arch/ppc/syslib/ppc85xx_setup.c19
-rw-r--r--arch/ppc/syslib/prom_init.c10
20 files changed, 1003 insertions, 462 deletions
diff --git a/arch/ppc/syslib/Makefile b/arch/ppc/syslib/Makefile
index dd418ea3426c..dec5bf4f6879 100644
--- a/arch/ppc/syslib/Makefile
+++ b/arch/ppc/syslib/Makefile
@@ -81,7 +81,7 @@ obj-$(CONFIG_SBC82xx) += todc_time.o
81obj-$(CONFIG_SPRUCE) += cpc700_pic.o indirect_pci.o pci_auto.o \ 81obj-$(CONFIG_SPRUCE) += cpc700_pic.o indirect_pci.o pci_auto.o \
82 todc_time.o 82 todc_time.o
83obj-$(CONFIG_8260) += m8260_setup.o 83obj-$(CONFIG_8260) += m8260_setup.o
84obj-$(CONFIG_PCI_8260) += m8260_pci.o indirect_pci.o 84obj-$(CONFIG_PCI_8260) += m82xx_pci.o indirect_pci.o pci_auto.o
85obj-$(CONFIG_8260_PCI9) += m8260_pci_erratum9.o 85obj-$(CONFIG_8260_PCI9) += m8260_pci_erratum9.o
86obj-$(CONFIG_CPM2) += cpm2_common.o cpm2_pic.o 86obj-$(CONFIG_CPM2) += cpm2_common.o cpm2_pic.o
87ifeq ($(CONFIG_PPC_GEN550),y) 87ifeq ($(CONFIG_PPC_GEN550),y)
@@ -92,12 +92,12 @@ ifeq ($(CONFIG_SERIAL_MPSC_CONSOLE),y)
92obj-$(CONFIG_SERIAL_TEXT_DEBUG) += mv64x60_dbg.o 92obj-$(CONFIG_SERIAL_TEXT_DEBUG) += mv64x60_dbg.o
93endif 93endif
94obj-$(CONFIG_BOOTX_TEXT) += btext.o 94obj-$(CONFIG_BOOTX_TEXT) += btext.o
95obj-$(CONFIG_MPC10X_BRIDGE) += mpc10x_common.o indirect_pci.o 95obj-$(CONFIG_MPC10X_BRIDGE) += mpc10x_common.o indirect_pci.o ppc_sys.o
96obj-$(CONFIG_MPC10X_OPENPIC) += open_pic.o 96obj-$(CONFIG_MPC10X_OPENPIC) += open_pic.o
97obj-$(CONFIG_40x) += dcr.o 97obj-$(CONFIG_40x) += dcr.o
98obj-$(CONFIG_BOOKE) += dcr.o 98obj-$(CONFIG_BOOKE) += dcr.o
99obj-$(CONFIG_85xx) += open_pic.o ppc85xx_common.o ppc85xx_setup.o \ 99obj-$(CONFIG_85xx) += open_pic.o ppc85xx_common.o ppc85xx_setup.o \
100 ppc_sys.o mpc85xx_sys.o \ 100 ppc_sys.o i8259.o mpc85xx_sys.o \
101 mpc85xx_devices.o 101 mpc85xx_devices.o
102ifeq ($(CONFIG_85xx),y) 102ifeq ($(CONFIG_85xx),y)
103obj-$(CONFIG_PCI) += indirect_pci.o pci_auto.o 103obj-$(CONFIG_PCI) += indirect_pci.o pci_auto.o
@@ -107,6 +107,7 @@ obj-$(CONFIG_83xx) += ipic.o ppc83xx_setup.o ppc_sys.o \
107ifeq ($(CONFIG_83xx),y) 107ifeq ($(CONFIG_83xx),y)
108obj-$(CONFIG_PCI) += indirect_pci.o pci_auto.o 108obj-$(CONFIG_PCI) += indirect_pci.o pci_auto.o
109endif 109endif
110obj-$(CONFIG_MPC8548_CDS) += todc_time.o
110obj-$(CONFIG_MPC8555_CDS) += todc_time.o 111obj-$(CONFIG_MPC8555_CDS) += todc_time.o
111obj-$(CONFIG_PPC_MPC52xx) += mpc52xx_setup.o mpc52xx_pic.o \ 112obj-$(CONFIG_PPC_MPC52xx) += mpc52xx_setup.o mpc52xx_pic.o \
112 mpc52xx_sys.o mpc52xx_devices.o ppc_sys.o 113 mpc52xx_sys.o mpc52xx_devices.o ppc_sys.o
diff --git a/arch/ppc/syslib/ipic.c b/arch/ppc/syslib/ipic.c
index acb2cde3171f..580ed658e872 100644
--- a/arch/ppc/syslib/ipic.c
+++ b/arch/ppc/syslib/ipic.c
@@ -479,7 +479,7 @@ void __init ipic_init(phys_addr_t phys_addr,
479 temp = 0; 479 temp = 0;
480 for (i = 0 ; i < senses_count ; i++) { 480 for (i = 0 ; i < senses_count ; i++) {
481 if ((senses[i] & IRQ_SENSE_MASK) == IRQ_SENSE_EDGE) { 481 if ((senses[i] & IRQ_SENSE_MASK) == IRQ_SENSE_EDGE) {
482 temp |= 1 << (16 - i); 482 temp |= 1 << (15 - i);
483 if (i != 0) 483 if (i != 0)
484 irq_desc[i + irq_offset + MPC83xx_IRQ_EXT1 - 1].status = 0; 484 irq_desc[i + irq_offset + MPC83xx_IRQ_EXT1 - 1].status = 0;
485 else 485 else
diff --git a/arch/ppc/syslib/m8260_pci.c b/arch/ppc/syslib/m8260_pci.c
deleted file mode 100644
index 057cc3f8ff37..000000000000
--- a/arch/ppc/syslib/m8260_pci.c
+++ /dev/null
@@ -1,193 +0,0 @@
1/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2004 Red Hat, Inc.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <linux/kernel.h>
27#include <linux/init.h>
28#include <linux/pci.h>
29#include <linux/slab.h>
30#include <linux/delay.h>
31
32#include <asm/byteorder.h>
33#include <asm/io.h>
34#include <asm/irq.h>
35#include <asm/uaccess.h>
36#include <asm/machdep.h>
37#include <asm/pci-bridge.h>
38#include <asm/immap_cpm2.h>
39#include <asm/mpc8260.h>
40
41#include "m8260_pci.h"
42
43
44/* PCI bus configuration registers.
45 */
46
47static void __init m8260_setup_pci(struct pci_controller *hose)
48{
49 volatile cpm2_map_t *immap = cpm2_immr;
50 unsigned long pocmr;
51 u16 tempShort;
52
53#ifndef CONFIG_ATC /* already done in U-Boot */
54 /*
55 * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
56 * and local bus for PCI (SIUMCR [LBPC]).
57 */
58 immap->im_siu_conf.siu_82xx.sc_siumcr = 0x00640000;
59#endif
60
61 /* Make PCI lowest priority */
62 /* Each 4 bits is a device bus request and the MS 4bits
63 is highest priority */
64 /* Bus 4bit value
65 --- ----------
66 CPM high 0b0000
67 CPM middle 0b0001
68 CPM low 0b0010
69 PCI reguest 0b0011
70 Reserved 0b0100
71 Reserved 0b0101
72 Internal Core 0b0110
73 External Master 1 0b0111
74 External Master 2 0b1000
75 External Master 3 0b1001
76 The rest are reserved */
77 immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x61207893;
78
79 /* Park bus on core while modifying PCI Bus accesses */
80 immap->im_siu_conf.siu_82xx.sc_ppc_acr = 0x6;
81
82 /*
83 * Set up master window that allows the CPU to access PCI space. This
84 * window is set up using the first SIU PCIBR registers.
85 */
86 immap->im_memctl.memc_pcimsk0 = MPC826x_PCI_MASK;
87 immap->im_memctl.memc_pcibr0 = MPC826x_PCI_BASE | PCIBR_ENABLE;
88
89 /* Disable machine check on no response or target abort */
90 immap->im_pci.pci_emr = cpu_to_le32(0x1fe7);
91 /* Release PCI RST (by default the PCI RST signal is held low) */
92 immap->im_pci.pci_gcr = cpu_to_le32(PCIGCR_PCI_BUS_EN);
93
94 /* give it some time */
95 mdelay(1);
96
97 /*
98 * Set up master window that allows the CPU to access PCI Memory (prefetch)
99 * space. This window is set up using the first set of Outbound ATU registers.
100 */
101 immap->im_pci.pci_potar0 = cpu_to_le32(MPC826x_PCI_LOWER_MEM >> 12);
102 immap->im_pci.pci_pobar0 = cpu_to_le32((MPC826x_PCI_LOWER_MEM - MPC826x_PCI_MEM_OFFSET) >> 12);
103 pocmr = ((MPC826x_PCI_UPPER_MEM - MPC826x_PCI_LOWER_MEM) >> 12) ^ 0xfffff;
104 immap->im_pci.pci_pocmr0 = cpu_to_le32(pocmr | POCMR_ENABLE | POCMR_PREFETCH_EN);
105
106 /*
107 * Set up master window that allows the CPU to access PCI Memory (non-prefetch)
108 * space. This window is set up using the second set of Outbound ATU registers.
109 */
110 immap->im_pci.pci_potar1 = cpu_to_le32(MPC826x_PCI_LOWER_MMIO >> 12);
111 immap->im_pci.pci_pobar1 = cpu_to_le32((MPC826x_PCI_LOWER_MMIO - MPC826x_PCI_MMIO_OFFSET) >> 12);
112 pocmr = ((MPC826x_PCI_UPPER_MMIO - MPC826x_PCI_LOWER_MMIO) >> 12) ^ 0xfffff;
113 immap->im_pci.pci_pocmr1 = cpu_to_le32(pocmr | POCMR_ENABLE);
114
115 /*
116 * Set up master window that allows the CPU to access PCI IO space. This window
117 * is set up using the third set of Outbound ATU registers.
118 */
119 immap->im_pci.pci_potar2 = cpu_to_le32(MPC826x_PCI_IO_BASE >> 12);
120 immap->im_pci.pci_pobar2 = cpu_to_le32(MPC826x_PCI_LOWER_IO >> 12);
121 pocmr = ((MPC826x_PCI_UPPER_IO - MPC826x_PCI_LOWER_IO) >> 12) ^ 0xfffff;
122 immap->im_pci.pci_pocmr2 = cpu_to_le32(pocmr | POCMR_ENABLE | POCMR_PCI_IO);
123
124 /*
125 * Set up slave window that allows PCI masters to access MPC826x local memory.
126 * This window is set up using the first set of Inbound ATU registers
127 */
128
129 immap->im_pci.pci_pitar0 = cpu_to_le32(MPC826x_PCI_SLAVE_MEM_LOCAL >> 12);
130 immap->im_pci.pci_pibar0 = cpu_to_le32(MPC826x_PCI_SLAVE_MEM_BUS >> 12);
131 pocmr = ((MPC826x_PCI_SLAVE_MEM_SIZE-1) >> 12) ^ 0xfffff;
132 immap->im_pci.pci_picmr0 = cpu_to_le32(pocmr | PICMR_ENABLE | PICMR_PREFETCH_EN);
133
134 /* See above for description - puts PCI request as highest priority */
135 immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x03124567;
136
137 /* Park the bus on the PCI */
138 immap->im_siu_conf.siu_82xx.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
139
140 /* Host mode - specify the bridge as a host-PCI bridge */
141 early_write_config_word(hose, 0, 0, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_HOST);
142
143 /* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */
144 early_read_config_word(hose, 0, 0, PCI_COMMAND, &tempShort);
145 early_write_config_word(hose, 0, 0, PCI_COMMAND,
146 tempShort | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
147}
148
149void __init m8260_find_bridges(void)
150{
151 extern int pci_assign_all_busses;
152 struct pci_controller * hose;
153
154 pci_assign_all_busses = 1;
155
156 hose = pcibios_alloc_controller();
157
158 if (!hose)
159 return;
160
161 ppc_md.pci_swizzle = common_swizzle;
162
163 hose->first_busno = 0;
164 hose->bus_offset = 0;
165 hose->last_busno = 0xff;
166
167 setup_m8260_indirect_pci(hose,
168 (unsigned long)&cpm2_immr->im_pci.pci_cfg_addr,
169 (unsigned long)&cpm2_immr->im_pci.pci_cfg_data);
170
171 m8260_setup_pci(hose);
172 hose->pci_mem_offset = MPC826x_PCI_MEM_OFFSET;
173
174 hose->io_base_virt = ioremap(MPC826x_PCI_IO_BASE,
175 MPC826x_PCI_IO_SIZE);
176 isa_io_base = (unsigned long) hose->io_base_virt;
177
178 /* setup resources */
179 pci_init_resource(&hose->mem_resources[0],
180 MPC826x_PCI_LOWER_MEM,
181 MPC826x_PCI_UPPER_MEM,
182 IORESOURCE_MEM|IORESOURCE_PREFETCH, "PCI prefetchable memory");
183
184 pci_init_resource(&hose->mem_resources[1],
185 MPC826x_PCI_LOWER_MMIO,
186 MPC826x_PCI_UPPER_MMIO,
187 IORESOURCE_MEM, "PCI memory");
188
189 pci_init_resource(&hose->io_resource,
190 MPC826x_PCI_LOWER_IO,
191 MPC826x_PCI_UPPER_IO,
192 IORESOURCE_IO, "PCI I/O");
193}
diff --git a/arch/ppc/syslib/m8260_pci.h b/arch/ppc/syslib/m8260_pci.h
deleted file mode 100644
index d1352120acd7..000000000000
--- a/arch/ppc/syslib/m8260_pci.h
+++ /dev/null
@@ -1,76 +0,0 @@
1
2#ifndef _PPC_KERNEL_M8260_PCI_H
3#define _PPC_KERNEL_M8260_PCI_H
4
5#include <asm/m8260_pci.h>
6
7/*
8 * Local->PCI map (from CPU) controlled by
9 * MPC826x master window
10 *
11 * 0x80000000 - 0xBFFFFFFF Total CPU2PCI space PCIBR0
12 *
13 * 0x80000000 - 0x9FFFFFFF PCI Mem with prefetch (Outbound ATU #1)
14 * 0xA0000000 - 0xAFFFFFFF PCI Mem w/o prefetch (Outbound ATU #2)
15 * 0xB0000000 - 0xB0FFFFFF 32-bit PCI IO (Outbound ATU #3)
16 *
17 * PCI->Local map (from PCI)
18 * MPC826x slave window controlled by
19 *
20 * 0x00000000 - 0x07FFFFFF MPC826x local memory (Inbound ATU #1)
21 */
22
23/*
24 * Slave window that allows PCI masters to access MPC826x local memory.
25 * This window is set up using the first set of Inbound ATU registers
26 */
27
28#ifndef MPC826x_PCI_SLAVE_MEM_LOCAL
29#define MPC826x_PCI_SLAVE_MEM_LOCAL (((struct bd_info *)__res)->bi_memstart)
30#define MPC826x_PCI_SLAVE_MEM_BUS (((struct bd_info *)__res)->bi_memstart)
31#define MPC826x_PCI_SLAVE_MEM_SIZE (((struct bd_info *)__res)->bi_memsize)
32#endif
33
34/*
35 * This is the window that allows the CPU to access PCI address space.
36 * It will be setup with the SIU PCIBR0 register. All three PCI master
37 * windows, which allow the CPU to access PCI prefetch, non prefetch,
38 * and IO space (see below), must all fit within this window.
39 */
40#ifndef MPC826x_PCI_BASE
41#define MPC826x_PCI_BASE 0x80000000
42#define MPC826x_PCI_MASK 0xc0000000
43#endif
44
45#ifndef MPC826x_PCI_LOWER_MEM
46#define MPC826x_PCI_LOWER_MEM 0x80000000
47#define MPC826x_PCI_UPPER_MEM 0x9fffffff
48#define MPC826x_PCI_MEM_OFFSET 0x00000000
49#endif
50
51#ifndef MPC826x_PCI_LOWER_MMIO
52#define MPC826x_PCI_LOWER_MMIO 0xa0000000
53#define MPC826x_PCI_UPPER_MMIO 0xafffffff
54#define MPC826x_PCI_MMIO_OFFSET 0x00000000
55#endif
56
57#ifndef MPC826x_PCI_LOWER_IO
58#define MPC826x_PCI_LOWER_IO 0x00000000
59#define MPC826x_PCI_UPPER_IO 0x00ffffff
60#define MPC826x_PCI_IO_BASE 0xb0000000
61#define MPC826x_PCI_IO_SIZE 0x01000000
62#endif
63
64#ifndef _IO_BASE
65#define _IO_BASE isa_io_base
66#endif
67
68#ifdef CONFIG_8260_PCI9
69struct pci_controller;
70extern void setup_m8260_indirect_pci(struct pci_controller* hose,
71 u32 cfg_addr, u32 cfg_data);
72#else
73#define setup_m8260_indirect_pci setup_indirect_pci
74#endif
75
76#endif /* _PPC_KERNEL_M8260_PCI_H */
diff --git a/arch/ppc/syslib/m8260_pci_erratum9.c b/arch/ppc/syslib/m8260_pci_erratum9.c
index 9c0582d639e0..1dc7e4e1d491 100644
--- a/arch/ppc/syslib/m8260_pci_erratum9.c
+++ b/arch/ppc/syslib/m8260_pci_erratum9.c
@@ -31,7 +31,7 @@
31#include <asm/immap_cpm2.h> 31#include <asm/immap_cpm2.h>
32#include <asm/cpm2.h> 32#include <asm/cpm2.h>
33 33
34#include "m8260_pci.h" 34#include "m82xx_pci.h"
35 35
36#ifdef CONFIG_8260_PCI9 36#ifdef CONFIG_8260_PCI9
37/*#include <asm/mpc8260_pci9.h>*/ /* included in asm/io.h */ 37/*#include <asm/mpc8260_pci9.h>*/ /* included in asm/io.h */
@@ -248,11 +248,11 @@ EXPORT_SYMBOL(idma_pci9_read_le);
248 248
249static inline int is_pci_mem(unsigned long addr) 249static inline int is_pci_mem(unsigned long addr)
250{ 250{
251 if (addr >= MPC826x_PCI_LOWER_MMIO && 251 if (addr >= M82xx_PCI_LOWER_MMIO &&
252 addr <= MPC826x_PCI_UPPER_MMIO) 252 addr <= M82xx_PCI_UPPER_MMIO)
253 return 1; 253 return 1;
254 if (addr >= MPC826x_PCI_LOWER_MEM && 254 if (addr >= M82xx_PCI_LOWER_MEM &&
255 addr <= MPC826x_PCI_UPPER_MEM) 255 addr <= M82xx_PCI_UPPER_MEM)
256 return 1; 256 return 1;
257 return 0; 257 return 0;
258} 258}
diff --git a/arch/ppc/syslib/m8260_setup.c b/arch/ppc/syslib/m8260_setup.c
index 23ea3f694de2..fda75d79050c 100644
--- a/arch/ppc/syslib/m8260_setup.c
+++ b/arch/ppc/syslib/m8260_setup.c
@@ -34,7 +34,8 @@
34unsigned char __res[sizeof(bd_t)]; 34unsigned char __res[sizeof(bd_t)];
35 35
36extern void cpm2_reset(void); 36extern void cpm2_reset(void);
37extern void m8260_find_bridges(void); 37extern void pq2_find_bridges(void);
38extern void pq2pci_init_irq(void);
38extern void idma_pci9_init(void); 39extern void idma_pci9_init(void);
39 40
40/* Place-holder for board-specific init */ 41/* Place-holder for board-specific init */
@@ -56,7 +57,7 @@ m8260_setup_arch(void)
56 idma_pci9_init(); 57 idma_pci9_init();
57#endif 58#endif
58#ifdef CONFIG_PCI_8260 59#ifdef CONFIG_PCI_8260
59 m8260_find_bridges(); 60 pq2_find_bridges();
60#endif 61#endif
61#ifdef CONFIG_BLK_DEV_INITRD 62#ifdef CONFIG_BLK_DEV_INITRD
62 if (initrd_start) 63 if (initrd_start)
@@ -173,6 +174,12 @@ m8260_init_IRQ(void)
173 * in case the boot rom changed something on us. 174 * in case the boot rom changed something on us.
174 */ 175 */
175 cpm2_immr->im_intctl.ic_siprr = 0x05309770; 176 cpm2_immr->im_intctl.ic_siprr = 0x05309770;
177
178#if defined(CONFIG_PCI) && (defined(CONFIG_ADS8272) || defined(CONFIG_PQ2FADS))
179 /* Initialize stuff for the 82xx CPLD IC and install demux */
180 pq2pci_init_irq();
181#endif
182
176} 183}
177 184
178/* 185/*
diff --git a/arch/ppc/syslib/m82xx_pci.c b/arch/ppc/syslib/m82xx_pci.c
new file mode 100644
index 000000000000..5e7a7edcea74
--- /dev/null
+++ b/arch/ppc/syslib/m82xx_pci.c
@@ -0,0 +1,383 @@
1/*
2 *
3 * (C) Copyright 2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
6 * (C) Copyright 2004 Red Hat, Inc.
7 *
8 * 2005 (c) MontaVista Software, Inc.
9 * Vitaly Bordug <vbordug@ru.mvista.com>
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30#include <linux/kernel.h>
31#include <linux/init.h>
32#include <linux/pci.h>
33#include <linux/slab.h>
34#include <linux/delay.h>
35#include <linux/irq.h>
36#include <linux/interrupt.h>
37
38#include <asm/byteorder.h>
39#include <asm/io.h>
40#include <asm/irq.h>
41#include <asm/uaccess.h>
42#include <asm/machdep.h>
43#include <asm/pci-bridge.h>
44#include <asm/immap_cpm2.h>
45#include <asm/mpc8260.h>
46#include <asm/cpm2.h>
47
48#include "m82xx_pci.h"
49
50/*
51 * Interrupt routing
52 */
53
54static inline int
55pq2pci_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
56{
57 static char pci_irq_table[][4] =
58 /*
59 * PCI IDSEL/INTPIN->INTLINE
60 * A B C D
61 */
62 {
63 { PIRQA, PIRQB, PIRQC, PIRQD }, /* IDSEL 22 - PCI slot 0 */
64 { PIRQD, PIRQA, PIRQB, PIRQC }, /* IDSEL 23 - PCI slot 1 */
65 { PIRQC, PIRQD, PIRQA, PIRQB }, /* IDSEL 24 - PCI slot 2 */
66 };
67
68 const long min_idsel = 22, max_idsel = 24, irqs_per_slot = 4;
69 return PCI_IRQ_TABLE_LOOKUP;
70}
71
72static void
73pq2pci_mask_irq(unsigned int irq)
74{
75 int bit = irq - NR_CPM_INTS;
76
77 *(volatile unsigned long *) PCI_INT_MASK_REG |= (1 << (31 - bit));
78 return;
79}
80
81static void
82pq2pci_unmask_irq(unsigned int irq)
83{
84 int bit = irq - NR_CPM_INTS;
85
86 *(volatile unsigned long *) PCI_INT_MASK_REG &= ~(1 << (31 - bit));
87 return;
88}
89
90static void
91pq2pci_mask_and_ack(unsigned int irq)
92{
93 int bit = irq - NR_CPM_INTS;
94
95 *(volatile unsigned long *) PCI_INT_MASK_REG |= (1 << (31 - bit));
96 return;
97}
98
99static void
100pq2pci_end_irq(unsigned int irq)
101{
102 int bit = irq - NR_CPM_INTS;
103
104 *(volatile unsigned long *) PCI_INT_MASK_REG &= ~(1 << (31 - bit));
105 return;
106}
107
108struct hw_interrupt_type pq2pci_ic = {
109 "PQ2 PCI",
110 NULL,
111 NULL,
112 pq2pci_unmask_irq,
113 pq2pci_mask_irq,
114 pq2pci_mask_and_ack,
115 pq2pci_end_irq,
116 0
117};
118
119static irqreturn_t
120pq2pci_irq_demux(int irq, void *dev_id, struct pt_regs *regs)
121{
122 unsigned long stat, mask, pend;
123 int bit;
124
125 for(;;) {
126 stat = *(volatile unsigned long *) PCI_INT_STAT_REG;
127 mask = *(volatile unsigned long *) PCI_INT_MASK_REG;
128 pend = stat & ~mask & 0xf0000000;
129 if (!pend)
130 break;
131 for (bit = 0; pend != 0; ++bit, pend <<= 1) {
132 if (pend & 0x80000000)
133 __do_IRQ(NR_CPM_INTS + bit, regs);
134 }
135 }
136
137 return IRQ_HANDLED;
138}
139
140static struct irqaction pq2pci_irqaction = {
141 .handler = pq2pci_irq_demux,
142 .flags = SA_INTERRUPT,
143 .mask = CPU_MASK_NONE,
144 .name = "PQ2 PCI cascade",
145};
146
147
148void
149pq2pci_init_irq(void)
150{
151 int irq;
152 volatile cpm2_map_t *immap = cpm2_immr;
153#if defined CONFIG_ADS8272
154 /* configure chip select for PCI interrupt controller */
155 immap->im_memctl.memc_br3 = PCI_INT_STAT_REG | 0x00001801;
156 immap->im_memctl.memc_or3 = 0xffff8010;
157#elif defined CONFIG_PQ2FADS
158 immap->im_memctl.memc_br8 = PCI_INT_STAT_REG | 0x00001801;
159 immap->im_memctl.memc_or8 = 0xffff8010;
160#endif
161 for (irq = NR_CPM_INTS; irq < NR_CPM_INTS + 4; irq++)
162 irq_desc[irq].handler = &pq2pci_ic;
163
164 /* make PCI IRQ level sensitive */
165 immap->im_intctl.ic_siexr &=
166 ~(1 << (14 - (PCI_INT_TO_SIU - SIU_INT_IRQ1)));
167
168 /* mask all PCI interrupts */
169 *(volatile unsigned long *) PCI_INT_MASK_REG |= 0xfff00000;
170
171 /* install the demultiplexer for the PCI cascade interrupt */
172 setup_irq(PCI_INT_TO_SIU, &pq2pci_irqaction);
173 return;
174}
175
176static int
177pq2pci_exclude_device(u_char bus, u_char devfn)
178{
179 return PCIBIOS_SUCCESSFUL;
180}
181
182/* PCI bus configuration registers.
183 */
184static void
185pq2ads_setup_pci(struct pci_controller *hose)
186{
187 __u32 val;
188 volatile cpm2_map_t *immap = cpm2_immr;
189 bd_t* binfo = (bd_t*) __res;
190 u32 sccr = immap->im_clkrst.car_sccr;
191 uint pci_div,freq,time;
192 /* PCI int lowest prio */
193 /* Each 4 bits is a device bus request and the MS 4bits
194 is highest priority */
195 /* Bus 4bit value
196 --- ----------
197 CPM high 0b0000
198 CPM middle 0b0001
199 CPM low 0b0010
200 PCI reguest 0b0011
201 Reserved 0b0100
202 Reserved 0b0101
203 Internal Core 0b0110
204 External Master 1 0b0111
205 External Master 2 0b1000
206 External Master 3 0b1001
207 The rest are reserved
208 */
209 immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x61207893;
210 /* park bus on core */
211 immap->im_siu_conf.siu_82xx.sc_ppc_acr = PPC_ACR_BUS_PARK_CORE;
212 /*
213 * Set up master windows that allow the CPU to access PCI space. These
214 * windows are set up using the two SIU PCIBR registers.
215 */
216
217 immap->im_memctl.memc_pcimsk0 = M82xx_PCI_PRIM_WND_SIZE;
218 immap->im_memctl.memc_pcibr0 = M82xx_PCI_PRIM_WND_BASE | PCIBR_ENABLE;
219
220#ifdef M82xx_PCI_SEC_WND_SIZE
221 immap->im_memctl.memc_pcimsk1 = M82xx_PCI_SEC_WND_SIZE;
222 immap->im_memctl.memc_pcibr1 = M82xx_PCI_SEC_WND_BASE | PCIBR_ENABLE;
223#endif
224
225#if defined CONFIG_ADS8272
226 immap->im_siu_conf.siu_82xx.sc_siumcr =
227 (immap->im_siu_conf.siu_82xx.sc_siumcr &
228 ~(SIUMCR_BBD | SIUMCR_ESE | SIUMCR_PBSE |
229 SIUMCR_CDIS | SIUMCR_DPPC11 | SIUMCR_L2CPC11 |
230 SIUMCR_LBPC11 | SIUMCR_APPC11 |
231 SIUMCR_CS10PC11 | SIUMCR_BCTLC11 | SIUMCR_MMR11)) |
232 SIUMCR_DPPC11 | SIUMCR_L2CPC01 | SIUMCR_LBPC00 |
233 SIUMCR_APPC10 | SIUMCR_CS10PC00 |
234 SIUMCR_BCTLC00 | SIUMCR_MMR11 ;
235
236#elif defined CONFIG_PQ2FADS
237 /*
238 * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
239 * and local bus for PCI (SIUMCR [LBPC]).
240 */
241 immap->im_siu_conf.siu_82xx.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
242 ~(SIUMCR_L2PC11 | SIUMCR_LBPC11 | SIUMCR_CS10PC11 | SIUMCR_APPC11) |
243 SIUMCR_BBD | SIUMCR_LBPC01 | SIUMCR_DPPC11 | SIUMCR_APPC10;
244#endif
245 /* Enable PCI */
246 immap->im_pci.pci_gcr = cpu_to_le32(PCIGCR_PCI_BUS_EN);
247
248 pci_div = ( (sccr & SCCR_PCI_MODCK) ? 2 : 1) *
249 ( ( (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT) + 1);
250 freq = (uint)((2*binfo->bi_cpmfreq)/(pci_div));
251 time = (int)666666/freq;
252 /* due to PCI Local Bus spec, some devices needs to wait such a long
253 time after RST deassertion. More specifically, 0.508s for 66MHz & twice more for 33 */
254 printk("%s: The PCI bus is %d Mhz.\nWaiting %s after deasserting RST...\n",__FILE__,freq,
255 (time==1) ? "0.5 seconds":"1 second" );
256
257 {
258 int i;
259 for(i=0;i<(500*time);i++)
260 udelay(1000);
261 }
262
263 /* setup ATU registers */
264 immap->im_pci.pci_pocmr0 = cpu_to_le32(POCMR_ENABLE | POCMR_PCI_IO |
265 ((~(M82xx_PCI_IO_SIZE - 1U)) >> POTA_ADDR_SHIFT));
266 immap->im_pci.pci_potar0 = cpu_to_le32(M82xx_PCI_LOWER_IO >> POTA_ADDR_SHIFT);
267 immap->im_pci.pci_pobar0 = cpu_to_le32(M82xx_PCI_IO_BASE >> POTA_ADDR_SHIFT);
268
269 /* Set-up non-prefetchable window */
270 immap->im_pci.pci_pocmr1 = cpu_to_le32(POCMR_ENABLE | ((~(M82xx_PCI_MMIO_SIZE-1U)) >> POTA_ADDR_SHIFT));
271 immap->im_pci.pci_potar1 = cpu_to_le32(M82xx_PCI_LOWER_MMIO >> POTA_ADDR_SHIFT);
272 immap->im_pci.pci_pobar1 = cpu_to_le32((M82xx_PCI_LOWER_MMIO - M82xx_PCI_MMIO_OFFSET) >> POTA_ADDR_SHIFT);
273
274 /* Set-up prefetchable window */
275 immap->im_pci.pci_pocmr2 = cpu_to_le32(POCMR_ENABLE |POCMR_PREFETCH_EN |
276 (~(M82xx_PCI_MEM_SIZE-1U) >> POTA_ADDR_SHIFT));
277 immap->im_pci.pci_potar2 = cpu_to_le32(M82xx_PCI_LOWER_MEM >> POTA_ADDR_SHIFT);
278 immap->im_pci.pci_pobar2 = cpu_to_le32((M82xx_PCI_LOWER_MEM - M82xx_PCI_MEM_OFFSET) >> POTA_ADDR_SHIFT);
279
280 /* Inbound transactions from PCI memory space */
281 immap->im_pci.pci_picmr0 = cpu_to_le32(PICMR_ENABLE | PICMR_PREFETCH_EN |
282 ((~(M82xx_PCI_SLAVE_MEM_SIZE-1U)) >> PITA_ADDR_SHIFT));
283 immap->im_pci.pci_pibar0 = cpu_to_le32(M82xx_PCI_SLAVE_MEM_BUS >> PITA_ADDR_SHIFT);
284 immap->im_pci.pci_pitar0 = cpu_to_le32(M82xx_PCI_SLAVE_MEM_LOCAL>> PITA_ADDR_SHIFT);
285
286#if defined CONFIG_ADS8272
287 /* PCI int highest prio */
288 immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x01236745;
289#elif defined CONFIG_PQ2FADS
290 immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x03124567;
291#endif
292 /* park bus on PCI */
293 immap->im_siu_conf.siu_82xx.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
294
295 /* Enable bus mastering and inbound memory transactions */
296 early_read_config_dword(hose, hose->first_busno, 0, PCI_COMMAND, &val);
297 val &= 0xffff0000;
298 val |= PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER;
299 early_write_config_dword(hose, hose->first_busno, 0, PCI_COMMAND, val);
300
301}
302
303void __init pq2_find_bridges(void)
304{
305 extern int pci_assign_all_busses;
306 struct pci_controller * hose;
307 int host_bridge;
308
309 pci_assign_all_busses = 1;
310
311 hose = pcibios_alloc_controller();
312
313 if (!hose)
314 return;
315
316 ppc_md.pci_swizzle = common_swizzle;
317
318 hose->first_busno = 0;
319 hose->bus_offset = 0;
320 hose->last_busno = 0xff;
321
322#ifdef CONFIG_ADS8272
323 hose->set_cfg_type = 1;
324#endif
325
326 setup_m8260_indirect_pci(hose,
327 (unsigned long)&cpm2_immr->im_pci.pci_cfg_addr,
328 (unsigned long)&cpm2_immr->im_pci.pci_cfg_data);
329
330 /* Make sure it is a supported bridge */
331 early_read_config_dword(hose,
332 0,
333 PCI_DEVFN(0,0),
334 PCI_VENDOR_ID,
335 &host_bridge);
336 switch (host_bridge) {
337 case PCI_DEVICE_ID_MPC8265:
338 break;
339 case PCI_DEVICE_ID_MPC8272:
340 break;
341 default:
342 printk("Attempting to use unrecognized host bridge ID"
343 " 0x%08x.\n", host_bridge);
344 break;
345 }
346
347 pq2ads_setup_pci(hose);
348
349 hose->io_space.start = M82xx_PCI_LOWER_IO;
350 hose->io_space.end = M82xx_PCI_UPPER_IO;
351 hose->mem_space.start = M82xx_PCI_LOWER_MEM;
352 hose->mem_space.end = M82xx_PCI_UPPER_MMIO;
353 hose->pci_mem_offset = M82xx_PCI_MEM_OFFSET;
354
355 isa_io_base =
356 (unsigned long) ioremap(M82xx_PCI_IO_BASE,
357 M82xx_PCI_IO_SIZE);
358 hose->io_base_virt = (void *) isa_io_base;
359
360 /* setup resources */
361 pci_init_resource(&hose->mem_resources[0],
362 M82xx_PCI_LOWER_MEM,
363 M82xx_PCI_UPPER_MEM,
364 IORESOURCE_MEM|IORESOURCE_PREFETCH, "PCI prefetchable memory");
365
366 pci_init_resource(&hose->mem_resources[1],
367 M82xx_PCI_LOWER_MMIO,
368 M82xx_PCI_UPPER_MMIO,
369 IORESOURCE_MEM, "PCI memory");
370
371 pci_init_resource(&hose->io_resource,
372 M82xx_PCI_LOWER_IO,
373 M82xx_PCI_UPPER_IO,
374 IORESOURCE_IO | 1, "PCI I/O");
375
376 ppc_md.pci_exclude_device = pq2pci_exclude_device;
377 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
378
379 ppc_md.pci_map_irq = pq2pci_map_irq;
380 ppc_md.pcibios_fixup = NULL;
381 ppc_md.pcibios_fixup_bus = NULL;
382
383}
diff --git a/arch/ppc/syslib/m82xx_pci.h b/arch/ppc/syslib/m82xx_pci.h
new file mode 100644
index 000000000000..924f73f8e595
--- /dev/null
+++ b/arch/ppc/syslib/m82xx_pci.h
@@ -0,0 +1,92 @@
1
2#ifndef _PPC_KERNEL_M82XX_PCI_H
3#define _PPC_KERNEL_M82XX_PCI_H
4
5#include <asm/m8260_pci.h>
6/*
7 * Local->PCI map (from CPU) controlled by
8 * MPC826x master window
9 *
10 * 0xF6000000 - 0xF7FFFFFF IO space
11 * 0x80000000 - 0xBFFFFFFF CPU2PCI memory space PCIBR0
12 *
13 * 0x80000000 - 0x9FFFFFFF PCI Mem with prefetch (Outbound ATU #1)
14 * 0xA0000000 - 0xBFFFFFFF PCI Mem w/o prefetch (Outbound ATU #2)
15 * 0xF6000000 - 0xF7FFFFFF 32-bit PCI IO (Outbound ATU #3)
16 *
17 * PCI->Local map (from PCI)
18 * MPC826x slave window controlled by
19 *
20 * 0x00000000 - 0x07FFFFFF MPC826x local memory (Inbound ATU #1)
21 */
22
23/*
24 * Slave window that allows PCI masters to access MPC826x local memory.
25 * This window is set up using the first set of Inbound ATU registers
26 */
27
28#ifndef M82xx_PCI_SLAVE_MEM_LOCAL
29#define M82xx_PCI_SLAVE_MEM_LOCAL (((struct bd_info *)__res)->bi_memstart)
30#define M82xx_PCI_SLAVE_MEM_BUS (((struct bd_info *)__res)->bi_memstart)
31#define M82xx_PCI_SLAVE_MEM_SIZE (((struct bd_info *)__res)->bi_memsize)
32#endif
33
34/*
35 * This is the window that allows the CPU to access PCI address space.
36 * It will be setup with the SIU PCIBR0 register. All three PCI master
37 * windows, which allow the CPU to access PCI prefetch, non prefetch,
38 * and IO space (see below), must all fit within this window.
39 */
40
41#ifndef M82xx_PCI_LOWER_MEM
42#define M82xx_PCI_LOWER_MEM 0x80000000
43#define M82xx_PCI_UPPER_MEM 0x9fffffff
44#define M82xx_PCI_MEM_OFFSET 0x00000000
45#define M82xx_PCI_MEM_SIZE 0x20000000
46#endif
47
48#ifndef M82xx_PCI_LOWER_MMIO
49#define M82xx_PCI_LOWER_MMIO 0xa0000000
50#define M82xx_PCI_UPPER_MMIO 0xafffffff
51#define M82xx_PCI_MMIO_OFFSET 0x00000000
52#define M82xx_PCI_MMIO_SIZE 0x20000000
53#endif
54
55#ifndef M82xx_PCI_LOWER_IO
56#define M82xx_PCI_LOWER_IO 0x00000000
57#define M82xx_PCI_UPPER_IO 0x01ffffff
58#define M82xx_PCI_IO_BASE 0xf6000000
59#define M82xx_PCI_IO_SIZE 0x02000000
60#endif
61
62#ifndef M82xx_PCI_PRIM_WND_SIZE
63#define M82xx_PCI_PRIM_WND_SIZE ~(M82xx_PCI_IO_SIZE - 1U)
64#define M82xx_PCI_PRIM_WND_BASE (M82xx_PCI_IO_BASE)
65#endif
66
67#ifndef M82xx_PCI_SEC_WND_SIZE
68#define M82xx_PCI_SEC_WND_SIZE ~(M82xx_PCI_MEM_SIZE + M82xx_PCI_MMIO_SIZE - 1U)
69#define M82xx_PCI_SEC_WND_BASE (M82xx_PCI_LOWER_MEM)
70#endif
71
72#ifndef POTA_ADDR_SHIFT
73#define POTA_ADDR_SHIFT 12
74#endif
75
76#ifndef PITA_ADDR_SHIFT
77#define PITA_ADDR_SHIFT 12
78#endif
79
80#ifndef _IO_BASE
81#define _IO_BASE isa_io_base
82#endif
83
84#ifdef CONFIG_8260_PCI9
85struct pci_controller;
86extern void setup_m8260_indirect_pci(struct pci_controller* hose,
87 u32 cfg_addr, u32 cfg_data);
88#else
89#define setup_m8260_indirect_pci setup_indirect_pci
90#endif
91
92#endif /* _PPC_KERNEL_M8260_PCI_H */
diff --git a/arch/ppc/syslib/mpc10x_common.c b/arch/ppc/syslib/mpc10x_common.c
index fd93adfd464c..8fc5f4154521 100644
--- a/arch/ppc/syslib/mpc10x_common.c
+++ b/arch/ppc/syslib/mpc10x_common.c
@@ -21,6 +21,9 @@
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/pci.h> 22#include <linux/pci.h>
23#include <linux/slab.h> 23#include <linux/slab.h>
24#include <linux/serial_8250.h>
25#include <linux/fsl_devices.h>
26#include <linux/device.h>
24 27
25#include <asm/byteorder.h> 28#include <asm/byteorder.h>
26#include <asm/io.h> 29#include <asm/io.h>
@@ -30,16 +33,7 @@
30#include <asm/pci-bridge.h> 33#include <asm/pci-bridge.h>
31#include <asm/open_pic.h> 34#include <asm/open_pic.h>
32#include <asm/mpc10x.h> 35#include <asm/mpc10x.h>
33#include <asm/ocp.h> 36#include <asm/ppc_sys.h>
34
35/* The OCP structure is fixed by code below, before OCP initialises.
36 paddr depends on where the board places the EUMB.
37 - fixed in mpc10x_bridge_init().
38 irq depends on two things:
39 > does the board use the EPIC at all? (PCORE does not).
40 > is the EPIC in serial or parallel mode?
41 - fixed in mpc10x_set_openpic().
42*/
43 37
44#ifdef CONFIG_MPC10X_OPENPIC 38#ifdef CONFIG_MPC10X_OPENPIC
45#ifdef CONFIG_EPIC_SERIAL_MODE 39#ifdef CONFIG_EPIC_SERIAL_MODE
@@ -50,35 +44,140 @@
50#define MPC10X_I2C_IRQ (EPIC_IRQ_BASE + NUM_8259_INTERRUPTS) 44#define MPC10X_I2C_IRQ (EPIC_IRQ_BASE + NUM_8259_INTERRUPTS)
51#define MPC10X_DMA0_IRQ (EPIC_IRQ_BASE + 1 + NUM_8259_INTERRUPTS) 45#define MPC10X_DMA0_IRQ (EPIC_IRQ_BASE + 1 + NUM_8259_INTERRUPTS)
52#define MPC10X_DMA1_IRQ (EPIC_IRQ_BASE + 2 + NUM_8259_INTERRUPTS) 46#define MPC10X_DMA1_IRQ (EPIC_IRQ_BASE + 2 + NUM_8259_INTERRUPTS)
47#define MPC10X_UART0_IRQ (EPIC_IRQ_BASE + 4 + NUM_8259_INTERRUPTS)
53#else 48#else
54#define MPC10X_I2C_IRQ OCP_IRQ_NA 49#define MPC10X_I2C_IRQ -1
55#define MPC10X_DMA0_IRQ OCP_IRQ_NA 50#define MPC10X_DMA0_IRQ -1
56#define MPC10X_DMA1_IRQ OCP_IRQ_NA 51#define MPC10X_DMA1_IRQ -1
52#define MPC10X_UART0_IRQ -1
57#endif 53#endif
58 54
59 55static struct fsl_i2c_platform_data mpc10x_i2c_pdata = {
60struct ocp_def core_ocp[] = { 56 .device_flags = 0,
61 { .vendor = OCP_VENDOR_INVALID
62 }
63}; 57};
64 58
65static struct ocp_fs_i2c_data mpc10x_i2c_data = { 59static struct plat_serial8250_port serial_platform_data[] = {
66 .flags = 0 60 [0] = {
61 .mapbase = 0x4500,
62 .iotype = UPIO_MEM,
63 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
64 },
65 [1] = {
66 .mapbase = 0x4600,
67 .iotype = UPIO_MEM,
68 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
69 },
70 { },
67}; 71};
68static struct ocp_def mpc10x_i2c_ocp = { 72
69 .vendor = OCP_VENDOR_MOTOROLA, 73struct platform_device ppc_sys_platform_devices[] = {
70 .function = OCP_FUNC_IIC, 74 [MPC10X_IIC1] = {
71 .index = 0, 75 .name = "fsl-i2c",
72 .additions = &mpc10x_i2c_data 76 .id = 1,
77 .dev.platform_data = &mpc10x_i2c_pdata,
78 .num_resources = 2,
79 .resource = (struct resource[]) {
80 {
81 .start = MPC10X_EUMB_I2C_OFFSET,
82 .end = MPC10X_EUMB_I2C_OFFSET +
83 MPC10X_EUMB_I2C_SIZE - 1,
84 .flags = IORESOURCE_MEM,
85 },
86 {
87 .flags = IORESOURCE_IRQ
88 },
89 },
90 },
91 [MPC10X_DMA0] = {
92 .name = "fsl-dma",
93 .id = 0,
94 .num_resources = 2,
95 .resource = (struct resource[]) {
96 {
97 .start = MPC10X_EUMB_DMA_OFFSET + 0x10,
98 .end = MPC10X_EUMB_DMA_OFFSET + 0x1f,
99 .flags = IORESOURCE_MEM,
100 },
101 {
102 .flags = IORESOURCE_IRQ,
103 },
104 },
105 },
106 [MPC10X_DMA1] = {
107 .name = "fsl-dma",
108 .id = 1,
109 .num_resources = 2,
110 .resource = (struct resource[]) {
111 {
112 .start = MPC10X_EUMB_DMA_OFFSET + 0x20,
113 .end = MPC10X_EUMB_DMA_OFFSET + 0x2f,
114 .flags = IORESOURCE_MEM,
115 },
116 {
117 .flags = IORESOURCE_IRQ,
118 },
119 },
120 },
121 [MPC10X_DMA1] = {
122 .name = "fsl-dma",
123 .id = 1,
124 .num_resources = 2,
125 .resource = (struct resource[]) {
126 {
127 .start = MPC10X_EUMB_DMA_OFFSET + 0x20,
128 .end = MPC10X_EUMB_DMA_OFFSET + 0x2f,
129 .flags = IORESOURCE_MEM,
130 },
131 {
132 .flags = IORESOURCE_IRQ,
133 },
134 },
135 },
136 [MPC10X_DUART] = {
137 .name = "serial8250",
138 .id = 0,
139 .dev.platform_data = serial_platform_data,
140 },
73}; 141};
74 142
75static struct ocp_def mpc10x_dma_ocp[2] = { 143/* We use the PCI ID to match on */
76{ .vendor = OCP_VENDOR_MOTOROLA, 144struct ppc_sys_spec *cur_ppc_sys_spec;
77 .function = OCP_FUNC_DMA, 145struct ppc_sys_spec ppc_sys_specs[] = {
78 .index = 0 }, 146 {
79{ .vendor = OCP_VENDOR_MOTOROLA, 147 .ppc_sys_name = "8245",
80 .function = OCP_FUNC_DMA, 148 .mask = 0xFFFFFFFF,
81 .index = 1 } 149 .value = MPC10X_BRIDGE_8245,
150 .num_devices = 4,
151 .device_list = (enum ppc_sys_devices[])
152 {
153 MPC10X_IIC1, MPC10X_DMA0, MPC10X_DMA1, MPC10X_DUART,
154 },
155 },
156 {
157 .ppc_sys_name = "8240",
158 .mask = 0xFFFFFFFF,
159 .value = MPC10X_BRIDGE_8240,
160 .num_devices = 3,
161 .device_list = (enum ppc_sys_devices[])
162 {
163 MPC10X_IIC1, MPC10X_DMA0, MPC10X_DMA1,
164 },
165 },
166 {
167 .ppc_sys_name = "107",
168 .mask = 0xFFFFFFFF,
169 .value = MPC10X_BRIDGE_107,
170 .num_devices = 3,
171 .device_list = (enum ppc_sys_devices[])
172 {
173 MPC10X_IIC1, MPC10X_DMA0, MPC10X_DMA1,
174 },
175 },
176 { /* default match */
177 .ppc_sys_name = "",
178 .mask = 0x00000000,
179 .value = 0x00000000,
180 },
82}; 181};
83 182
84/* Set resources to match bridge memory map */ 183/* Set resources to match bridge memory map */
@@ -132,7 +231,7 @@ mpc10x_bridge_init(struct pci_controller *hose,
132 uint new_map, 231 uint new_map,
133 uint phys_eumb_base) 232 uint phys_eumb_base)
134{ 233{
135 int host_bridge, picr1, picr1_bit; 234 int host_bridge, picr1, picr1_bit, i;
136 ulong pci_config_addr, pci_config_data; 235 ulong pci_config_addr, pci_config_data;
137 u_char pir, byte; 236 u_char pir, byte;
138 237
@@ -273,7 +372,7 @@ mpc10x_bridge_init(struct pci_controller *hose,
273 printk("Host bridge in Agent mode\n"); 372 printk("Host bridge in Agent mode\n");
274 /* Read or Set LMBAR & PCSRBAR? */ 373 /* Read or Set LMBAR & PCSRBAR? */
275 } 374 }
276 375
277 /* Set base addr of the 8240/107 EUMB. */ 376 /* Set base addr of the 8240/107 EUMB. */
278 early_write_config_dword(hose, 377 early_write_config_dword(hose,
279 0, 378 0,
@@ -287,17 +386,6 @@ mpc10x_bridge_init(struct pci_controller *hose,
287 ioremap(phys_eumb_base + MPC10X_EUMB_EPIC_OFFSET, 386 ioremap(phys_eumb_base + MPC10X_EUMB_EPIC_OFFSET,
288 MPC10X_EUMB_EPIC_SIZE); 387 MPC10X_EUMB_EPIC_SIZE);
289#endif 388#endif
290 mpc10x_i2c_ocp.paddr = phys_eumb_base + MPC10X_EUMB_I2C_OFFSET;
291 mpc10x_i2c_ocp.irq = MPC10X_I2C_IRQ;
292 ocp_add_one_device(&mpc10x_i2c_ocp);
293 mpc10x_dma_ocp[0].paddr = phys_eumb_base +
294 MPC10X_EUMB_DMA_OFFSET + 0x100;
295 mpc10x_dma_ocp[0].irq = MPC10X_DMA0_IRQ;
296 ocp_add_one_device(&mpc10x_dma_ocp[0]);
297 mpc10x_dma_ocp[1].paddr = phys_eumb_base +
298 MPC10X_EUMB_DMA_OFFSET + 0x200;
299 mpc10x_dma_ocp[1].irq = MPC10X_DMA1_IRQ;
300 ocp_add_one_device(&mpc10x_dma_ocp[1]);
301 } 389 }
302 390
303#ifdef CONFIG_MPC10X_STORE_GATHERING 391#ifdef CONFIG_MPC10X_STORE_GATHERING
@@ -306,6 +394,29 @@ mpc10x_bridge_init(struct pci_controller *hose,
306 mpc10x_disable_store_gathering(hose); 394 mpc10x_disable_store_gathering(hose);
307#endif 395#endif
308 396
397 /* setup platform devices for MPC10x bridges */
398 identify_ppc_sys_by_id (host_bridge);
399
400 for (i = 0; i < cur_ppc_sys_spec->num_devices; i++) {
401 unsigned int dev_id = cur_ppc_sys_spec->device_list[i];
402 ppc_sys_fixup_mem_resource(&ppc_sys_platform_devices[dev_id],
403 phys_eumb_base);
404 }
405
406 /* IRQ's are determined at runtime */
407 ppc_sys_platform_devices[MPC10X_IIC1].resource[1].start = MPC10X_I2C_IRQ;
408 ppc_sys_platform_devices[MPC10X_IIC1].resource[1].end = MPC10X_I2C_IRQ;
409 ppc_sys_platform_devices[MPC10X_DMA0].resource[1].start = MPC10X_DMA0_IRQ;
410 ppc_sys_platform_devices[MPC10X_DMA0].resource[1].end = MPC10X_DMA0_IRQ;
411 ppc_sys_platform_devices[MPC10X_DMA1].resource[1].start = MPC10X_DMA1_IRQ;
412 ppc_sys_platform_devices[MPC10X_DMA1].resource[1].end = MPC10X_DMA1_IRQ;
413
414 serial_platform_data[0].mapbase += phys_eumb_base;
415 serial_platform_data[0].irq = MPC10X_UART0_IRQ;
416
417 serial_platform_data[1].mapbase += phys_eumb_base;
418 serial_platform_data[1].irq = MPC10X_UART0_IRQ + 1;
419
309 /* 420 /*
310 * 8240 erratum 26, 8241/8245 erratum 29, 107 erratum 23: speculative 421 * 8240 erratum 26, 8241/8245 erratum 29, 107 erratum 23: speculative
311 * PCI reads may return stale data so turn off. 422 * PCI reads may return stale data so turn off.
@@ -330,7 +441,7 @@ mpc10x_bridge_init(struct pci_controller *hose,
330 * 8245 (Rev 2., dated 10/2003) says PICR2[0] is reserverd. 441 * 8245 (Rev 2., dated 10/2003) says PICR2[0] is reserverd.
331 */ 442 */
332 if (host_bridge == MPC10X_BRIDGE_8245) { 443 if (host_bridge == MPC10X_BRIDGE_8245) {
333 ulong picr2; 444 u32 picr2;
334 445
335 early_read_config_dword(hose, 0, PCI_DEVFN(0,0), 446 early_read_config_dword(hose, 0, PCI_DEVFN(0,0),
336 MPC10X_CFG_PICR2_REG, &picr2); 447 MPC10X_CFG_PICR2_REG, &picr2);
@@ -504,6 +615,8 @@ void __init mpc10x_set_openpic(void)
504 openpic_set_sources(EPIC_IRQ_BASE, 3, OpenPIC_Addr + 0x11020); 615 openpic_set_sources(EPIC_IRQ_BASE, 3, OpenPIC_Addr + 0x11020);
505 /* Skip reserved space and map Message Unit Interrupt (I2O) */ 616 /* Skip reserved space and map Message Unit Interrupt (I2O) */
506 openpic_set_sources(EPIC_IRQ_BASE + 3, 1, OpenPIC_Addr + 0x110C0); 617 openpic_set_sources(EPIC_IRQ_BASE + 3, 1, OpenPIC_Addr + 0x110C0);
618 /* Skip reserved space and map Serial Interupts */
619 openpic_set_sources(EPIC_IRQ_BASE + 4, 2, OpenPIC_Addr + 0x11120);
507 620
508 openpic_init(NUM_8259_INTERRUPTS); 621 openpic_init(NUM_8259_INTERRUPTS);
509} 622}
diff --git a/arch/ppc/syslib/mpc83xx_devices.c b/arch/ppc/syslib/mpc83xx_devices.c
index 5c1a919eaabf..75c8e9834ae7 100644
--- a/arch/ppc/syslib/mpc83xx_devices.c
+++ b/arch/ppc/syslib/mpc83xx_devices.c
@@ -61,6 +61,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
61 .iotype = UPIO_MEM, 61 .iotype = UPIO_MEM,
62 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, 62 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
63 }, 63 },
64 { },
64}; 65};
65 66
66struct platform_device ppc_sys_platform_devices[] = { 67struct platform_device ppc_sys_platform_devices[] = {
diff --git a/arch/ppc/syslib/mpc85xx_devices.c b/arch/ppc/syslib/mpc85xx_devices.c
index a231795ee26f..8af322dd476a 100644
--- a/arch/ppc/syslib/mpc85xx_devices.c
+++ b/arch/ppc/syslib/mpc85xx_devices.c
@@ -40,6 +40,42 @@ static struct gianfar_platform_data mpc85xx_tsec2_pdata = {
40 .phy_reg_addr = MPC85xx_ENET1_OFFSET, 40 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
41}; 41};
42 42
43static struct gianfar_platform_data mpc85xx_etsec1_pdata = {
44 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
45 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
46 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
47 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
48 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
49 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
50};
51
52static struct gianfar_platform_data mpc85xx_etsec2_pdata = {
53 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
54 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
55 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
56 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
57 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
58 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
59};
60
61static struct gianfar_platform_data mpc85xx_etsec3_pdata = {
62 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
63 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
64 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
65 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
66 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
67 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
68};
69
70static struct gianfar_platform_data mpc85xx_etsec4_pdata = {
71 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
72 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
73 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
74 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
75 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
76 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
77};
78
43static struct gianfar_platform_data mpc85xx_fec_pdata = { 79static struct gianfar_platform_data mpc85xx_fec_pdata = {
44 .phy_reg_addr = MPC85xx_ENET1_OFFSET, 80 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
45}; 81};
@@ -48,6 +84,10 @@ static struct fsl_i2c_platform_data mpc85xx_fsl_i2c_pdata = {
48 .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR, 84 .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
49}; 85};
50 86
87static struct fsl_i2c_platform_data mpc85xx_fsl_i2c2_pdata = {
88 .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
89};
90
51static struct plat_serial8250_port serial_platform_data[] = { 91static struct plat_serial8250_port serial_platform_data[] = {
52 [0] = { 92 [0] = {
53 .mapbase = 0x4500, 93 .mapbase = 0x4500,
@@ -61,6 +101,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
61 .iotype = UPIO_MEM, 101 .iotype = UPIO_MEM,
62 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ, 102 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ,
63 }, 103 },
104 { },
64}; 105};
65 106
66struct platform_device ppc_sys_platform_devices[] = { 107struct platform_device ppc_sys_platform_devices[] = {
@@ -280,7 +321,6 @@ struct platform_device ppc_sys_platform_devices[] = {
280 }, 321 },
281 }, 322 },
282 }, 323 },
283#ifdef CONFIG_CPM2
284 [MPC85xx_CPM_FCC1] = { 324 [MPC85xx_CPM_FCC1] = {
285 .name = "fsl-cpm-fcc", 325 .name = "fsl-cpm-fcc",
286 .id = 1, 326 .id = 1,
@@ -534,7 +574,151 @@ struct platform_device ppc_sys_platform_devices[] = {
534 }, 574 },
535 }, 575 },
536 }, 576 },
537#endif /* CONFIG_CPM2 */ 577 [MPC85xx_eTSEC1] = {
578 .name = "fsl-gianfar",
579 .id = 1,
580 .dev.platform_data = &mpc85xx_etsec1_pdata,
581 .num_resources = 4,
582 .resource = (struct resource[]) {
583 {
584 .start = MPC85xx_ENET1_OFFSET,
585 .end = MPC85xx_ENET1_OFFSET +
586 MPC85xx_ENET1_SIZE - 1,
587 .flags = IORESOURCE_MEM,
588 },
589 {
590 .name = "tx",
591 .start = MPC85xx_IRQ_TSEC1_TX,
592 .end = MPC85xx_IRQ_TSEC1_TX,
593 .flags = IORESOURCE_IRQ,
594 },
595 {
596 .name = "rx",
597 .start = MPC85xx_IRQ_TSEC1_RX,
598 .end = MPC85xx_IRQ_TSEC1_RX,
599 .flags = IORESOURCE_IRQ,
600 },
601 {
602 .name = "error",
603 .start = MPC85xx_IRQ_TSEC1_ERROR,
604 .end = MPC85xx_IRQ_TSEC1_ERROR,
605 .flags = IORESOURCE_IRQ,
606 },
607 },
608 },
609 [MPC85xx_eTSEC2] = {
610 .name = "fsl-gianfar",
611 .id = 2,
612 .dev.platform_data = &mpc85xx_etsec2_pdata,
613 .num_resources = 4,
614 .resource = (struct resource[]) {
615 {
616 .start = MPC85xx_ENET2_OFFSET,
617 .end = MPC85xx_ENET2_OFFSET +
618 MPC85xx_ENET2_SIZE - 1,
619 .flags = IORESOURCE_MEM,
620 },
621 {
622 .name = "tx",
623 .start = MPC85xx_IRQ_TSEC2_TX,
624 .end = MPC85xx_IRQ_TSEC2_TX,
625 .flags = IORESOURCE_IRQ,
626 },
627 {
628 .name = "rx",
629 .start = MPC85xx_IRQ_TSEC2_RX,
630 .end = MPC85xx_IRQ_TSEC2_RX,
631 .flags = IORESOURCE_IRQ,
632 },
633 {
634 .name = "error",
635 .start = MPC85xx_IRQ_TSEC2_ERROR,
636 .end = MPC85xx_IRQ_TSEC2_ERROR,
637 .flags = IORESOURCE_IRQ,
638 },
639 },
640 },
641 [MPC85xx_eTSEC3] = {
642 .name = "fsl-gianfar",
643 .id = 3,
644 .dev.platform_data = &mpc85xx_etsec3_pdata,
645 .num_resources = 4,
646 .resource = (struct resource[]) {
647 {
648 .start = MPC85xx_ENET3_OFFSET,
649 .end = MPC85xx_ENET3_OFFSET +
650 MPC85xx_ENET3_SIZE - 1,
651 .flags = IORESOURCE_MEM,
652 },
653 {
654 .name = "tx",
655 .start = MPC85xx_IRQ_TSEC3_TX,
656 .end = MPC85xx_IRQ_TSEC3_TX,
657 .flags = IORESOURCE_IRQ,
658 },
659 {
660 .name = "rx",
661 .start = MPC85xx_IRQ_TSEC3_RX,
662 .end = MPC85xx_IRQ_TSEC3_RX,
663 .flags = IORESOURCE_IRQ,
664 },
665 {
666 .name = "error",
667 .start = MPC85xx_IRQ_TSEC3_ERROR,
668 .end = MPC85xx_IRQ_TSEC3_ERROR,
669 .flags = IORESOURCE_IRQ,
670 },
671 },
672 },
673 [MPC85xx_eTSEC4] = {
674 .name = "fsl-gianfar",
675 .id = 4,
676 .dev.platform_data = &mpc85xx_etsec4_pdata,
677 .num_resources = 4,
678 .resource = (struct resource[]) {
679 {
680 .start = 0x27000,
681 .end = 0x27fff,
682 .flags = IORESOURCE_MEM,
683 },
684 {
685 .name = "tx",
686 .start = MPC85xx_IRQ_TSEC4_TX,
687 .end = MPC85xx_IRQ_TSEC4_TX,
688 .flags = IORESOURCE_IRQ,
689 },
690 {
691 .name = "rx",
692 .start = MPC85xx_IRQ_TSEC4_RX,
693 .end = MPC85xx_IRQ_TSEC4_RX,
694 .flags = IORESOURCE_IRQ,
695 },
696 {
697 .name = "error",
698 .start = MPC85xx_IRQ_TSEC4_ERROR,
699 .end = MPC85xx_IRQ_TSEC4_ERROR,
700 .flags = IORESOURCE_IRQ,
701 },
702 },
703 },
704 [MPC85xx_IIC2] = {
705 .name = "fsl-i2c",
706 .id = 2,
707 .dev.platform_data = &mpc85xx_fsl_i2c2_pdata,
708 .num_resources = 2,
709 .resource = (struct resource[]) {
710 {
711 .start = 0x03100,
712 .end = 0x031ff,
713 .flags = IORESOURCE_MEM,
714 },
715 {
716 .start = MPC85xx_IRQ_IIC1,
717 .end = MPC85xx_IRQ_IIC1,
718 .flags = IORESOURCE_IRQ,
719 },
720 },
721 },
538}; 722};
539 723
540static int __init mach_mpc85xx_fixup(struct platform_device *pdev) 724static int __init mach_mpc85xx_fixup(struct platform_device *pdev)
diff --git a/arch/ppc/syslib/mpc85xx_sys.c b/arch/ppc/syslib/mpc85xx_sys.c
index d806a92a9401..6e3184ab354f 100644
--- a/arch/ppc/syslib/mpc85xx_sys.c
+++ b/arch/ppc/syslib/mpc85xx_sys.c
@@ -110,6 +110,111 @@ struct ppc_sys_spec ppc_sys_specs[] = {
110 MPC85xx_CPM_USB, 110 MPC85xx_CPM_USB,
111 }, 111 },
112 }, 112 },
113 /* SVRs on 8548 rev1.0 matches for 8548/8547/8545 */
114 {
115 .ppc_sys_name = "8548E",
116 .mask = 0xFFFF00F0,
117 .value = 0x80390010,
118 .num_devices = 13,
119 .device_list = (enum ppc_sys_devices[])
120 {
121 MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3,
122 MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2,
123 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
124 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2,
125 },
126 },
127 {
128 .ppc_sys_name = "8548",
129 .mask = 0xFFFF00F0,
130 .value = 0x80310010,
131 .num_devices = 12,
132 .device_list = (enum ppc_sys_devices[])
133 {
134 MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3,
135 MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2,
136 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
137 MPC85xx_PERFMON, MPC85xx_DUART,
138 },
139 },
140 {
141 .ppc_sys_name = "8547E",
142 .mask = 0xFFFF00F0,
143 .value = 0x80390010,
144 .num_devices = 13,
145 .device_list = (enum ppc_sys_devices[])
146 {
147 MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3,
148 MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2,
149 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
150 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2,
151 },
152 },
153 {
154 .ppc_sys_name = "8547",
155 .mask = 0xFFFF00F0,
156 .value = 0x80310010,
157 .num_devices = 12,
158 .device_list = (enum ppc_sys_devices[])
159 {
160 MPC85xx_eTSEC1, MPC85xx_eTSEC2, MPC85xx_eTSEC3,
161 MPC85xx_eTSEC4, MPC85xx_IIC1, MPC85xx_IIC2,
162 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
163 MPC85xx_PERFMON, MPC85xx_DUART,
164 },
165 },
166 {
167 .ppc_sys_name = "8545E",
168 .mask = 0xFFFF00F0,
169 .value = 0x80390010,
170 .num_devices = 11,
171 .device_list = (enum ppc_sys_devices[])
172 {
173 MPC85xx_eTSEC1, MPC85xx_eTSEC2,
174 MPC85xx_IIC1, MPC85xx_IIC2,
175 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
176 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2,
177 },
178 },
179 {
180 .ppc_sys_name = "8545",
181 .mask = 0xFFFF00F0,
182 .value = 0x80310010,
183 .num_devices = 10,
184 .device_list = (enum ppc_sys_devices[])
185 {
186 MPC85xx_eTSEC1, MPC85xx_eTSEC2,
187 MPC85xx_IIC1, MPC85xx_IIC2,
188 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
189 MPC85xx_PERFMON, MPC85xx_DUART,
190 },
191 },
192 {
193 .ppc_sys_name = "8543E",
194 .mask = 0xFFFF00F0,
195 .value = 0x803A0010,
196 .num_devices = 11,
197 .device_list = (enum ppc_sys_devices[])
198 {
199 MPC85xx_eTSEC1, MPC85xx_eTSEC2,
200 MPC85xx_IIC1, MPC85xx_IIC2,
201 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
202 MPC85xx_PERFMON, MPC85xx_DUART, MPC85xx_SEC2,
203 },
204 },
205 {
206 .ppc_sys_name = "8543",
207 .mask = 0xFFFF00F0,
208 .value = 0x80320010,
209 .num_devices = 10,
210 .device_list = (enum ppc_sys_devices[])
211 {
212 MPC85xx_eTSEC1, MPC85xx_eTSEC2,
213 MPC85xx_IIC1, MPC85xx_IIC2,
214 MPC85xx_DMA0, MPC85xx_DMA1, MPC85xx_DMA2, MPC85xx_DMA3,
215 MPC85xx_PERFMON, MPC85xx_DUART,
216 },
217 },
113 { /* default match */ 218 { /* default match */
114 .ppc_sys_name = "", 219 .ppc_sys_name = "",
115 .mask = 0x00000000, 220 .mask = 0x00000000,
diff --git a/arch/ppc/syslib/ocp.c b/arch/ppc/syslib/ocp.c
index a5156c5179a6..e5fd2ae503ea 100644
--- a/arch/ppc/syslib/ocp.c
+++ b/arch/ppc/syslib/ocp.c
@@ -68,7 +68,7 @@ static int ocp_inited;
68/* Sysfs support */ 68/* Sysfs support */
69#define OCP_DEF_ATTR(field, format_string) \ 69#define OCP_DEF_ATTR(field, format_string) \
70static ssize_t \ 70static ssize_t \
71show_##field(struct device *dev, char *buf) \ 71show_##field(struct device *dev, struct device_attribute *attr, char *buf) \
72{ \ 72{ \
73 struct ocp_device *odev = to_ocp_dev(dev); \ 73 struct ocp_device *odev = to_ocp_dev(dev); \
74 \ 74 \
diff --git a/arch/ppc/syslib/of_device.c b/arch/ppc/syslib/of_device.c
index 46269ed21aee..49c0e34e2d6b 100644
--- a/arch/ppc/syslib/of_device.c
+++ b/arch/ppc/syslib/of_device.c
@@ -161,7 +161,7 @@ void of_unregister_driver(struct of_platform_driver *drv)
161} 161}
162 162
163 163
164static ssize_t dev_show_devspec(struct device *dev, char *buf) 164static ssize_t dev_show_devspec(struct device *dev, struct device_attribute *attr, char *buf)
165{ 165{
166 struct of_device *ofdev; 166 struct of_device *ofdev;
167 167
diff --git a/arch/ppc/syslib/open_pic.c b/arch/ppc/syslib/open_pic.c
index 7619e16fccae..b45d8268bf93 100644
--- a/arch/ppc/syslib/open_pic.c
+++ b/arch/ppc/syslib/open_pic.c
@@ -21,7 +21,6 @@
21#include <asm/signal.h> 21#include <asm/signal.h>
22#include <asm/io.h> 22#include <asm/io.h>
23#include <asm/irq.h> 23#include <asm/irq.h>
24#include <asm/prom.h>
25#include <asm/sections.h> 24#include <asm/sections.h>
26#include <asm/open_pic.h> 25#include <asm/open_pic.h>
27#include <asm/i8259.h> 26#include <asm/i8259.h>
@@ -275,7 +274,7 @@ static void __init openpic_enable_sie(void)
275} 274}
276#endif 275#endif
277 276
278#if defined(CONFIG_EPIC_SERIAL_MODE) || defined(CONFIG_PM) 277#if defined(CONFIG_EPIC_SERIAL_MODE)
279static void openpic_reset(void) 278static void openpic_reset(void)
280{ 279{
281 openpic_setfield(&OpenPIC->Global.Global_Configuration0, 280 openpic_setfield(&OpenPIC->Global.Global_Configuration0,
@@ -557,12 +556,10 @@ static void __init openpic_initipi(u_int ipi, u_int pri, u_int vec)
557 */ 556 */
558void openpic_cause_IPI(u_int ipi, cpumask_t cpumask) 557void openpic_cause_IPI(u_int ipi, cpumask_t cpumask)
559{ 558{
560 cpumask_t phys;
561 DECL_THIS_CPU; 559 DECL_THIS_CPU;
562 560
563 CHECK_THIS_CPU; 561 CHECK_THIS_CPU;
564 check_arg_ipi(ipi); 562 check_arg_ipi(ipi);
565 phys = physmask(cpumask);
566 openpic_write(&OpenPIC->THIS_CPU.IPI_Dispatch(ipi), 563 openpic_write(&OpenPIC->THIS_CPU.IPI_Dispatch(ipi),
567 cpus_addr(physmask(cpumask))[0]); 564 cpus_addr(physmask(cpumask))[0]);
568} 565}
@@ -995,8 +992,6 @@ int openpic_resume(struct sys_device *sysdev)
995 return 0; 992 return 0;
996 } 993 }
997 994
998 openpic_reset();
999
1000 /* OpenPIC sometimes seem to need some time to be fully back up... */ 995 /* OpenPIC sometimes seem to need some time to be fully back up... */
1001 do { 996 do {
1002 openpic_set_spurious(OPENPIC_VEC_SPURIOUS); 997 openpic_set_spurious(OPENPIC_VEC_SPURIOUS);
diff --git a/arch/ppc/syslib/open_pic2.c b/arch/ppc/syslib/open_pic2.c
index ea26da0d8b6b..7e272c51a497 100644
--- a/arch/ppc/syslib/open_pic2.c
+++ b/arch/ppc/syslib/open_pic2.c
@@ -25,7 +25,6 @@
25#include <asm/signal.h> 25#include <asm/signal.h>
26#include <asm/io.h> 26#include <asm/io.h>
27#include <asm/irq.h> 27#include <asm/irq.h>
28#include <asm/prom.h>
29#include <asm/sections.h> 28#include <asm/sections.h>
30#include <asm/open_pic.h> 29#include <asm/open_pic.h>
31#include <asm/i8259.h> 30#include <asm/i8259.h>
diff --git a/arch/ppc/syslib/ppc4xx_kgdb.c b/arch/ppc/syslib/ppc4xx_kgdb.c
deleted file mode 100644
index fe8668bf8137..000000000000
--- a/arch/ppc/syslib/ppc4xx_kgdb.c
+++ /dev/null
@@ -1,124 +0,0 @@
1#include <linux/config.h>
2#include <linux/types.h>
3#include <asm/ibm4xx.h>
4#include <linux/kernel.h>
5
6
7
8#define LSR_DR 0x01 /* Data ready */
9#define LSR_OE 0x02 /* Overrun */
10#define LSR_PE 0x04 /* Parity error */
11#define LSR_FE 0x08 /* Framing error */
12#define LSR_BI 0x10 /* Break */
13#define LSR_THRE 0x20 /* Xmit holding register empty */
14#define LSR_TEMT 0x40 /* Xmitter empty */
15#define LSR_ERR 0x80 /* Error */
16
17#include <platforms/4xx/ibm_ocp.h>
18
19extern struct NS16550* COM_PORTS[];
20#ifndef NULL
21#define NULL 0x00
22#endif
23
24static volatile struct NS16550 *kgdb_debugport = NULL;
25
26volatile struct NS16550 *
27NS16550_init(int chan)
28{
29 volatile struct NS16550 *com_port;
30 int quot;
31#ifdef BASE_BAUD
32 quot = BASE_BAUD / 9600;
33#else
34 quot = 0x000c; /* 0xc = 9600 baud (on a pc) */
35#endif
36
37 com_port = (struct NS16550 *) COM_PORTS[chan];
38
39 com_port->lcr = 0x00;
40 com_port->ier = 0xFF;
41 com_port->ier = 0x00;
42 com_port->lcr = com_port->lcr | 0x80; /* Access baud rate */
43 com_port->dll = ( quot & 0x00ff ); /* 0xc = 9600 baud */
44 com_port->dlm = ( quot & 0xff00 ) >> 8;
45 com_port->lcr = 0x03; /* 8 data, 1 stop, no parity */
46 com_port->mcr = 0x00; /* RTS/DTR */
47 com_port->fcr = 0x07; /* Clear & enable FIFOs */
48
49 return( com_port );
50}
51
52
53void
54NS16550_putc(volatile struct NS16550 *com_port, unsigned char c)
55{
56 while ((com_port->lsr & LSR_THRE) == 0)
57 ;
58 com_port->thr = c;
59 return;
60}
61
62unsigned char
63NS16550_getc(volatile struct NS16550 *com_port)
64{
65 while ((com_port->lsr & LSR_DR) == 0)
66 ;
67 return (com_port->rbr);
68}
69
70unsigned char
71NS16550_tstc(volatile struct NS16550 *com_port)
72{
73 return ((com_port->lsr & LSR_DR) != 0);
74}
75
76
77#if defined(CONFIG_KGDB_TTYS0)
78#define KGDB_PORT 0
79#elif defined(CONFIG_KGDB_TTYS1)
80#define KGDB_PORT 1
81#elif defined(CONFIG_KGDB_TTYS2)
82#define KGDB_PORT 2
83#elif defined(CONFIG_KGDB_TTYS3)
84#define KGDB_PORT 3
85#else
86#error "invalid kgdb_tty port"
87#endif
88
89void putDebugChar( unsigned char c )
90{
91 if ( kgdb_debugport == NULL )
92 kgdb_debugport = NS16550_init(KGDB_PORT);
93 NS16550_putc( kgdb_debugport, c );
94}
95
96int getDebugChar( void )
97{
98 if (kgdb_debugport == NULL)
99 kgdb_debugport = NS16550_init(KGDB_PORT);
100
101 return(NS16550_getc(kgdb_debugport));
102}
103
104void kgdb_interruptible(int enable)
105{
106 return;
107}
108
109void putDebugString(char* str)
110{
111 while (*str != '\0') {
112 putDebugChar(*str);
113 str++;
114 }
115 putDebugChar('\r');
116 return;
117}
118
119void
120kgdb_map_scc(void)
121{
122 printk("kgdb init \n");
123 kgdb_debugport = NS16550_init(KGDB_PORT);
124}
diff --git a/arch/ppc/syslib/ppc83xx_setup.c b/arch/ppc/syslib/ppc83xx_setup.c
index c28f9d679484..602a86891f7f 100644
--- a/arch/ppc/syslib/ppc83xx_setup.c
+++ b/arch/ppc/syslib/ppc83xx_setup.c
@@ -23,12 +23,12 @@
23#include <linux/serial_core.h> 23#include <linux/serial_core.h>
24#include <linux/serial_8250.h> 24#include <linux/serial_8250.h>
25 25
26#include <asm/prom.h>
27#include <asm/time.h> 26#include <asm/time.h>
28#include <asm/mpc83xx.h> 27#include <asm/mpc83xx.h>
29#include <asm/mmu.h> 28#include <asm/mmu.h>
30#include <asm/ppc_sys.h> 29#include <asm/ppc_sys.h>
31#include <asm/kgdb.h> 30#include <asm/kgdb.h>
31#include <asm/delay.h>
32 32
33#include <syslib/ppc83xx_setup.h> 33#include <syslib/ppc83xx_setup.h>
34 34
@@ -117,7 +117,34 @@ mpc83xx_early_serial_map(void)
117void 117void
118mpc83xx_restart(char *cmd) 118mpc83xx_restart(char *cmd)
119{ 119{
120 volatile unsigned char __iomem *reg;
121 unsigned char tmp;
122
123 reg = ioremap(BCSR_PHYS_ADDR, BCSR_SIZE);
124
120 local_irq_disable(); 125 local_irq_disable();
126
127 /*
128 * Unlock the BCSR bits so a PRST will update the contents.
129 * Otherwise the reset asserts but doesn't clear.
130 */
131 tmp = in_8(reg + BCSR_MISC_REG3_OFF);
132 tmp |= BCSR_MISC_REG3_CNFLOCK; /* low true, high false */
133 out_8(reg + BCSR_MISC_REG3_OFF, tmp);
134
135 /*
136 * Trigger a reset via a low->high transition of the
137 * PORESET bit.
138 */
139 tmp = in_8(reg + BCSR_MISC_REG2_OFF);
140 tmp &= ~BCSR_MISC_REG2_PORESET;
141 out_8(reg + BCSR_MISC_REG2_OFF, tmp);
142
143 udelay(1);
144
145 tmp |= BCSR_MISC_REG2_PORESET;
146 out_8(reg + BCSR_MISC_REG2_OFF, tmp);
147
121 for(;;); 148 for(;;);
122} 149}
123 150
diff --git a/arch/ppc/syslib/ppc85xx_setup.c b/arch/ppc/syslib/ppc85xx_setup.c
index 152c3ef1312a..ca95d79a704e 100644
--- a/arch/ppc/syslib/ppc85xx_setup.c
+++ b/arch/ppc/syslib/ppc85xx_setup.c
@@ -23,7 +23,6 @@
23#include <linux/serial_core.h> 23#include <linux/serial_core.h>
24#include <linux/serial_8250.h> 24#include <linux/serial_8250.h>
25 25
26#include <asm/prom.h>
27#include <asm/time.h> 26#include <asm/time.h>
28#include <asm/mpc85xx.h> 27#include <asm/mpc85xx.h>
29#include <asm/immap_85xx.h> 28#include <asm/immap_85xx.h>
@@ -33,6 +32,8 @@
33 32
34#include <syslib/ppc85xx_setup.h> 33#include <syslib/ppc85xx_setup.h>
35 34
35extern void abort(void);
36
36/* Return the amount of memory */ 37/* Return the amount of memory */
37unsigned long __init 38unsigned long __init
38mpc85xx_find_end_of_memory(void) 39mpc85xx_find_end_of_memory(void)
@@ -132,6 +133,12 @@ mpc85xx_halt(void)
132} 133}
133 134
134#ifdef CONFIG_PCI 135#ifdef CONFIG_PCI
136
137#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
138extern void mpc85xx_cds_enable_via(struct pci_controller *hose);
139extern void mpc85xx_cds_fixup_via(struct pci_controller *hose);
140#endif
141
135static void __init 142static void __init
136mpc85xx_setup_pci1(struct pci_controller *hose) 143mpc85xx_setup_pci1(struct pci_controller *hose)
137{ 144{
@@ -302,8 +309,18 @@ mpc85xx_setup_hose(void)
302 309
303 ppc_md.pci_exclude_device = mpc85xx_exclude_device; 310 ppc_md.pci_exclude_device = mpc85xx_exclude_device;
304 311
312#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
313 /* Pre pciauto_bus_scan VIA init */
314 mpc85xx_cds_enable_via(hose_a);
315#endif
316
305 hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno); 317 hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno);
306 318
319#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
320 /* Post pciauto_bus_scan VIA fixup */
321 mpc85xx_cds_fixup_via(hose_a);
322#endif
323
307#ifdef CONFIG_85xx_PCI2 324#ifdef CONFIG_85xx_PCI2
308 hose_b = pcibios_alloc_controller(); 325 hose_b = pcibios_alloc_controller();
309 326
diff --git a/arch/ppc/syslib/prom_init.c b/arch/ppc/syslib/prom_init.c
index 2cee87137f2e..7f15136830f4 100644
--- a/arch/ppc/syslib/prom_init.c
+++ b/arch/ppc/syslib/prom_init.c
@@ -626,8 +626,18 @@ inspect_node(phandle node, struct device_node *dad,
626 l = call_prom("package-to-path", 3, 1, node, 626 l = call_prom("package-to-path", 3, 1, node,
627 mem_start, mem_end - mem_start); 627 mem_start, mem_end - mem_start);
628 if (l >= 0) { 628 if (l >= 0) {
629 char *p, *ep;
630
629 np->full_name = PTRUNRELOC((char *) mem_start); 631 np->full_name = PTRUNRELOC((char *) mem_start);
630 *(char *)(mem_start + l) = 0; 632 *(char *)(mem_start + l) = 0;
633 /* Fixup an Apple bug where they have bogus \0 chars in the
634 * middle of the path in some properties
635 */
636 for (p = (char *)mem_start, ep = p + l; p < ep; p++)
637 if ((*p) == '\0') {
638 memmove(p, p+1, ep - p);
639 ep--;
640 }
631 mem_start = ALIGNUL(mem_start + l + 1); 641 mem_start = ALIGNUL(mem_start + l + 1);
632 } 642 }
633 643
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-16 11:50:33 -0500