Automatic merge of /spare/repo/linux-2.6/.git branch HEAD

8 files changed, 196 insertions, 41 deletions

diff --git a/arch/ppc/platforms/83xx/mpc834x_sys.c b/arch/ppc/platforms/83xx/mpc834x_sys.c
index b3b0f51979d2..e6348b5a1ddc 100644
--- a/arch/ppc/platforms/83xx/mpc834x_sys.c
+++ b/arch/ppc/platforms/83xx/mpc834x_sys.c
@@ -127,7 +127,6 @@ mpc834x_sys_map_io(void)
 {
         /* we steal the lowest ioremap addr for virt space */
         io_block_mapping(VIRT_IMMRBAR, immrbar, 1024*1024, _PAGE_IO);
-        io_block_mapping(BCSR_VIRT_ADDR, BCSR_PHYS_ADDR, BCSR_SIZE, _PAGE_IO);
 }
 
 int
diff --git a/arch/ppc/platforms/83xx/mpc834x_sys.h b/arch/ppc/platforms/83xx/mpc834x_sys.h
index f4d055ae19c1..a2f6e49d7151 100644
--- a/arch/ppc/platforms/83xx/mpc834x_sys.h
+++ b/arch/ppc/platforms/83xx/mpc834x_sys.h
@@ -26,9 +26,14 @@
 #define VIRT_IMMRBAR            ((uint)0xfe000000)
 
 #define BCSR_PHYS_ADDR          ((uint)0xf8000000)
-#define BCSR_VIRT_ADDR          ((uint)0xfe100000)
 #define BCSR_SIZE               ((uint)(32 * 1024))
 
+#define BCSR_MISC_REG2_OFF      0x07
+#define BCSR_MISC_REG2_PORESET  0x01
+
+#define BCSR_MISC_REG3_OFF      0x08
+#define BCSR_MISC_REG3_CNFLOCK  0x80
+
 #ifdef CONFIG_PCI
 /* PCI interrupt controller */
 #define PIRQA        MPC83xx_IRQ_IRQ4
diff --git a/arch/ppc/platforms/85xx/mpc8540_ads.c b/arch/ppc/platforms/85xx/mpc8540_ads.c
index 4d857d6d633d..583838ab02d8 100644
--- a/arch/ppc/platforms/85xx/mpc8540_ads.c
+++ b/arch/ppc/platforms/85xx/mpc8540_ads.c
@@ -210,6 +210,9 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 #if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
         ppc_md.progress = gen550_progress;
 #endif  /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */
+#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_KGDB)
+        ppc_md.early_serial_map = mpc85xx_early_serial_map;
+#endif  /* CONFIG_SERIAL_8250 && CONFIG_KGDB */
 
         if (ppc_md.progress)
                 ppc_md.progress("mpc8540ads_init(): exit", 0);
diff --git a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
index 6c020d67ad70..e7cfa498568c 100644
--- a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
+++ b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
@@ -44,6 +44,7 @@
 #include <asm/machdep.h>
 #include <asm/prom.h>
 #include <asm/open_pic.h>
+#include <asm/i8259.h>
 #include <asm/bootinfo.h>
 #include <asm/pci-bridge.h>
 #include <asm/mpc85xx.h>
@@ -181,6 +182,7 @@ void __init
 mpc85xx_cds_init_IRQ(void)
 {
         bd_t *binfo = (bd_t *) __res;
+        int i;
 
         /* Determine the Physical Address of the OpenPIC regs */
         phys_addr_t OpenPIC_PAddr = binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
@@ -198,6 +200,15 @@ mpc85xx_cds_init_IRQ(void)
          */
         openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
 
+#ifdef CONFIG_PCI
+        openpic_hookup_cascade(PIRQ0A, "82c59 cascade", i8259_irq);
+
+        for (i = 0; i < NUM_8259_INTERRUPTS; i++)
+                irq_desc[i].handler = &i8259_pic;
+
+        i8259_init(0);
+#endif
+
 #ifdef CONFIG_CPM2
         /* Setup CPM2 PIC */
         cpm2_init_IRQ();
@@ -231,7 +242,7 @@ mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
                          * interrupt on slot */
                 {
                         { 0, 1, 2, 3 }, /* 16 - PMC */
-                        { 3, 0, 0, 0 }, /* 17 P2P (Tsi320) */
+                        { 0, 1, 2, 3 }, /* 17 P2P (Tsi320) */
                         { 0, 1, 2, 3 }, /* 18 - Slot 1 */
                         { 1, 2, 3, 0 }, /* 19 - Slot 2 */
                         { 2, 3, 0, 1 }, /* 20 - Slot 3 */
@@ -280,13 +291,135 @@ mpc85xx_exclude_device(u_char bus, u_char devfn)
                         return PCIBIOS_DEVICE_NOT_FOUND;
 #endif
         /* We explicitly do not go past the Tundra 320 Bridge */
-        if (bus == 1)
+        if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
                 return PCIBIOS_DEVICE_NOT_FOUND;
         if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
                 return PCIBIOS_DEVICE_NOT_FOUND;
         else
                 return PCIBIOS_SUCCESSFUL;
 }
+
+void __init
+mpc85xx_cds_enable_via(struct pci_controller *hose)
+{
+        u32 pci_class;
+        u16 vid, did;
+
+        early_read_config_dword(hose, 0, 0x88, PCI_CLASS_REVISION, &pci_class);
+        if ((pci_class >> 16) != PCI_CLASS_BRIDGE_PCI)
+                return;
+
+        /* Configure P2P so that we can reach bus 1 */
+        early_write_config_byte(hose, 0, 0x88, PCI_PRIMARY_BUS, 0);
+        early_write_config_byte(hose, 0, 0x88, PCI_SECONDARY_BUS, 1);
+        early_write_config_byte(hose, 0, 0x88, PCI_SUBORDINATE_BUS, 0xff);
+
+        early_read_config_word(hose, 1, 0x10, PCI_VENDOR_ID, &vid);
+        early_read_config_word(hose, 1, 0x10, PCI_DEVICE_ID, &did);
+
+        if ((vid != PCI_VENDOR_ID_VIA) ||
+                        (did != PCI_DEVICE_ID_VIA_82C686))
+                return;
+
+        /* Enable USB and IDE functions */
+        early_write_config_byte(hose, 1, 0x10, 0x48, 0x08);
+}
+
+void __init
+mpc85xx_cds_fixup_via(struct pci_controller *hose)
+{
+        u32 pci_class;
+        u16 vid, did;
+
+        early_read_config_dword(hose, 0, 0x88, PCI_CLASS_REVISION, &pci_class);
+        if ((pci_class >> 16) != PCI_CLASS_BRIDGE_PCI)
+                return;
+
+        /*
+         * Force the backplane P2P bridge to have a window
+         * open from 0x00000000-0x00001fff in PCI I/O space.
+         * This allows legacy I/O (i8259, etc) on the VIA
+         * southbridge to be accessed.
+         */
+        early_write_config_byte(hose, 0, 0x88, PCI_IO_BASE, 0x00);
+        early_write_config_word(hose, 0, 0x88, PCI_IO_BASE_UPPER16, 0x0000);
+        early_write_config_byte(hose, 0, 0x88, PCI_IO_LIMIT, 0x10);
+        early_write_config_word(hose, 0, 0x88, PCI_IO_LIMIT_UPPER16, 0x0000);
+
+        early_read_config_word(hose, 1, 0x10, PCI_VENDOR_ID, &vid);
+        early_read_config_word(hose, 1, 0x10, PCI_DEVICE_ID, &did);
+        if ((vid != PCI_VENDOR_ID_VIA) ||
+                        (did != PCI_DEVICE_ID_VIA_82C686))
+                return;
+
+        /*
+         * Since the P2P window was forced to cover the fixed
+         * legacy I/O addresses, it is necessary to manually
+         * place the base addresses for the IDE and USB functions
+         * within this window.
+         */
+        /* Function 1, IDE */
+        early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_0, 0x1ff8);
+        early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_1, 0x1ff4);
+        early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_2, 0x1fe8);
+        early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_3, 0x1fe4);
+        early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_4, 0x1fd0);
+
+        /* Function 2, USB ports 0-1 */
+        early_write_config_dword(hose, 1, 0x12, PCI_BASE_ADDRESS_4, 0x1fa0);
+
+        /* Function 3, USB ports 2-3 */
+        early_write_config_dword(hose, 1, 0x13, PCI_BASE_ADDRESS_4, 0x1f80);
+
+        /* Function 5, Power Management */
+        early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_0, 0x1e00);
+        early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_1, 0x1dfc);
+        early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_2, 0x1df8);
+
+        /* Function 6, AC97 Interface */
+        early_write_config_dword(hose, 1, 0x16, PCI_BASE_ADDRESS_0, 0x1c00);
+}
+
+void __init
+mpc85xx_cds_pcibios_fixup(void)
+{
+        struct pci_dev *dev = NULL;
+        u_char          c;
+
+        if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
+                                        PCI_DEVICE_ID_VIA_82C586_1, NULL))) {
+                /*
+                 * U-Boot does not set the enable bits
+                 * for the IDE device. Force them on here.
+                 */
+                pci_read_config_byte(dev, 0x40, &c);
+                c |= 0x03; /* IDE: Chip Enable Bits */
+                pci_write_config_byte(dev, 0x40, c);
+
+                /*
+                 * Since only primary interface works, force the
+                 * IDE function to standard primary IDE interrupt
+                 * w/ 8259 offset
+                 */
+                dev->irq = 14;
+                pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
+        }
+
+        /*
+         * Force legacy USB interrupt routing
+         */
+        if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
+                                        PCI_DEVICE_ID_VIA_82C586_2, NULL))) {
+                dev->irq = 10;
+                pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 10);
+        }
+
+        if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
+                                        PCI_DEVICE_ID_VIA_82C586_2, dev))) {
+                dev->irq = 11;
+                pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
+        }
+}
 #endif /* CONFIG_PCI */
 
 TODC_ALLOC();
@@ -328,6 +461,9 @@ mpc85xx_cds_setup_arch(void)
         loops_per_jiffy = freq / HZ;
 
 #ifdef CONFIG_PCI
+        /* VIA IDE configuration */
+        ppc_md.pcibios_fixup = mpc85xx_cds_pcibios_fixup;
+
         /* setup PCI host bridges */
         mpc85xx_setup_hose();
 #endif
@@ -459,6 +595,9 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 #if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
         ppc_md.progress = gen550_progress;
 #endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */
+#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_KGDB)
+        ppc_md.early_serial_map = mpc85xx_early_serial_map;
+#endif  /* CONFIG_SERIAL_8250 && CONFIG_KGDB */
 
         if (ppc_md.progress)
                 ppc_md.progress("mpc85xx_cds_init(): exit", 0);
diff --git a/arch/ppc/platforms/85xx/mpc85xx_cds_common.h b/arch/ppc/platforms/85xx/mpc85xx_cds_common.h
index 7627d77504bd..12b292c6ae32 100644
--- a/arch/ppc/platforms/85xx/mpc85xx_cds_common.h
+++ b/arch/ppc/platforms/85xx/mpc85xx_cds_common.h
@@ -77,4 +77,7 @@
 
 #define MPC85XX_PCI2_IO_SIZE         0x01000000
 
+#define NR_8259_INTS                 16
+#define CPM_IRQ_OFFSET               NR_8259_INTS
+
 #endif /* __MACH_MPC85XX_CDS_H__ */
diff --git a/arch/ppc/platforms/85xx/sbc8560.c b/arch/ppc/platforms/85xx/sbc8560.c
index 9ab05e590c3e..7b9e1543e175 100644
--- a/arch/ppc/platforms/85xx/sbc8560.c
+++ b/arch/ppc/platforms/85xx/sbc8560.c
@@ -221,6 +221,9 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 #if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
         ppc_md.progress = gen550_progress;
 #endif  /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */
+#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_KGDB)
+        ppc_md.early_serial_map = sbc8560_early_serial_map;
+#endif  /* CONFIG_SERIAL_8250 && CONFIG_KGDB */
 
         if (ppc_md.progress)
                 ppc_md.progress("sbc8560_init(): exit", 0);
diff --git a/arch/ppc/platforms/pmac_cpufreq.c b/arch/ppc/platforms/pmac_cpufreq.c
index f7fb2786cd50..937f46df711e 100644
--- a/arch/ppc/platforms/pmac_cpufreq.c
+++ b/arch/ppc/platforms/pmac_cpufreq.c
@@ -85,14 +85,11 @@ static int no_schedule;
 static int has_cpu_l2lve;
 
 
-#define PMAC_CPU_LOW_SPEED      1
-#define PMAC_CPU_HIGH_SPEED     0
-
 /* There are only two frequency states for each processor. Values
  * are in kHz for the time being.
  */
-#define CPUFREQ_HIGH                  PMAC_CPU_HIGH_SPEED
-#define CPUFREQ_LOW                   PMAC_CPU_LOW_SPEED
+#define CPUFREQ_HIGH                  0
+#define CPUFREQ_LOW                   1
 
 static struct cpufreq_frequency_table pmac_cpu_freqs[] = {
         {CPUFREQ_HIGH,          0},
@@ -100,6 +97,11 @@ static struct cpufreq_frequency_table pmac_cpu_freqs[] = {
         {0,                     CPUFREQ_TABLE_END},
 };
 
+static struct freq_attr* pmac_cpu_freqs_attr[] = {
+        &cpufreq_freq_attr_scaling_available_freqs,
+        NULL,
+};
+
 static inline void local_delay(unsigned long ms)
 {
         if (no_schedule)
@@ -269,6 +271,8 @@ static int __pmac pmu_set_cpu_speed(int low_speed)
 #ifdef DEBUG_FREQ
         printk(KERN_DEBUG "HID1, before: %x\n", mfspr(SPRN_HID1));
 #endif
+        pmu_suspend();
+
         /* Disable all interrupt sources on openpic */
         pic_prio = openpic_get_priority();
         openpic_set_priority(0xf);
@@ -343,6 +347,8 @@ static int __pmac pmu_set_cpu_speed(int low_speed)
         debug_calc_bogomips();
 #endif
 
+        pmu_resume();
+
         preempt_enable();
 
         return 0;
@@ -355,7 +361,7 @@ static int __pmac do_set_cpu_speed(int speed_mode, int notify)
         static unsigned long prev_l3cr;
 
         freqs.old = cur_freq;
-        freqs.new = (speed_mode == PMAC_CPU_HIGH_SPEED) ? hi_freq : low_freq;
+        freqs.new = (speed_mode == CPUFREQ_HIGH) ? hi_freq : low_freq;
         freqs.cpu = smp_processor_id();
 
         if (freqs.old == freqs.new)
@@ -363,7 +369,7 @@ static int __pmac do_set_cpu_speed(int speed_mode, int notify)
 
         if (notify)
                 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
-        if (speed_mode == PMAC_CPU_LOW_SPEED &&
+        if (speed_mode == CPUFREQ_LOW &&
             cpu_has_feature(CPU_FTR_L3CR)) {
                 l3cr = _get_L3CR();
                 if (l3cr & L3CR_L3E) {
@@ -371,8 +377,8 @@ static int __pmac do_set_cpu_speed(int speed_mode, int notify)
                         _set_L3CR(0);
                 }
         }
-        set_speed_proc(speed_mode == PMAC_CPU_LOW_SPEED);
-        if (speed_mode == PMAC_CPU_HIGH_SPEED &&
+        set_speed_proc(speed_mode == CPUFREQ_LOW);
+        if (speed_mode == CPUFREQ_HIGH &&
             cpu_has_feature(CPU_FTR_L3CR)) {
                 l3cr = _get_L3CR();
                 if ((prev_l3cr & L3CR_L3E) && l3cr != prev_l3cr)
@@ -380,7 +386,7 @@ static int __pmac do_set_cpu_speed(int speed_mode, int notify)
         }
         if (notify)
                 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
-        cur_freq = (speed_mode == PMAC_CPU_HIGH_SPEED) ? hi_freq : low_freq;
+        cur_freq = (speed_mode == CPUFREQ_HIGH) ? hi_freq : low_freq;
 
         return 0;
 }
@@ -423,7 +429,8 @@ static int __pmac pmac_cpufreq_cpu_init(struct cpufreq_policy *policy)
         policy->cpuinfo.transition_latency      = CPUFREQ_ETERNAL;
         policy->cur = cur_freq;
 
-        return cpufreq_frequency_table_cpuinfo(policy, &pmac_cpu_freqs[0]);
+        cpufreq_frequency_table_get_attr(pmac_cpu_freqs, policy->cpu);
+        return cpufreq_frequency_table_cpuinfo(policy, pmac_cpu_freqs);
 }
 
 static u32 __pmac read_gpio(struct device_node *np)
@@ -457,7 +464,7 @@ static int __pmac pmac_cpufreq_suspend(struct cpufreq_policy *policy, u32 state)
         no_schedule = 1;
         sleep_freq = cur_freq;
         if (cur_freq == low_freq)
-                do_set_cpu_speed(PMAC_CPU_HIGH_SPEED, 0);
+                do_set_cpu_speed(CPUFREQ_HIGH, 0);
         return 0;
 }
 
@@ -473,8 +480,8 @@ static int __pmac pmac_cpufreq_resume(struct cpufreq_policy *policy)
          * is that we force a switch to whatever it was, which is
          * probably high speed due to our suspend() routine
          */
-        do_set_cpu_speed(sleep_freq == low_freq ? PMAC_CPU_LOW_SPEED
-                         : PMAC_CPU_HIGH_SPEED, 0);
+        do_set_cpu_speed(sleep_freq == low_freq ?
+                         CPUFREQ_LOW : CPUFREQ_HIGH, 0);
 
         no_schedule = 0;
         return 0;
@@ -488,6 +495,7 @@ static struct cpufreq_driver pmac_cpufreq_driver = {
         .suspend        = pmac_cpufreq_suspend,
         .resume         = pmac_cpufreq_resume,
         .flags          = CPUFREQ_PM_NO_WARN,
+        .attr           = pmac_cpu_freqs_attr,
         .name           = "powermac",
         .owner          = THIS_MODULE,
 };
diff --git a/arch/ppc/platforms/pq2ads.h b/arch/ppc/platforms/pq2ads.h
index cf5e5dd06d63..067d9a5aebc1 100644
--- a/arch/ppc/platforms/pq2ads.h
+++ b/arch/ppc/platforms/pq2ads.h
@@ -49,10 +49,10 @@
 /* PCI interrupt controller */
 #define PCI_INT_STAT_REG        0xF8200000
 #define PCI_INT_MASK_REG        0xF8200004
-#define PIRQA                   (NR_SIU_INTS + 0)
-#define PIRQB                   (NR_SIU_INTS + 1)
-#define PIRQC                   (NR_SIU_INTS + 2)
-#define PIRQD                   (NR_SIU_INTS + 3)
+#define PIRQA                   (NR_CPM_INTS + 0)
+#define PIRQB                   (NR_CPM_INTS + 1)
+#define PIRQC                   (NR_CPM_INTS + 2)
+#define PIRQD                   (NR_CPM_INTS + 3)
 
 /*
  * PCI memory map definitions for MPC8266ADS-PCI.
@@ -68,28 +68,23 @@
  *      0x00000000-0x1FFFFFFF   0x00000000-0x1FFFFFFF   MPC8266 local memory
  */
 
-/* window for a PCI master to access MPC8266 memory */
-#define PCI_SLV_MEM_LOCAL       0x00000000      /* Local base */
-#define PCI_SLV_MEM_BUS         0x00000000      /* PCI base */
+/* All the other PCI memory map definitions reside at syslib/m82xx_pci.h
+   Here we should redefine what is unique for this board */
+#define M82xx_PCI_SLAVE_MEM_LOCAL       0x00000000      /* Local base */
+#define M82xx_PCI_SLAVE_MEM_BUS         0x00000000      /* PCI base */
+#define M82xx_PCI_SLAVE_MEM_SIZE        0x10000000      /* 256 Mb */
 
-/* window for the processor to access PCI memory with prefetching */
-#define PCI_MSTR_MEM_LOCAL      0x80000000      /* Local base */
-#define PCI_MSTR_MEM_BUS        0x80000000      /* PCI base   */
-#define PCI_MSTR_MEM_SIZE       0x20000000      /* 512MB */
+#define M82xx_PCI_SLAVE_SEC_WND_SIZE    ~(0x40000000 - 1U)      /* 2 x 512Mb  */
+#define M82xx_PCI_SLAVE_SEC_WND_BASE    0x80000000              /* PCI Memory base */
 
-/* window for the processor to access PCI memory without prefetching */
-#define PCI_MSTR_MEMIO_LOCAL    0xA0000000      /* Local base */
-#define PCI_MSTR_MEMIO_BUS      0xA0000000      /* PCI base   */
-#define PCI_MSTR_MEMIO_SIZE     0x20000000      /* 512MB */
+#if defined(CONFIG_ADS8272)
+#define PCI_INT_TO_SIU  SIU_INT_IRQ2
+#elif defined(CONFIG_PQ2FADS)
+#define PCI_INT_TO_SIU  SIU_INT_IRQ6
+#else
+#warning PCI Bridge will be without interrupts support
+#endif
 
-/* window for the processor to access PCI I/O */
-#define PCI_MSTR_IO_LOCAL       0xF4000000      /* Local base */
-#define PCI_MSTR_IO_BUS         0x00000000      /* PCI base   */
-#define PCI_MSTR_IO_SIZE        0x04000000      /* 64MB */
-
-#define _IO_BASE                PCI_MSTR_IO_LOCAL
-#define _ISA_MEM_BASE           PCI_MSTR_MEMIO_LOCAL
-#define PCI_DRAM_OFFSET         PCI_SLV_MEM_BUS
 #endif /* CONFIG_PCI */
 
 #endif /* __MACH_ADS8260_DEFS */