[PATCH] ppc32: board-specific part of fs_enet update

This contains board-specific portion to respect driver changes (for 8272ads ,
885ads and 866ads).  Altered platform_data structures as well as initial setup
routines relevant to fs_enet.

Changes to the mpc8560ads ppc/ code are also introduced, but mainly as
reference, since the entire board support is going to appear in arch/powerpc.

Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Jeff Garzik <jeff@garzik.org>

2 files changed, 108 insertions, 0 deletions

diff --git a/arch/ppc/platforms/85xx/mpc8560_ads.c b/arch/ppc/platforms/85xx/mpc8560_ads.c
index d90cd24d018e..94badafe4ef1 100644
--- a/arch/ppc/platforms/85xx/mpc8560_ads.c
+++ b/arch/ppc/platforms/85xx/mpc8560_ads.c
@@ -29,6 +29,7 @@
 #include <linux/initrd.h>
 #include <linux/module.h>
 #include <linux/fsl_devices.h>
+#include <linux/fs_enet_pd.h>
 
 #include <asm/system.h>
 #include <asm/pgtable.h>
@@ -58,6 +59,71 @@
  * Setup the architecture
  *
  */
+static void init_fcc_ioports(void)
+{
+        struct immap *immap;
+        struct io_port *io;
+        u32 tempval;
+
+        immap = cpm2_immr;
+
+        io = &immap->im_ioport;
+        /* FCC2/3 are on the ports B/C. */
+        tempval = in_be32(&io->iop_pdirb);
+        tempval &= ~PB2_DIRB0;
+        tempval |= PB2_DIRB1;
+        out_be32(&io->iop_pdirb, tempval);
+
+        tempval = in_be32(&io->iop_psorb);
+        tempval &= ~PB2_PSORB0;
+        tempval |= PB2_PSORB1;
+        out_be32(&io->iop_psorb, tempval);
+
+        tempval = in_be32(&io->iop_pparb);
+        tempval |= (PB2_DIRB0 | PB2_DIRB1);
+        out_be32(&io->iop_pparb, tempval);
+
+        tempval = in_be32(&io->iop_pdirb);
+        tempval &= ~PB3_DIRB0;
+        tempval |= PB3_DIRB1;
+        out_be32(&io->iop_pdirb, tempval);
+
+        tempval = in_be32(&io->iop_psorb);
+        tempval &= ~PB3_PSORB0;
+        tempval |= PB3_PSORB1;
+        out_be32(&io->iop_psorb, tempval);
+
+        tempval = in_be32(&io->iop_pparb);
+        tempval |= (PB3_DIRB0 | PB3_DIRB1);
+        out_be32(&io->iop_pparb, tempval);
+
+        tempval = in_be32(&io->iop_pdirc);
+        tempval |= PC3_DIRC1;
+        out_be32(&io->iop_pdirc, tempval);
+
+        tempval = in_be32(&io->iop_pparc);
+        tempval |= PC3_DIRC1;
+        out_be32(&io->iop_pparc, tempval);
+
+        /* Port C has clocks......  */
+        tempval = in_be32(&io->iop_psorc);
+        tempval &= ~(CLK_TRX);
+        out_be32(&io->iop_psorc, tempval);
+
+        tempval = in_be32(&io->iop_pdirc);
+        tempval &= ~(CLK_TRX);
+        out_be32(&io->iop_pdirc, tempval);
+        tempval = in_be32(&io->iop_pparc);
+        tempval |= (CLK_TRX);
+        out_be32(&io->iop_pparc, tempval);
+
+        /* Configure Serial Interface clock routing.
+         * First,  clear all FCC bits to zero,
+         * then set the ones we want.
+         */
+        immap->im_cpmux.cmx_fcr &= ~(CPMUX_CLK_MASK);
+        immap->im_cpmux.cmx_fcr |= CPMUX_CLK_ROUTE;
+}
 
 static void __init
 mpc8560ads_setup_arch(void)
@@ -66,6 +132,7 @@ mpc8560ads_setup_arch(void)
         unsigned int freq;
         struct gianfar_platform_data *pdata;
         struct gianfar_mdio_data *mdata;
+        struct fs_platform_info *fpi;
 
         cpm2_reset();
 
@@ -110,6 +177,28 @@ mpc8560ads_setup_arch(void)
                 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
         }
 
+        init_fcc_ioports();
+        ppc_sys_device_remove(MPC85xx_CPM_FCC1);
+
+        fpi = (struct fs_platform_info *) ppc_sys_get_pdata(MPC85xx_CPM_FCC2);
+        if (fpi) {
+                memcpy(fpi->macaddr, binfo->bi_enet2addr, 6);
+                fpi->bus_id = "0:02";
+                fpi->phy_addr = 2;
+                fpi->dpram_offset = (u32)cpm2_immr->im_dprambase;
+                fpi->fcc_regs_c = (u32)&cpm2_immr->im_fcc_c[1];
+        }
+
+        fpi = (struct fs_platform_info *) ppc_sys_get_pdata(MPC85xx_CPM_FCC3);
+        if (fpi) {
+                memcpy(fpi->macaddr, binfo->bi_enet2addr, 6);
+                fpi->macaddr[5] += 1;
+                fpi->bus_id = "0:03";
+                fpi->phy_addr = 3;
+                fpi->dpram_offset = (u32)cpm2_immr->im_dprambase;
+                fpi->fcc_regs_c = (u32)&cpm2_immr->im_fcc_c[2];
+        }
+
 #ifdef CONFIG_BLK_DEV_INITRD
         if (initrd_start)
                 ROOT_DEV = Root_RAM0;
diff --git a/arch/ppc/platforms/85xx/mpc85xx_ads_common.h b/arch/ppc/platforms/85xx/mpc85xx_ads_common.h
index abf32281655d..c8c322fe3680 100644
--- a/arch/ppc/platforms/85xx/mpc85xx_ads_common.h
+++ b/arch/ppc/platforms/85xx/mpc85xx_ads_common.h
@@ -45,4 +45,23 @@ extern void mpc85xx_ads_map_io(void) __init;
 
 #define MPC85XX_PCI1_IO_SIZE    0x01000000
 
+/* FCC1 Clock Source Configuration.  These can be
+ * redefined in the board specific file.
+ *    Can only choose from CLK9-12 */
+#define F1_RXCLK       12
+#define F1_TXCLK       11
+
+/* FCC2 Clock Source Configuration.  These can be
+ * redefined in the board specific file.
+ *    Can only choose from CLK13-16 */
+#define F2_RXCLK       13
+#define F2_TXCLK       14
+
+/* FCC3 Clock Source Configuration.  These can be
+ * redefined in the board specific file.
+ *    Can only choose from CLK13-16 */
+#define F3_RXCLK       15
+#define F3_TXCLK       16
+
+
 #endif                          /* __MACH_MPC85XX_ADS_H__ */