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authorKumar Gala <galak@freescale.com>2005-06-25 17:54:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-06-25 19:24:26 -0400
commit62aa751d16399637325852bc0a1fcf13c2476dd7 (patch)
tree5d2bcc52ea85e05e5d487be73500847614bc8bcd /arch/ppc/platforms/85xx/mpc8540_ads.c
parent09ffd94fb15d85fbf9eebb8180f50264b264d6fe (diff)
[PATCH] ppc32: Check return of ppc_sys_get_pdata before accessing pointer
Ensure that the returned pointer from ppc_sys_get_pdata is not NULL before we start using it. This handles any cases where we have variants of processors on the same board with different functionality. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/ppc/platforms/85xx/mpc8540_ads.c')
-rw-r--r--arch/ppc/platforms/85xx/mpc8540_ads.c46
1 files changed, 26 insertions, 20 deletions
diff --git a/arch/ppc/platforms/85xx/mpc8540_ads.c b/arch/ppc/platforms/85xx/mpc8540_ads.c
index a2ed611cd936..ddd2e9a5bb12 100644
--- a/arch/ppc/platforms/85xx/mpc8540_ads.c
+++ b/arch/ppc/platforms/85xx/mpc8540_ads.c
@@ -92,28 +92,34 @@ mpc8540ads_setup_arch(void)
92 92
93 /* setup the board related information for the enet controllers */ 93 /* setup the board related information for the enet controllers */
94 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1); 94 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
95 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 95 if (pdata) {
96 pdata->interruptPHY = MPC85xx_IRQ_EXT5; 96 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
97 pdata->phyid = 0; 97 pdata->interruptPHY = MPC85xx_IRQ_EXT5;
98 /* fixup phy address */ 98 pdata->phyid = 0;
99 pdata->phy_reg_addr += binfo->bi_immr_base; 99 /* fixup phy address */
100 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); 100 pdata->phy_reg_addr += binfo->bi_immr_base;
101 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
102 }
101 103
102 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2); 104 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
103 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; 105 if (pdata) {
104 pdata->interruptPHY = MPC85xx_IRQ_EXT5; 106 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
105 pdata->phyid = 1; 107 pdata->interruptPHY = MPC85xx_IRQ_EXT5;
106 /* fixup phy address */ 108 pdata->phyid = 1;
107 pdata->phy_reg_addr += binfo->bi_immr_base; 109 /* fixup phy address */
108 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); 110 pdata->phy_reg_addr += binfo->bi_immr_base;
109 111 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
110 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_FEC); 112 }
111 pdata->board_flags = 0; 113
112 pdata->interruptPHY = MPC85xx_IRQ_EXT5; 114 if (pdata) {
113 pdata->phyid = 3; 115 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_FEC);
114 /* fixup phy address */ 116 pdata->board_flags = 0;
115 pdata->phy_reg_addr += binfo->bi_immr_base; 117 pdata->interruptPHY = MPC85xx_IRQ_EXT5;
116 memcpy(pdata->mac_addr, binfo->bi_enet2addr, 6); 118 pdata->phyid = 3;
119 /* fixup phy address */
120 pdata->phy_reg_addr += binfo->bi_immr_base;
121 memcpy(pdata->mac_addr, binfo->bi_enet2addr, 6);
122 }
117 123
118#ifdef CONFIG_BLK_DEV_INITRD 124#ifdef CONFIG_BLK_DEV_INITRD
119 if (initrd_start) 125 if (initrd_start)