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authorKumar Gala <galak@kernel.crashing.org>2011-11-04 10:47:49 -0400
committerKumar Gala <galak@kernel.crashing.org>2011-11-24 03:01:39 -0500
commitb9db022c62f72bc5a029f20851b012895a6ea7ca (patch)
treefdd6987a68f4857280d9fc215ba3b0b44c2c2811 /arch/powerpc
parent8389c823b50bfb81eccdb115f486459adacf4b17 (diff)
powerpc/85xx: Rework P4080DS device trees
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Adding of MPIC timer blocks * Dropping "fsl,p4080-IP..." from compatibles for standard blocks * Removed mpic interrupt-parent from dcsr-epu node, just use top level * Removed mpic interrupt-parent from sec nodes, just use top level Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc')
-rw-r--r--arch/powerpc/boot/dts/fsl/p4080si-post.dtsi342
-rw-r--r--arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi145
-rw-r--r--arch/powerpc/boot/dts/p4080ds.dts14
-rw-r--r--arch/powerpc/boot/dts/p4080si.dtsi755
4 files changed, 498 insertions, 758 deletions
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
new file mode 100644
index 000000000000..1510991a40d3
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
@@ -0,0 +1,342 @@
1/*
2 * P4080/P4040 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
37 interrupts = <25 2 0 0>;
38 #address-cells = <2>;
39 #size-cells = <1>;
40};
41
42/* controller at 0x200000 */
43&pci0 {
44 compatible = "fsl,p4080-pcie";
45 device_type = "pci";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0x0 0xff>;
49 clock-frequency = <33333333>;
50 interrupts = <16 2 1 15>;
51 pcie@0 {
52 reg = <0 0 0 0 0>;
53 #interrupt-cells = <1>;
54 #size-cells = <2>;
55 #address-cells = <3>;
56 device_type = "pci";
57 interrupts = <16 2 1 15>;
58 interrupt-map-mask = <0xf800 0 0 7>;
59 interrupt-map = <
60 /* IDSEL 0x0 */
61 0000 0 0 1 &mpic 40 1 0 0
62 0000 0 0 2 &mpic 1 1 0 0
63 0000 0 0 3 &mpic 2 1 0 0
64 0000 0 0 4 &mpic 3 1 0 0
65 >;
66 };
67};
68
69/* controller at 0x201000 */
70&pci1 {
71 compatible = "fsl,p4080-pcie";
72 device_type = "pci";
73 #size-cells = <2>;
74 #address-cells = <3>;
75 bus-range = <0 0xff>;
76 clock-frequency = <33333333>;
77 interrupts = <16 2 1 14>;
78 pcie@0 {
79 reg = <0 0 0 0 0>;
80 #interrupt-cells = <1>;
81 #size-cells = <2>;
82 #address-cells = <3>;
83 device_type = "pci";
84 interrupts = <16 2 1 14>;
85 interrupt-map-mask = <0xf800 0 0 7>;
86 interrupt-map = <
87 /* IDSEL 0x0 */
88 0000 0 0 1 &mpic 41 1 0 0
89 0000 0 0 2 &mpic 5 1 0 0
90 0000 0 0 3 &mpic 6 1 0 0
91 0000 0 0 4 &mpic 7 1 0 0
92 >;
93 };
94};
95
96/* controller at 0x202000 */
97&pci2 {
98 compatible = "fsl,p4080-pcie";
99 device_type = "pci";
100 #size-cells = <2>;
101 #address-cells = <3>;
102 bus-range = <0x0 0xff>;
103 clock-frequency = <33333333>;
104 interrupts = <16 2 1 13>;
105 pcie@0 {
106 reg = <0 0 0 0 0>;
107 #interrupt-cells = <1>;
108 #size-cells = <2>;
109 #address-cells = <3>;
110 device_type = "pci";
111 interrupts = <16 2 1 13>;
112 interrupt-map-mask = <0xf800 0 0 7>;
113 interrupt-map = <
114 /* IDSEL 0x0 */
115 0000 0 0 1 &mpic 42 1 0 0
116 0000 0 0 2 &mpic 9 1 0 0
117 0000 0 0 3 &mpic 10 1 0 0
118 0000 0 0 4 &mpic 11 1 0 0
119 >;
120 };
121};
122
123&rio {
124 #address-cells = <2>;
125 #size-cells = <2>;
126 compatible = "fsl,rapidio-delta";
127 interrupts = <
128 16 2 1 11 /* err_irq */
129 56 2 0 0 /* bell_outb_irq */
130 57 2 0 0 /* bell_inb_irq */
131 60 2 0 0 /* msg1_tx_irq */
132 61 2 0 0 /* msg1_rx_irq */
133 62 2 0 0 /* msg2_tx_irq */
134 63 2 0 0>; /* msg2_rx_irq */
135};
136
137&dcsr {
138 #address-cells = <1>;
139 #size-cells = <1>;
140 compatible = "fsl,dcsr", "simple-bus";
141
142 dcsr-epu@0 {
143 compatible = "fsl,dcsr-epu";
144 interrupts = <52 2 0 0
145 84 2 0 0
146 85 2 0 0>;
147 reg = <0x0 0x1000>;
148 };
149 dcsr-npc {
150 compatible = "fsl,dcsr-npc";
151 reg = <0x1000 0x1000 0x1000000 0x8000>;
152 };
153 dcsr-nxc@2000 {
154 compatible = "fsl,dcsr-nxc";
155 reg = <0x2000 0x1000>;
156 };
157 dcsr-corenet {
158 compatible = "fsl,dcsr-corenet";
159 reg = <0x8000 0x1000 0xB0000 0x1000>;
160 };
161 dcsr-dpaa@9000 {
162 compatible = "fsl,p4080-dcsr-dpaa", "fsl,dcsr-dpaa";
163 reg = <0x9000 0x1000>;
164 };
165 dcsr-ocn@11000 {
166 compatible = "fsl,p4080-dcsr-ocn", "fsl,dcsr-ocn";
167 reg = <0x11000 0x1000>;
168 };
169 dcsr-ddr@12000 {
170 compatible = "fsl,dcsr-ddr";
171 dev-handle = <&ddr1>;
172 reg = <0x12000 0x1000>;
173 };
174 dcsr-ddr@13000 {
175 compatible = "fsl,dcsr-ddr";
176 dev-handle = <&ddr2>;
177 reg = <0x13000 0x1000>;
178 };
179 dcsr-nal@18000 {
180 compatible = "fsl,p4080-dcsr-nal", "fsl,dcsr-nal";
181 reg = <0x18000 0x1000>;
182 };
183 dcsr-rcpm@22000 {
184 compatible = "fsl,p4080-dcsr-rcpm", "fsl,dcsr-rcpm";
185 reg = <0x22000 0x1000>;
186 };
187 dcsr-cpu-sb-proxy@40000 {
188 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
189 cpu-handle = <&cpu0>;
190 reg = <0x40000 0x1000>;
191 };
192 dcsr-cpu-sb-proxy@41000 {
193 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
194 cpu-handle = <&cpu1>;
195 reg = <0x41000 0x1000>;
196 };
197 dcsr-cpu-sb-proxy@42000 {
198 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
199 cpu-handle = <&cpu2>;
200 reg = <0x42000 0x1000>;
201 };
202 dcsr-cpu-sb-proxy@43000 {
203 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
204 cpu-handle = <&cpu3>;
205 reg = <0x43000 0x1000>;
206 };
207 dcsr-cpu-sb-proxy@44000 {
208 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
209 cpu-handle = <&cpu4>;
210 reg = <0x44000 0x1000>;
211 };
212 dcsr-cpu-sb-proxy@45000 {
213 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
214 cpu-handle = <&cpu5>;
215 reg = <0x45000 0x1000>;
216 };
217 dcsr-cpu-sb-proxy@46000 {
218 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
219 cpu-handle = <&cpu6>;
220 reg = <0x46000 0x1000>;
221 };
222 dcsr-cpu-sb-proxy@47000 {
223 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
224 cpu-handle = <&cpu7>;
225 reg = <0x47000 0x1000>;
226 };
227
228};
229
230&soc {
231 #address-cells = <1>;
232 #size-cells = <1>;
233 device_type = "soc";
234 compatible = "simple-bus";
235
236 soc-sram-error {
237 compatible = "fsl,soc-sram-error";
238 interrupts = <16 2 1 29>;
239 };
240
241 corenet-law@0 {
242 compatible = "fsl,corenet-law";
243 reg = <0x0 0x1000>;
244 fsl,num-laws = <32>;
245 };
246
247 ddr1: memory-controller@8000 {
248 compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller";
249 reg = <0x8000 0x1000>;
250 interrupts = <16 2 1 23>;
251 };
252
253 ddr2: memory-controller@9000 {
254 compatible = "fsl,qoriq-memory-controller-v4.4","fsl,qoriq-memory-controller";
255 reg = <0x9000 0x1000>;
256 interrupts = <16 2 1 22>;
257 };
258
259 cpc: l3-cache-controller@10000 {
260 compatible = "fsl,p4080-l3-cache-controller", "cache";
261 reg = <0x10000 0x1000
262 0x11000 0x1000>;
263 interrupts = <16 2 1 27
264 16 2 1 26>;
265 };
266
267 corenet-cf@18000 {
268 compatible = "fsl,corenet-cf";
269 reg = <0x18000 0x1000>;
270 interrupts = <16 2 1 31>;
271 fsl,ccf-num-csdids = <32>;
272 fsl,ccf-num-snoopids = <32>;
273 };
274
275 iommu@20000 {
276 compatible = "fsl,pamu-v1.0", "fsl,pamu";
277 reg = <0x20000 0x5000>;
278 interrupts = <
279 24 2 0 0
280 16 2 1 30>;
281 };
282
283/include/ "qoriq-mpic.dtsi"
284
285 guts: global-utilities@e0000 {
286 compatible = "fsl,qoriq-device-config-1.0";
287 reg = <0xe0000 0xe00>;
288 fsl,has-rstcr;
289 #sleep-cells = <1>;
290 fsl,liodn-bits = <12>;
291 };
292
293 pins: global-utilities@e0e00 {
294 compatible = "fsl,qoriq-pin-control-1.0";
295 reg = <0xe0e00 0x200>;
296 #sleep-cells = <2>;
297 };
298
299 clockgen: global-utilities@e1000 {
300 compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0";
301 reg = <0xe1000 0x1000>;
302 clock-frequency = <0>;
303 };
304
305 rcpm: global-utilities@e2000 {
306 compatible = "fsl,qoriq-rcpm-1.0";
307 reg = <0xe2000 0x1000>;
308 #sleep-cells = <1>;
309 };
310
311 sfp: sfp@e8000 {
312 compatible = "fsl,p4080-sfp", "fsl,qoriq-sfp-1.0";
313 reg = <0xe8000 0x1000>;
314 };
315
316 serdes: serdes@ea000 {
317 compatible = "fsl,p4080-serdes";
318 reg = <0xea000 0x1000>;
319 };
320
321/include/ "qoriq-dma-0.dtsi"
322/include/ "qoriq-dma-1.dtsi"
323/include/ "qoriq-espi-0.dtsi"
324 spi@110000 {
325 fsl,espi-num-chipselects = <4>;
326 };
327
328/include/ "qoriq-esdhc-0.dtsi"
329 sdhc@114000 {
330 voltage-ranges = <3300 3300>;
331 sdhci,auto-cmd12;
332 };
333
334/include/ "qoriq-i2c-0.dtsi"
335/include/ "qoriq-i2c-1.dtsi"
336/include/ "qoriq-duart-0.dtsi"
337/include/ "qoriq-duart-1.dtsi"
338/include/ "qoriq-gpio-0.dtsi"
339/include/ "qoriq-usb2-mph-0.dtsi"
340/include/ "qoriq-usb2-dr-0.dtsi"
341/include/ "qoriq-sec4.0-0.dtsi"
342};
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
new file mode 100644
index 000000000000..b353ac9da01c
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
@@ -0,0 +1,145 @@
1/*
2 * P4080/P4040 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,P4080";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 ccsr = &soc;
44 dcsr = &dcsr;
45
46 serial0 = &serial0;
47 serial1 = &serial1;
48 serial2 = &serial2;
49 serial3 = &serial3;
50 pci0 = &pci0;
51 pci1 = &pci1;
52 pci2 = &pci2;
53 usb0 = &usb0;
54 usb1 = &usb1;
55 dma0 = &dma0;
56 dma1 = &dma1;
57 sdhc = &sdhc;
58 msi0 = &msi0;
59 msi1 = &msi1;
60 msi2 = &msi2;
61
62 crypto = &crypto;
63 sec_jr0 = &sec_jr0;
64 sec_jr1 = &sec_jr1;
65 sec_jr2 = &sec_jr2;
66 sec_jr3 = &sec_jr3;
67 rtic_a = &rtic_a;
68 rtic_b = &rtic_b;
69 rtic_c = &rtic_c;
70 rtic_d = &rtic_d;
71 sec_mon = &sec_mon;
72
73 rio0 = &rapidio0;
74 };
75
76 cpus {
77 #address-cells = <1>;
78 #size-cells = <0>;
79
80 cpu0: PowerPC,e500mc@0 {
81 device_type = "cpu";
82 reg = <0>;
83 next-level-cache = <&L2_0>;
84 L2_0: l2-cache {
85 next-level-cache = <&cpc>;
86 };
87 };
88 cpu1: PowerPC,e500mc@1 {
89 device_type = "cpu";
90 reg = <1>;
91 next-level-cache = <&L2_1>;
92 L2_1: l2-cache {
93 next-level-cache = <&cpc>;
94 };
95 };
96 cpu2: PowerPC,e500mc@2 {
97 device_type = "cpu";
98 reg = <2>;
99 next-level-cache = <&L2_2>;
100 L2_2: l2-cache {
101 next-level-cache = <&cpc>;
102 };
103 };
104 cpu3: PowerPC,e500mc@3 {
105 device_type = "cpu";
106 reg = <3>;
107 next-level-cache = <&L2_3>;
108 L2_3: l2-cache {
109 next-level-cache = <&cpc>;
110 };
111 };
112 cpu4: PowerPC,e500mc@4 {
113 device_type = "cpu";
114 reg = <4>;
115 next-level-cache = <&L2_4>;
116 L2_4: l2-cache {
117 next-level-cache = <&cpc>;
118 };
119 };
120 cpu5: PowerPC,e500mc@5 {
121 device_type = "cpu";
122 reg = <5>;
123 next-level-cache = <&L2_5>;
124 L2_5: l2-cache {
125 next-level-cache = <&cpc>;
126 };
127 };
128 cpu6: PowerPC,e500mc@6 {
129 device_type = "cpu";
130 reg = <6>;
131 next-level-cache = <&L2_6>;
132 L2_6: l2-cache {
133 next-level-cache = <&cpc>;
134 };
135 };
136 cpu7: PowerPC,e500mc@7 {
137 device_type = "cpu";
138 reg = <7>;
139 next-level-cache = <&L2_7>;
140 L2_7: l2-cache {
141 next-level-cache = <&cpc>;
142 };
143 };
144 };
145};
diff --git a/arch/powerpc/boot/dts/p4080ds.dts b/arch/powerpc/boot/dts/p4080ds.dts
index c7916dc28014..8ea1ae908156 100644
--- a/arch/powerpc/boot/dts/p4080ds.dts
+++ b/arch/powerpc/boot/dts/p4080ds.dts
@@ -32,7 +32,7 @@
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */ 33 */
34 34
35/include/ "p4080si.dtsi" 35/include/ "fsl/p4080si-pre.dtsi"
36 36
37/ { 37/ {
38 model = "fsl,P4080DS"; 38 model = "fsl,P4080DS";
@@ -50,6 +50,9 @@
50 }; 50 };
51 51
52 soc: soc@ffe000000 { 52 soc: soc@ffe000000 {
53 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
54 reg = <0xf 0xfe000000 0 0x00001000>;
55
53 spi@110000 { 56 spi@110000 {
54 flash@0 { 57 flash@0 {
55 #address-cells = <1>; 58 #address-cells = <1>;
@@ -105,12 +108,12 @@
105 }; 108 };
106 }; 109 };
107 110
108 rapidio0: rapidio@ffe0c0000 { 111 rio: rapidio0: rapidio@ffe0c0000 {
109 reg = <0xf 0xfe0c0000 0 0x20000>; 112 reg = <0xf 0xfe0c0000 0 0x20000>;
110 ranges = <0 0 0xc 0x20000000 0 0x01000000>; 113 ranges = <0 0 0xc 0x20000000 0 0x01000000>;
111 }; 114 };
112 115
113 localbus@ffe124000 { 116 lbc: localbus@ffe124000 {
114 reg = <0xf 0xfe124000 0 0x1000>; 117 reg = <0xf 0xfe124000 0 0x1000>;
115 ranges = <0 0 0xf 0xe8000000 0x08000000 118 ranges = <0 0 0xf 0xe8000000 0x08000000
116 3 0 0xf 0xffdf0000 0x00008000>; 119 3 0 0xf 0xffdf0000 0x00008000>;
@@ -132,6 +135,7 @@
132 reg = <0xf 0xfe200000 0 0x1000>; 135 reg = <0xf 0xfe200000 0 0x1000>;
133 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 136 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
134 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; 137 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
138 fsl,msi = <&msi0>;
135 pcie@0 { 139 pcie@0 {
136 ranges = <0x02000000 0 0xe0000000 140 ranges = <0x02000000 0 0xe0000000
137 0x02000000 0 0xe0000000 141 0x02000000 0 0xe0000000
@@ -147,6 +151,7 @@
147 reg = <0xf 0xfe201000 0 0x1000>; 151 reg = <0xf 0xfe201000 0 0x1000>;
148 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 152 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
149 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; 153 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
154 fsl,msi = <&msi1>;
150 pcie@0 { 155 pcie@0 {
151 ranges = <0x02000000 0 0xe0000000 156 ranges = <0x02000000 0 0xe0000000
152 0x02000000 0 0xe0000000 157 0x02000000 0 0xe0000000
@@ -162,6 +167,7 @@
162 reg = <0xf 0xfe202000 0 0x1000>; 167 reg = <0xf 0xfe202000 0 0x1000>;
163 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 168 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
164 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; 169 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
170 fsl,msi = <&msi2>;
165 pcie@0 { 171 pcie@0 {
166 ranges = <0x02000000 0 0xe0000000 172 ranges = <0x02000000 0 0xe0000000
167 0x02000000 0 0xe0000000 173 0x02000000 0 0xe0000000
@@ -174,3 +180,5 @@
174 }; 180 };
175 181
176}; 182};
183
184/include/ "fsl/p4080si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p4080si.dtsi b/arch/powerpc/boot/dts/p4080si.dtsi
deleted file mode 100644
index f20c01ab2473..000000000000
--- a/arch/powerpc/boot/dts/p4080si.dtsi
+++ /dev/null
@@ -1,755 +0,0 @@
1/*
2 * P4080 Silicon Device Tree Source
3 *
4 * Copyright 2009-2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36
37/ {
38 compatible = "fsl,P4080";
39 #address-cells = <2>;
40 #size-cells = <2>;
41 interrupt-parent = <&mpic>;
42
43 aliases {
44 ccsr = &soc;
45 dcsr = &dcsr;
46
47 serial0 = &serial0;
48 serial1 = &serial1;
49 serial2 = &serial2;
50 serial3 = &serial3;
51 pci0 = &pci0;
52 pci1 = &pci1;
53 pci2 = &pci2;
54 usb0 = &usb0;
55 usb1 = &usb1;
56 dma0 = &dma0;
57 dma1 = &dma1;
58 sdhc = &sdhc;
59 msi0 = &msi0;
60 msi1 = &msi1;
61 msi2 = &msi2;
62
63 crypto = &crypto;
64 sec_jr0 = &sec_jr0;
65 sec_jr1 = &sec_jr1;
66 sec_jr2 = &sec_jr2;
67 sec_jr3 = &sec_jr3;
68 rtic_a = &rtic_a;
69 rtic_b = &rtic_b;
70 rtic_c = &rtic_c;
71 rtic_d = &rtic_d;
72 sec_mon = &sec_mon;
73
74 rio0 = &rapidio0;
75 };
76
77 cpus {
78 #address-cells = <1>;
79 #size-cells = <0>;
80
81 cpu0: PowerPC,e500mc@0 {
82 device_type = "cpu";
83 reg = <0>;
84 next-level-cache = <&L2_0>;
85 L2_0: l2-cache {
86 next-level-cache = <&cpc>;
87 };
88 };
89 cpu1: PowerPC,e500mc@1 {
90 device_type = "cpu";
91 reg = <1>;
92 next-level-cache = <&L2_1>;
93 L2_1: l2-cache {
94 next-level-cache = <&cpc>;
95 };
96 };
97 cpu2: PowerPC,e500mc@2 {
98 device_type = "cpu";
99 reg = <2>;
100 next-level-cache = <&L2_2>;
101 L2_2: l2-cache {
102 next-level-cache = <&cpc>;
103 };
104 };
105 cpu3: PowerPC,e500mc@3 {
106 device_type = "cpu";
107 reg = <3>;
108 next-level-cache = <&L2_3>;
109 L2_3: l2-cache {
110 next-level-cache = <&cpc>;
111 };
112 };
113 cpu4: PowerPC,e500mc@4 {
114 device_type = "cpu";
115 reg = <4>;
116 next-level-cache = <&L2_4>;
117 L2_4: l2-cache {
118 next-level-cache = <&cpc>;
119 };
120 };
121 cpu5: PowerPC,e500mc@5 {
122 device_type = "cpu";
123 reg = <5>;
124 next-level-cache = <&L2_5>;
125 L2_5: l2-cache {
126 next-level-cache = <&cpc>;
127 };
128 };
129 cpu6: PowerPC,e500mc@6 {
130 device_type = "cpu";
131 reg = <6>;
132 next-level-cache = <&L2_6>;
133 L2_6: l2-cache {
134 next-level-cache = <&cpc>;
135 };
136 };
137 cpu7: PowerPC,e500mc@7 {
138 device_type = "cpu";
139 reg = <7>;
140 next-level-cache = <&L2_7>;
141 L2_7: l2-cache {
142 next-level-cache = <&cpc>;
143 };
144 };
145 };
146
147 dcsr: dcsr@f00000000 {
148 #address-cells = <1>;
149 #size-cells = <1>;
150 compatible = "fsl,dcsr", "simple-bus";
151
152 dcsr-epu@0 {
153 compatible = "fsl,dcsr-epu";
154 interrupts = <52 2 0 0
155 84 2 0 0
156 85 2 0 0>;
157 interrupt-parent = <&mpic>;
158 reg = <0x0 0x1000>;
159 };
160 dcsr-npc {
161 compatible = "fsl,dcsr-npc";
162 reg = <0x1000 0x1000 0x1000000 0x8000>;
163 };
164 dcsr-nxc@2000 {
165 compatible = "fsl,dcsr-nxc";
166 reg = <0x2000 0x1000>;
167 };
168 dcsr-corenet {
169 compatible = "fsl,dcsr-corenet";
170 reg = <0x8000 0x1000 0xB0000 0x1000>;
171 };
172 dcsr-dpaa@9000 {
173 compatible = "fsl,p4080-dcsr-dpaa", "fsl,dcsr-dpaa";
174 reg = <0x9000 0x1000>;
175 };
176 dcsr-ocn@11000 {
177 compatible = "fsl,p4080-dcsr-ocn", "fsl,dcsr-ocn";
178 reg = <0x11000 0x1000>;
179 };
180 dcsr-ddr@12000 {
181 compatible = "fsl,dcsr-ddr";
182 dev-handle = <&ddr1>;
183 reg = <0x12000 0x1000>;
184 };
185 dcsr-ddr@13000 {
186 compatible = "fsl,dcsr-ddr";
187 dev-handle = <&ddr2>;
188 reg = <0x13000 0x1000>;
189 };
190 dcsr-nal@18000 {
191 compatible = "fsl,p4080-dcsr-nal", "fsl,dcsr-nal";
192 reg = <0x18000 0x1000>;
193 };
194 dcsr-rcpm@22000 {
195 compatible = "fsl,p4080-dcsr-rcpm", "fsl,dcsr-rcpm";
196 reg = <0x22000 0x1000>;
197 };
198 dcsr-cpu-sb-proxy@40000 {
199 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
200 cpu-handle = <&cpu0>;
201 reg = <0x40000 0x1000>;
202 };
203 dcsr-cpu-sb-proxy@41000 {
204 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
205 cpu-handle = <&cpu1>;
206 reg = <0x41000 0x1000>;
207 };
208 dcsr-cpu-sb-proxy@42000 {
209 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
210 cpu-handle = <&cpu2>;
211 reg = <0x42000 0x1000>;
212 };
213 dcsr-cpu-sb-proxy@43000 {
214 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
215 cpu-handle = <&cpu3>;
216 reg = <0x43000 0x1000>;
217 };
218 dcsr-cpu-sb-proxy@44000 {
219 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
220 cpu-handle = <&cpu4>;
221 reg = <0x44000 0x1000>;
222 };
223 dcsr-cpu-sb-proxy@45000 {
224 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
225 cpu-handle = <&cpu5>;
226 reg = <0x45000 0x1000>;
227 };
228 dcsr-cpu-sb-proxy@46000 {
229 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
230 cpu-handle = <&cpu6>;
231 reg = <0x46000 0x1000>;
232 };
233 dcsr-cpu-sb-proxy@47000 {
234 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
235 cpu-handle = <&cpu7>;
236 reg = <0x47000 0x1000>;
237 };
238 };
239
240 soc: soc@ffe000000 {
241 #address-cells = <1>;
242 #size-cells = <1>;
243 device_type = "soc";
244 compatible = "simple-bus";
245 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
246 reg = <0xf 0xfe000000 0 0x00001000>;
247
248 soc-sram-error {
249 compatible = "fsl,soc-sram-error";
250 interrupts = <16 2 1 29>;
251 };
252
253 corenet-law@0 {
254 compatible = "fsl,corenet-law";
255 reg = <0x0 0x1000>;
256 fsl,num-laws = <32>;
257 };
258
259 ddr1: memory-controller@8000 {
260 compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller";
261 reg = <0x8000 0x1000>;
262 interrupts = <16 2 1 23>;
263 };
264
265 ddr2: memory-controller@9000 {
266 compatible = "fsl,qoriq-memory-controller-v4.4","fsl,qoriq-memory-controller";
267 reg = <0x9000 0x1000>;
268 interrupts = <16 2 1 22>;
269 };
270
271 cpc: l3-cache-controller@10000 {
272 compatible = "fsl,p4080-l3-cache-controller", "cache";
273 reg = <0x10000 0x1000
274 0x11000 0x1000>;
275 interrupts = <16 2 1 27
276 16 2 1 26>;
277 };
278
279 corenet-cf@18000 {
280 compatible = "fsl,corenet-cf";
281 reg = <0x18000 0x1000>;
282 interrupts = <16 2 1 31>;
283 fsl,ccf-num-csdids = <32>;
284 fsl,ccf-num-snoopids = <32>;
285 };
286
287 iommu@20000 {
288 compatible = "fsl,pamu-v1.0", "fsl,pamu";
289 reg = <0x20000 0x5000>;
290 interrupts = <
291 24 2 0 0
292 16 2 1 30>;
293 };
294
295 mpic: pic@40000 {
296 clock-frequency = <0>;
297 interrupt-controller;
298 #address-cells = <0>;
299 #interrupt-cells = <4>;
300 reg = <0x40000 0x40000>;
301 compatible = "fsl,mpic", "chrp,open-pic";
302 device_type = "open-pic";
303 };
304
305 msi0: msi@41600 {
306 compatible = "fsl,mpic-msi";
307 reg = <0x41600 0x200>;
308 msi-available-ranges = <0 0x100>;
309 interrupts = <
310 0xe0 0 0 0
311 0xe1 0 0 0
312 0xe2 0 0 0
313 0xe3 0 0 0
314 0xe4 0 0 0
315 0xe5 0 0 0
316 0xe6 0 0 0
317 0xe7 0 0 0>;
318 };
319
320 msi1: msi@41800 {
321 compatible = "fsl,mpic-msi";
322 reg = <0x41800 0x200>;
323 msi-available-ranges = <0 0x100>;
324 interrupts = <
325 0xe8 0 0 0
326 0xe9 0 0 0
327 0xea 0 0 0
328 0xeb 0 0 0
329 0xec 0 0 0
330 0xed 0 0 0
331 0xee 0 0 0
332 0xef 0 0 0>;
333 };
334
335 msi2: msi@41a00 {
336 compatible = "fsl,mpic-msi";
337 reg = <0x41a00 0x200>;
338 msi-available-ranges = <0 0x100>;
339 interrupts = <
340 0xf0 0 0 0
341 0xf1 0 0 0
342 0xf2 0 0 0
343 0xf3 0 0 0
344 0xf4 0 0 0
345 0xf5 0 0 0
346 0xf6 0 0 0
347 0xf7 0 0 0>;
348 };
349
350 guts: global-utilities@e0000 {
351 compatible = "fsl,qoriq-device-config-1.0";
352 reg = <0xe0000 0xe00>;
353 fsl,has-rstcr;
354 #sleep-cells = <1>;
355 fsl,liodn-bits = <12>;
356 };
357
358 pins: global-utilities@e0e00 {
359 compatible = "fsl,qoriq-pin-control-1.0";
360 reg = <0xe0e00 0x200>;
361 #sleep-cells = <2>;
362 };
363
364 clockgen: global-utilities@e1000 {
365 compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0";
366 reg = <0xe1000 0x1000>;
367 clock-frequency = <0>;
368 };
369
370 rcpm: global-utilities@e2000 {
371 compatible = "fsl,qoriq-rcpm-1.0";
372 reg = <0xe2000 0x1000>;
373 #sleep-cells = <1>;
374 };
375
376 sfp: sfp@e8000 {
377 compatible = "fsl,p4080-sfp", "fsl,qoriq-sfp-1.0";
378 reg = <0xe8000 0x1000>;
379 };
380
381 serdes: serdes@ea000 {
382 compatible = "fsl,p4080-serdes";
383 reg = <0xea000 0x1000>;
384 };
385
386 dma0: dma@100300 {
387 #address-cells = <1>;
388 #size-cells = <1>;
389 compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
390 reg = <0x100300 0x4>;
391 ranges = <0x0 0x100100 0x200>;
392 cell-index = <0>;
393 dma-channel@0 {
394 compatible = "fsl,p4080-dma-channel",
395 "fsl,eloplus-dma-channel";
396 reg = <0x0 0x80>;
397 cell-index = <0>;
398 interrupts = <28 2 0 0>;
399 };
400 dma-channel@80 {
401 compatible = "fsl,p4080-dma-channel",
402 "fsl,eloplus-dma-channel";
403 reg = <0x80 0x80>;
404 cell-index = <1>;
405 interrupts = <29 2 0 0>;
406 };
407 dma-channel@100 {
408 compatible = "fsl,p4080-dma-channel",
409 "fsl,eloplus-dma-channel";
410 reg = <0x100 0x80>;
411 cell-index = <2>;
412 interrupts = <30 2 0 0>;
413 };
414 dma-channel@180 {
415 compatible = "fsl,p4080-dma-channel",
416 "fsl,eloplus-dma-channel";
417 reg = <0x180 0x80>;
418 cell-index = <3>;
419 interrupts = <31 2 0 0>;
420 };
421 };
422
423 dma1: dma@101300 {
424 #address-cells = <1>;
425 #size-cells = <1>;
426 compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
427 reg = <0x101300 0x4>;
428 ranges = <0x0 0x101100 0x200>;
429 cell-index = <1>;
430 dma-channel@0 {
431 compatible = "fsl,p4080-dma-channel",
432 "fsl,eloplus-dma-channel";
433 reg = <0x0 0x80>;
434 cell-index = <0>;
435 interrupts = <32 2 0 0>;
436 };
437 dma-channel@80 {
438 compatible = "fsl,p4080-dma-channel",
439 "fsl,eloplus-dma-channel";
440 reg = <0x80 0x80>;
441 cell-index = <1>;
442 interrupts = <33 2 0 0>;
443 };
444 dma-channel@100 {
445 compatible = "fsl,p4080-dma-channel",
446 "fsl,eloplus-dma-channel";
447 reg = <0x100 0x80>;
448 cell-index = <2>;
449 interrupts = <34 2 0 0>;
450 };
451 dma-channel@180 {
452 compatible = "fsl,p4080-dma-channel",
453 "fsl,eloplus-dma-channel";
454 reg = <0x180 0x80>;
455 cell-index = <3>;
456 interrupts = <35 2 0 0>;
457 };
458 };
459
460 spi@110000 {
461 #address-cells = <1>;
462 #size-cells = <0>;
463 compatible = "fsl,p4080-espi", "fsl,mpc8536-espi";
464 reg = <0x110000 0x1000>;
465 interrupts = <53 0x2 0 0>;
466 fsl,espi-num-chipselects = <4>;
467 };
468
469 sdhc: sdhc@114000 {
470 compatible = "fsl,p4080-esdhc", "fsl,esdhc";
471 reg = <0x114000 0x1000>;
472 interrupts = <48 2 0 0>;
473 voltage-ranges = <3300 3300>;
474 sdhci,auto-cmd12;
475 clock-frequency = <0>;
476 };
477
478 i2c@118000 {
479 #address-cells = <1>;
480 #size-cells = <0>;
481 cell-index = <0>;
482 compatible = "fsl-i2c";
483 reg = <0x118000 0x100>;
484 interrupts = <38 2 0 0>;
485 dfsrr;
486 };
487
488 i2c@118100 {
489 #address-cells = <1>;
490 #size-cells = <0>;
491 cell-index = <1>;
492 compatible = "fsl-i2c";
493 reg = <0x118100 0x100>;
494 interrupts = <38 2 0 0>;
495 dfsrr;
496 };
497
498 i2c@119000 {
499 #address-cells = <1>;
500 #size-cells = <0>;
501 cell-index = <2>;
502 compatible = "fsl-i2c";
503 reg = <0x119000 0x100>;
504 interrupts = <39 2 0 0>;
505 dfsrr;
506 };
507
508 i2c@119100 {
509 #address-cells = <1>;
510 #size-cells = <0>;
511 cell-index = <3>;
512 compatible = "fsl-i2c";
513 reg = <0x119100 0x100>;
514 interrupts = <39 2 0 0>;
515 dfsrr;
516 };
517
518 serial0: serial@11c500 {
519 cell-index = <0>;
520 device_type = "serial";
521 compatible = "ns16550";
522 reg = <0x11c500 0x100>;
523 clock-frequency = <0>;
524 interrupts = <36 2 0 0>;
525 };
526
527 serial1: serial@11c600 {
528 cell-index = <1>;
529 device_type = "serial";
530 compatible = "ns16550";
531 reg = <0x11c600 0x100>;
532 clock-frequency = <0>;
533 interrupts = <36 2 0 0>;
534 };
535
536 serial2: serial@11d500 {
537 cell-index = <2>;
538 device_type = "serial";
539 compatible = "ns16550";
540 reg = <0x11d500 0x100>;
541 clock-frequency = <0>;
542 interrupts = <37 2 0 0>;
543 };
544
545 serial3: serial@11d600 {
546 cell-index = <3>;
547 device_type = "serial";
548 compatible = "ns16550";
549 reg = <0x11d600 0x100>;
550 clock-frequency = <0>;
551 interrupts = <37 2 0 0>;
552 };
553
554 gpio0: gpio@130000 {
555 compatible = "fsl,p4080-gpio", "fsl,qoriq-gpio";
556 reg = <0x130000 0x1000>;
557 interrupts = <55 2 0 0>;
558 #gpio-cells = <2>;
559 gpio-controller;
560 };
561
562 usb0: usb@210000 {
563 compatible = "fsl,p4080-usb2-mph",
564 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
565 reg = <0x210000 0x1000>;
566 #address-cells = <1>;
567 #size-cells = <0>;
568 interrupts = <44 0x2 0 0>;
569 };
570
571 usb1: usb@211000 {
572 compatible = "fsl,p4080-usb2-dr",
573 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
574 reg = <0x211000 0x1000>;
575 #address-cells = <1>;
576 #size-cells = <0>;
577 interrupts = <45 0x2 0 0>;
578 };
579
580 crypto: crypto@300000 {
581 compatible = "fsl,sec-v4.0";
582 #address-cells = <1>;
583 #size-cells = <1>;
584 reg = <0x300000 0x10000>;
585 ranges = <0 0x300000 0x10000>;
586 interrupt-parent = <&mpic>;
587 interrupts = <92 2 0 0>;
588
589 sec_jr0: jr@1000 {
590 compatible = "fsl,sec-v4.0-job-ring";
591 reg = <0x1000 0x1000>;
592 interrupt-parent = <&mpic>;
593 interrupts = <88 2 0 0>;
594 };
595
596 sec_jr1: jr@2000 {
597 compatible = "fsl,sec-v4.0-job-ring";
598 reg = <0x2000 0x1000>;
599 interrupt-parent = <&mpic>;
600 interrupts = <89 2 0 0>;
601 };
602
603 sec_jr2: jr@3000 {
604 compatible = "fsl,sec-v4.0-job-ring";
605 reg = <0x3000 0x1000>;
606 interrupt-parent = <&mpic>;
607 interrupts = <90 2 0 0>;
608 };
609
610 sec_jr3: jr@4000 {
611 compatible = "fsl,sec-v4.0-job-ring";
612 reg = <0x4000 0x1000>;
613 interrupt-parent = <&mpic>;
614 interrupts = <91 2 0 0>;
615 };
616
617 rtic@6000 {
618 compatible = "fsl,sec-v4.0-rtic";
619 #address-cells = <1>;
620 #size-cells = <1>;
621 reg = <0x6000 0x100>;
622 ranges = <0x0 0x6100 0xe00>;
623
624 rtic_a: rtic-a@0 {
625 compatible = "fsl,sec-v4.0-rtic-memory";
626 reg = <0x00 0x20 0x100 0x80>;
627 };
628
629 rtic_b: rtic-b@20 {
630 compatible = "fsl,sec-v4.0-rtic-memory";
631 reg = <0x20 0x20 0x200 0x80>;
632 };
633
634 rtic_c: rtic-c@40 {
635 compatible = "fsl,sec-v4.0-rtic-memory";
636 reg = <0x40 0x20 0x300 0x80>;
637 };
638
639 rtic_d: rtic-d@60 {
640 compatible = "fsl,sec-v4.0-rtic-memory";
641 reg = <0x60 0x20 0x500 0x80>;
642 };
643 };
644 };
645
646 sec_mon: sec_mon@314000 {
647 compatible = "fsl,sec-v4.0-mon";
648 reg = <0x314000 0x1000>;
649 interrupt-parent = <&mpic>;
650 interrupts = <93 2 0 0>;
651 };
652 };
653
654 rapidio0: rapidio@ffe0c0000 {
655 #address-cells = <2>;
656 #size-cells = <2>;
657 compatible = "fsl,rapidio-delta";
658 interrupts = <
659 16 2 1 11 /* err_irq */
660 56 2 0 0 /* bell_outb_irq */
661 57 2 0 0 /* bell_inb_irq */
662 60 2 0 0 /* msg1_tx_irq */
663 61 2 0 0 /* msg1_rx_irq */
664 62 2 0 0 /* msg2_tx_irq */
665 63 2 0 0>; /* msg2_rx_irq */
666 };
667
668 localbus@ffe124000 {
669 compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
670 interrupts = <25 2 0 0>;
671 #address-cells = <2>;
672 #size-cells = <1>;
673 };
674
675 pci0: pcie@ffe200000 {
676 compatible = "fsl,p4080-pcie";
677 device_type = "pci";
678 #size-cells = <2>;
679 #address-cells = <3>;
680 bus-range = <0x0 0xff>;
681 clock-frequency = <0x1fca055>;
682 fsl,msi = <&msi0>;
683 interrupts = <16 2 1 15>;
684 pcie@0 {
685 reg = <0 0 0 0 0>;
686 #interrupt-cells = <1>;
687 #size-cells = <2>;
688 #address-cells = <3>;
689 device_type = "pci";
690 interrupts = <16 2 1 15>;
691 interrupt-map-mask = <0xf800 0 0 7>;
692 interrupt-map = <
693 /* IDSEL 0x0 */
694 0000 0 0 1 &mpic 40 1 0 0
695 0000 0 0 2 &mpic 1 1 0 0
696 0000 0 0 3 &mpic 2 1 0 0
697 0000 0 0 4 &mpic 3 1 0 0
698 >;
699 };
700 };
701
702 pci1: pcie@ffe201000 {
703 compatible = "fsl,p4080-pcie";
704 device_type = "pci";
705 #size-cells = <2>;
706 #address-cells = <3>;
707 bus-range = <0 0xff>;
708 clock-frequency = <0x1fca055>;
709 fsl,msi = <&msi1>;
710 interrupts = <16 2 1 14>;
711 pcie@0 {
712 reg = <0 0 0 0 0>;
713 #interrupt-cells = <1>;
714 #size-cells = <2>;
715 #address-cells = <3>;
716 device_type = "pci";
717 interrupts = <16 2 1 14>;
718 interrupt-map-mask = <0xf800 0 0 7>;
719 interrupt-map = <
720 /* IDSEL 0x0 */
721 0000 0 0 1 &mpic 41 1 0 0
722 0000 0 0 2 &mpic 5 1 0 0
723 0000 0 0 3 &mpic 6 1 0 0
724 0000 0 0 4 &mpic 7 1 0 0
725 >;
726 };
727 };
728
729 pci2: pcie@ffe202000 {
730 compatible = "fsl,p4080-pcie";
731 device_type = "pci";
732 #size-cells = <2>;
733 #address-cells = <3>;
734 bus-range = <0x0 0xff>;
735 clock-frequency = <0x1fca055>;
736 fsl,msi = <&msi2>;
737 interrupts = <16 2 1 13>;
738 pcie@0 {
739 reg = <0 0 0 0 0>;
740 #interrupt-cells = <1>;
741 #size-cells = <2>;
742 #address-cells = <3>;
743 device_type = "pci";
744 interrupts = <16 2 1 13>;
745 interrupt-map-mask = <0xf800 0 0 7>;
746 interrupt-map = <
747 /* IDSEL 0x0 */
748 0000 0 0 1 &mpic 42 1 0 0
749 0000 0 0 2 &mpic 9 1 0 0
750 0000 0 0 3 &mpic 10 1 0 0
751 0000 0 0 4 &mpic 11 1 0 0
752 >;
753 };
754 };
755};
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-09 11:27:13 -0500