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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2012-07-12 23:38:26 -0400
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2012-07-12 23:38:26 -0400
commitaf3bf7fbe0148aadc8fedd6f5e5279cabef9ced5 (patch)
tree25e3b1099ecf851bb7b5f6e6d3ffcdeb33de32f0 /arch/powerpc
parent10db8d212864cb6741df7d7fafda5ab6661f6f88 (diff)
parentb915341b4be29b3b2c02da932b69871e9b55ca4b (diff)
Merge remote-tracking branch 'kumar/next' into next
Freescale updates for 3.6
Diffstat (limited to 'arch/powerpc')
-rw-r--r--arch/powerpc/Kconfig2
-rw-r--r--arch/powerpc/boot/Makefile1
-rw-r--r--arch/powerpc/boot/dts/bsc9131rdb.dts34
-rw-r--r--arch/powerpc/boot/dts/bsc9131rdb.dtsi142
-rw-r--r--arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi193
-rw-r--r--arch/powerpc/boot/dts/fsl/bsc9131si-pre.dtsi (renamed from arch/powerpc/boot/dts/fsl/p3060si-pre.dtsi)84
-rw-r--r--arch/powerpc/boot/dts/fsl/p1021si-post.dtsi16
-rw-r--r--arch/powerpc/boot/dts/fsl/p3060si-post.dtsi302
-rw-r--r--arch/powerpc/boot/dts/mgcoge.dts23
-rw-r--r--arch/powerpc/boot/dts/mpc8536ds.dtsi8
-rw-r--r--arch/powerpc/boot/dts/mpc8544ds.dtsi9
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds.dtsi17
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts8
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts11
-rw-r--r--arch/powerpc/boot/dts/p1010rdb.dtsi12
-rw-r--r--arch/powerpc/boot/dts/p1021rdb-pc.dtsi (renamed from arch/powerpc/boot/dts/p1021rdb.dtsi)2
-rw-r--r--arch/powerpc/boot/dts/p1021rdb-pc_32b.dts (renamed from arch/powerpc/boot/dts/p1021rdb.dts)4
-rw-r--r--arch/powerpc/boot/dts/p1021rdb-pc_36b.dts (renamed from arch/powerpc/boot/dts/p1021rdb_36b.dts)4
-rw-r--r--arch/powerpc/boot/dts/p1022ds.dtsi20
-rw-r--r--arch/powerpc/boot/dts/p1024rdb.dtsi228
-rw-r--r--arch/powerpc/boot/dts/p1024rdb_32b.dts87
-rw-r--r--arch/powerpc/boot/dts/p1024rdb_36b.dts87
-rw-r--r--arch/powerpc/boot/dts/p1025rdb.dtsi40
-rw-r--r--arch/powerpc/boot/dts/p2020ds.dtsi10
-rw-r--r--arch/powerpc/boot/dts/p2020rdb.dts2
-rw-r--r--arch/powerpc/boot/dts/p2041rdb.dts41
-rw-r--r--arch/powerpc/boot/dts/p3060qds.dts242
-rw-r--r--arch/powerpc/boot/dts/sbc8560.dts406
-rw-r--r--arch/powerpc/configs/83xx/kmeter1_defconfig22
-rw-r--r--arch/powerpc/configs/85xx/sbc8560_defconfig65
-rw-r--r--arch/powerpc/configs/corenet32_smp_defconfig10
-rw-r--r--arch/powerpc/configs/corenet64_smp_defconfig66
-rw-r--r--arch/powerpc/configs/mgcoge_defconfig12
-rw-r--r--arch/powerpc/configs/mpc85xx_defconfig24
-rw-r--r--arch/powerpc/configs/mpc85xx_smp_defconfig25
-rw-r--r--arch/powerpc/include/asm/immap_qe.h4
-rw-r--r--arch/powerpc/include/asm/qe.h1
-rw-r--r--arch/powerpc/kernel/head_fsl_booke.S23
-rw-r--r--arch/powerpc/kernel/setup-common.c27
-rw-r--r--arch/powerpc/kernel/setup_32.c24
-rw-r--r--arch/powerpc/platforms/82xx/km82xx.c5
-rw-r--r--arch/powerpc/platforms/83xx/km83xx.c100
-rw-r--r--arch/powerpc/platforms/85xx/Kconfig43
-rw-r--r--arch/powerpc/platforms/85xx/Makefile4
-rw-r--r--arch/powerpc/platforms/85xx/bsc913x_rdb.c67
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_ds.c97
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_rdb.c22
-rw-r--r--arch/powerpc/platforms/85xx/p1022_ds.c106
-rw-r--r--arch/powerpc/platforms/85xx/p3060_qds.c77
-rw-r--r--arch/powerpc/platforms/85xx/qemu_e500.c72
-rw-r--r--arch/powerpc/platforms/85xx/sbc8560.c254
-rw-r--r--arch/powerpc/platforms/Kconfig.cputype4
-rw-r--r--arch/powerpc/sysdev/fsl_pci.c73
-rw-r--r--arch/powerpc/sysdev/fsl_pci.h8
-rw-r--r--arch/powerpc/sysdev/mpic.c2
-rw-r--r--arch/powerpc/sysdev/qe_lib/qe.c3
56 files changed, 1601 insertions, 1674 deletions
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 050cb371a69e..9a5d3cdc3e12 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -653,7 +653,7 @@ config SBUS
653config FSL_SOC 653config FSL_SOC
654 bool 654 bool
655 select HAVE_CAN_FLEXCAN if NET && CAN 655 select HAVE_CAN_FLEXCAN if NET && CAN
656 select PPC_CLOCK if CAN_FLEXCAN 656 select PPC_CLOCK
657 657
658config FSL_PCI 658config FSL_PCI
659 bool 659 bool
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index c802a90ae2d7..b7d833382be4 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -276,7 +276,6 @@ image-$(CONFIG_TQM8548) += cuImage.tqm8548
276image-$(CONFIG_TQM8555) += cuImage.tqm8555 276image-$(CONFIG_TQM8555) += cuImage.tqm8555
277image-$(CONFIG_TQM8560) += cuImage.tqm8560 277image-$(CONFIG_TQM8560) += cuImage.tqm8560
278image-$(CONFIG_SBC8548) += cuImage.sbc8548 278image-$(CONFIG_SBC8548) += cuImage.sbc8548
279image-$(CONFIG_SBC8560) += cuImage.sbc8560
280image-$(CONFIG_KSI8560) += cuImage.ksi8560 279image-$(CONFIG_KSI8560) += cuImage.ksi8560
281 280
282# Board ports in arch/powerpc/platform/embedded6xx/Kconfig 281# Board ports in arch/powerpc/platform/embedded6xx/Kconfig
diff --git a/arch/powerpc/boot/dts/bsc9131rdb.dts b/arch/powerpc/boot/dts/bsc9131rdb.dts
new file mode 100644
index 000000000000..e13d2d4877b0
--- /dev/null
+++ b/arch/powerpc/boot/dts/bsc9131rdb.dts
@@ -0,0 +1,34 @@
1/*
2 * BSC9131 RDB Device Tree Source
3 *
4 * Copyright 2011-2012 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/include/ "fsl/bsc9131si-pre.dtsi"
13
14/ {
15 model = "fsl,bsc9131rdb";
16 compatible = "fsl,bsc9131rdb";
17
18 memory {
19 device_type = "memory";
20 };
21
22 board_ifc: ifc: ifc@ff71e000 {
23 /* NAND Flash on board */
24 ranges = <0x0 0x0 0x0 0xff800000 0x00004000>;
25 reg = <0x0 0xff71e000 0x0 0x2000>;
26 };
27
28 board_soc: soc: soc@ff700000 {
29 ranges = <0x0 0x0 0xff700000 0x100000>;
30 };
31};
32
33/include/ "bsc9131rdb.dtsi"
34/include/ "fsl/bsc9131si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/bsc9131rdb.dtsi b/arch/powerpc/boot/dts/bsc9131rdb.dtsi
new file mode 100644
index 000000000000..638adda2c218
--- /dev/null
+++ b/arch/powerpc/boot/dts/bsc9131rdb.dtsi
@@ -0,0 +1,142 @@
1/*
2 * BSC9131 RDB Device Tree Source stub (no addresses or top-level ranges)
3 *
4 * Copyright 2011-2012 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&board_ifc {
36
37 nand@0,0 {
38 #address-cells = <1>;
39 #size-cells = <1>;
40 compatible = "fsl,ifc-nand";
41 reg = <0x0 0x0 0x4000>;
42
43 partition@0 {
44 /* This location must not be altered */
45 /* 3MB for u-boot Bootloader Image */
46 reg = <0x0 0x00300000>;
47 label = "NAND U-Boot Image";
48 read-only;
49 };
50
51 partition@300000 {
52 /* 1MB for DTB Image */
53 reg = <0x00300000 0x00100000>;
54 label = "NAND DTB Image";
55 };
56
57 partition@400000 {
58 /* 8MB for Linux Kernel Image */
59 reg = <0x00400000 0x00800000>;
60 label = "NAND Linux Kernel Image";
61 };
62
63 partition@c00000 {
64 /* Rest space for Root file System Image */
65 reg = <0x00c00000 0x07400000>;
66 label = "NAND RFS Image";
67 };
68 };
69};
70
71&board_soc {
72 /* BSC9131RDB does not have any device on i2c@3100 */
73 i2c@3100 {
74 status = "disabled";
75 };
76
77 spi@7000 {
78 flash@0 {
79 #address-cells = <1>;
80 #size-cells = <1>;
81 compatible = "spansion,s25sl12801";
82 reg = <0>;
83 spi-max-frequency = <50000000>;
84
85 /* 512KB for u-boot Bootloader Image */
86 partition@0 {
87 reg = <0x0 0x00080000>;
88 label = "SPI Flash U-Boot Image";
89 read-only;
90 };
91
92 /* 512KB for DTB Image */
93 partition@80000 {
94 reg = <0x00080000 0x00080000>;
95 label = "SPI Flash DTB Image";
96 };
97
98 /* 4MB for Linux Kernel Image */
99 partition@100000 {
100 reg = <0x00100000 0x00400000>;
101 label = "SPI Flash Kernel Image";
102 };
103
104 /*11MB for RFS Image */
105 partition@500000 {
106 reg = <0x00500000 0x00B00000>;
107 label = "SPI Flash RFS Image";
108 };
109
110 };
111 };
112
113 usb@22000 {
114 phy_type = "ulpi";
115 };
116
117 mdio@24000 {
118 phy0: ethernet-phy@0 {
119 interrupts = <3 1 0 0>;
120 reg = <0x0>;
121 };
122
123 phy1: ethernet-phy@1 {
124 interrupts = <2 1 0 0>;
125 reg = <0x3>;
126 };
127 };
128
129 sdhci@2e000 {
130 status = "disabled";
131 };
132
133 enet0: ethernet@b0000 {
134 phy-handle = <&phy0>;
135 phy-connection-type = "rgmii-id";
136 };
137
138 enet1: ethernet@b1000 {
139 phy-handle = <&phy1>;
140 phy-connection-type = "rgmii-id";
141 };
142};
diff --git a/arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi b/arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi
new file mode 100644
index 000000000000..5180d9d37989
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi
@@ -0,0 +1,193 @@
1/*
2 * BSC9131 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011-2012 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&ifc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,ifc", "simple-bus";
39 interrupts = <16 2 0 0 20 2 0 0>;
40};
41
42&soc {
43 #address-cells = <1>;
44 #size-cells = <1>;
45 device_type = "soc";
46 compatible = "fsl,bsc9131-immr", "simple-bus";
47 bus-frequency = <0>; // Filled out by uboot.
48
49 ecm-law@0 {
50 compatible = "fsl,ecm-law";
51 reg = <0x0 0x1000>;
52 fsl,num-laws = <12>;
53 };
54
55 ecm@1000 {
56 compatible = "fsl,bsc9131-ecm", "fsl,ecm";
57 reg = <0x1000 0x1000>;
58 interrupts = <16 2 0 0>;
59 };
60
61 memory-controller@2000 {
62 compatible = "fsl,bsc9131-memory-controller";
63 reg = <0x2000 0x1000>;
64 interrupts = <16 2 0 0>;
65 };
66
67/include/ "pq3-i2c-0.dtsi"
68 i2c@3000 {
69 interrupts = <17 2 0 0>;
70 };
71
72/include/ "pq3-i2c-1.dtsi"
73 i2c@3100 {
74 interrupts = <17 2 0 0>;
75 };
76
77/include/ "pq3-duart-0.dtsi"
78 serial0: serial@4500 {
79 interrupts = <18 2 0 0>;
80 };
81
82 serial1: serial@4600 {
83 interrupts = <18 2 0 0 >;
84 };
85/include/ "pq3-espi-0.dtsi"
86 spi0: spi@7000 {
87 fsl,espi-num-chipselects = <1>;
88 interrupts = <22 0x2 0 0>;
89 };
90
91/include/ "pq3-gpio-0.dtsi"
92 gpio-controller@f000 {
93 interrupts = <19 0x2 0 0>;
94 };
95
96 L2: l2-cache-controller@20000 {
97 compatible = "fsl,bsc9131-l2-cache-controller";
98 reg = <0x20000 0x1000>;
99 cache-line-size = <32>; // 32 bytes
100 cache-size = <0x40000>; // L2,256K
101 interrupts = <16 2 0 0>;
102 };
103
104/include/ "pq3-dma-0.dtsi"
105
106dma@21300 {
107
108 dma-channel@0 {
109 interrupts = <62 2 0 0>;
110 };
111
112 dma-channel@80 {
113 interrupts = <63 2 0 0>;
114 };
115
116 dma-channel@100 {
117 interrupts = <64 2 0 0>;
118 };
119
120 dma-channel@180 {
121 interrupts = <65 2 0 0>;
122 };
123};
124
125/include/ "pq3-usb2-dr-0.dtsi"
126usb@22000 {
127 compatible = "fsl-usb2-dr","fsl-usb2-dr-v2.2";
128 interrupts = <40 0x2 0 0>;
129};
130
131/include/ "pq3-esdhc-0.dtsi"
132 sdhc@2e000 {
133 fsl,sdhci-auto-cmd12;
134 interrupts = <41 0x2 0 0>;
135 };
136
137/include/ "pq3-sec4.4-0.dtsi"
138crypto@30000 {
139 interrupts = <57 2 0 0>;
140
141 sec_jr0: jr@1000 {
142 interrupts = <58 2 0 0>;
143 };
144
145 sec_jr1: jr@2000 {
146 interrupts = <59 2 0 0>;
147 };
148
149 sec_jr2: jr@3000 {
150 interrupts = <60 2 0 0>;
151 };
152
153 sec_jr3: jr@4000 {
154 interrupts = <61 2 0 0>;
155 };
156};
157
158/include/ "pq3-mpic.dtsi"
159
160timer@41100 {
161 compatible = "fsl,mpic-v1.2-msgr", "fsl,mpic-msg";
162 reg = <0x41400 0x200>;
163 interrupts = <
164 0xb0 2
165 0xb1 2
166 0xb2 2
167 0xb3 2>;
168};
169
170/include/ "pq3-etsec2-0.dtsi"
171enet0: ethernet@b0000 {
172 queue-group@b0000 {
173 fsl,rx-bit-map = <0xff>;
174 fsl,tx-bit-map = <0xff>;
175 interrupts = <26 2 0 0 27 2 0 0 28 2 0 0>;
176 };
177};
178
179/include/ "pq3-etsec2-1.dtsi"
180enet1: ethernet@b1000 {
181 queue-group@b1000 {
182 fsl,rx-bit-map = <0xff>;
183 fsl,tx-bit-map = <0xff>;
184 interrupts = <33 2 0 0 34 2 0 0 35 2 0 0>;
185 };
186};
187
188global-utilities@e0000 {
189 compatible = "fsl,bsc9131-guts";
190 reg = <0xe0000 0x1000>;
191 fsl,has-rstcr;
192 };
193};
diff --git a/arch/powerpc/boot/dts/fsl/p3060si-pre.dtsi b/arch/powerpc/boot/dts/fsl/bsc9131si-pre.dtsi
index 00c8e70e7b90..743e4aeda349 100644
--- a/arch/powerpc/boot/dts/fsl/p3060si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/bsc9131si-pre.dtsi
@@ -1,7 +1,7 @@
1/* 1/*
2 * P3060 Silicon/SoC Device Tree Source (pre include) 2 * BSC9131 Silicon/SoC Device Tree Source (pre include)
3 * 3 *
4 * Copyright 2011 Freescale Semiconductor Inc. 4 * Copyright 2011-2012 Freescale Semiconductor Inc.
5 * 5 *
6 * Redistribution and use in source and binary forms, with or without 6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met: 7 * modification, are permitted provided that the following conditions are met:
@@ -34,92 +34,26 @@
34 34
35/dts-v1/; 35/dts-v1/;
36/ { 36/ {
37 compatible = "fsl,P3060"; 37 compatible = "fsl,BSC9131";
38 #address-cells = <2>; 38 #address-cells = <2>;
39 #size-cells = <2>; 39 #size-cells = <2>;
40 interrupt-parent = <&mpic>; 40 interrupt-parent = <&mpic>;
41 41
42 aliases { 42 aliases {
43 ccsr = &soc;
44 dcsr = &dcsr;
45
46 serial0 = &serial0; 43 serial0 = &serial0;
47 serial1 = &serial1; 44 ethernet0 = &enet0;
48 serial2 = &serial2; 45 ethernet1 = &enet1;
49 serial3 = &serial3;
50 pci0 = &pci0;
51 pci1 = &pci1;
52 usb0 = &usb0;
53 usb1 = &usb1;
54 dma0 = &dma0;
55 dma1 = &dma1;
56 msi0 = &msi0;
57 msi1 = &msi1;
58 msi2 = &msi2;
59
60 crypto = &crypto;
61 sec_jr0 = &sec_jr0;
62 sec_jr1 = &sec_jr1;
63 sec_jr2 = &sec_jr2;
64 sec_jr3 = &sec_jr3;
65 rtic_a = &rtic_a;
66 rtic_b = &rtic_b;
67 rtic_c = &rtic_c;
68 rtic_d = &rtic_d;
69 sec_mon = &sec_mon;
70 }; 46 };
71 47
72 cpus { 48 cpus {
73 #address-cells = <1>; 49 #address-cells = <1>;
74 #size-cells = <0>; 50 #size-cells = <0>;
75 51
76 cpu0: PowerPC,e500mc@0 { 52 PowerPC,BSC9131@0 {
77 device_type = "cpu";
78 reg = <0>;
79 next-level-cache = <&L2_0>;
80 L2_0: l2-cache {
81 next-level-cache = <&cpc>;
82 };
83 };
84 cpu1: PowerPC,e500mc@1 {
85 device_type = "cpu";
86 reg = <1>;
87 next-level-cache = <&L2_1>;
88 L2_1: l2-cache {
89 next-level-cache = <&cpc>;
90 };
91 };
92 cpu4: PowerPC,e500mc@4 {
93 device_type = "cpu";
94 reg = <4>;
95 next-level-cache = <&L2_4>;
96 L2_4: l2-cache {
97 next-level-cache = <&cpc>;
98 };
99 };
100 cpu5: PowerPC,e500mc@5 {
101 device_type = "cpu";
102 reg = <5>;
103 next-level-cache = <&L2_5>;
104 L2_5: l2-cache {
105 next-level-cache = <&cpc>;
106 };
107 };
108 cpu6: PowerPC,e500mc@6 {
109 device_type = "cpu";
110 reg = <6>;
111 next-level-cache = <&L2_6>;
112 L2_6: l2-cache {
113 next-level-cache = <&cpc>;
114 };
115 };
116 cpu7: PowerPC,e500mc@7 {
117 device_type = "cpu"; 53 device_type = "cpu";
118 reg = <7>; 54 compatible = "fsl,e500v2";
119 next-level-cache = <&L2_7>; 55 reg = <0x0>;
120 L2_7: l2-cache { 56 next-level-cache = <&L2>;
121 next-level-cache = <&cpc>;
122 };
123 }; 57 };
124 }; 58 };
125}; 59};
diff --git a/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
index 4252ef85fb7a..adb82fd9057f 100644
--- a/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
@@ -1,7 +1,7 @@
1/* 1/*
2 * P1021/P1012 Silicon/SoC Device Tree Source (post include) 2 * P1021/P1012 Silicon/SoC Device Tree Source (post include)
3 * 3 *
4 * Copyright 2011 Freescale Semiconductor Inc. 4 * Copyright 2011-2012 Freescale Semiconductor Inc.
5 * 5 *
6 * Redistribution and use in source and binary forms, with or without 6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met: 7 * modification, are permitted provided that the following conditions are met:
@@ -213,6 +213,20 @@
213 interrupt-parent = <&qeic>; 213 interrupt-parent = <&qeic>;
214 }; 214 };
215 215
216 ucc@2600 {
217 cell-index = <7>;
218 reg = <0x2600 0x200>;
219 interrupts = <42>;
220 interrupt-parent = <&qeic>;
221 };
222
223 ucc@2200 {
224 cell-index = <3>;
225 reg = <0x2200 0x200>;
226 interrupts = <34>;
227 interrupt-parent = <&qeic>;
228 };
229
216 muram@10000 { 230 muram@10000 {
217 #address-cells = <1>; 231 #address-cells = <1>;
218 #size-cells = <1>; 232 #size-cells = <1>;
diff --git a/arch/powerpc/boot/dts/fsl/p3060si-post.dtsi b/arch/powerpc/boot/dts/fsl/p3060si-post.dtsi
deleted file mode 100644
index b3e56929eee2..000000000000
--- a/arch/powerpc/boot/dts/fsl/p3060si-post.dtsi
+++ /dev/null
@@ -1,302 +0,0 @@
1/*
2 * P3060 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 compatible = "fsl,p3060-elbc", "fsl,elbc", "simple-bus";
37 interrupts = <25 2 0 0>;
38 #address-cells = <2>;
39 #size-cells = <1>;
40};
41
42/* controller at 0x200000 */
43&pci0 {
44 compatible = "fsl,p3060-pcie", "fsl,qoriq-pcie-v2.2";
45 device_type = "pci";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0x0 0xff>;
49 clock-frequency = <33333333>;
50 interrupts = <16 2 1 15>;
51 pcie@0 {
52 reg = <0 0 0 0 0>;
53 #interrupt-cells = <1>;
54 #size-cells = <2>;
55 #address-cells = <3>;
56 device_type = "pci";
57 interrupts = <16 2 1 15>;
58 interrupt-map-mask = <0xf800 0 0 7>;
59 interrupt-map = <
60 /* IDSEL 0x0 */
61 0000 0 0 1 &mpic 40 1 0 0
62 0000 0 0 2 &mpic 1 1 0 0
63 0000 0 0 3 &mpic 2 1 0 0
64 0000 0 0 4 &mpic 3 1 0 0
65 >;
66 };
67};
68
69/* controller at 0x201000 */
70&pci1 {
71 compatible = "fsl,p3060-pcie", "fsl,qoriq-pcie-v2.2";
72 device_type = "pci";
73 #size-cells = <2>;
74 #address-cells = <3>;
75 bus-range = <0 0xff>;
76 clock-frequency = <33333333>;
77 interrupts = <16 2 1 14>;
78 pcie@0 {
79 reg = <0 0 0 0 0>;
80 #interrupt-cells = <1>;
81 #size-cells = <2>;
82 #address-cells = <3>;
83 device_type = "pci";
84 interrupts = <16 2 1 14>;
85 interrupt-map-mask = <0xf800 0 0 7>;
86 interrupt-map = <
87 /* IDSEL 0x0 */
88 0000 0 0 1 &mpic 41 1 0 0
89 0000 0 0 2 &mpic 5 1 0 0
90 0000 0 0 3 &mpic 6 1 0 0
91 0000 0 0 4 &mpic 7 1 0 0
92 >;
93 };
94};
95
96&rio {
97 compatible = "fsl,srio";
98 interrupts = <16 2 1 11>;
99 #address-cells = <2>;
100 #size-cells = <2>;
101 fsl,srio-rmu-handle = <&rmu>;
102 ranges;
103
104 port1 {
105 #address-cells = <2>;
106 #size-cells = <2>;
107 cell-index = <1>;
108 };
109
110 port2 {
111 #address-cells = <2>;
112 #size-cells = <2>;
113 cell-index = <2>;
114 };
115};
116
117&dcsr {
118 #address-cells = <1>;
119 #size-cells = <1>;
120 compatible = "fsl,dcsr", "simple-bus";
121
122 dcsr-epu@0 {
123 compatible = "fsl,dcsr-epu";
124 interrupts = <52 2 0 0
125 84 2 0 0
126 85 2 0 0>;
127 reg = <0x0 0x1000>;
128 };
129 dcsr-npc {
130 compatible = "fsl,dcsr-npc";
131 reg = <0x1000 0x1000 0x1000000 0x8000>;
132 };
133 dcsr-nxc@2000 {
134 compatible = "fsl,dcsr-nxc";
135 reg = <0x2000 0x1000>;
136 };
137 dcsr-corenet {
138 compatible = "fsl,dcsr-corenet";
139 reg = <0x8000 0x1000 0xB0000 0x1000>;
140 };
141 dcsr-dpaa@9000 {
142 compatible = "fsl,p3060-dcsr-dpaa", "fsl,dcsr-dpaa";
143 reg = <0x9000 0x1000>;
144 };
145 dcsr-ocn@11000 {
146 compatible = "fsl,p3060-dcsr-ocn", "fsl,dcsr-ocn";
147 reg = <0x11000 0x1000>;
148 };
149 dcsr-ddr@12000 {
150 compatible = "fsl,dcsr-ddr";
151 dev-handle = <&ddr1>;
152 reg = <0x12000 0x1000>;
153 };
154 dcsr-nal@18000 {
155 compatible = "fsl,p3060-dcsr-nal", "fsl,dcsr-nal";
156 reg = <0x18000 0x1000>;
157 };
158 dcsr-rcpm@22000 {
159 compatible = "fsl,p3060-dcsr-rcpm", "fsl,dcsr-rcpm";
160 reg = <0x22000 0x1000>;
161 };
162 dcsr-cpu-sb-proxy@40000 {
163 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
164 cpu-handle = <&cpu0>;
165 reg = <0x40000 0x1000>;
166 };
167 dcsr-cpu-sb-proxy@41000 {
168 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
169 cpu-handle = <&cpu1>;
170 reg = <0x41000 0x1000>;
171 };
172 dcsr-cpu-sb-proxy@44000 {
173 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
174 cpu-handle = <&cpu4>;
175 reg = <0x44000 0x1000>;
176 };
177 dcsr-cpu-sb-proxy@45000 {
178 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
179 cpu-handle = <&cpu5>;
180 reg = <0x45000 0x1000>;
181 };
182 dcsr-cpu-sb-proxy@46000 {
183 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
184 cpu-handle = <&cpu6>;
185 reg = <0x46000 0x1000>;
186 };
187 dcsr-cpu-sb-proxy@47000 {
188 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
189 cpu-handle = <&cpu7>;
190 reg = <0x47000 0x1000>;
191 };
192
193};
194
195&soc {
196 #address-cells = <1>;
197 #size-cells = <1>;
198 device_type = "soc";
199 compatible = "simple-bus";
200
201 soc-sram-error {
202 compatible = "fsl,soc-sram-error";
203 interrupts = <16 2 1 29>;
204 };
205
206 corenet-law@0 {
207 compatible = "fsl,corenet-law";
208 reg = <0x0 0x1000>;
209 fsl,num-laws = <32>;
210 };
211
212 ddr1: memory-controller@8000 {
213 compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller";
214 reg = <0x8000 0x1000>;
215 interrupts = <16 2 1 23>;
216 };
217
218 cpc: l3-cache-controller@10000 {
219 compatible = "fsl,p3060-l3-cache-controller", "cache";
220 reg = <0x10000 0x1000
221 0x11000 0x1000>;
222 interrupts = <16 2 1 27
223 16 2 1 26>;
224 };
225
226 corenet-cf@18000 {
227 compatible = "fsl,corenet-cf";
228 reg = <0x18000 0x1000>;
229 interrupts = <16 2 1 31>;
230 fsl,ccf-num-csdids = <32>;
231 fsl,ccf-num-snoopids = <32>;
232 };
233
234 iommu@20000 {
235 compatible = "fsl,pamu-v1.0", "fsl,pamu";
236 reg = <0x20000 0x5000>;
237 interrupts = <
238 24 2 0 0
239 16 2 1 30>;
240 };
241
242/include/ "qoriq-rmu-0.dtsi"
243/include/ "qoriq-mpic.dtsi"
244
245 guts: global-utilities@e0000 {
246 compatible = "fsl,qoriq-device-config-1.0";
247 reg = <0xe0000 0xe00>;
248 fsl,has-rstcr;
249 #sleep-cells = <1>;
250 fsl,liodn-bits = <12>;
251 };
252
253 pins: global-utilities@e0e00 {
254 compatible = "fsl,qoriq-pin-control-1.0";
255 reg = <0xe0e00 0x200>;
256 #sleep-cells = <2>;
257 };
258
259 clockgen: global-utilities@e1000 {
260 compatible = "fsl,p3060-clockgen", "fsl,qoriq-clockgen-1.0";
261 reg = <0xe1000 0x1000>;
262 clock-frequency = <0>;
263 };
264
265 rcpm: global-utilities@e2000 {
266 compatible = "fsl,qoriq-rcpm-1.0";
267 reg = <0xe2000 0x1000>;
268 #sleep-cells = <1>;
269 };
270
271 sfp: sfp@e8000 {
272 compatible = "fsl,p3060-sfp", "fsl,qoriq-sfp-1.0";
273 reg = <0xe8000 0x1000>;
274 };
275
276 serdes: serdes@ea000 {
277 compatible = "fsl,p3060-serdes";
278 reg = <0xea000 0x1000>;
279 };
280
281/include/ "qoriq-dma-0.dtsi"
282/include/ "qoriq-dma-1.dtsi"
283/include/ "qoriq-espi-0.dtsi"
284 spi@110000 {
285 fsl,espi-num-chipselects = <4>;
286 };
287
288/include/ "qoriq-i2c-0.dtsi"
289/include/ "qoriq-i2c-1.dtsi"
290/include/ "qoriq-duart-0.dtsi"
291/include/ "qoriq-duart-1.dtsi"
292/include/ "qoriq-gpio-0.dtsi"
293/include/ "qoriq-usb2-mph-0.dtsi"
294 usb@210000 {
295 compatible = "fsl-usb2-mph-v2.2", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
296 };
297/include/ "qoriq-usb2-dr-0.dtsi"
298 usb@211000 {
299 compatible = "fsl-usb2-dr-v2.2", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
300 };
301/include/ "qoriq-sec4.1-0.dtsi"
302};
diff --git a/arch/powerpc/boot/dts/mgcoge.dts b/arch/powerpc/boot/dts/mgcoge.dts
index ededaf5ac015..d72fb5e219d0 100644
--- a/arch/powerpc/boot/dts/mgcoge.dts
+++ b/arch/powerpc/boot/dts/mgcoge.dts
@@ -222,6 +222,29 @@
222 interrupt-parent = <&PIC>; 222 interrupt-parent = <&PIC>;
223 usb-clock = <5>; 223 usb-clock = <5>;
224 }; 224 };
225 spi@11aa0 {
226 cell-index = <0>;
227 compatible = "fsl,spi", "fsl,cpm2-spi";
228 reg = <0x11a80 0x40 0x89fc 0x2>;
229 interrupts = <2 8>;
230 interrupt-parent = <&PIC>;
231 gpios = < &cpm2_pio_d 19 0>;
232 #address-cells = <1>;
233 #size-cells = <0>;
234 ds3106@1 {
235 compatible = "gen,spidev";
236 reg = <0>;
237 spi-max-frequency = <8000000>;
238 };
239 };
240
241 };
242
243 cpm2_pio_d: gpio-controller@10d60 {
244 #gpio-cells = <2>;
245 compatible = "fsl,cpm2-pario-bank";
246 reg = <0x10d60 0x14>;
247 gpio-controller;
225 }; 248 };
226 249
227 cpm2_pio_c: gpio-controller@10d40 { 250 cpm2_pio_c: gpio-controller@10d40 {
diff --git a/arch/powerpc/boot/dts/mpc8536ds.dtsi b/arch/powerpc/boot/dts/mpc8536ds.dtsi
index cc46dbd9746d..d304a2d68c62 100644
--- a/arch/powerpc/boot/dts/mpc8536ds.dtsi
+++ b/arch/powerpc/boot/dts/mpc8536ds.dtsi
@@ -203,6 +203,14 @@
203 reg = <1>; 203 reg = <1>;
204 device_type = "ethernet-phy"; 204 device_type = "ethernet-phy";
205 }; 205 };
206 sgmii_phy0: sgmii-phy@0 {
207 interrupts = <6 1 0 0>;
208 reg = <0x1d>;
209 };
210 sgmii_phy1: sgmii-phy@1 {
211 interrupts = <6 1 0 0>;
212 reg = <0x1c>;
213 };
206 tbi0: tbi-phy@11 { 214 tbi0: tbi-phy@11 {
207 reg = <0x11>; 215 reg = <0x11>;
208 device_type = "tbi-phy"; 216 device_type = "tbi-phy";
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dtsi b/arch/powerpc/boot/dts/mpc8544ds.dtsi
index 270f64b90f4e..77ebc9f1d37c 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dtsi
+++ b/arch/powerpc/boot/dts/mpc8544ds.dtsi
@@ -51,6 +51,15 @@
51 device_type = "ethernet-phy"; 51 device_type = "ethernet-phy";
52 }; 52 };
53 53
54 sgmii_phy0: sgmii-phy@0 {
55 interrupts = <6 1 0 0>;
56 reg = <0x1c>;
57 };
58 sgmii_phy1: sgmii-phy@1 {
59 interrupts = <6 1 0 0>;
60 reg = <0x1d>;
61 };
62
54 tbi0: tbi-phy@11 { 63 tbi0: tbi-phy@11 {
55 reg = <0x11>; 64 reg = <0x11>;
56 device_type = "tbi-phy"; 65 device_type = "tbi-phy";
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dtsi b/arch/powerpc/boot/dts/mpc8572ds.dtsi
index 14178944e220..357490bb84da 100644
--- a/arch/powerpc/boot/dts/mpc8572ds.dtsi
+++ b/arch/powerpc/boot/dts/mpc8572ds.dtsi
@@ -169,6 +169,23 @@
169 reg = <0x3>; 169 reg = <0x3>;
170 }; 170 };
171 171
172 sgmii_phy0: sgmii-phy@0 {
173 interrupts = <6 1 0 0>;
174 reg = <0x1c>;
175 };
176 sgmii_phy1: sgmii-phy@1 {
177 interrupts = <6 1 0 0>;
178 reg = <0x1d>;
179 };
180 sgmii_phy2: sgmii-phy@2 {
181 interrupts = <7 1 0 0>;
182 reg = <0x1e>;
183 };
184 sgmii_phy3: sgmii-phy@3 {
185 interrupts = <7 1 0 0>;
186 reg = <0x1f>;
187 };
188
172 tbi0: tbi-phy@11 { 189 tbi0: tbi-phy@11 {
173 reg = <0x11>; 190 reg = <0x11>;
174 device_type = "tbi-phy"; 191 device_type = "tbi-phy";
diff --git a/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts b/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
index d34d12712125..ef9ef56b3eeb 100644
--- a/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
@@ -67,10 +67,10 @@
67 msi@41600 { 67 msi@41600 {
68 msi-available-ranges = <0 0x80>; 68 msi-available-ranges = <0 0x80>;
69 interrupts = < 69 interrupts = <
70 0xe0 0 70 0xe0 0 0 0
71 0xe1 0 71 0xe1 0 0 0
72 0xe2 0 72 0xe2 0 0 0
73 0xe3 0>; 73 0xe3 0 0 0>;
74 }; 74 };
75 timer@42100 { 75 timer@42100 {
76 status = "disabled"; 76 status = "disabled";
diff --git a/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts b/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
index d6a8fafc0d0d..24564ee108e5 100644
--- a/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
@@ -67,9 +67,6 @@
67 ethernet@24000 { 67 ethernet@24000 {
68 status = "disabled"; 68 status = "disabled";
69 }; 69 };
70 mdio@24520 {
71 status = "disabled";
72 };
73 ptp_clock@24e00 { 70 ptp_clock@24e00 {
74 status = "disabled"; 71 status = "disabled";
75 }; 72 };
@@ -100,10 +97,10 @@
100 msi@41600 { 97 msi@41600 {
101 msi-available-ranges = <0x80 0x80>; 98 msi-available-ranges = <0x80 0x80>;
102 interrupts = < 99 interrupts = <
103 0xe4 0 100 0xe4 0 0 0
104 0xe5 0 101 0xe5 0 0 0
105 0xe6 0 102 0xe6 0 0 0
106 0xe7 0>; 103 0xe7 0 0 0>;
107 }; 104 };
108 global-utilities@e0000 { 105 global-utilities@e0000 {
109 status = "disabled"; 106 status = "disabled";
diff --git a/arch/powerpc/boot/dts/p1010rdb.dtsi b/arch/powerpc/boot/dts/p1010rdb.dtsi
index 49776143a1b8..ec7c27a64671 100644
--- a/arch/powerpc/boot/dts/p1010rdb.dtsi
+++ b/arch/powerpc/boot/dts/p1010rdb.dtsi
@@ -126,12 +126,24 @@
126 126
127&board_soc { 127&board_soc {
128 i2c@3000 { 128 i2c@3000 {
129 eeprom@50 {
130 compatible = "st,24c256";
131 reg = <0x50>;
132 };
133
129 rtc@68 { 134 rtc@68 {
130 compatible = "pericom,pt7c4338"; 135 compatible = "pericom,pt7c4338";
131 reg = <0x68>; 136 reg = <0x68>;
132 }; 137 };
133 }; 138 };
134 139
140 i2c@3100 {
141 eeprom@52 {
142 compatible = "atmel,24c01";
143 reg = <0x52>;
144 };
145 };
146
135 spi@7000 { 147 spi@7000 {
136 flash@0 { 148 flash@0 {
137 #address-cells = <1>; 149 #address-cells = <1>;
diff --git a/arch/powerpc/boot/dts/p1021rdb.dtsi b/arch/powerpc/boot/dts/p1021rdb-pc.dtsi
index b973461ab751..c13abfbbe2e2 100644
--- a/arch/powerpc/boot/dts/p1021rdb.dtsi
+++ b/arch/powerpc/boot/dts/p1021rdb-pc.dtsi
@@ -1,7 +1,7 @@
1/* 1/*
2 * P1021 RDB Device Tree Source stub (no addresses or top-level ranges) 2 * P1021 RDB Device Tree Source stub (no addresses or top-level ranges)
3 * 3 *
4 * Copyright 2011 Freescale Semiconductor Inc. 4 * Copyright 2012 Freescale Semiconductor Inc.
5 * 5 *
6 * Redistribution and use in source and binary forms, with or without 6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met: 7 * modification, are permitted provided that the following conditions are met:
diff --git a/arch/powerpc/boot/dts/p1021rdb.dts b/arch/powerpc/boot/dts/p1021rdb-pc_32b.dts
index 90b6b4caa273..7cefa12b629a 100644
--- a/arch/powerpc/boot/dts/p1021rdb.dts
+++ b/arch/powerpc/boot/dts/p1021rdb-pc_32b.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * P1021 RDB Device Tree Source 2 * P1021 RDB Device Tree Source
3 * 3 *
4 * Copyright 2011 Freescale Semiconductor Inc. 4 * Copyright 2012 Freescale Semiconductor Inc.
5 * 5 *
6 * Redistribution and use in source and binary forms, with or without 6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met: 7 * modification, are permitted provided that the following conditions are met:
@@ -92,5 +92,5 @@
92 }; 92 };
93}; 93};
94 94
95/include/ "p1021rdb.dtsi" 95/include/ "p1021rdb-pc.dtsi"
96/include/ "fsl/p1021si-post.dtsi" 96/include/ "fsl/p1021si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1021rdb_36b.dts b/arch/powerpc/boot/dts/p1021rdb-pc_36b.dts
index ea6d8b5fa10b..53d0c889039c 100644
--- a/arch/powerpc/boot/dts/p1021rdb_36b.dts
+++ b/arch/powerpc/boot/dts/p1021rdb-pc_36b.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * P1021 RDB Device Tree Source (36-bit address map) 2 * P1021 RDB Device Tree Source (36-bit address map)
3 * 3 *
4 * Copyright 2011 Freescale Semiconductor Inc. 4 * Copyright 2012 Freescale Semiconductor Inc.
5 * 5 *
6 * Redistribution and use in source and binary forms, with or without 6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met: 7 * modification, are permitted provided that the following conditions are met:
@@ -92,5 +92,5 @@
92 }; 92 };
93}; 93};
94 94
95/include/ "p1021rdb.dtsi" 95/include/ "p1021rdb-pc.dtsi"
96/include/ "fsl/p1021si-post.dtsi" 96/include/ "fsl/p1021si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1022ds.dtsi b/arch/powerpc/boot/dts/p1022ds.dtsi
index 7cdb505036bb..c3344b04d8ff 100644
--- a/arch/powerpc/boot/dts/p1022ds.dtsi
+++ b/arch/powerpc/boot/dts/p1022ds.dtsi
@@ -33,22 +33,6 @@
33 */ 33 */
34 34
35&board_lbc { 35&board_lbc {
36 /*
37 * This node is used to access the pixis via "indirect" mode,
38 * which is done by writing the pixis register index to chip
39 * select 0 and the value to/from chip select 1. Indirect
40 * mode is the only way to access the pixis when DIU video
41 * is enabled. Note that this assumes that the first column
42 * of the 'ranges' property above is the chip select number.
43 */
44 board-control@0,0 {
45 compatible = "fsl,p1022ds-indirect-pixis";
46 reg = <0x0 0x0 1 /* CS0 */
47 0x1 0x0 1>; /* CS1 */
48 interrupt-parent = <&mpic>;
49 interrupts = <8 0 0 0>;
50 };
51
52 nor@0,0 { 36 nor@0,0 {
53 #address-cells = <1>; 37 #address-cells = <1>;
54 #size-cells = <1>; 38 #size-cells = <1>;
@@ -161,6 +145,10 @@
161 * the clock is enabled. 145 * the clock is enabled.
162 */ 146 */
163 }; 147 };
148 rtc@68 {
149 compatible = "dallas,ds1339";
150 reg = <0x68>;
151 };
164 }; 152 };
165 153
166 spi@7000 { 154 spi@7000 {
diff --git a/arch/powerpc/boot/dts/p1024rdb.dtsi b/arch/powerpc/boot/dts/p1024rdb.dtsi
new file mode 100644
index 000000000000..b05dcb40f800
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1024rdb.dtsi
@@ -0,0 +1,228 @@
1/*
2 * P1024 RDB Device Tree Source stub (no addresses or top-level ranges)
3 *
4 * Copyright 2012 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
40 reg = <0x0 0x0 0x1000000>;
41 bank-width = <2>;
42 device-width = <1>;
43
44 partition@0 {
45 /* This location must not be altered */
46 /* 256KB for Vitesse 7385 Switch firmware */
47 reg = <0x0 0x00040000>;
48 label = "NOR Vitesse-7385 Firmware";
49 read-only;
50 };
51
52 partition@40000 {
53 /* 256KB for DTB Image */
54 reg = <0x00040000 0x00040000>;
55 label = "NOR DTB Image";
56 };
57
58 partition@80000 {
59 /* 3.5 MB for Linux Kernel Image */
60 reg = <0x00080000 0x00380000>;
61 label = "NOR Linux Kernel Image";
62 };
63
64 partition@400000 {
65 /* 11MB for JFFS2 based Root file System */
66 reg = <0x00400000 0x00b00000>;
67 label = "NOR JFFS2 Root File System";
68 };
69
70 partition@f00000 {
71 /* This location must not be altered */
72 /* 512KB for u-boot Bootloader Image */
73 /* 512KB for u-boot Environment Variables */
74 reg = <0x00f00000 0x00100000>;
75 label = "NOR U-Boot Image";
76 read-only;
77 };
78 };
79
80 nand@1,0 {
81 #address-cells = <1>;
82 #size-cells = <1>;
83 compatible = "fsl,p1020-fcm-nand",
84 "fsl,elbc-fcm-nand";
85 reg = <0x1 0x0 0x40000>;
86
87 partition@0 {
88 /* This location must not be altered */
89 /* 1MB for u-boot Bootloader Image */
90 reg = <0x0 0x00100000>;
91 label = "NAND U-Boot Image";
92 read-only;
93 };
94
95 partition@100000 {
96 /* 1MB for DTB Image */
97 reg = <0x00100000 0x00100000>;
98 label = "NAND DTB Image";
99 };
100
101 partition@200000 {
102 /* 4MB for Linux Kernel Image */
103 reg = <0x00200000 0x00400000>;
104 label = "NAND Linux Kernel Image";
105 };
106
107 partition@600000 {
108 /* 4MB for Compressed Root file System Image */
109 reg = <0x00600000 0x00400000>;
110 label = "NAND Compressed RFS Image";
111 };
112
113 partition@a00000 {
114 /* 15MB for JFFS2 based Root file System */
115 reg = <0x00a00000 0x00f00000>;
116 label = "NAND JFFS2 Root File System";
117 };
118
119 partition@1900000 {
120 /* 7MB for User Writable Area */
121 reg = <0x01900000 0x00700000>;
122 label = "NAND Writable User area";
123 };
124 };
125};
126
127&soc {
128 spi@7000 {
129 flash@0 {
130 #address-cells = <1>;
131 #size-cells = <1>;
132 compatible = "spansion,m25p80";
133 reg = <0>;
134 spi-max-frequency = <40000000>;
135
136 partition@0 {
137 /* 512KB for u-boot Bootloader Image */
138 reg = <0x0 0x00080000>;
139 label = "SPI U-Boot Image";
140 read-only;
141 };
142
143 partition@80000 {
144 /* 512KB for DTB Image */
145 reg = <0x00080000 0x00080000>;
146 label = "SPI DTB Image";
147 };
148
149 partition@100000 {
150 /* 4MB for Linux Kernel Image */
151 reg = <0x00100000 0x00400000>;
152 label = "SPI Linux Kernel Image";
153 };
154
155 partition@500000 {
156 /* 4MB for Compressed RFS Image */
157 reg = <0x00500000 0x00400000>;
158 label = "SPI Compressed RFS Image";
159 };
160
161 partition@900000 {
162 /* 7MB for JFFS2 based RFS */
163 reg = <0x00900000 0x00700000>;
164 label = "SPI JFFS2 RFS";
165 };
166 };
167 };
168
169 i2c@3000 {
170 rtc@68 {
171 compatible = "dallas,ds1339";
172 reg = <0x68>;
173 };
174 };
175
176 usb@22000 {
177 phy_type = "ulpi";
178 };
179
180 usb@23000 {
181 status = "disabled";
182 };
183
184 mdio@24000 {
185 phy0: ethernet-phy@0 {
186 interrupts = <3 1 0 0>;
187 reg = <0x0>;
188 };
189 phy1: ethernet-phy@1 {
190 interrupts = <2 1 0 0>;
191 reg = <0x1>;
192 };
193 phy2: ethernet-phy@2 {
194 interrupts = <1 1 0 0>;
195 reg = <0x2>;
196 };
197 };
198
199 mdio@25000 {
200 tbi0: tbi-phy@11 {
201 reg = <0x11>;
202 device_type = "tbi-phy";
203 };
204 };
205
206 mdio@26000 {
207 tbi1: tbi-phy@11 {
208 reg = <0x11>;
209 device_type = "tbi-phy";
210 };
211 };
212
213 ethernet@b0000 {
214 phy-handle = <&phy2>;
215 phy-connection-type = "rgmii-id";
216 };
217
218 ethernet@b1000 {
219 phy-handle = <&phy0>;
220 tbi-handle = <&tbi0>;
221 phy-connection-type = "sgmii";
222 };
223
224 ethernet@b2000 {
225 phy-handle = <&phy1>;
226 phy-connection-type = "rgmii-id";
227 };
228};
diff --git a/arch/powerpc/boot/dts/p1024rdb_32b.dts b/arch/powerpc/boot/dts/p1024rdb_32b.dts
new file mode 100644
index 000000000000..90e803e9ba5f
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1024rdb_32b.dts
@@ -0,0 +1,87 @@
1/*
2 * P1024 RDB 32Bit Physical Address Map Device Tree Source
3 *
4 * Copyright 2012 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/p1020si-pre.dtsi"
36/ {
37 model = "fsl,P1024RDB";
38 compatible = "fsl,P1024RDB";
39
40 memory {
41 device_type = "memory";
42 };
43
44 lbc: localbus@ffe05000 {
45 reg = <0x0 0xffe05000 0 0x1000>;
46 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
47 0x1 0x0 0x0 0xff800000 0x00040000>;
48 };
49
50 soc: soc@ffe00000 {
51 ranges = <0x0 0x0 0xffe00000 0x100000>;
52 };
53
54 pci0: pcie@ffe09000 {
55 reg = <0x0 0xffe09000 0 0x1000>;
56 ranges = <0x2000000 0x0 0xe0000000 0x0 0xa0000000 0x0 0x20000000
57 0x1000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x10000>;
58 pcie@0 {
59 ranges = <0x2000000 0x0 0xe0000000
60 0x2000000 0x0 0xe0000000
61 0x0 0x20000000
62
63 0x1000000 0x0 0x0
64 0x1000000 0x0 0x0
65 0x0 0x100000>;
66 };
67 };
68
69 pci1: pcie@ffe0a000 {
70 reg = <0x0 0xffe0a000 0 0x1000>;
71 ranges = <0x2000000 0x0 0xe0000000 0x0 0x80000000 0x0 0x20000000
72 0x1000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x10000>;
73 pcie@0 {
74 reg = <0x0 0x0 0x0 0x0 0x0>;
75 ranges = <0x2000000 0x0 0xe0000000
76 0x2000000 0x0 0xe0000000
77 0x0 0x20000000
78
79 0x1000000 0x0 0x0
80 0x1000000 0x0 0x0
81 0x0 0x100000>;
82 };
83 };
84};
85
86/include/ "p1024rdb.dtsi"
87/include/ "fsl/p1020si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1024rdb_36b.dts b/arch/powerpc/boot/dts/p1024rdb_36b.dts
new file mode 100644
index 000000000000..3656825b65a1
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1024rdb_36b.dts
@@ -0,0 +1,87 @@
1/*
2 * P1024 RDB 36Bit Physical Address Map Device Tree Source
3 *
4 * Copyright 2012 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/p1020si-pre.dtsi"
36/ {
37 model = "fsl,P1024RDB";
38 compatible = "fsl,P1024RDB";
39
40 memory {
41 device_type = "memory";
42 };
43
44 lbc: localbus@fffe05000 {
45 reg = <0xf 0xffe05000 0 0x1000>;
46 ranges = <0x0 0x0 0xf 0xef000000 0x01000000
47 0x1 0x0 0xf 0xff800000 0x00040000>;
48 };
49
50 soc: soc@fffe00000 {
51 ranges = <0x0 0xf 0xffe00000 0x100000>;
52 };
53
54 pci0: pcie@fffe09000 {
55 reg = <0xf 0xffe09000 0 0x1000>;
56 ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
57 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
58 pcie@0 {
59 ranges = <0x2000000 0x0 0xe0000000
60 0x2000000 0x0 0xe0000000
61 0x0 0x20000000
62
63 0x1000000 0x0 0x0
64 0x1000000 0x0 0x0
65 0x0 0x100000>;
66 };
67 };
68
69 pci1: pcie@fffe0a000 {
70 reg = <0xf 0xffe0a000 0 0x1000>;
71 ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
72 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
73 pcie@0 {
74 reg = <0x0 0x0 0x0 0x0 0x0>;
75 ranges = <0x2000000 0x0 0xe0000000
76 0x2000000 0x0 0xe0000000
77 0x0 0x20000000
78
79 0x1000000 0x0 0x0
80 0x1000000 0x0 0x0
81 0x0 0x100000>;
82 };
83 };
84};
85
86/include/ "p1024rdb.dtsi"
87/include/ "fsl/p1020si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1025rdb.dtsi b/arch/powerpc/boot/dts/p1025rdb.dtsi
index cf3676fc714b..f50256482297 100644
--- a/arch/powerpc/boot/dts/p1025rdb.dtsi
+++ b/arch/powerpc/boot/dts/p1025rdb.dtsi
@@ -282,5 +282,45 @@
282 0x1 0x4 0x2 0x0 0x2 0x0 /* ENET5_RX_DV_SER5_CTS_B */ 282 0x1 0x4 0x2 0x0 0x2 0x0 /* ENET5_RX_DV_SER5_CTS_B */
283 0x1 0x8 0x2 0x0 0x2 0x0>; /* ENET5_RX_ER_SER5_CD_B */ 283 0x1 0x8 0x2 0x0 0x2 0x0>; /* ENET5_RX_ER_SER5_CD_B */
284 }; 284 };
285
286 pio3: ucc_pin@03 {
287 pio-map = <
288 /* port pin dir open_drain assignment has_irq */
289 0x0 0x16 0x2 0x0 0x2 0x0 /* SER7_CD_B*/
290 0x0 0x12 0x2 0x0 0x2 0x0 /* SER7_CTS_B*/
291 0x0 0x13 0x1 0x0 0x2 0x0 /* SER7_RTS_B*/
292 0x0 0x14 0x2 0x0 0x2 0x0 /* SER7_RXD0*/
293 0x0 0x15 0x1 0x0 0x2 0x0>; /* SER7_TXD0*/
294 };
295
296 pio4: ucc_pin@04 {
297 pio-map = <
298 /* port pin dir open_drain assignment has_irq */
299 0x1 0x0 0x2 0x0 0x2 0x0 /* SER3_CD_B*/
300 0x0 0x1c 0x2 0x0 0x2 0x0 /* SER3_CTS_B*/
301 0x0 0x1d 0x1 0x0 0x2 0x0 /* SER3_RTS_B*/
302 0x0 0x1e 0x2 0x0 0x2 0x0 /* SER3_RXD0*/
303 0x0 0x1f 0x1 0x0 0x2 0x0>; /* SER3_TXD0*/
304 };
305 };
306};
307
308&qe {
309 serial2: ucc@2600 {
310 device_type = "serial";
311 compatible = "ucc_uart";
312 port-number = <0>;
313 rx-clock-name = "brg6";
314 tx-clock-name = "brg6";
315 pio-handle = <&pio3>;
316 };
317
318 serial3: ucc@2200 {
319 device_type = "serial";
320 compatible = "ucc_uart";
321 port-number = <1>;
322 rx-clock-name = "brg2";
323 tx-clock-name = "brg2";
324 pio-handle = <&pio4>;
285 }; 325 };
286}; 326};
diff --git a/arch/powerpc/boot/dts/p2020ds.dtsi b/arch/powerpc/boot/dts/p2020ds.dtsi
index d3b939c573b0..e699cf95b063 100644
--- a/arch/powerpc/boot/dts/p2020ds.dtsi
+++ b/arch/powerpc/boot/dts/p2020ds.dtsi
@@ -150,6 +150,16 @@
150 interrupts = <3 1 0 0>; 150 interrupts = <3 1 0 0>;
151 reg = <0x2>; 151 reg = <0x2>;
152 }; 152 };
153
154 sgmii_phy1: sgmii-phy@1 {
155 interrupts = <5 1 0 0>;
156 reg = <0x1c>;
157 };
158 sgmii_phy2: sgmii-phy@2 {
159 interrupts = <5 1 0 0>;
160 reg = <0x1d>;
161 };
162
153 tbi0: tbi-phy@11 { 163 tbi0: tbi-phy@11 {
154 reg = <0x11>; 164 reg = <0x11>;
155 device_type = "tbi-phy"; 165 device_type = "tbi-phy";
diff --git a/arch/powerpc/boot/dts/p2020rdb.dts b/arch/powerpc/boot/dts/p2020rdb.dts
index 153bc76bb48e..4d52bce1d5b0 100644
--- a/arch/powerpc/boot/dts/p2020rdb.dts
+++ b/arch/powerpc/boot/dts/p2020rdb.dts
@@ -34,7 +34,7 @@
34 34
35 /* NOR and NAND Flashes */ 35 /* NOR and NAND Flashes */
36 ranges = <0x0 0x0 0x0 0xef000000 0x01000000 36 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
37 0x1 0x0 0x0 0xff800000 0x00040000 37 0x1 0x0 0x0 0xffa00000 0x00040000
38 0x2 0x0 0x0 0xffb00000 0x00020000>; 38 0x2 0x0 0x0 0xffb00000 0x00020000>;
39 39
40 nor@0,0 { 40 nor@0,0 {
diff --git a/arch/powerpc/boot/dts/p2041rdb.dts b/arch/powerpc/boot/dts/p2041rdb.dts
index 285213976a7f..baab0347dab0 100644
--- a/arch/powerpc/boot/dts/p2041rdb.dts
+++ b/arch/powerpc/boot/dts/p2041rdb.dts
@@ -121,7 +121,8 @@
121 121
122 lbc: localbus@ffe124000 { 122 lbc: localbus@ffe124000 {
123 reg = <0xf 0xfe124000 0 0x1000>; 123 reg = <0xf 0xfe124000 0 0x1000>;
124 ranges = <0 0 0xf 0xe8000000 0x08000000>; 124 ranges = <0 0 0xf 0xe8000000 0x08000000
125 1 0 0xf 0xffa00000 0x00040000>;
125 126
126 flash@0,0 { 127 flash@0,0 {
127 compatible = "cfi-flash"; 128 compatible = "cfi-flash";
@@ -129,6 +130,44 @@
129 bank-width = <2>; 130 bank-width = <2>;
130 device-width = <2>; 131 device-width = <2>;
131 }; 132 };
133
134 nand@1,0 {
135 #address-cells = <1>;
136 #size-cells = <1>;
137 compatible = "fsl,elbc-fcm-nand";
138 reg = <0x1 0x0 0x40000>;
139
140 partition@0 {
141 label = "NAND U-Boot Image";
142 reg = <0x0 0x02000000>;
143 read-only;
144 };
145
146 partition@2000000 {
147 label = "NAND Root File System";
148 reg = <0x02000000 0x10000000>;
149 };
150
151 partition@12000000 {
152 label = "NAND Compressed RFS Image";
153 reg = <0x12000000 0x08000000>;
154 };
155
156 partition@1a000000 {
157 label = "NAND Linux Kernel Image";
158 reg = <0x1a000000 0x04000000>;
159 };
160
161 partition@1e000000 {
162 label = "NAND DTB Image";
163 reg = <0x1e000000 0x01000000>;
164 };
165
166 partition@1f000000 {
167 label = "NAND Writable User area";
168 reg = <0x1f000000 0x01000000>;
169 };
170 };
132 }; 171 };
133 172
134 pci0: pcie@ffe200000 { 173 pci0: pcie@ffe200000 {
diff --git a/arch/powerpc/boot/dts/p3060qds.dts b/arch/powerpc/boot/dts/p3060qds.dts
deleted file mode 100644
index 9ae875c8a211..000000000000
--- a/arch/powerpc/boot/dts/p3060qds.dts
+++ /dev/null
@@ -1,242 +0,0 @@
1/*
2 * P3060QDS Device Tree Source
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/p3060si-pre.dtsi"
36
37/ {
38 model = "fsl,P3060QDS";
39 compatible = "fsl,P3060QDS";
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
43
44 memory {
45 device_type = "memory";
46 };
47
48 dcsr: dcsr@f00000000 {
49 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
50 };
51
52 soc: soc@ffe000000 {
53 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
54 reg = <0xf 0xfe000000 0 0x00001000>;
55 spi@110000 {
56 flash@0 {
57 #address-cells = <1>;
58 #size-cells = <1>;
59 compatible = "spansion,s25sl12801";
60 reg = <0>;
61 spi-max-frequency = <40000000>; /* input clock */
62 partition@u-boot {
63 label = "u-boot";
64 reg = <0x00000000 0x00100000>;
65 read-only;
66 };
67 partition@kernel {
68 label = "kernel";
69 reg = <0x00100000 0x00500000>;
70 read-only;
71 };
72 partition@dtb {
73 label = "dtb";
74 reg = <0x00600000 0x00100000>;
75 read-only;
76 };
77 partition@fs {
78 label = "file system";
79 reg = <0x00700000 0x00900000>;
80 };
81 };
82 flash@1 {
83 #address-cells = <1>;
84 #size-cells = <1>;
85 compatible = "spansion,en25q32b";
86 reg = <1>;
87 spi-max-frequency = <40000000>; /* input clock */
88 partition@spi1 {
89 label = "spi1";
90 reg = <0x00000000 0x00400000>;
91 };
92 };
93 flash@2 {
94 #address-cells = <1>;
95 #size-cells = <1>;
96 compatible = "atmel,at45db081d";
97 reg = <2>;
98 spi-max-frequency = <40000000>; /* input clock */
99 partition@spi1 {
100 label = "spi2";
101 reg = <0x00000000 0x00100000>;
102 };
103 };
104 flash@3 {
105 #address-cells = <1>;
106 #size-cells = <1>;
107 compatible = "spansion,sst25wf040";
108 reg = <3>;
109 spi-max-frequency = <40000000>; /* input clock */
110 partition@spi3 {
111 label = "spi3";
112 reg = <0x00000000 0x00080000>;
113 };
114 };
115 };
116
117 i2c@118000 {
118 eeprom@51 {
119 compatible = "at24,24c256";
120 reg = <0x51>;
121 };
122 eeprom@53 {
123 compatible = "at24,24c256";
124 reg = <0x53>;
125 };
126 rtc@68 {
127 compatible = "dallas,ds3232";
128 reg = <0x68>;
129 interrupts = <0x1 0x1 0 0>;
130 };
131 };
132
133 usb0: usb@210000 {
134 phy_type = "ulpi";
135 };
136
137 usb1: usb@211000 {
138 dr_mode = "host";
139 phy_type = "ulpi";
140 };
141 };
142
143 rio: rapidio@ffe0c0000 {
144 reg = <0xf 0xfe0c0000 0 0x11000>;
145
146 port1 {
147 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
148 };
149 port2 {
150 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
151 };
152 };
153
154 lbc: localbus@ffe124000 {
155 reg = <0xf 0xfe124000 0 0x1000>;
156 ranges = <0 0 0xf 0xe8000000 0x08000000
157 2 0 0xf 0xffa00000 0x00040000
158 3 0 0xf 0xffdf0000 0x00008000>;
159
160 flash@0,0 {
161 compatible = "cfi-flash";
162 reg = <0 0 0x08000000>;
163 bank-width = <2>;
164 device-width = <2>;
165 };
166
167 nand@2,0 {
168 #address-cells = <1>;
169 #size-cells = <1>;
170 compatible = "fsl,elbc-fcm-nand";
171 reg = <0x2 0x0 0x40000>;
172
173 partition@0 {
174 label = "NAND U-Boot Image";
175 reg = <0x0 0x02000000>;
176 read-only;
177 };
178
179 partition@2000000 {
180 label = "NAND Root File System";
181 reg = <0x02000000 0x10000000>;
182 };
183
184 partition@12000000 {
185 label = "NAND Compressed RFS Image";
186 reg = <0x12000000 0x08000000>;
187 };
188
189 partition@1a000000 {
190 label = "NAND Linux Kernel Image";
191 reg = <0x1a000000 0x04000000>;
192 };
193
194 partition@1e000000 {
195 label = "NAND DTB Image";
196 reg = <0x1e000000 0x01000000>;
197 };
198
199 partition@1f000000 {
200 label = "NAND Writable User area";
201 reg = <0x1f000000 0x21000000>;
202 };
203 };
204
205 board-control@3,0 {
206 compatible = "fsl,p3060qds-fpga", "fsl,fpga-qixis";
207 reg = <3 0 0x100>;
208 };
209 };
210
211 pci0: pcie@ffe200000 {
212 reg = <0xf 0xfe200000 0 0x1000>;
213 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
214 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
215 pcie@0 {
216 ranges = <0x02000000 0 0xe0000000
217 0x02000000 0 0xe0000000
218 0 0x20000000
219
220 0x01000000 0 0x00000000
221 0x01000000 0 0x00000000
222 0 0x00010000>;
223 };
224 };
225
226 pci1: pcie@ffe201000 {
227 reg = <0xf 0xfe201000 0 0x1000>;
228 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
229 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
230 pcie@0 {
231 ranges = <0x02000000 0 0xe0000000
232 0x02000000 0 0xe0000000
233 0 0x20000000
234
235 0x01000000 0 0x00000000
236 0x01000000 0 0x00000000
237 0 0x00010000>;
238 };
239 };
240};
241
242/include/ "fsl/p3060si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/sbc8560.dts b/arch/powerpc/boot/dts/sbc8560.dts
deleted file mode 100644
index 72078eb15616..000000000000
--- a/arch/powerpc/boot/dts/sbc8560.dts
+++ /dev/null
@@ -1,406 +0,0 @@
1/*
2 * SBC8560 Device Tree Source
3 *
4 * Copyright 2007 Wind River Systems Inc.
5 *
6 * Paul Gortmaker (see MAINTAINERS for contact information)
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14/dts-v1/;
15
16/ {
17 model = "SBC8560";
18 compatible = "SBC8560";
19 #address-cells = <1>;
20 #size-cells = <1>;
21
22 aliases {
23 ethernet0 = &enet0;
24 ethernet1 = &enet1;
25 ethernet2 = &enet2;
26 ethernet3 = &enet3;
27 serial0 = &serial0;
28 serial1 = &serial1;
29 pci0 = &pci0;
30 };
31
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 PowerPC,8560@0 {
37 device_type = "cpu";
38 reg = <0>;
39 d-cache-line-size = <0x20>; // 32 bytes
40 i-cache-line-size = <0x20>; // 32 bytes
41 d-cache-size = <0x8000>; // L1, 32K
42 i-cache-size = <0x8000>; // L1, 32K
43 timebase-frequency = <0>; // From uboot
44 bus-frequency = <0>;
45 clock-frequency = <0>;
46 next-level-cache = <&L2>;
47 };
48 };
49
50 memory {
51 device_type = "memory";
52 reg = <0x00000000 0x20000000>;
53 };
54
55 soc@ff700000 {
56 #address-cells = <1>;
57 #size-cells = <1>;
58 device_type = "soc";
59 ranges = <0x0 0xff700000 0x00100000>;
60 clock-frequency = <0>;
61
62 ecm-law@0 {
63 compatible = "fsl,ecm-law";
64 reg = <0x0 0x1000>;
65 fsl,num-laws = <8>;
66 };
67
68 ecm@1000 {
69 compatible = "fsl,mpc8560-ecm", "fsl,ecm";
70 reg = <0x1000 0x1000>;
71 interrupts = <17 2>;
72 interrupt-parent = <&mpic>;
73 };
74
75 memory-controller@2000 {
76 compatible = "fsl,mpc8560-memory-controller";
77 reg = <0x2000 0x1000>;
78 interrupt-parent = <&mpic>;
79 interrupts = <0x12 0x2>;
80 };
81
82 L2: l2-cache-controller@20000 {
83 compatible = "fsl,mpc8560-l2-cache-controller";
84 reg = <0x20000 0x1000>;
85 cache-line-size = <0x20>; // 32 bytes
86 cache-size = <0x40000>; // L2, 256K
87 interrupt-parent = <&mpic>;
88 interrupts = <0x10 0x2>;
89 };
90
91 i2c@3000 {
92 #address-cells = <1>;
93 #size-cells = <0>;
94 cell-index = <0>;
95 compatible = "fsl-i2c";
96 reg = <0x3000 0x100>;
97 interrupts = <0x2b 0x2>;
98 interrupt-parent = <&mpic>;
99 dfsrr;
100 };
101
102 i2c@3100 {
103 #address-cells = <1>;
104 #size-cells = <0>;
105 cell-index = <1>;
106 compatible = "fsl-i2c";
107 reg = <0x3100 0x100>;
108 interrupts = <0x2b 0x2>;
109 interrupt-parent = <&mpic>;
110 dfsrr;
111 };
112
113 dma@21300 {
114 #address-cells = <1>;
115 #size-cells = <1>;
116 compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma";
117 reg = <0x21300 0x4>;
118 ranges = <0x0 0x21100 0x200>;
119 cell-index = <0>;
120 dma-channel@0 {
121 compatible = "fsl,mpc8560-dma-channel",
122 "fsl,eloplus-dma-channel";
123 reg = <0x0 0x80>;
124 cell-index = <0>;
125 interrupt-parent = <&mpic>;
126 interrupts = <20 2>;
127 };
128 dma-channel@80 {
129 compatible = "fsl,mpc8560-dma-channel",
130 "fsl,eloplus-dma-channel";
131 reg = <0x80 0x80>;
132 cell-index = <1>;
133 interrupt-parent = <&mpic>;
134 interrupts = <21 2>;
135 };
136 dma-channel@100 {
137 compatible = "fsl,mpc8560-dma-channel",
138 "fsl,eloplus-dma-channel";
139 reg = <0x100 0x80>;
140 cell-index = <2>;
141 interrupt-parent = <&mpic>;
142 interrupts = <22 2>;
143 };
144 dma-channel@180 {
145 compatible = "fsl,mpc8560-dma-channel",
146 "fsl,eloplus-dma-channel";
147 reg = <0x180 0x80>;
148 cell-index = <3>;
149 interrupt-parent = <&mpic>;
150 interrupts = <23 2>;
151 };
152 };
153
154 enet0: ethernet@24000 {
155 #address-cells = <1>;
156 #size-cells = <1>;
157 cell-index = <0>;
158 device_type = "network";
159 model = "TSEC";
160 compatible = "gianfar";
161 reg = <0x24000 0x1000>;
162 ranges = <0x0 0x24000 0x1000>;
163 local-mac-address = [ 00 00 00 00 00 00 ];
164 interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
165 interrupt-parent = <&mpic>;
166 tbi-handle = <&tbi0>;
167 phy-handle = <&phy0>;
168
169 mdio@520 {
170 #address-cells = <1>;
171 #size-cells = <0>;
172 compatible = "fsl,gianfar-mdio";
173 reg = <0x520 0x20>;
174 phy0: ethernet-phy@19 {
175 interrupt-parent = <&mpic>;
176 interrupts = <0x6 0x1>;
177 reg = <0x19>;
178 device_type = "ethernet-phy";
179 };
180 phy1: ethernet-phy@1a {
181 interrupt-parent = <&mpic>;
182 interrupts = <0x7 0x1>;
183 reg = <0x1a>;
184 device_type = "ethernet-phy";
185 };
186 phy2: ethernet-phy@1b {
187 interrupt-parent = <&mpic>;
188 interrupts = <0x8 0x1>;
189 reg = <0x1b>;
190 device_type = "ethernet-phy";
191 };
192 phy3: ethernet-phy@1c {
193 interrupt-parent = <&mpic>;
194 interrupts = <0x8 0x1>;
195 reg = <0x1c>;
196 device_type = "ethernet-phy";
197 };
198 tbi0: tbi-phy@11 {
199 reg = <0x11>;
200 device_type = "tbi-phy";
201 };
202 };
203 };
204
205 enet1: ethernet@25000 {
206 #address-cells = <1>;
207 #size-cells = <1>;
208 cell-index = <1>;
209 device_type = "network";
210 model = "TSEC";
211 compatible = "gianfar";
212 reg = <0x25000 0x1000>;
213 ranges = <0x0 0x25000 0x1000>;
214 local-mac-address = [ 00 00 00 00 00 00 ];
215 interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
216 interrupt-parent = <&mpic>;
217 tbi-handle = <&tbi1>;
218 phy-handle = <&phy1>;
219
220 mdio@520 {
221 #address-cells = <1>;
222 #size-cells = <0>;
223 compatible = "fsl,gianfar-tbi";
224 reg = <0x520 0x20>;
225
226 tbi1: tbi-phy@11 {
227 reg = <0x11>;
228 device_type = "tbi-phy";
229 };
230 };
231 };
232
233 mpic: pic@40000 {
234 interrupt-controller;
235 #address-cells = <0>;
236 #interrupt-cells = <2>;
237 compatible = "chrp,open-pic";
238 reg = <0x40000 0x40000>;
239 device_type = "open-pic";
240 };
241
242 cpm@919c0 {
243 #address-cells = <1>;
244 #size-cells = <1>;
245 compatible = "fsl,mpc8560-cpm", "fsl,cpm2";
246 reg = <0x919c0 0x30>;
247 ranges;
248
249 muram@80000 {
250 #address-cells = <1>;
251 #size-cells = <1>;
252 ranges = <0x0 0x80000 0x10000>;
253
254 data@0 {
255 compatible = "fsl,cpm-muram-data";
256 reg = <0x0 0x4000 0x9000 0x2000>;
257 };
258 };
259
260 brg@919f0 {
261 compatible = "fsl,mpc8560-brg",
262 "fsl,cpm2-brg",
263 "fsl,cpm-brg";
264 reg = <0x919f0 0x10 0x915f0 0x10>;
265 clock-frequency = <165000000>;
266 };
267
268 cpmpic: pic@90c00 {
269 interrupt-controller;
270 #address-cells = <0>;
271 #interrupt-cells = <2>;
272 interrupts = <0x2e 0x2>;
273 interrupt-parent = <&mpic>;
274 reg = <0x90c00 0x80>;
275 compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
276 };
277
278 enet2: ethernet@91320 {
279 device_type = "network";
280 compatible = "fsl,mpc8560-fcc-enet",
281 "fsl,cpm2-fcc-enet";
282 reg = <0x91320 0x20 0x88500 0x100 0x913b0 0x1>;
283 local-mac-address = [ 00 00 00 00 00 00 ];
284 fsl,cpm-command = <0x16200300>;
285 interrupts = <0x21 0x8>;
286 interrupt-parent = <&cpmpic>;
287 phy-handle = <&phy2>;
288 };
289
290 enet3: ethernet@91340 {
291 device_type = "network";
292 compatible = "fsl,mpc8560-fcc-enet",
293 "fsl,cpm2-fcc-enet";
294 reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>;
295 local-mac-address = [ 00 00 00 00 00 00 ];
296 fsl,cpm-command = <0x1a400300>;
297 interrupts = <0x22 0x8>;
298 interrupt-parent = <&cpmpic>;
299 phy-handle = <&phy3>;
300 };
301 };
302
303 global-utilities@e0000 {
304 compatible = "fsl,mpc8560-guts";
305 reg = <0xe0000 0x1000>;
306 };
307 };
308
309 pci0: pci@ff708000 {
310 #interrupt-cells = <1>;
311 #size-cells = <2>;
312 #address-cells = <3>;
313 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
314 device_type = "pci";
315 reg = <0xff708000 0x1000>;
316 clock-frequency = <66666666>;
317 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
318 interrupt-map = <
319
320 /* IDSEL 0x02 */
321 0x1000 0x0 0x0 0x1 &mpic 0x2 0x1
322 0x1000 0x0 0x0 0x2 &mpic 0x3 0x1
323 0x1000 0x0 0x0 0x3 &mpic 0x4 0x1
324 0x1000 0x0 0x0 0x4 &mpic 0x5 0x1>;
325
326 interrupt-parent = <&mpic>;
327 interrupts = <0x18 0x2>;
328 bus-range = <0x0 0x0>;
329 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
330 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
331 };
332
333 localbus@ff705000 {
334 compatible = "fsl,mpc8560-localbus", "simple-bus";
335 #address-cells = <2>;
336 #size-cells = <1>;
337 reg = <0xff705000 0x100>; // BRx, ORx, etc.
338
339 ranges = <
340 0x0 0x0 0xff800000 0x0800000 // 8MB boot flash
341 0x1 0x0 0xe4000000 0x4000000 // 64MB flash
342 0x3 0x0 0x20000000 0x4000000 // 64MB SDRAM
343 0x4 0x0 0x24000000 0x4000000 // 64MB SDRAM
344 0x5 0x0 0xfc000000 0x0c00000 // EPLD
345 0x6 0x0 0xe0000000 0x4000000 // 64MB flash
346 0x7 0x0 0x80000000 0x0200000 // ATM1,2
347 >;
348
349 epld@5,0 {
350 compatible = "wrs,epld-localbus";
351 #address-cells = <2>;
352 #size-cells = <1>;
353 reg = <0x5 0x0 0xc00000>;
354 ranges = <
355 0x0 0x0 0x5 0x000000 0x1fff // LED disp.
356 0x1 0x0 0x5 0x100000 0x1fff // switches
357 0x2 0x0 0x5 0x200000 0x1fff // ID reg.
358 0x3 0x0 0x5 0x300000 0x1fff // status reg.
359 0x4 0x0 0x5 0x400000 0x1fff // reset reg.
360 0x5 0x0 0x5 0x500000 0x1fff // Wind port
361 0x7 0x0 0x5 0x700000 0x1fff // UART #1
362 0x8 0x0 0x5 0x800000 0x1fff // UART #2
363 0x9 0x0 0x5 0x900000 0x1fff // RTC
364 0xb 0x0 0x5 0xb00000 0x1fff // EEPROM
365 >;
366
367 bidr@2,0 {
368 compatible = "wrs,sbc8560-bidr";
369 reg = <0x2 0x0 0x10>;
370 };
371
372 bcsr@3,0 {
373 compatible = "wrs,sbc8560-bcsr";
374 reg = <0x3 0x0 0x10>;
375 };
376
377 brstcr@4,0 {
378 compatible = "wrs,sbc8560-brstcr";
379 reg = <0x4 0x0 0x10>;
380 };
381
382 serial0: serial@7,0 {
383 device_type = "serial";
384 compatible = "ns16550";
385 reg = <0x7 0x0 0x100>;
386 clock-frequency = <1843200>;
387 interrupts = <0x9 0x2>;
388 interrupt-parent = <&mpic>;
389 };
390
391 serial1: serial@8,0 {
392 device_type = "serial";
393 compatible = "ns16550";
394 reg = <0x8 0x0 0x100>;
395 clock-frequency = <1843200>;
396 interrupts = <0xa 0x2>;
397 interrupt-parent = <&mpic>;
398 };
399
400 rtc@9,0 {
401 compatible = "m48t59";
402 reg = <0x9 0x0 0x1fff>;
403 };
404 };
405 };
406};
diff --git a/arch/powerpc/configs/83xx/kmeter1_defconfig b/arch/powerpc/configs/83xx/kmeter1_defconfig
index 07e1bbadebfe..a0dfef1fcdb7 100644
--- a/arch/powerpc/configs/83xx/kmeter1_defconfig
+++ b/arch/powerpc/configs/83xx/kmeter1_defconfig
@@ -2,14 +2,14 @@ CONFIG_EXPERIMENTAL=y
2# CONFIG_SWAP is not set 2# CONFIG_SWAP is not set
3CONFIG_SYSVIPC=y 3CONFIG_SYSVIPC=y
4CONFIG_POSIX_MQUEUE=y 4CONFIG_POSIX_MQUEUE=y
5CONFIG_SPARSE_IRQ=y
6CONFIG_LOG_BUF_SHIFT=14 5CONFIG_LOG_BUF_SHIFT=14
7CONFIG_EXPERT=y 6CONFIG_EXPERT=y
8# CONFIG_HOTPLUG is not set
9CONFIG_SLAB=y 7CONFIG_SLAB=y
10CONFIG_MODULES=y 8CONFIG_MODULES=y
11CONFIG_MODULE_UNLOAD=y 9CONFIG_MODULE_UNLOAD=y
12# CONFIG_BLK_DEV_BSG is not set 10# CONFIG_BLK_DEV_BSG is not set
11CONFIG_PARTITION_ADVANCED=y
12# CONFIG_MSDOS_PARTITION is not set
13# CONFIG_IOSCHED_DEADLINE is not set 13# CONFIG_IOSCHED_DEADLINE is not set
14# CONFIG_IOSCHED_CFQ is not set 14# CONFIG_IOSCHED_CFQ is not set
15# CONFIG_PPC_CHRP is not set 15# CONFIG_PPC_CHRP is not set
@@ -31,11 +31,10 @@ CONFIG_IP_PNP=y
31# CONFIG_INET_XFRM_MODE_BEET is not set 31# CONFIG_INET_XFRM_MODE_BEET is not set
32# CONFIG_INET_LRO is not set 32# CONFIG_INET_LRO is not set
33# CONFIG_IPV6 is not set 33# CONFIG_IPV6 is not set
34CONFIG_TIPC=y
34CONFIG_BRIDGE=m 35CONFIG_BRIDGE=m
35CONFIG_VLAN_8021Q=y 36CONFIG_VLAN_8021Q=y
36CONFIG_MTD=y 37CONFIG_MTD=y
37CONFIG_MTD_CONCAT=y
38CONFIG_MTD_PARTITIONS=y
39CONFIG_MTD_CMDLINE_PARTS=y 38CONFIG_MTD_CMDLINE_PARTS=y
40CONFIG_MTD_CHAR=y 39CONFIG_MTD_CHAR=y
41CONFIG_MTD_BLOCK=y 40CONFIG_MTD_BLOCK=y
@@ -50,17 +49,15 @@ CONFIG_MTD_UBI_DEBUG=y
50CONFIG_PROC_DEVICETREE=y 49CONFIG_PROC_DEVICETREE=y
51CONFIG_NETDEVICES=y 50CONFIG_NETDEVICES=y
52CONFIG_DUMMY=y 51CONFIG_DUMMY=y
53CONFIG_TUN=y
54CONFIG_MII=y 52CONFIG_MII=y
55CONFIG_MARVELL_PHY=y 53CONFIG_TUN=y
56CONFIG_NET_ETHERNET=y
57CONFIG_UCC_GETH=y 54CONFIG_UCC_GETH=y
58# CONFIG_NETDEV_10000 is not set 55CONFIG_MARVELL_PHY=y
59CONFIG_WAN=y
60CONFIG_HDLC=y
61CONFIG_PPP=y 56CONFIG_PPP=y
62CONFIG_PPP_MULTILINK=y 57CONFIG_PPP_MULTILINK=y
63CONFIG_PPPOE=y 58CONFIG_PPPOE=y
59CONFIG_WAN=y
60CONFIG_HDLC=y
64# CONFIG_INPUT is not set 61# CONFIG_INPUT is not set
65# CONFIG_SERIO is not set 62# CONFIG_SERIO is not set
66# CONFIG_VT is not set 63# CONFIG_VT is not set
@@ -77,10 +74,7 @@ CONFIG_UIO=y
77# CONFIG_DNOTIFY is not set 74# CONFIG_DNOTIFY is not set
78CONFIG_TMPFS=y 75CONFIG_TMPFS=y
79CONFIG_JFFS2_FS=y 76CONFIG_JFFS2_FS=y
77CONFIG_UBIFS_FS=y
80CONFIG_NFS_FS=y 78CONFIG_NFS_FS=y
81CONFIG_NFS_V3=y 79CONFIG_NFS_V3=y
82CONFIG_ROOT_NFS=y 80CONFIG_ROOT_NFS=y
83CONFIG_PARTITION_ADVANCED=y
84# CONFIG_MSDOS_PARTITION is not set
85# CONFIG_RCU_CPU_STALL_DETECTOR is not set
86CONFIG_SYSCTL_SYSCALL_CHECK=y
diff --git a/arch/powerpc/configs/85xx/sbc8560_defconfig b/arch/powerpc/configs/85xx/sbc8560_defconfig
deleted file mode 100644
index f7fdb0318e4c..000000000000
--- a/arch/powerpc/configs/85xx/sbc8560_defconfig
+++ /dev/null
@@ -1,65 +0,0 @@
1CONFIG_PPC_85xx=y
2CONFIG_EXPERIMENTAL=y
3CONFIG_SYSVIPC=y
4CONFIG_LOG_BUF_SHIFT=14
5CONFIG_BLK_DEV_INITRD=y
6# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
7CONFIG_EXPERT=y
8CONFIG_SLAB=y
9# CONFIG_BLK_DEV_BSG is not set
10CONFIG_SBC8560=y
11CONFIG_BINFMT_MISC=y
12CONFIG_SPARSE_IRQ=y
13# CONFIG_SECCOMP is not set
14CONFIG_NET=y
15CONFIG_PACKET=y
16CONFIG_UNIX=y
17CONFIG_XFRM_USER=y
18CONFIG_INET=y
19CONFIG_IP_MULTICAST=y
20CONFIG_IP_PNP=y
21CONFIG_IP_PNP_DHCP=y
22CONFIG_IP_PNP_BOOTP=y
23CONFIG_SYN_COOKIES=y
24# CONFIG_INET_LRO is not set
25# CONFIG_IPV6 is not set
26CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
27# CONFIG_FW_LOADER is not set
28CONFIG_PROC_DEVICETREE=y
29CONFIG_BLK_DEV_LOOP=y
30CONFIG_BLK_DEV_RAM=y
31CONFIG_BLK_DEV_RAM_SIZE=32768
32CONFIG_NETDEVICES=y
33CONFIG_BROADCOM_PHY=y
34CONFIG_NET_ETHERNET=y
35CONFIG_MII=y
36CONFIG_GIANFAR=y
37# CONFIG_INPUT_MOUSEDEV is not set
38# CONFIG_INPUT_KEYBOARD is not set
39# CONFIG_INPUT_MOUSE is not set
40# CONFIG_SERIO is not set
41# CONFIG_VT is not set
42CONFIG_SERIAL_8250=y
43CONFIG_SERIAL_8250_CONSOLE=y
44CONFIG_SERIAL_8250_NR_UARTS=2
45CONFIG_SERIAL_8250_RUNTIME_UARTS=2
46# CONFIG_HW_RANDOM is not set
47CONFIG_VIDEO_OUTPUT_CONTROL=y
48CONFIG_RTC_CLASS=y
49CONFIG_RTC_DRV_M48T59=y
50CONFIG_INOTIFY=y
51CONFIG_PROC_KCORE=y
52CONFIG_TMPFS=y
53CONFIG_NFS_FS=y
54CONFIG_ROOT_NFS=y
55CONFIG_PARTITION_ADVANCED=y
56# CONFIG_MSDOS_PARTITION is not set
57CONFIG_MAGIC_SYSRQ=y
58CONFIG_DEBUG_KERNEL=y
59CONFIG_DETECT_HUNG_TASK=y
60CONFIG_DEBUG_MUTEXES=y
61# CONFIG_DEBUG_BUGVERBOSE is not set
62# CONFIG_RCU_CPU_STALL_DETECTOR is not set
63CONFIG_SYSCTL_SYSCALL_CHECK=y
64CONFIG_PPC_EARLY_DEBUG=y
65# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/powerpc/configs/corenet32_smp_defconfig b/arch/powerpc/configs/corenet32_smp_defconfig
index 91db656294e8..cbb98c1234fd 100644
--- a/arch/powerpc/configs/corenet32_smp_defconfig
+++ b/arch/powerpc/configs/corenet32_smp_defconfig
@@ -23,7 +23,6 @@ CONFIG_MODVERSIONS=y
23# CONFIG_BLK_DEV_BSG is not set 23# CONFIG_BLK_DEV_BSG is not set
24CONFIG_P2041_RDB=y 24CONFIG_P2041_RDB=y
25CONFIG_P3041_DS=y 25CONFIG_P3041_DS=y
26CONFIG_P3060_QDS=y
27CONFIG_P4080_DS=y 26CONFIG_P4080_DS=y
28CONFIG_P5020_DS=y 27CONFIG_P5020_DS=y
29CONFIG_HIGHMEM=y 28CONFIG_HIGHMEM=y
@@ -32,10 +31,12 @@ CONFIG_HIGH_RES_TIMERS=y
32# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set 31# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
33CONFIG_BINFMT_MISC=m 32CONFIG_BINFMT_MISC=m
34CONFIG_KEXEC=y 33CONFIG_KEXEC=y
34CONFIG_IRQ_ALL_CPUS=y
35CONFIG_FORCE_MAX_ZONEORDER=13 35CONFIG_FORCE_MAX_ZONEORDER=13
36CONFIG_FSL_LBC=y 36CONFIG_FSL_LBC=y
37CONFIG_PCI=y 37CONFIG_PCI=y
38CONFIG_PCIEPORTBUS=y 38CONFIG_PCIEPORTBUS=y
39CONFIG_PCI_MSI=y
39# CONFIG_PCIEASPM is not set 40# CONFIG_PCIEASPM is not set
40CONFIG_RAPIDIO=y 41CONFIG_RAPIDIO=y
41CONFIG_FSL_RIO=y 42CONFIG_FSL_RIO=y
@@ -76,6 +77,11 @@ CONFIG_MTD_BLOCK=y
76CONFIG_MTD_CFI=y 77CONFIG_MTD_CFI=y
77CONFIG_MTD_CFI_AMDSTD=y 78CONFIG_MTD_CFI_AMDSTD=y
78CONFIG_MTD_PHYSMAP_OF=y 79CONFIG_MTD_PHYSMAP_OF=y
80CONFIG_MTD_NAND=y
81CONFIG_MTD_NAND_ECC=y
82CONFIG_MTD_NAND_IDS=y
83CONFIG_MTD_NAND_FSL_IFC=y
84CONFIG_MTD_NAND_FSL_ELBC=y
79CONFIG_MTD_M25P80=y 85CONFIG_MTD_M25P80=y
80CONFIG_PROC_DEVICETREE=y 86CONFIG_PROC_DEVICETREE=y
81CONFIG_BLK_DEV_LOOP=y 87CONFIG_BLK_DEV_LOOP=y
@@ -136,6 +142,8 @@ CONFIG_USB_OHCI_HCD_PPC_OF_LE=y
136CONFIG_USB_STORAGE=y 142CONFIG_USB_STORAGE=y
137CONFIG_MMC=y 143CONFIG_MMC=y
138CONFIG_MMC_SDHCI=y 144CONFIG_MMC_SDHCI=y
145CONFIG_MMC_SDHCI_OF=y
146CONFIG_MMC_SDHCI_OF_ESDHC=y
139CONFIG_EDAC=y 147CONFIG_EDAC=y
140CONFIG_EDAC_MM_EDAC=y 148CONFIG_EDAC_MM_EDAC=y
141CONFIG_EDAC_MPC85XX=y 149CONFIG_EDAC_MPC85XX=y
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig
index 6798343580f0..dd89de8b0b7f 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -6,7 +6,9 @@ CONFIG_NR_CPUS=2
6CONFIG_EXPERIMENTAL=y 6CONFIG_EXPERIMENTAL=y
7CONFIG_SYSVIPC=y 7CONFIG_SYSVIPC=y
8CONFIG_BSD_PROCESS_ACCT=y 8CONFIG_BSD_PROCESS_ACCT=y
9CONFIG_SPARSE_IRQ=y 9CONFIG_IRQ_DOMAIN_DEBUG=y
10CONFIG_NO_HZ=y
11CONFIG_HIGH_RES_TIMERS=y
10CONFIG_IKCONFIG=y 12CONFIG_IKCONFIG=y
11CONFIG_IKCONFIG_PROC=y 13CONFIG_IKCONFIG_PROC=y
12CONFIG_LOG_BUF_SHIFT=14 14CONFIG_LOG_BUF_SHIFT=14
@@ -18,11 +20,14 @@ CONFIG_MODULE_UNLOAD=y
18CONFIG_MODULE_FORCE_UNLOAD=y 20CONFIG_MODULE_FORCE_UNLOAD=y
19CONFIG_MODVERSIONS=y 21CONFIG_MODVERSIONS=y
20# CONFIG_BLK_DEV_BSG is not set 22# CONFIG_BLK_DEV_BSG is not set
23CONFIG_PARTITION_ADVANCED=y
24CONFIG_MAC_PARTITION=y
21CONFIG_P5020_DS=y 25CONFIG_P5020_DS=y
22# CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set 26# CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set
23CONFIG_NO_HZ=y
24CONFIG_HIGH_RES_TIMERS=y
25CONFIG_BINFMT_MISC=m 27CONFIG_BINFMT_MISC=m
28CONFIG_IRQ_ALL_CPUS=y
29CONFIG_PCIEPORTBUS=y
30CONFIG_PCI_MSI=y
26CONFIG_RAPIDIO=y 31CONFIG_RAPIDIO=y
27CONFIG_FSL_RIO=y 32CONFIG_FSL_RIO=y
28CONFIG_NET=y 33CONFIG_NET=y
@@ -51,12 +56,25 @@ CONFIG_INET_ESP=y
51CONFIG_IPV6=y 56CONFIG_IPV6=y
52CONFIG_IP_SCTP=m 57CONFIG_IP_SCTP=m
53CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 58CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
59CONFIG_MTD=y
60CONFIG_MTD_CMDLINE_PARTS=y
61CONFIG_MTD_CHAR=y
62CONFIG_MTD_BLOCK=y
63CONFIG_MTD_CFI=y
64CONFIG_MTD_CFI_AMDSTD=y
65CONFIG_MTD_PHYSMAP_OF=y
66CONFIG_MTD_M25P80=y
67CONFIG_MTD_NAND=y
68CONFIG_MTD_NAND_FSL_ELBC=y
69CONFIG_MTD_NAND_FSL_IFC=y
54CONFIG_PROC_DEVICETREE=y 70CONFIG_PROC_DEVICETREE=y
55CONFIG_BLK_DEV_LOOP=y 71CONFIG_BLK_DEV_LOOP=y
56CONFIG_BLK_DEV_RAM=y 72CONFIG_BLK_DEV_RAM=y
57CONFIG_BLK_DEV_RAM_SIZE=131072 73CONFIG_BLK_DEV_RAM_SIZE=131072
58CONFIG_MISC_DEVICES=y
59CONFIG_EEPROM_LEGACY=y 74CONFIG_EEPROM_LEGACY=y
75CONFIG_ATA=y
76CONFIG_SATA_FSL=y
77CONFIG_SATA_SIL24=y
60CONFIG_NETDEVICES=y 78CONFIG_NETDEVICES=y
61CONFIG_DUMMY=y 79CONFIG_DUMMY=y
62CONFIG_INPUT_FF_MEMLESS=m 80CONFIG_INPUT_FF_MEMLESS=m
@@ -66,39 +84,59 @@ CONFIG_INPUT_FF_MEMLESS=m
66CONFIG_SERIO_LIBPS2=y 84CONFIG_SERIO_LIBPS2=y
67CONFIG_SERIAL_8250=y 85CONFIG_SERIAL_8250=y
68CONFIG_SERIAL_8250_CONSOLE=y 86CONFIG_SERIAL_8250_CONSOLE=y
69CONFIG_SERIAL_8250_EXTENDED=y
70CONFIG_SERIAL_8250_MANY_PORTS=y 87CONFIG_SERIAL_8250_MANY_PORTS=y
71CONFIG_SERIAL_8250_DETECT_IRQ=y 88CONFIG_SERIAL_8250_DETECT_IRQ=y
72CONFIG_SERIAL_8250_RSA=y 89CONFIG_SERIAL_8250_RSA=y
73CONFIG_I2C=y 90CONFIG_I2C=y
74CONFIG_I2C_CHARDEV=y 91CONFIG_I2C_CHARDEV=y
75CONFIG_I2C_MPC=y 92CONFIG_I2C_MPC=y
93CONFIG_SPI=y
94CONFIG_SPI_GPIO=y
95CONFIG_SPI_FSL_SPI=y
96CONFIG_SPI_FSL_ESPI=y
76# CONFIG_HWMON is not set 97# CONFIG_HWMON is not set
77CONFIG_VIDEO_OUTPUT_CONTROL=y 98CONFIG_VIDEO_OUTPUT_CONTROL=y
78# CONFIG_HID_SUPPORT is not set 99CONFIG_USB_HID=m
79# CONFIG_USB_SUPPORT is not set 100CONFIG_USB=y
101CONFIG_USB_MON=y
102CONFIG_USB_EHCI_HCD=y
103CONFIG_USB_EHCI_FSL=y
104CONFIG_USB_STORAGE=y
105CONFIG_MMC=y
106CONFIG_MMC_SDHCI=y
107CONFIG_EDAC=y
108CONFIG_EDAC_MM_EDAC=y
80CONFIG_DMADEVICES=y 109CONFIG_DMADEVICES=y
81CONFIG_FSL_DMA=y 110CONFIG_FSL_DMA=y
82CONFIG_EXT2_FS=y 111CONFIG_EXT2_FS=y
83CONFIG_EXT3_FS=y 112CONFIG_EXT3_FS=y
84# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set 113CONFIG_ISO9660_FS=m
114CONFIG_JOLIET=y
115CONFIG_ZISOFS=y
116CONFIG_UDF_FS=m
117CONFIG_MSDOS_FS=m
118CONFIG_VFAT_FS=y
119CONFIG_NTFS_FS=y
85CONFIG_PROC_KCORE=y 120CONFIG_PROC_KCORE=y
86CONFIG_TMPFS=y 121CONFIG_TMPFS=y
87CONFIG_HUGETLBFS=y 122CONFIG_HUGETLBFS=y
88# CONFIG_MISC_FILESYSTEMS is not set 123# CONFIG_MISC_FILESYSTEMS is not set
89CONFIG_PARTITION_ADVANCED=y 124CONFIG_NFS_FS=y
90CONFIG_MAC_PARTITION=y 125CONFIG_NFS_V4=y
91CONFIG_NLS=y 126CONFIG_ROOT_NFS=y
127CONFIG_NFSD=m
128CONFIG_NLS_ISO8859_1=y
92CONFIG_NLS_UTF8=m 129CONFIG_NLS_UTF8=m
93CONFIG_CRC_T10DIF=y 130CONFIG_CRC_T10DIF=y
94CONFIG_CRC_ITU_T=m
95CONFIG_FRAME_WARN=1024 131CONFIG_FRAME_WARN=1024
132CONFIG_MAGIC_SYSRQ=y
96CONFIG_DEBUG_FS=y 133CONFIG_DEBUG_FS=y
134CONFIG_DEBUG_SHIRQ=y
97CONFIG_DETECT_HUNG_TASK=y 135CONFIG_DETECT_HUNG_TASK=y
98CONFIG_DEBUG_INFO=y 136CONFIG_DEBUG_INFO=y
99CONFIG_SYSCTL_SYSCALL_CHECK=y 137CONFIG_CRYPTO_NULL=y
100CONFIG_IRQ_DOMAIN_DEBUG=y
101CONFIG_CRYPTO_PCBC=m 138CONFIG_CRYPTO_PCBC=m
139CONFIG_CRYPTO_MD4=y
102CONFIG_CRYPTO_SHA256=y 140CONFIG_CRYPTO_SHA256=y
103CONFIG_CRYPTO_SHA512=y 141CONFIG_CRYPTO_SHA512=y
104CONFIG_CRYPTO_AES=y 142CONFIG_CRYPTO_AES=y
diff --git a/arch/powerpc/configs/mgcoge_defconfig b/arch/powerpc/configs/mgcoge_defconfig
index 0d36b0e1e268..8fa84f156ef3 100644
--- a/arch/powerpc/configs/mgcoge_defconfig
+++ b/arch/powerpc/configs/mgcoge_defconfig
@@ -2,7 +2,6 @@ CONFIG_EXPERIMENTAL=y
2# CONFIG_SWAP is not set 2# CONFIG_SWAP is not set
3CONFIG_SYSVIPC=y 3CONFIG_SYSVIPC=y
4CONFIG_POSIX_MQUEUE=y 4CONFIG_POSIX_MQUEUE=y
5CONFIG_SPARSE_IRQ=y
6CONFIG_IKCONFIG=y 5CONFIG_IKCONFIG=y
7CONFIG_IKCONFIG_PROC=y 6CONFIG_IKCONFIG_PROC=y
8CONFIG_LOG_BUF_SHIFT=14 7CONFIG_LOG_BUF_SHIFT=14
@@ -12,6 +11,7 @@ CONFIG_KALLSYMS_ALL=y
12# CONFIG_PCSPKR_PLATFORM is not set 11# CONFIG_PCSPKR_PLATFORM is not set
13CONFIG_EMBEDDED=y 12CONFIG_EMBEDDED=y
14CONFIG_SLAB=y 13CONFIG_SLAB=y
14CONFIG_PARTITION_ADVANCED=y
15# CONFIG_IOSCHED_CFQ is not set 15# CONFIG_IOSCHED_CFQ is not set
16# CONFIG_PPC_PMAC is not set 16# CONFIG_PPC_PMAC is not set
17CONFIG_PPC_82xx=y 17CONFIG_PPC_82xx=y
@@ -49,12 +49,9 @@ CONFIG_PROC_DEVICETREE=y
49CONFIG_BLK_DEV_LOOP=y 49CONFIG_BLK_DEV_LOOP=y
50CONFIG_BLK_DEV_RAM=y 50CONFIG_BLK_DEV_RAM=y
51CONFIG_NETDEVICES=y 51CONFIG_NETDEVICES=y
52CONFIG_FIXED_PHY=y
53CONFIG_NET_ETHERNET=y
54CONFIG_FS_ENET=y 52CONFIG_FS_ENET=y
55CONFIG_FS_ENET_MDIO_FCC=y 53CONFIG_FS_ENET_MDIO_FCC=y
56# CONFIG_NETDEV_1000 is not set 54CONFIG_FIXED_PHY=y
57# CONFIG_NETDEV_10000 is not set
58# CONFIG_WLAN is not set 55# CONFIG_WLAN is not set
59# CONFIG_INPUT is not set 56# CONFIG_INPUT is not set
60# CONFIG_SERIO is not set 57# CONFIG_SERIO is not set
@@ -64,6 +61,8 @@ CONFIG_SERIAL_CPM_CONSOLE=y
64CONFIG_I2C=y 61CONFIG_I2C=y
65CONFIG_I2C_CHARDEV=y 62CONFIG_I2C_CHARDEV=y
66CONFIG_I2C_CPM=y 63CONFIG_I2C_CPM=y
64CONFIG_SPI=y
65CONFIG_SPI_FSL_SPI=y
67# CONFIG_HWMON is not set 66# CONFIG_HWMON is not set
68CONFIG_USB_GADGET=y 67CONFIG_USB_GADGET=y
69CONFIG_USB_FSL_USB2=y 68CONFIG_USB_FSL_USB2=y
@@ -80,8 +79,6 @@ CONFIG_SQUASHFS=y
80CONFIG_NFS_FS=y 79CONFIG_NFS_FS=y
81CONFIG_NFS_V3=y 80CONFIG_NFS_V3=y
82CONFIG_ROOT_NFS=y 81CONFIG_ROOT_NFS=y
83CONFIG_PARTITION_ADVANCED=y
84CONFIG_NLS=y
85CONFIG_NLS_CODEPAGE_437=y 82CONFIG_NLS_CODEPAGE_437=y
86CONFIG_NLS_ASCII=y 83CONFIG_NLS_ASCII=y
87CONFIG_NLS_ISO8859_1=y 84CONFIG_NLS_ISO8859_1=y
@@ -90,7 +87,6 @@ CONFIG_MAGIC_SYSRQ=y
90CONFIG_DEBUG_FS=y 87CONFIG_DEBUG_FS=y
91# CONFIG_SCHED_DEBUG is not set 88# CONFIG_SCHED_DEBUG is not set
92CONFIG_DEBUG_INFO=y 89CONFIG_DEBUG_INFO=y
93CONFIG_SYSCTL_SYSCALL_CHECK=y
94CONFIG_BDI_SWITCH=y 90CONFIG_BDI_SWITCH=y
95CONFIG_CRYPTO_ECB=y 91CONFIG_CRYPTO_ECB=y
96CONFIG_CRYPTO_PCBC=y 92CONFIG_CRYPTO_PCBC=y
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index 62bb723c5b54..03ee911c4577 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -74,6 +74,30 @@ CONFIG_INET_ESP=y
74CONFIG_IPV6=y 74CONFIG_IPV6=y
75CONFIG_IP_SCTP=m 75CONFIG_IP_SCTP=m
76CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 76CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
77CONFIG_MTD=y
78CONFIG_MTD_CMDLINE_PARTS=y
79CONFIG_MTD_CHAR=y
80CONFIG_MTD_BLOCK=y
81CONFIG_MTD_CFI=y
82CONFIG_FTL=y
83CONFIG_MTD_GEN_PROBE=y
84CONFIG_MTD_MAP_BANK_WIDTH_1=y
85CONFIG_MTD_MAP_BANK_WIDTH_2=y
86CONFIG_MTD_MAP_BANK_WIDTH_4=y
87CONFIG_MTD_CFI_I1=y
88CONFIG_MTD_CFI_I2=y
89CONFIG_MTD_CFI_INTELEXT=y
90CONFIG_MTD_CFI_AMDSTD=y
91CONFIG_MTD_CFI_UTIL=y
92CONFIG_MTD_PHYSMAP_OF=y
93CONFIG_MTD_PARTITIONS=y
94CONFIG_MTD_OF_PARTS=y
95CONFIG_MTD_NAND=y
96CONFIG_MTD_NAND_FSL_ELBC=y
97CONFIG_MTD_NAND_FSL_IFC=y
98CONFIG_MTD_NAND_IDS=y
99CONFIG_MTD_NAND_ECC=y
100CONFIG_MTD_M25P80=y
77CONFIG_PROC_DEVICETREE=y 101CONFIG_PROC_DEVICETREE=y
78CONFIG_BLK_DEV_LOOP=y 102CONFIG_BLK_DEV_LOOP=y
79CONFIG_BLK_DEV_NBD=y 103CONFIG_BLK_DEV_NBD=y
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig
index d1828427ae55..fdfa84dc908f 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -46,6 +46,7 @@ CONFIG_NO_HZ=y
46CONFIG_HIGH_RES_TIMERS=y 46CONFIG_HIGH_RES_TIMERS=y
47CONFIG_BINFMT_MISC=m 47CONFIG_BINFMT_MISC=m
48CONFIG_MATH_EMULATION=y 48CONFIG_MATH_EMULATION=y
49CONFIG_IRQ_ALL_CPUS=y
49CONFIG_FORCE_MAX_ZONEORDER=12 50CONFIG_FORCE_MAX_ZONEORDER=12
50CONFIG_PCI=y 51CONFIG_PCI=y
51CONFIG_PCI_MSI=y 52CONFIG_PCI_MSI=y
@@ -76,6 +77,30 @@ CONFIG_INET_ESP=y
76CONFIG_IPV6=y 77CONFIG_IPV6=y
77CONFIG_IP_SCTP=m 78CONFIG_IP_SCTP=m
78CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 79CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
80CONFIG_MTD=y
81CONFIG_MTD_CMDLINE_PARTS=y
82CONFIG_MTD_CHAR=y
83CONFIG_MTD_BLOCK=y
84CONFIG_MTD_CFI=y
85CONFIG_FTL=y
86CONFIG_MTD_GEN_PROBE=y
87CONFIG_MTD_MAP_BANK_WIDTH_1=y
88CONFIG_MTD_MAP_BANK_WIDTH_2=y
89CONFIG_MTD_MAP_BANK_WIDTH_4=y
90CONFIG_MTD_CFI_I1=y
91CONFIG_MTD_CFI_I2=y
92CONFIG_MTD_CFI_INTELEXT=y
93CONFIG_MTD_CFI_AMDSTD=y
94CONFIG_MTD_CFI_UTIL=y
95CONFIG_MTD_PHYSMAP_OF=y
96CONFIG_MTD_PARTITIONS=y
97CONFIG_MTD_OF_PARTS=y
98CONFIG_MTD_NAND=y
99CONFIG_MTD_NAND_FSL_ELBC=y
100CONFIG_MTD_NAND_FSL_IFC=y
101CONFIG_MTD_NAND_IDS=y
102CONFIG_MTD_NAND_ECC=y
103CONFIG_MTD_M25P80=y
79CONFIG_PROC_DEVICETREE=y 104CONFIG_PROC_DEVICETREE=y
80CONFIG_BLK_DEV_LOOP=y 105CONFIG_BLK_DEV_LOOP=y
81CONFIG_BLK_DEV_NBD=y 106CONFIG_BLK_DEV_NBD=y
diff --git a/arch/powerpc/include/asm/immap_qe.h b/arch/powerpc/include/asm/immap_qe.h
index 0edb6842b13d..61e8490786b8 100644
--- a/arch/powerpc/include/asm/immap_qe.h
+++ b/arch/powerpc/include/asm/immap_qe.h
@@ -26,7 +26,9 @@
26struct qe_iram { 26struct qe_iram {
27 __be32 iadd; /* I-RAM Address Register */ 27 __be32 iadd; /* I-RAM Address Register */
28 __be32 idata; /* I-RAM Data Register */ 28 __be32 idata; /* I-RAM Data Register */
29 u8 res0[0x78]; 29 u8 res0[0x04];
30 __be32 iready; /* I-RAM Ready Register */
31 u8 res1[0x70];
30} __attribute__ ((packed)); 32} __attribute__ ((packed));
31 33
32/* QE Interrupt Controller */ 34/* QE Interrupt Controller */
diff --git a/arch/powerpc/include/asm/qe.h b/arch/powerpc/include/asm/qe.h
index 5e0b6d511e14..229571a49391 100644
--- a/arch/powerpc/include/asm/qe.h
+++ b/arch/powerpc/include/asm/qe.h
@@ -499,6 +499,7 @@ enum comm_dir {
499/* I-RAM */ 499/* I-RAM */
500#define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */ 500#define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */
501#define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */ 501#define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */
502#define QE_IRAM_READY 0x80000000 /* Ready */
502 503
503/* UPC */ 504/* UPC */
504#define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */ 505#define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index 7e7bd88674db..0f59863c3ade 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -556,8 +556,10 @@ END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
556 /* SPE Unavailable */ 556 /* SPE Unavailable */
557 START_EXCEPTION(SPEUnavailable) 557 START_EXCEPTION(SPEUnavailable)
558 NORMAL_EXCEPTION_PROLOG(SPE_UNAVAIL) 558 NORMAL_EXCEPTION_PROLOG(SPE_UNAVAIL)
559 bne load_up_spe 559 beq 1f
560 addi r3,r1,STACK_FRAME_OVERHEAD 560 bl load_up_spe
561 b fast_exception_return
5621: addi r3,r1,STACK_FRAME_OVERHEAD
561 EXC_XFER_EE_LITE(0x2010, KernelSPE) 563 EXC_XFER_EE_LITE(0x2010, KernelSPE)
562#else 564#else
563 EXCEPTION(0x2020, SPE_UNAVAIL, SPEUnavailable, \ 565 EXCEPTION(0x2020, SPE_UNAVAIL, SPEUnavailable, \
@@ -778,7 +780,7 @@ tlb_write_entry:
778/* Note that the SPE support is closely modeled after the AltiVec 780/* Note that the SPE support is closely modeled after the AltiVec
779 * support. Changes to one are likely to be applicable to the 781 * support. Changes to one are likely to be applicable to the
780 * other! */ 782 * other! */
781load_up_spe: 783_GLOBAL(load_up_spe)
782/* 784/*
783 * Disable SPE for the task which had SPE previously, 785 * Disable SPE for the task which had SPE previously,
784 * and save its SPE registers in its thread_struct. 786 * and save its SPE registers in its thread_struct.
@@ -826,20 +828,7 @@ load_up_spe:
826 subi r4,r5,THREAD 828 subi r4,r5,THREAD
827 stw r4,last_task_used_spe@l(r3) 829 stw r4,last_task_used_spe@l(r3)
828#endif /* !CONFIG_SMP */ 830#endif /* !CONFIG_SMP */
829 /* restore registers and return */ 831 blr
8302: REST_4GPRS(3, r11)
831 lwz r10,_CCR(r11)
832 REST_GPR(1, r11)
833 mtcr r10
834 lwz r10,_LINK(r11)
835 mtlr r10
836 REST_GPR(10, r11)
837 mtspr SPRN_SRR1,r9
838 mtspr SPRN_SRR0,r12
839 REST_GPR(9, r11)
840 REST_GPR(12, r11)
841 lwz r11,GPR11(r11)
842 rfi
843 832
844/* 833/*
845 * SPE unavailable trap from kernel - print a message, but let 834 * SPE unavailable trap from kernel - print a message, but let
diff --git a/arch/powerpc/kernel/setup-common.c b/arch/powerpc/kernel/setup-common.c
index afd4f051f3f2..bdc499c17872 100644
--- a/arch/powerpc/kernel/setup-common.c
+++ b/arch/powerpc/kernel/setup-common.c
@@ -720,6 +720,33 @@ static int powerpc_debugfs_init(void)
720arch_initcall(powerpc_debugfs_init); 720arch_initcall(powerpc_debugfs_init);
721#endif 721#endif
722 722
723#ifdef CONFIG_BOOKE_WDT
724extern u32 booke_wdt_enabled;
725extern u32 booke_wdt_period;
726
727/* Checks wdt=x and wdt_period=xx command-line option */
728notrace int __init early_parse_wdt(char *p)
729{
730 if (p && strncmp(p, "0", 1) != 0)
731 booke_wdt_enabled = 1;
732
733 return 0;
734}
735early_param("wdt", early_parse_wdt);
736
737int __init early_parse_wdt_period(char *p)
738{
739 unsigned long ret;
740 if (p) {
741 if (!kstrtol(p, 0, &ret))
742 booke_wdt_period = ret;
743 }
744
745 return 0;
746}
747early_param("wdt_period", early_parse_wdt_period);
748#endif /* CONFIG_BOOKE_WDT */
749
723void ppc_printk_progress(char *s, unsigned short hex) 750void ppc_printk_progress(char *s, unsigned short hex)
724{ 751{
725 pr_info("%s\n", s); 752 pr_info("%s\n", s);
diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c
index ec8a53fa9e8f..a8f54ecb091f 100644
--- a/arch/powerpc/kernel/setup_32.c
+++ b/arch/powerpc/kernel/setup_32.c
@@ -149,30 +149,6 @@ notrace void __init machine_init(u64 dt_ptr)
149 ppc_md.progress("id mach(): done", 0x200); 149 ppc_md.progress("id mach(): done", 0x200);
150} 150}
151 151
152#ifdef CONFIG_BOOKE_WDT
153extern u32 booke_wdt_enabled;
154extern u32 booke_wdt_period;
155
156/* Checks wdt=x and wdt_period=xx command-line option */
157notrace int __init early_parse_wdt(char *p)
158{
159 if (p && strncmp(p, "0", 1) != 0)
160 booke_wdt_enabled = 1;
161
162 return 0;
163}
164early_param("wdt", early_parse_wdt);
165
166int __init early_parse_wdt_period (char *p)
167{
168 if (p)
169 booke_wdt_period = simple_strtoul(p, NULL, 0);
170
171 return 0;
172}
173early_param("wdt_period", early_parse_wdt_period);
174#endif /* CONFIG_BOOKE_WDT */
175
176/* Checks "l2cr=xxxx" command-line option */ 152/* Checks "l2cr=xxxx" command-line option */
177int __init ppc_setup_l2cr(char *str) 153int __init ppc_setup_l2cr(char *str)
178{ 154{
diff --git a/arch/powerpc/platforms/82xx/km82xx.c b/arch/powerpc/platforms/82xx/km82xx.c
index 3661bcdc326a..cf964e19573a 100644
--- a/arch/powerpc/platforms/82xx/km82xx.c
+++ b/arch/powerpc/platforms/82xx/km82xx.c
@@ -128,6 +128,11 @@ static __initdata struct cpm_pin km82xx_pins[] = {
128 {3, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, /* TXP */ 128 {3, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, /* TXP */
129 {3, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, /* TXN */ 129 {3, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, /* TXN */
130 {3, 25, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* RXD */ 130 {3, 25, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* RXD */
131
132 /* SPI */
133 {3, 16, CPM_PIN_INPUT | CPM_PIN_SECONDARY},/* SPI_MISO PD16 */
134 {3, 17, CPM_PIN_INPUT | CPM_PIN_SECONDARY},/* SPI_MOSI PD17 */
135 {3, 18, CPM_PIN_INPUT | CPM_PIN_SECONDARY},/* SPI_CLK PD18 */
131}; 136};
132 137
133static void __init init_ioports(void) 138static void __init init_ioports(void)
diff --git a/arch/powerpc/platforms/83xx/km83xx.c b/arch/powerpc/platforms/83xx/km83xx.c
index a266ba876863..89923d723349 100644
--- a/arch/powerpc/platforms/83xx/km83xx.c
+++ b/arch/powerpc/platforms/83xx/km83xx.c
@@ -3,7 +3,7 @@
3 * Author: Heiko Schocher <hs@denx.de> 3 * Author: Heiko Schocher <hs@denx.de>
4 * 4 *
5 * Description: 5 * Description:
6 * Keymile KMETER1 board specific routines. 6 * Keymile 83xx platform specific routines.
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify it 8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the 9 * under the terms of the GNU General Public License as published by the
@@ -70,54 +70,88 @@ static void __init mpc83xx_km_setup_arch(void)
70 for_each_node_by_name(np, "spi") 70 for_each_node_by_name(np, "spi")
71 par_io_of_config(np); 71 par_io_of_config(np);
72 72
73 for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;) 73 for_each_node_by_name(np, "ucc")
74 par_io_of_config(np); 74 par_io_of_config(np);
75 } 75 }
76 76
77 np = of_find_compatible_node(NULL, "network", "ucc_geth"); 77 np = of_find_compatible_node(NULL, "network", "ucc_geth");
78 if (np != NULL) { 78 if (np != NULL) {
79 uint svid; 79 /*
80 * handle mpc8360E Erratum QE_ENET10:
81 * RGMII AC values do not meet the specification
82 */
83 uint svid = mfspr(SPRN_SVR);
84 struct device_node *np_par;
85 struct resource res;
86 void __iomem *base;
87 int ret;
88
89 np_par = of_find_node_by_name(NULL, "par_io");
90 if (np_par == NULL) {
91 printk(KERN_WARNING "%s couldn;t find par_io node\n",
92 __func__);
93 return;
94 }
95 /* Map Parallel I/O ports registers */
96 ret = of_address_to_resource(np_par, 0, &res);
97 if (ret) {
98 printk(KERN_WARNING "%s couldn;t map par_io registers\n",
99 __func__);
100 return;
101 }
102
103 base = ioremap(res.start, res.end - res.start + 1);
104
105 /*
106 * set output delay adjustments to default values according
107 * table 5 in Errata Rev. 5, 9/2011:
108 *
109 * write 0b01 to UCC1 bits 18:19
110 * write 0b01 to UCC2 option 1 bits 4:5
111 * write 0b01 to UCC2 option 2 bits 16:17
112 */
113 clrsetbits_be32((base + 0xa8), 0x0c00f000, 0x04005000);
114
115 /*
116 * set output delay adjustments to default values according
117 * table 3-13 in Reference Manual Rev.3 05/2010:
118 *
119 * write 0b01 to UCC2 option 2 bits 16:17
120 * write 0b0101 to UCC1 bits 20:23
121 * write 0b0101 to UCC2 option 1 bits 24:27
122 */
123 clrsetbits_be32((base + 0xac), 0x0000cff0, 0x00004550);
80 124
81 /* handle mpc8360ea rev.2.1 erratum 2: RGMII Timing */
82 svid = mfspr(SPRN_SVR);
83 if (SVR_REV(svid) == 0x0021) { 125 if (SVR_REV(svid) == 0x0021) {
84 struct device_node *np_par; 126 /*
85 struct resource res; 127 * UCC2 option 1: write 0b1010 to bits 24:27
86 void __iomem *base; 128 * at address IMMRBAR+0x14AC
87 int ret; 129 */
88 130 clrsetbits_be32((base + 0xac), 0x000000f0, 0x000000a0);
89 np_par = of_find_node_by_name(NULL, "par_io"); 131 } else if (SVR_REV(svid) == 0x0020) {
90 if (np_par == NULL) { 132 /*
91 printk(KERN_WARNING "%s couldn;t find par_io node\n", 133 * UCC1: write 0b11 to bits 18:19
92 __func__); 134 * at address IMMRBAR+0x14A8
93 return; 135 */
94 } 136 setbits32((base + 0xa8), 0x00003000);
95 /* Map Parallel I/O ports registers */
96 ret = of_address_to_resource(np_par, 0, &res);
97 if (ret) {
98 printk(KERN_WARNING "%s couldn;t map par_io registers\n",
99 __func__);
100 return;
101 }
102 base = ioremap(res.start, resource_size(&res));
103 137
104 /* 138 /*
105 * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2) 139 * UCC2 option 1: write 0b11 to bits 4:5
106 * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1) 140 * at address IMMRBAR+0x14A8
107 */ 141 */
108 setbits32((base + 0xa8), 0x0c003000); 142 setbits32((base + 0xa8), 0x0c000000);
109 143
110 /* 144 /*
111 * IMMR + 0x14AC[20:27] = 10101010 145 * UCC2 option 2: write 0b11 to bits 16:17
112 * (data delay for both UCC's) 146 * at address IMMRBAR+0x14AC
113 */ 147 */
114 clrsetbits_be32((base + 0xac), 0xff0, 0xaa0); 148 setbits32((base + 0xac), 0x0000c000);
115 iounmap(base);
116 of_node_put(np_par);
117 } 149 }
150 iounmap(base);
151 of_node_put(np_par);
118 of_node_put(np); 152 of_node_put(np);
119 } 153 }
120#endif /* CONFIG_QUICC_ENGINE */ 154#endif /* CONFIG_QUICC_ENGINE */
121} 155}
122 156
123machine_device_initcall(mpc83xx_km, mpc83xx_declare_of_platform_devices); 157machine_device_initcall(mpc83xx_km, mpc83xx_declare_of_platform_devices);
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index f000d81c4e31..159c01e91463 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -23,6 +23,15 @@ config FSL_85XX_CACHE_SRAM
23 cache-sram-size and cache-sram-offset kernel boot 23 cache-sram-size and cache-sram-offset kernel boot
24 parameters should be passed when this option is enabled. 24 parameters should be passed when this option is enabled.
25 25
26config BSC9131_RDB
27 bool "Freescale BSC9131RDB"
28 select DEFAULT_UIMAGE
29 help
30 This option enables support for the Freescale BSC9131RDB board.
31 The BSC9131 is a heterogeneous SoC containing an e500v2 powerpc and a
32 StarCore SC3850 DSP
33 Manufacturer : Freescale Semiconductor, Inc
34
26config MPC8540_ADS 35config MPC8540_ADS
27 bool "Freescale MPC8540 ADS" 36 bool "Freescale MPC8540 ADS"
28 select DEFAULT_UIMAGE 37 select DEFAULT_UIMAGE
@@ -175,12 +184,6 @@ config SBC8548
175 help 184 help
176 This option enables support for the Wind River SBC8548 board 185 This option enables support for the Wind River SBC8548 board
177 186
178config SBC8560
179 bool "Wind River SBC8560"
180 select DEFAULT_UIMAGE
181 help
182 This option enables support for the Wind River SBC8560 board
183
184config GE_IMP3A 187config GE_IMP3A
185 bool "GE Intelligent Platforms IMP3A" 188 bool "GE Intelligent Platforms IMP3A"
186 select DEFAULT_UIMAGE 189 select DEFAULT_UIMAGE
@@ -222,18 +225,6 @@ config P3041_DS
222 help 225 help
223 This option enables support for the P3041 DS board 226 This option enables support for the P3041 DS board
224 227
225config P3060_QDS
226 bool "Freescale P3060 QDS"
227 select DEFAULT_UIMAGE
228 select PPC_E500MC
229 select PHYS_64BIT
230 select SWIOTLB
231 select GPIO_MPC8XXX
232 select HAS_RAPIDIO
233 select PPC_EPAPR_HV_PIC
234 help
235 This option enables support for the P3060 QDS board
236
237config P4080_DS 228config P4080_DS
238 bool "Freescale P4080 DS" 229 bool "Freescale P4080 DS"
239 select DEFAULT_UIMAGE 230 select DEFAULT_UIMAGE
@@ -263,6 +254,22 @@ config P5020_DS
263 help 254 help
264 This option enables support for the P5020 DS board 255 This option enables support for the P5020 DS board
265 256
257config PPC_QEMU_E500
258 bool "QEMU generic e500 platform"
259 depends on EXPERIMENTAL
260 select DEFAULT_UIMAGE
261 help
262 This option enables support for running as a QEMU guest using
263 QEMU's generic e500 machine. This is not required if you're
264 using a QEMU machine that targets a specific board, such as
265 mpc8544ds.
266
267 Unlike most e500 boards that target a specific CPU, this
268 platform works with any e500-family CPU that QEMU supports.
269 Thus, you'll need to make sure CONFIG_PPC_E500MC is set or
270 unset based on the emulated CPU (or actual host CPU in the case
271 of KVM).
272
266endif # FSL_SOC_BOOKE 273endif # FSL_SOC_BOOKE
267 274
268config TQM85xx 275config TQM85xx
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 2125d4ca068a..3dfe81175036 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -5,6 +5,7 @@ obj-$(CONFIG_SMP) += smp.o
5 5
6obj-y += common.o 6obj-y += common.o
7 7
8obj-$(CONFIG_BSC9131_RDB) += bsc913x_rdb.o
8obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o 9obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o
9obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o 10obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o
10obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o 11obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o
@@ -17,14 +18,13 @@ obj-$(CONFIG_P1022_DS) += p1022_ds.o
17obj-$(CONFIG_P1023_RDS) += p1023_rds.o 18obj-$(CONFIG_P1023_RDS) += p1023_rds.o
18obj-$(CONFIG_P2041_RDB) += p2041_rdb.o corenet_ds.o 19obj-$(CONFIG_P2041_RDB) += p2041_rdb.o corenet_ds.o
19obj-$(CONFIG_P3041_DS) += p3041_ds.o corenet_ds.o 20obj-$(CONFIG_P3041_DS) += p3041_ds.o corenet_ds.o
20obj-$(CONFIG_P3060_QDS) += p3060_qds.o corenet_ds.o
21obj-$(CONFIG_P4080_DS) += p4080_ds.o corenet_ds.o 21obj-$(CONFIG_P4080_DS) += p4080_ds.o corenet_ds.o
22obj-$(CONFIG_P5020_DS) += p5020_ds.o corenet_ds.o 22obj-$(CONFIG_P5020_DS) += p5020_ds.o corenet_ds.o
23obj-$(CONFIG_STX_GP3) += stx_gp3.o 23obj-$(CONFIG_STX_GP3) += stx_gp3.o
24obj-$(CONFIG_TQM85xx) += tqm85xx.o 24obj-$(CONFIG_TQM85xx) += tqm85xx.o
25obj-$(CONFIG_SBC8560) += sbc8560.o
26obj-$(CONFIG_SBC8548) += sbc8548.o 25obj-$(CONFIG_SBC8548) += sbc8548.o
27obj-$(CONFIG_SOCRATES) += socrates.o socrates_fpga_pic.o 26obj-$(CONFIG_SOCRATES) += socrates.o socrates_fpga_pic.o
28obj-$(CONFIG_KSI8560) += ksi8560.o 27obj-$(CONFIG_KSI8560) += ksi8560.o
29obj-$(CONFIG_XES_MPC85xx) += xes_mpc85xx.o 28obj-$(CONFIG_XES_MPC85xx) += xes_mpc85xx.o
30obj-$(CONFIG_GE_IMP3A) += ge_imp3a.o 29obj-$(CONFIG_GE_IMP3A) += ge_imp3a.o
30obj-$(CONFIG_PPC_QEMU_E500) += qemu_e500.o
diff --git a/arch/powerpc/platforms/85xx/bsc913x_rdb.c b/arch/powerpc/platforms/85xx/bsc913x_rdb.c
new file mode 100644
index 000000000000..9d57bedb940c
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/bsc913x_rdb.c
@@ -0,0 +1,67 @@
1/*
2 * BSC913xRDB Board Setup
3 *
4 * Author: Priyanka Jain <Priyanka.Jain@freescale.com>
5 *
6 * Copyright 2011-2012 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/of_platform.h>
15#include <linux/pci.h>
16#include <asm/mpic.h>
17#include <sysdev/fsl_soc.h>
18#include <asm/udbg.h>
19
20#include "mpc85xx.h"
21
22void __init bsc913x_rdb_pic_init(void)
23{
24 struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
25 MPIC_SINGLE_DEST_CPU,
26 0, 256, " OpenPIC ");
27
28 if (!mpic)
29 pr_err("bsc913x: Failed to allocate MPIC structure\n");
30 else
31 mpic_init(mpic);
32}
33
34/*
35 * Setup the architecture
36 */
37static void __init bsc913x_rdb_setup_arch(void)
38{
39 if (ppc_md.progress)
40 ppc_md.progress("bsc913x_rdb_setup_arch()", 0);
41
42 pr_info("bsc913x board from Freescale Semiconductor\n");
43}
44
45machine_device_initcall(bsc9131_rdb, mpc85xx_common_publish_devices);
46
47/*
48 * Called very early, device-tree isn't unflattened
49 */
50
51static int __init bsc9131_rdb_probe(void)
52{
53 unsigned long root = of_get_flat_dt_root();
54
55 return of_flat_dt_is_compatible(root, "fsl,bsc9131rdb");
56}
57
58define_machine(bsc9131_rdb) {
59 .name = "BSC9131 RDB",
60 .probe = bsc9131_rdb_probe,
61 .setup_arch = bsc913x_rdb_setup_arch,
62 .init_IRQ = bsc913x_rdb_pic_init,
63 .get_irq = mpic_get_irq,
64 .restart = fsl_rstcr_restart,
65 .calibrate_decr = generic_calibrate_decr,
66 .progress = udbg_progress,
67};
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ds.c b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
index d30f6c47917d..6d3265fe7718 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
@@ -114,71 +114,53 @@ void __init mpc85xx_ds_pic_init(void)
114} 114}
115 115
116#ifdef CONFIG_PCI 116#ifdef CONFIG_PCI
117static int primary_phb_addr;
118extern int uli_exclude_device(struct pci_controller *hose, 117extern int uli_exclude_device(struct pci_controller *hose,
119 u_char bus, u_char devfn); 118 u_char bus, u_char devfn);
120 119
120static struct device_node *pci_with_uli;
121
121static int mpc85xx_exclude_device(struct pci_controller *hose, 122static int mpc85xx_exclude_device(struct pci_controller *hose,
122 u_char bus, u_char devfn) 123 u_char bus, u_char devfn)
123{ 124{
124 struct device_node* node; 125 if (hose->dn == pci_with_uli)
125 struct resource rsrc;
126
127 node = hose->dn;
128 of_address_to_resource(node, 0, &rsrc);
129
130 if ((rsrc.start & 0xfffff) == primary_phb_addr) {
131 return uli_exclude_device(hose, bus, devfn); 126 return uli_exclude_device(hose, bus, devfn);
132 }
133 127
134 return PCIBIOS_SUCCESSFUL; 128 return PCIBIOS_SUCCESSFUL;
135} 129}
136#endif /* CONFIG_PCI */ 130#endif /* CONFIG_PCI */
137 131
138/* 132static void __init mpc85xx_ds_pci_init(void)
139 * Setup the architecture
140 */
141static void __init mpc85xx_ds_setup_arch(void)
142{ 133{
143#ifdef CONFIG_PCI 134#ifdef CONFIG_PCI
144 struct device_node *np; 135 struct device_node *node;
145 struct pci_controller *hose;
146#endif
147 dma_addr_t max = 0xffffffff;
148 136
149 if (ppc_md.progress) 137 fsl_pci_init();
150 ppc_md.progress("mpc85xx_ds_setup_arch()", 0);
151 138
152#ifdef CONFIG_PCI 139 /* See if we have a ULI under the primary */
153 for_each_node_by_type(np, "pci") { 140
154 if (of_device_is_compatible(np, "fsl,mpc8540-pci") || 141 node = of_find_node_by_name(NULL, "uli1575");
155 of_device_is_compatible(np, "fsl,mpc8548-pcie") || 142 while ((pci_with_uli = of_get_parent(node))) {
156 of_device_is_compatible(np, "fsl,p2020-pcie")) { 143 of_node_put(node);
157 struct resource rsrc; 144 node = pci_with_uli;
158 of_address_to_resource(np, 0, &rsrc); 145
159 if ((rsrc.start & 0xfffff) == primary_phb_addr) 146 if (pci_with_uli == fsl_pci_primary) {
160 fsl_add_bridge(np, 1); 147 ppc_md.pci_exclude_device = mpc85xx_exclude_device;
161 else 148 break;
162 fsl_add_bridge(np, 0);
163
164 hose = pci_find_hose_for_OF_device(np);
165 max = min(max, hose->dma_window_base_cur +
166 hose->dma_window_size);
167 } 149 }
168 } 150 }
169
170 ppc_md.pci_exclude_device = mpc85xx_exclude_device;
171#endif 151#endif
152}
172 153
173 mpc85xx_smp_init(); 154/*
155 * Setup the architecture
156 */
157static void __init mpc85xx_ds_setup_arch(void)
158{
159 if (ppc_md.progress)
160 ppc_md.progress("mpc85xx_ds_setup_arch()", 0);
174 161
175#ifdef CONFIG_SWIOTLB 162 mpc85xx_ds_pci_init();
176 if ((memblock_end_of_DRAM() - 1) > max) { 163 mpc85xx_smp_init();
177 ppc_swiotlb_enable = 1;
178 set_pci_dma_ops(&swiotlb_dma_ops);
179 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
180 }
181#endif
182 164
183 printk("MPC85xx DS board from Freescale Semiconductor\n"); 165 printk("MPC85xx DS board from Freescale Semiconductor\n");
184} 166}
@@ -190,14 +172,7 @@ static int __init mpc8544_ds_probe(void)
190{ 172{
191 unsigned long root = of_get_flat_dt_root(); 173 unsigned long root = of_get_flat_dt_root();
192 174
193 if (of_flat_dt_is_compatible(root, "MPC8544DS")) { 175 return !!of_flat_dt_is_compatible(root, "MPC8544DS");
194#ifdef CONFIG_PCI
195 primary_phb_addr = 0xb000;
196#endif
197 return 1;
198 }
199
200 return 0;
201} 176}
202 177
203machine_device_initcall(mpc8544_ds, mpc85xx_common_publish_devices); 178machine_device_initcall(mpc8544_ds, mpc85xx_common_publish_devices);
@@ -215,14 +190,7 @@ static int __init mpc8572_ds_probe(void)
215{ 190{
216 unsigned long root = of_get_flat_dt_root(); 191 unsigned long root = of_get_flat_dt_root();
217 192
218 if (of_flat_dt_is_compatible(root, "fsl,MPC8572DS")) { 193 return !!of_flat_dt_is_compatible(root, "fsl,MPC8572DS");
219#ifdef CONFIG_PCI
220 primary_phb_addr = 0x8000;
221#endif
222 return 1;
223 }
224
225 return 0;
226} 194}
227 195
228/* 196/*
@@ -232,14 +200,7 @@ static int __init p2020_ds_probe(void)
232{ 200{
233 unsigned long root = of_get_flat_dt_root(); 201 unsigned long root = of_get_flat_dt_root();
234 202
235 if (of_flat_dt_is_compatible(root, "fsl,P2020DS")) { 203 return !!of_flat_dt_is_compatible(root, "fsl,P2020DS");
236#ifdef CONFIG_PCI
237 primary_phb_addr = 0x9000;
238#endif
239 return 1;
240 }
241
242 return 0;
243} 204}
244 205
245define_machine(mpc8544_ds) { 206define_machine(mpc8544_ds) {
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index 313fce4f5574..1910fdcb75b2 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -169,6 +169,7 @@ machine_device_initcall(p1020_rdb_pc, mpc85xx_common_publish_devices);
169machine_device_initcall(p1020_utm_pc, mpc85xx_common_publish_devices); 169machine_device_initcall(p1020_utm_pc, mpc85xx_common_publish_devices);
170machine_device_initcall(p1021_rdb_pc, mpc85xx_common_publish_devices); 170machine_device_initcall(p1021_rdb_pc, mpc85xx_common_publish_devices);
171machine_device_initcall(p1025_rdb, mpc85xx_common_publish_devices); 171machine_device_initcall(p1025_rdb, mpc85xx_common_publish_devices);
172machine_device_initcall(p1024_rdb, mpc85xx_common_publish_devices);
172 173
173/* 174/*
174 * Called very early, device-tree isn't unflattened 175 * Called very early, device-tree isn't unflattened
@@ -237,6 +238,13 @@ static int __init p1020_utm_pc_probe(void)
237 return of_flat_dt_is_compatible(root, "fsl,P1020UTM-PC"); 238 return of_flat_dt_is_compatible(root, "fsl,P1020UTM-PC");
238} 239}
239 240
241static int __init p1024_rdb_probe(void)
242{
243 unsigned long root = of_get_flat_dt_root();
244
245 return of_flat_dt_is_compatible(root, "fsl,P1024RDB");
246}
247
240define_machine(p2020_rdb) { 248define_machine(p2020_rdb) {
241 .name = "P2020 RDB", 249 .name = "P2020 RDB",
242 .probe = p2020_rdb_probe, 250 .probe = p2020_rdb_probe,
@@ -348,3 +356,17 @@ define_machine(p1020_rdb_pc) {
348 .calibrate_decr = generic_calibrate_decr, 356 .calibrate_decr = generic_calibrate_decr,
349 .progress = udbg_progress, 357 .progress = udbg_progress,
350}; 358};
359
360define_machine(p1024_rdb) {
361 .name = "P1024 RDB",
362 .probe = p1024_rdb_probe,
363 .setup_arch = mpc85xx_rdb_setup_arch,
364 .init_IRQ = mpc85xx_rdb_pic_init,
365#ifdef CONFIG_PCI
366 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
367#endif
368 .get_irq = mpic_get_irq,
369 .restart = fsl_rstcr_restart,
370 .calibrate_decr = generic_calibrate_decr,
371 .progress = udbg_progress,
372};
diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c b/arch/powerpc/platforms/85xx/p1022_ds.c
index 31d18b964f94..89ee02c54561 100644
--- a/arch/powerpc/platforms/85xx/p1022_ds.c
+++ b/arch/powerpc/platforms/85xx/p1022_ds.c
@@ -27,6 +27,7 @@
27#include <sysdev/fsl_pci.h> 27#include <sysdev/fsl_pci.h>
28#include <asm/udbg.h> 28#include <asm/udbg.h>
29#include <asm/fsl_guts.h> 29#include <asm/fsl_guts.h>
30#include <asm/fsl_lbc.h>
30#include "smp.h" 31#include "smp.h"
31 32
32#include "mpc85xx.h" 33#include "mpc85xx.h"
@@ -142,17 +143,73 @@ static void p1022ds_set_gamma_table(enum fsl_diu_monitor_port port,
142{ 143{
143} 144}
144 145
146struct fsl_law {
147 u32 lawbar;
148 u32 reserved1;
149 u32 lawar;
150 u32 reserved[5];
151};
152
153#define LAWBAR_MASK 0x00F00000
154#define LAWBAR_SHIFT 12
155
156#define LAWAR_EN 0x80000000
157#define LAWAR_TGT_MASK 0x01F00000
158#define LAW_TRGT_IF_LBC (0x04 << 20)
159
160#define LAWAR_MASK (LAWAR_EN | LAWAR_TGT_MASK)
161#define LAWAR_MATCH (LAWAR_EN | LAW_TRGT_IF_LBC)
162
163#define BR_BA 0xFFFF8000
164
165/*
166 * Map a BRx value to a physical address
167 *
168 * The localbus BRx registers only store the lower 32 bits of the address. To
169 * obtain the upper four bits, we need to scan the LAW table. The entry which
170 * maps to the localbus will contain the upper four bits.
171 */
172static phys_addr_t lbc_br_to_phys(const void *ecm, unsigned int count, u32 br)
173{
174#ifndef CONFIG_PHYS_64BIT
175 /*
176 * If we only have 32-bit addressing, then the BRx address *is* the
177 * physical address.
178 */
179 return br & BR_BA;
180#else
181 const struct fsl_law *law = ecm + 0xc08;
182 unsigned int i;
183
184 for (i = 0; i < count; i++) {
185 u64 lawbar = in_be32(&law[i].lawbar);
186 u32 lawar = in_be32(&law[i].lawar);
187
188 if ((lawar & LAWAR_MASK) == LAWAR_MATCH)
189 /* Extract the upper four bits */
190 return (br & BR_BA) | ((lawbar & LAWBAR_MASK) << 12);
191 }
192
193 return 0;
194#endif
195}
196
145/** 197/**
146 * p1022ds_set_monitor_port: switch the output to a different monitor port 198 * p1022ds_set_monitor_port: switch the output to a different monitor port
147 *
148 */ 199 */
149static void p1022ds_set_monitor_port(enum fsl_diu_monitor_port port) 200static void p1022ds_set_monitor_port(enum fsl_diu_monitor_port port)
150{ 201{
151 struct device_node *guts_node; 202 struct device_node *guts_node;
152 struct device_node *indirect_node = NULL; 203 struct device_node *lbc_node = NULL;
204 struct device_node *law_node = NULL;
153 struct ccsr_guts __iomem *guts; 205 struct ccsr_guts __iomem *guts;
206 struct fsl_lbc_regs *lbc = NULL;
207 void *ecm = NULL;
154 u8 __iomem *lbc_lcs0_ba = NULL; 208 u8 __iomem *lbc_lcs0_ba = NULL;
155 u8 __iomem *lbc_lcs1_ba = NULL; 209 u8 __iomem *lbc_lcs1_ba = NULL;
210 phys_addr_t cs0_addr, cs1_addr;
211 const __be32 *iprop;
212 unsigned int num_laws;
156 u8 b; 213 u8 b;
157 214
158 /* Map the global utilities registers. */ 215 /* Map the global utilities registers. */
@@ -168,25 +225,43 @@ static void p1022ds_set_monitor_port(enum fsl_diu_monitor_port port)
168 goto exit; 225 goto exit;
169 } 226 }
170 227
171 indirect_node = of_find_compatible_node(NULL, NULL, 228 lbc_node = of_find_compatible_node(NULL, NULL, "fsl,p1022-elbc");
172 "fsl,p1022ds-indirect-pixis"); 229 if (!lbc_node) {
173 if (!indirect_node) { 230 pr_err("p1022ds: missing localbus node\n");
174 pr_err("p1022ds: missing pixis indirect mode node\n");
175 goto exit; 231 goto exit;
176 } 232 }
177 233
178 lbc_lcs0_ba = of_iomap(indirect_node, 0); 234 lbc = of_iomap(lbc_node, 0);
179 if (!lbc_lcs0_ba) { 235 if (!lbc) {
180 pr_err("p1022ds: could not map localbus chip select 0\n"); 236 pr_err("p1022ds: could not map localbus node\n");
181 goto exit; 237 goto exit;
182 } 238 }
183 239
184 lbc_lcs1_ba = of_iomap(indirect_node, 1); 240 law_node = of_find_compatible_node(NULL, NULL, "fsl,ecm-law");
185 if (!lbc_lcs1_ba) { 241 if (!law_node) {
186 pr_err("p1022ds: could not map localbus chip select 1\n"); 242 pr_err("p1022ds: missing local access window node\n");
187 goto exit; 243 goto exit;
188 } 244 }
189 245
246 ecm = of_iomap(law_node, 0);
247 if (!ecm) {
248 pr_err("p1022ds: could not map local access window node\n");
249 goto exit;
250 }
251
252 iprop = of_get_property(law_node, "fsl,num-laws", 0);
253 if (!iprop) {
254 pr_err("p1022ds: LAW node is missing fsl,num-laws property\n");
255 goto exit;
256 }
257 num_laws = be32_to_cpup(iprop);
258
259 cs0_addr = lbc_br_to_phys(ecm, num_laws, in_be32(&lbc->bank[0].br));
260 cs1_addr = lbc_br_to_phys(ecm, num_laws, in_be32(&lbc->bank[1].br));
261
262 lbc_lcs0_ba = ioremap(cs0_addr, 1);
263 lbc_lcs1_ba = ioremap(cs1_addr, 1);
264
190 /* Make sure we're in indirect mode first. */ 265 /* Make sure we're in indirect mode first. */
191 if ((in_be32(&guts->pmuxcr) & PMUXCR_ELBCDIU_MASK) != 266 if ((in_be32(&guts->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
192 PMUXCR_ELBCDIU_DIU) { 267 PMUXCR_ELBCDIU_DIU) {
@@ -254,10 +329,15 @@ exit:
254 iounmap(lbc_lcs1_ba); 329 iounmap(lbc_lcs1_ba);
255 if (lbc_lcs0_ba) 330 if (lbc_lcs0_ba)
256 iounmap(lbc_lcs0_ba); 331 iounmap(lbc_lcs0_ba);
332 if (lbc)
333 iounmap(lbc);
334 if (ecm)
335 iounmap(ecm);
257 if (guts) 336 if (guts)
258 iounmap(guts); 337 iounmap(guts);
259 338
260 of_node_put(indirect_node); 339 of_node_put(law_node);
340 of_node_put(lbc_node);
261 of_node_put(guts_node); 341 of_node_put(guts_node);
262} 342}
263 343
diff --git a/arch/powerpc/platforms/85xx/p3060_qds.c b/arch/powerpc/platforms/85xx/p3060_qds.c
deleted file mode 100644
index 081cf4ac1881..000000000000
--- a/arch/powerpc/platforms/85xx/p3060_qds.c
+++ /dev/null
@@ -1,77 +0,0 @@
1/*
2 * P3060 QDS Setup
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#include <linux/kernel.h>
13#include <linux/interrupt.h>
14#include <linux/phy.h>
15#include <asm/machdep.h>
16#include <asm/udbg.h>
17#include <asm/mpic.h>
18#include <linux/of_platform.h>
19#include <sysdev/fsl_soc.h>
20#include <sysdev/fsl_pci.h>
21#include <asm/ehv_pic.h>
22#include "corenet_ds.h"
23
24/*
25 * Called very early, device-tree isn't unflattened
26 */
27static int __init p3060_qds_probe(void)
28{
29 unsigned long root = of_get_flat_dt_root();
30#ifdef CONFIG_SMP
31 extern struct smp_ops_t smp_85xx_ops;
32#endif
33
34 if (of_flat_dt_is_compatible(root, "fsl,P3060QDS"))
35 return 1;
36
37 /* Check if we're running under the Freescale hypervisor */
38 if (of_flat_dt_is_compatible(root, "fsl,P3060QDS-hv")) {
39 ppc_md.init_IRQ = ehv_pic_init;
40 ppc_md.get_irq = ehv_pic_get_irq;
41 ppc_md.restart = fsl_hv_restart;
42 ppc_md.power_off = fsl_hv_halt;
43 ppc_md.halt = fsl_hv_halt;
44#ifdef CONFIG_SMP
45 /*
46 * Disable the timebase sync operations because we can't write
47 * to the timebase registers under the hypervisor.
48 */
49 smp_85xx_ops.give_timebase = NULL;
50 smp_85xx_ops.take_timebase = NULL;
51#endif
52 return 1;
53 }
54
55 return 0;
56}
57
58define_machine(p3060_qds) {
59 .name = "P3060 QDS",
60 .probe = p3060_qds_probe,
61 .setup_arch = corenet_ds_setup_arch,
62 .init_IRQ = corenet_ds_pic_init,
63#ifdef CONFIG_PCI
64 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
65#endif
66 .get_irq = mpic_get_coreint_irq,
67 .restart = fsl_rstcr_restart,
68 .calibrate_decr = generic_calibrate_decr,
69 .progress = udbg_progress,
70 .power_save = e500_idle,
71};
72
73machine_device_initcall(p3060_qds, corenet_ds_publish_devices);
74
75#ifdef CONFIG_SWIOTLB
76machine_arch_initcall(p3060_qds, swiotlb_setup_bus_notifier);
77#endif
diff --git a/arch/powerpc/platforms/85xx/qemu_e500.c b/arch/powerpc/platforms/85xx/qemu_e500.c
new file mode 100644
index 000000000000..95a2e53af71b
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/qemu_e500.c
@@ -0,0 +1,72 @@
1/*
2 * Paravirt target for a generic QEMU e500 machine
3 *
4 * This is intended to be a flexible device-tree-driven platform, not fixed
5 * to a particular piece of hardware or a particular spec of virtual hardware,
6 * beyond the assumption of an e500-family CPU. Some things are still hardcoded
7 * here, such as MPIC, but this is a limitation of the current code rather than
8 * an interface contract with QEMU.
9 *
10 * Copyright 2012 Freescale Semiconductor Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17
18#include <linux/kernel.h>
19#include <linux/of_fdt.h>
20#include <asm/machdep.h>
21#include <asm/time.h>
22#include <asm/udbg.h>
23#include <asm/mpic.h>
24#include <sysdev/fsl_soc.h>
25#include <sysdev/fsl_pci.h>
26#include "smp.h"
27#include "mpc85xx.h"
28
29void __init qemu_e500_pic_init(void)
30{
31 struct mpic *mpic;
32
33 mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU,
34 0, 256, " OpenPIC ");
35
36 BUG_ON(mpic == NULL);
37 mpic_init(mpic);
38}
39
40static void __init qemu_e500_setup_arch(void)
41{
42 ppc_md.progress("qemu_e500_setup_arch()", 0);
43
44 fsl_pci_init();
45 mpc85xx_smp_init();
46}
47
48/*
49 * Called very early, device-tree isn't unflattened
50 */
51static int __init qemu_e500_probe(void)
52{
53 unsigned long root = of_get_flat_dt_root();
54
55 return !!of_flat_dt_is_compatible(root, "fsl,qemu-e500");
56}
57
58machine_device_initcall(qemu_e500, mpc85xx_common_publish_devices);
59
60define_machine(qemu_e500) {
61 .name = "QEMU e500",
62 .probe = qemu_e500_probe,
63 .setup_arch = qemu_e500_setup_arch,
64 .init_IRQ = qemu_e500_pic_init,
65#ifdef CONFIG_PCI
66 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
67#endif
68 .get_irq = mpic_get_irq,
69 .restart = fsl_rstcr_restart,
70 .calibrate_decr = generic_calibrate_decr,
71 .progress = udbg_progress,
72};
diff --git a/arch/powerpc/platforms/85xx/sbc8560.c b/arch/powerpc/platforms/85xx/sbc8560.c
deleted file mode 100644
index b1be632ede43..000000000000
--- a/arch/powerpc/platforms/85xx/sbc8560.c
+++ /dev/null
@@ -1,254 +0,0 @@
1/*
2 * Wind River SBC8560 setup and early boot code.
3 *
4 * Copyright 2007 Wind River Systems Inc.
5 *
6 * By Paul Gortmaker (see MAINTAINERS for contact information)
7 *
8 * Based largely on the MPC8560ADS support - Copyright 2005 Freescale Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <linux/stddef.h>
17#include <linux/kernel.h>
18#include <linux/pci.h>
19#include <linux/kdev_t.h>
20#include <linux/delay.h>
21#include <linux/seq_file.h>
22#include <linux/of_platform.h>
23
24#include <asm/time.h>
25#include <asm/machdep.h>
26#include <asm/pci-bridge.h>
27#include <asm/mpic.h>
28#include <mm/mmu_decl.h>
29#include <asm/udbg.h>
30
31#include <sysdev/fsl_soc.h>
32#include <sysdev/fsl_pci.h>
33
34#include "mpc85xx.h"
35
36#ifdef CONFIG_CPM2
37#include <asm/cpm2.h>
38#include <sysdev/cpm2_pic.h>
39#endif
40
41static void __init sbc8560_pic_init(void)
42{
43 struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
44 0, 256, " OpenPIC ");
45 BUG_ON(mpic == NULL);
46 mpic_init(mpic);
47
48 mpc85xx_cpm2_pic_init();
49}
50
51/*
52 * Setup the architecture
53 */
54#ifdef CONFIG_CPM2
55struct cpm_pin {
56 int port, pin, flags;
57};
58
59static const struct cpm_pin sbc8560_pins[] = {
60 /* SCC1 */
61 {3, 29, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
62 {3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
63 {3, 31, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
64
65 /* SCC2 */
66 {3, 26, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
67 {3, 27, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
68 {3, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
69
70 /* FCC2 */
71 {1, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
72 {1, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
73 {1, 20, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
74 {1, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
75 {1, 22, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
76 {1, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
77 {1, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
78 {1, 25, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
79 {1, 26, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
80 {1, 27, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
81 {1, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
82 {1, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
83 {1, 30, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
84 {1, 31, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
85 {2, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK14 */
86 {2, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK13 */
87
88 /* FCC3 */
89 {1, 4, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
90 {1, 5, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
91 {1, 6, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
92 {1, 7, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
93 {1, 8, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
94 {1, 9, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
95 {1, 10, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
96 {1, 11, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
97 {1, 12, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
98 {1, 13, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
99 {1, 14, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
100 {1, 15, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
101 {1, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
102 {1, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
103 {2, 16, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* CLK16 */
104 {2, 17, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* CLK15 */
105};
106
107static void __init init_ioports(void)
108{
109 int i;
110
111 for (i = 0; i < ARRAY_SIZE(sbc8560_pins); i++) {
112 const struct cpm_pin *pin = &sbc8560_pins[i];
113 cpm2_set_pin(pin->port, pin->pin, pin->flags);
114 }
115
116 cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX);
117 cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX);
118 cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_RX);
119 cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_TX);
120 cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK13, CPM_CLK_RX);
121 cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK14, CPM_CLK_TX);
122 cpm2_clk_setup(CPM_CLK_FCC3, CPM_CLK15, CPM_CLK_RX);
123 cpm2_clk_setup(CPM_CLK_FCC3, CPM_CLK16, CPM_CLK_TX);
124}
125#endif
126
127static void __init sbc8560_setup_arch(void)
128{
129#ifdef CONFIG_PCI
130 struct device_node *np;
131#endif
132
133 if (ppc_md.progress)
134 ppc_md.progress("sbc8560_setup_arch()", 0);
135
136#ifdef CONFIG_CPM2
137 cpm2_reset();
138 init_ioports();
139#endif
140
141#ifdef CONFIG_PCI
142 for_each_compatible_node(np, "pci", "fsl,mpc8540-pci")
143 fsl_add_bridge(np, 1);
144#endif
145}
146
147static void sbc8560_show_cpuinfo(struct seq_file *m)
148{
149 uint pvid, svid, phid1;
150
151 pvid = mfspr(SPRN_PVR);
152 svid = mfspr(SPRN_SVR);
153
154 seq_printf(m, "Vendor\t\t: Wind River\n");
155 seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
156 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
157
158 /* Display cpu Pll setting */
159 phid1 = mfspr(SPRN_HID1);
160 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
161}
162
163machine_device_initcall(sbc8560, mpc85xx_common_publish_devices);
164
165/*
166 * Called very early, device-tree isn't unflattened
167 */
168static int __init sbc8560_probe(void)
169{
170 unsigned long root = of_get_flat_dt_root();
171
172 return of_flat_dt_is_compatible(root, "SBC8560");
173}
174
175#ifdef CONFIG_RTC_DRV_M48T59
176static int __init sbc8560_rtc_init(void)
177{
178 struct device_node *np;
179 struct resource res;
180 struct platform_device *rtc_dev;
181
182 np = of_find_compatible_node(NULL, NULL, "m48t59");
183 if (np == NULL) {
184 printk("No RTC in DTB. Has it been eaten by wild dogs?\n");
185 return -ENODEV;
186 }
187
188 of_address_to_resource(np, 0, &res);
189 of_node_put(np);
190
191 printk("Found RTC (m48t59) at i/o 0x%x\n", res.start);
192
193 rtc_dev = platform_device_register_simple("rtc-m48t59", 0, &res, 1);
194
195 if (IS_ERR(rtc_dev)) {
196 printk("Registering sbc8560 RTC device failed\n");
197 return PTR_ERR(rtc_dev);
198 }
199
200 return 0;
201}
202
203arch_initcall(sbc8560_rtc_init);
204
205#endif /* M48T59 */
206
207static __u8 __iomem *brstcr;
208
209static int __init sbc8560_bdrstcr_init(void)
210{
211 struct device_node *np;
212 struct resource res;
213
214 np = of_find_compatible_node(NULL, NULL, "wrs,sbc8560-brstcr");
215 if (np == NULL) {
216 printk(KERN_WARNING "sbc8560: No board specific RSTCR in DTB.\n");
217 return -ENODEV;
218 }
219
220 of_address_to_resource(np, 0, &res);
221
222 printk(KERN_INFO "sbc8560: Found BRSTCR at %pR\n", &res);
223
224 brstcr = ioremap(res.start, resource_size(&res));
225 if(!brstcr)
226 printk(KERN_WARNING "sbc8560: ioremap of brstcr failed.\n");
227
228 of_node_put(np);
229
230 return 0;
231}
232
233arch_initcall(sbc8560_bdrstcr_init);
234
235void sbc8560_rstcr_restart(char * cmd)
236{
237 local_irq_disable();
238 if(brstcr)
239 clrbits8(brstcr, 0x80);
240
241 while(1);
242}
243
244define_machine(sbc8560) {
245 .name = "SBC8560",
246 .probe = sbc8560_probe,
247 .setup_arch = sbc8560_setup_arch,
248 .init_IRQ = sbc8560_pic_init,
249 .show_cpuinfo = sbc8560_show_cpuinfo,
250 .get_irq = mpic_get_irq,
251 .restart = sbc8560_rstcr_restart,
252 .calibrate_decr = generic_calibrate_decr,
253 .progress = udbg_progress,
254};
diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
index 61c9550819a2..30fd01de6bed 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++ b/arch/powerpc/platforms/Kconfig.cputype
@@ -159,6 +159,10 @@ config PPC_E500MC
159 bool "e500mc Support" 159 bool "e500mc Support"
160 select PPC_FPU 160 select PPC_FPU
161 depends on E500 161 depends on E500
162 help
163 This must be enabled for running on e500mc (and derivatives
164 such as e5500/e6500), and must be disabled for running on
165 e500v1 or e500v2.
162 166
163config PPC_FPU 167config PPC_FPU
164 bool 168 bool
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 6073288fed29..a7b2a600d0a4 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC83xx/85xx/86xx PCI/PCIE support routing. 2 * MPC83xx/85xx/86xx PCI/PCIE support routing.
3 * 3 *
4 * Copyright 2007-2011 Freescale Semiconductor, Inc. 4 * Copyright 2007-2012 Freescale Semiconductor, Inc.
5 * Copyright 2008-2009 MontaVista Software, Inc. 5 * Copyright 2008-2009 MontaVista Software, Inc.
6 * 6 *
7 * Initial author: Xianghua Xiao <x.xiao@freescale.com> 7 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
@@ -36,7 +36,7 @@
36 36
37static int fsl_pcie_bus_fixup, is_mpc83xx_pci; 37static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
38 38
39static void __init quirk_fsl_pcie_header(struct pci_dev *dev) 39static void __devinit quirk_fsl_pcie_header(struct pci_dev *dev)
40{ 40{
41 u8 progif; 41 u8 progif;
42 42
@@ -807,3 +807,72 @@ u64 fsl_pci_immrbar_base(struct pci_controller *hose)
807 807
808 return 0; 808 return 0;
809} 809}
810
811#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
812static const struct of_device_id pci_ids[] = {
813 { .compatible = "fsl,mpc8540-pci", },
814 { .compatible = "fsl,mpc8548-pcie", },
815 { .compatible = "fsl,mpc8610-pci", },
816 { .compatible = "fsl,mpc8641-pcie", },
817 { .compatible = "fsl,p1022-pcie", },
818 { .compatible = "fsl,p1010-pcie", },
819 { .compatible = "fsl,p1023-pcie", },
820 { .compatible = "fsl,p4080-pcie", },
821 { .compatible = "fsl,qoriq-pcie-v2.3", },
822 { .compatible = "fsl,qoriq-pcie-v2.2", },
823 {},
824};
825
826struct device_node *fsl_pci_primary;
827
828void __devinit fsl_pci_init(void)
829{
830 struct device_node *node;
831 struct pci_controller *hose;
832 dma_addr_t max = 0xffffffff;
833
834 /* Callers can specify the primary bus using other means. */
835 if (!fsl_pci_primary) {
836 /* If a PCI host bridge contains an ISA node, it's primary. */
837 node = of_find_node_by_type(NULL, "isa");
838 while ((fsl_pci_primary = of_get_parent(node))) {
839 of_node_put(node);
840 node = fsl_pci_primary;
841
842 if (of_match_node(pci_ids, node))
843 break;
844 }
845 }
846
847 node = NULL;
848 for_each_node_by_type(node, "pci") {
849 if (of_match_node(pci_ids, node)) {
850 /*
851 * If there's no PCI host bridge with ISA, arbitrarily
852 * designate one as primary. This can go away once
853 * various bugs with primary-less systems are fixed.
854 */
855 if (!fsl_pci_primary)
856 fsl_pci_primary = node;
857
858 fsl_add_bridge(node, fsl_pci_primary == node);
859 hose = pci_find_hose_for_OF_device(node);
860 max = min(max, hose->dma_window_base_cur +
861 hose->dma_window_size);
862 }
863 }
864
865#ifdef CONFIG_SWIOTLB
866 /*
867 * if we couldn't map all of DRAM via the dma windows
868 * we need SWIOTLB to handle buffers located outside of
869 * dma capable memory region
870 */
871 if (memblock_end_of_DRAM() - 1 > max) {
872 ppc_swiotlb_enable = 1;
873 set_pci_dma_ops(&swiotlb_dma_ops);
874 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
875 }
876#endif
877}
878#endif
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index a39ed5cc2c5a..baa0fd18289f 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -93,5 +93,13 @@ extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
93extern int mpc83xx_add_bridge(struct device_node *dev); 93extern int mpc83xx_add_bridge(struct device_node *dev);
94u64 fsl_pci_immrbar_base(struct pci_controller *hose); 94u64 fsl_pci_immrbar_base(struct pci_controller *hose);
95 95
96extern struct device_node *fsl_pci_primary;
97
98#ifdef CONFIG_FSL_PCI
99void fsl_pci_init(void);
100#else
101static inline void fsl_pci_init(void) {}
102#endif
103
96#endif /* __POWERPC_FSL_PCI_H */ 104#endif /* __POWERPC_FSL_PCI_H */
97#endif /* __KERNEL__ */ 105#endif /* __KERNEL__ */
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 395af1347749..906f29c05c54 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -1211,7 +1211,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
1211 if (of_get_property(node, "single-cpu-affinity", NULL)) 1211 if (of_get_property(node, "single-cpu-affinity", NULL))
1212 flags |= MPIC_SINGLE_DEST_CPU; 1212 flags |= MPIC_SINGLE_DEST_CPU;
1213 if (of_device_is_compatible(node, "fsl,mpic")) 1213 if (of_device_is_compatible(node, "fsl,mpic"))
1214 flags |= MPIC_FSL; 1214 flags |= MPIC_FSL | MPIC_LARGE_VECTORS;
1215 1215
1216 mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL); 1216 mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
1217 if (mpic == NULL) 1217 if (mpic == NULL)
diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c
index 818e763f8265..b04367529729 100644
--- a/arch/powerpc/sysdev/qe_lib/qe.c
+++ b/arch/powerpc/sysdev/qe_lib/qe.c
@@ -395,6 +395,9 @@ static void qe_upload_microcode(const void *base,
395 395
396 for (i = 0; i < be32_to_cpu(ucode->count); i++) 396 for (i = 0; i < be32_to_cpu(ucode->count); i++)
397 out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i])); 397 out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i]));
398
399 /* Set I-RAM Ready Register */
400 out_be32(&qe_immr->iram.iready, be32_to_cpu(QE_IRAM_READY));
398} 401}
399 402
400/* 403/*
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 06:26:49 -0500