diff options
| author | Michael Neuling <mikey@neuling.org> | 2013-04-30 16:17:03 -0400 |
|---|---|---|
| committer | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2013-05-01 20:36:55 -0400 |
| commit | 1ddf499e1a49e67c02b89e6565d091a0bda29a91 (patch) | |
| tree | 477d0d3ae72bdb1444993e1623b08978d63ceb45 /arch/powerpc | |
| parent | 1de2bd4e0c0f62c697a3b3e19bda431cf67ce20e (diff) | |
powerpc: Turn on the EBB H/FSCR bits
This turns Event Based Branching (EBB) on in the Hypervisor Facility Status and
Control Register (HFSCR) and Facility Status and Control Register (FSCR).
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc')
| -rw-r--r-- | arch/powerpc/include/asm/reg.h | 2 | ||||
| -rw-r--r-- | arch/powerpc/kernel/cpu_setup_power.S | 4 |
2 files changed, 4 insertions, 2 deletions
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index 178a85844462..93be5fb20394 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h | |||
| @@ -267,9 +267,11 @@ | |||
| 267 | #define SPRN_HSRR1 0x13B /* Hypervisor Save/Restore 1 */ | 267 | #define SPRN_HSRR1 0x13B /* Hypervisor Save/Restore 1 */ |
| 268 | #define SPRN_FSCR 0x099 /* Facility Status & Control Register */ | 268 | #define SPRN_FSCR 0x099 /* Facility Status & Control Register */ |
| 269 | #define FSCR_TAR (1 << (63-55)) /* Enable Target Address Register */ | 269 | #define FSCR_TAR (1 << (63-55)) /* Enable Target Address Register */ |
| 270 | #define FSCR_EBB (1 << (63-56)) /* Enable Event Based Branching */ | ||
| 270 | #define FSCR_DSCR (1 << (63-61)) /* Enable Data Stream Control Register */ | 271 | #define FSCR_DSCR (1 << (63-61)) /* Enable Data Stream Control Register */ |
| 271 | #define SPRN_HFSCR 0xbe /* HV=1 Facility Status & Control Register */ | 272 | #define SPRN_HFSCR 0xbe /* HV=1 Facility Status & Control Register */ |
| 272 | #define HFSCR_TAR (1 << (63-55)) /* Enable Target Address Register */ | 273 | #define HFSCR_TAR (1 << (63-55)) /* Enable Target Address Register */ |
| 274 | #define HFSCR_EBB (1 << (63-56)) /* Enable Event Based Branching */ | ||
| 273 | #define HFSCR_TM (1 << (63-58)) /* Enable Transactional Memory */ | 275 | #define HFSCR_TM (1 << (63-58)) /* Enable Transactional Memory */ |
| 274 | #define HFSCR_PM (1 << (63-60)) /* Enable prob/priv access to PMU SPRs */ | 276 | #define HFSCR_PM (1 << (63-60)) /* Enable prob/priv access to PMU SPRs */ |
| 275 | #define HFSCR_BHRB (1 << (63-59)) /* Enable Branch History Rolling Buffer*/ | 277 | #define HFSCR_BHRB (1 << (63-59)) /* Enable Branch History Rolling Buffer*/ |
diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S index 7b4db965b592..a283b6442b26 100644 --- a/arch/powerpc/kernel/cpu_setup_power.S +++ b/arch/powerpc/kernel/cpu_setup_power.S | |||
| @@ -123,14 +123,14 @@ __init_LPCR: | |||
| 123 | 123 | ||
| 124 | __init_FSCR: | 124 | __init_FSCR: |
| 125 | mfspr r3,SPRN_FSCR | 125 | mfspr r3,SPRN_FSCR |
| 126 | ori r3,r3,FSCR_TAR|FSCR_DSCR | 126 | ori r3,r3,FSCR_TAR|FSCR_DSCR|FSCR_EBB |
| 127 | mtspr SPRN_FSCR,r3 | 127 | mtspr SPRN_FSCR,r3 |
| 128 | blr | 128 | blr |
| 129 | 129 | ||
| 130 | __init_HFSCR: | 130 | __init_HFSCR: |
| 131 | mfspr r3,SPRN_HFSCR | 131 | mfspr r3,SPRN_HFSCR |
| 132 | ori r3,r3,HFSCR_TAR|HFSCR_TM|HFSCR_BHRB|HFSCR_PM|\ | 132 | ori r3,r3,HFSCR_TAR|HFSCR_TM|HFSCR_BHRB|HFSCR_PM|\ |
| 133 | HFSCR_DSCR|HFSCR_VECVSX|HFSCR_FP | 133 | HFSCR_DSCR|HFSCR_VECVSX|HFSCR_FP|HFSCR_EBB |
| 134 | mtspr SPRN_HFSCR,r3 | 134 | mtspr SPRN_HFSCR,r3 |
| 135 | blr | 135 | blr |
| 136 | 136 | ||