Merge branch 'master' of /usr/src/ntfs-2.6/

12 files changed, 9102 insertions, 0 deletions

diff --git a/arch/powerpc/xmon/Makefile b/arch/powerpc/xmon/Makefile
new file mode 100644
index 000000000000..79a784f0e7a9
--- /dev/null
+++ b/arch/powerpc/xmon/Makefile
@@ -0,0 +1,11 @@
+# Makefile for xmon
+
+ifdef CONFIG_PPC64
+EXTRA_CFLAGS += -mno-minimal-toc
+endif
+
+obj-$(CONFIG_8xx)       += start_8xx.o
+obj-$(CONFIG_6xx)       += start_32.o
+obj-$(CONFIG_4xx)       += start_32.o
+obj-$(CONFIG_PPC64)     += start_64.o
+obj-y                   += xmon.o ppc-dis.o ppc-opc.o subr_prf.o setjmp.o
diff --git a/arch/powerpc/xmon/ansidecl.h b/arch/powerpc/xmon/ansidecl.h
new file mode 100644
index 000000000000..c9b9f0929e9e
--- /dev/null
+++ b/arch/powerpc/xmon/ansidecl.h
@@ -0,0 +1,141 @@
+/* ANSI and traditional C compatibility macros
+   Copyright 1991, 1992 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+/* ANSI and traditional C compatibility macros
+
+   ANSI C is assumed if __STDC__ is #defined.
+
+   Macro        ANSI C definition       Traditional C definition
+   -----        ---- - ----------       ----------- - ----------
+   PTR          `void *'                `char *'
+   LONG_DOUBLE  `long double'           `double'
+   VOLATILE     `volatile'              `'
+   SIGNED       `signed'                `'
+   PTRCONST     `void *const'           `char *'
+   ANSI_PROTOTYPES  1                   not defined
+
+   CONST is also defined, but is obsolete.  Just use const.
+
+   DEFUN (name, arglist, args)
+
+        Defines function NAME.
+
+        ARGLIST lists the arguments, separated by commas and enclosed in
+        parentheses.  ARGLIST becomes the argument list in traditional C.
+
+        ARGS list the arguments with their types.  It becomes a prototype in
+        ANSI C, and the type declarations in traditional C.  Arguments should
+        be separated with `AND'.  For functions with a variable number of
+        arguments, the last thing listed should be `DOTS'.
+
+   DEFUN_VOID (name)
+
+        Defines a function NAME, which takes no arguments.
+
+   obsolete --     EXFUN (name, (prototype))    -- obsolete.
+
+        Replaced by PARAMS.  Do not use; will disappear someday soon.
+        Was used in external function declarations.
+        In ANSI C it is `NAME PROTOTYPE' (so PROTOTYPE should be enclosed in
+        parentheses).  In traditional C it is `NAME()'.
+        For a function that takes no arguments, PROTOTYPE should be `(void)'.
+
+    PARAMS ((args))
+
+        We could use the EXFUN macro to handle prototype declarations, but
+        the name is misleading and the result is ugly.  So we just define a
+        simple macro to handle the parameter lists, as in:
+
+              static int foo PARAMS ((int, char));
+
+        This produces:  `static int foo();' or `static int foo (int, char);'
+
+        EXFUN would have done it like this:
+
+              static int EXFUN (foo, (int, char));
+
+        but the function is not external...and it's hard to visually parse
+        the function name out of the mess.   EXFUN should be considered
+        obsolete; new code should be written to use PARAMS.
+
+    For example:
+        extern int printf PARAMS ((CONST char *format DOTS));
+        int DEFUN(fprintf, (stream, format),
+                  FILE *stream AND CONST char *format DOTS) { ... }
+        void DEFUN_VOID(abort) { ... }
+*/
+
+#ifndef _ANSIDECL_H
+
+#define _ANSIDECL_H     1
+
+
+/* Every source file includes this file,
+   so they will all get the switch for lint.  */
+/* LINTLIBRARY */
+
+
+#if defined (__STDC__) || defined (_AIX) || (defined (__mips) && defined (_SYSTYPE_SVR4)) || defined(WIN32)
+/* All known AIX compilers implement these things (but don't always
+   define __STDC__).  The RISC/OS MIPS compiler defines these things
+   in SVR4 mode, but does not define __STDC__.  */
+
+#define PTR             void *
+#define PTRCONST        void *CONST
+#define LONG_DOUBLE     long double
+
+#define AND             ,
+#define NOARGS          void
+#define CONST           const
+#define VOLATILE        volatile
+#define SIGNED          signed
+#define DOTS            , ...
+
+#define EXFUN(name, proto)              name proto
+#define DEFUN(name, arglist, args)      name(args)
+#define DEFUN_VOID(name)                name(void)
+
+#define PROTO(type, name, arglist)      type name arglist
+#define PARAMS(paramlist)               paramlist
+#define ANSI_PROTOTYPES                 1
+
+#else   /* Not ANSI C.  */
+
+#define PTR             char *
+#define PTRCONST        PTR
+#define LONG_DOUBLE     double
+
+#define AND             ;
+#define NOARGS
+#define CONST
+#ifndef const /* some systems define it in header files for non-ansi mode */
+#define const
+#endif
+#define VOLATILE
+#define SIGNED
+#define DOTS
+
+#define EXFUN(name, proto)              name()
+#define DEFUN(name, arglist, args)      name arglist args;
+#define DEFUN_VOID(name)                name()
+#define PROTO(type, name, arglist) type name ()
+#define PARAMS(paramlist)               ()
+
+#endif  /* ANSI C.  */
+
+#endif  /* ansidecl.h   */
diff --git a/arch/powerpc/xmon/nonstdio.h b/arch/powerpc/xmon/nonstdio.h
new file mode 100644
index 000000000000..84211a21c6f4
--- /dev/null
+++ b/arch/powerpc/xmon/nonstdio.h
@@ -0,0 +1,22 @@
+typedef int     FILE;
+extern FILE *xmon_stdin, *xmon_stdout;
+#define EOF     (-1)
+#define stdin   xmon_stdin
+#define stdout  xmon_stdout
+#define printf  xmon_printf
+#define fprintf xmon_fprintf
+#define fputs   xmon_fputs
+#define fgets   xmon_fgets
+#define putchar xmon_putchar
+#define getchar xmon_getchar
+#define putc    xmon_putc
+#define getc    xmon_getc
+#define fopen(n, m)     NULL
+#define fflush(f)       do {} while (0)
+#define fclose(f)       do {} while (0)
+extern char *fgets(char *, int, void *);
+extern void xmon_printf(const char *, ...);
+extern void xmon_fprintf(void *, const char *, ...);
+extern void xmon_sprintf(char *, const char *, ...);
+
+#define perror(s)       printf("%s: no files!\n", (s))
diff --git a/arch/powerpc/xmon/ppc-dis.c b/arch/powerpc/xmon/ppc-dis.c
new file mode 100644
index 000000000000..ac0a9d2427e0
--- /dev/null
+++ b/arch/powerpc/xmon/ppc-dis.c
@@ -0,0 +1,184 @@
+/* ppc-dis.c -- Disassemble PowerPC instructions
+   Copyright 1994 Free Software Foundation, Inc.
+   Written by Ian Lance Taylor, Cygnus Support
+
+This file is part of GDB, GAS, and the GNU binutils.
+
+GDB, GAS, and the GNU binutils are free software; you can redistribute
+them and/or modify them under the terms of the GNU General Public
+License as published by the Free Software Foundation; either version
+2, or (at your option) any later version.
+
+GDB, GAS, and the GNU binutils are distributed in the hope that they
+will be useful, but WITHOUT ANY WARRANTY; without even the implied
+warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+the GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this file; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#include "nonstdio.h"
+#include "ansidecl.h"
+#include "ppc.h"
+
+extern void print_address (unsigned long memaddr);
+
+/* Print a PowerPC or POWER instruction.  */
+
+int
+print_insn_powerpc (unsigned long insn, unsigned long memaddr, int dialect)
+{
+  const struct powerpc_opcode *opcode;
+  const struct powerpc_opcode *opcode_end;
+  unsigned long op;
+
+  if (dialect == 0)
+    dialect = PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_COMMON
+              | PPC_OPCODE_64 | PPC_OPCODE_POWER4 | PPC_OPCODE_ALTIVEC;
+
+  /* Get the major opcode of the instruction.  */
+  op = PPC_OP (insn);
+
+  /* Find the first match in the opcode table.  We could speed this up
+     a bit by doing a binary search on the major opcode.  */
+  opcode_end = powerpc_opcodes + powerpc_num_opcodes;
+ again:
+  for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++)
+    {
+      unsigned long table_op;
+      const unsigned char *opindex;
+      const struct powerpc_operand *operand;
+      int invalid;
+      int need_comma;
+      int need_paren;
+
+      table_op = PPC_OP (opcode->opcode);
+      if (op < table_op)
+        break;
+      if (op > table_op)
+        continue;
+
+      if ((insn & opcode->mask) != opcode->opcode
+          || (opcode->flags & dialect) == 0)
+        continue;
+
+      /* Make two passes over the operands.  First see if any of them
+         have extraction functions, and, if they do, make sure the
+         instruction is valid.  */
+      invalid = 0;
+      for (opindex = opcode->operands; *opindex != 0; opindex++)
+        {
+          operand = powerpc_operands + *opindex;
+          if (operand->extract)
+            (*operand->extract) (insn, dialect, &invalid);
+        }
+      if (invalid)
+        continue;
+
+      /* The instruction is valid.  */
+      printf("%s", opcode->name);
+      if (opcode->operands[0] != 0)
+        printf("\t");
+
+      /* Now extract and print the operands.  */
+      need_comma = 0;
+      need_paren = 0;
+      for (opindex = opcode->operands; *opindex != 0; opindex++)
+        {
+          long value;
+
+          operand = powerpc_operands + *opindex;
+
+          /* Operands that are marked FAKE are simply ignored.  We
+             already made sure that the extract function considered
+             the instruction to be valid.  */
+          if ((operand->flags & PPC_OPERAND_FAKE) != 0)
+            continue;
+
+          /* Extract the value from the instruction.  */
+          if (operand->extract)
+            value = (*operand->extract) (insn, dialect, &invalid);
+          else
+            {
+              value = (insn >> operand->shift) & ((1 << operand->bits) - 1);
+              if ((operand->flags & PPC_OPERAND_SIGNED) != 0
+                  && (value & (1 << (operand->bits - 1))) != 0)
+                value -= 1 << operand->bits;
+            }
+
+          /* If the operand is optional, and the value is zero, don't
+             print anything.  */
+          if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
+              && (operand->flags & PPC_OPERAND_NEXT) == 0
+              && value == 0)
+            continue;
+
+          if (need_comma)
+            {
+              printf(",");
+              need_comma = 0;
+            }
+
+          /* Print the operand as directed by the flags.  */
+          if ((operand->flags & PPC_OPERAND_GPR) != 0)
+            printf("r%ld", value);
+          else if ((operand->flags & PPC_OPERAND_FPR) != 0)
+            printf("f%ld", value);
+          else if ((operand->flags & PPC_OPERAND_VR) != 0)
+            printf("v%ld", value);
+          else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
+            print_address (memaddr + value);
+          else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
+            print_address (value & 0xffffffff);
+          else if ((operand->flags & PPC_OPERAND_CR) == 0
+                   || (dialect & PPC_OPCODE_PPC) == 0)
+            printf("%ld", value);
+          else
+            {
+              if (operand->bits == 3)
+                printf("cr%d", value);
+              else
+                {
+                  static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
+                  int cr;
+                  int cc;
+
+                  cr = value >> 2;
+                  if (cr != 0)
+                    printf("4*cr%d+", cr);
+                  cc = value & 3;
+                  printf("%s", cbnames[cc]);
+                }
+            }
+
+          if (need_paren)
+            {
+              printf(")");
+              need_paren = 0;
+            }
+
+          if ((operand->flags & PPC_OPERAND_PARENS) == 0)
+            need_comma = 1;
+          else
+            {
+              printf("(");
+              need_paren = 1;
+            }
+        }
+
+      /* We have found and printed an instruction; return.  */
+      return 4;
+    }
+
+  if ((dialect & PPC_OPCODE_ANY) != 0)
+    {
+      dialect = ~PPC_OPCODE_ANY;
+      goto again;
+    }
+
+  /* We could not find a match.  */
+  printf(".long 0x%lx", insn);
+
+  return 4;
+}
diff --git a/arch/powerpc/xmon/ppc-opc.c b/arch/powerpc/xmon/ppc-opc.c
new file mode 100644
index 000000000000..5ee8fc32f824
--- /dev/null
+++ b/arch/powerpc/xmon/ppc-opc.c
@@ -0,0 +1,4621 @@
+/* ppc-opc.c -- PowerPC opcode list
+   Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003
+   Free Software Foundation, Inc.
+   Written by Ian Lance Taylor, Cygnus Support
+
+   This file is part of GDB, GAS, and the GNU binutils.
+
+   GDB, GAS, and the GNU binutils are free software; you can redistribute
+   them and/or modify them under the terms of the GNU General Public
+   License as published by the Free Software Foundation; either version
+   2, or (at your option) any later version.
+
+   GDB, GAS, and the GNU binutils are distributed in the hope that they
+   will be useful, but WITHOUT ANY WARRANTY; without even the implied
+   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+   the GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING.  If not, write to the Free
+   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+   02111-1307, USA.  */
+
+#include <linux/stddef.h>
+#include "nonstdio.h"
+#include "ppc.h"
+
+#define ATTRIBUTE_UNUSED
+#define _(x)    x
+
+/* This file holds the PowerPC opcode table.  The opcode table
+   includes almost all of the extended instruction mnemonics.  This
+   permits the disassembler to use them, and simplifies the assembler
+   logic, at the cost of increasing the table size.  The table is
+   strictly constant data, so the compiler should be able to put it in
+   the .text section.
+
+   This file also holds the operand table.  All knowledge about
+   inserting operands into instructions and vice-versa is kept in this
+   file.  */
+
+/* Local insertion and extraction functions.  */
+
+static unsigned long insert_bat (unsigned long, long, int, const char **);
+static long extract_bat (unsigned long, int, int *);
+static unsigned long insert_bba (unsigned long, long, int, const char **);
+static long extract_bba (unsigned long, int, int *);
+static unsigned long insert_bd (unsigned long, long, int, const char **);
+static long extract_bd (unsigned long, int, int *);
+static unsigned long insert_bdm (unsigned long, long, int, const char **);
+static long extract_bdm (unsigned long, int, int *);
+static unsigned long insert_bdp (unsigned long, long, int, const char **);
+static long extract_bdp (unsigned long, int, int *);
+static unsigned long insert_bo (unsigned long, long, int, const char **);
+static long extract_bo (unsigned long, int, int *);
+static unsigned long insert_boe (unsigned long, long, int, const char **);
+static long extract_boe (unsigned long, int, int *);
+static unsigned long insert_dq (unsigned long, long, int, const char **);
+static long extract_dq (unsigned long, int, int *);
+static unsigned long insert_ds (unsigned long, long, int, const char **);
+static long extract_ds (unsigned long, int, int *);
+static unsigned long insert_de (unsigned long, long, int, const char **);
+static long extract_de (unsigned long, int, int *);
+static unsigned long insert_des (unsigned long, long, int, const char **);
+static long extract_des (unsigned long, int, int *);
+static unsigned long insert_fxm (unsigned long, long, int, const char **);
+static long extract_fxm (unsigned long, int, int *);
+static unsigned long insert_li (unsigned long, long, int, const char **);
+static long extract_li (unsigned long, int, int *);
+static unsigned long insert_mbe (unsigned long, long, int, const char **);
+static long extract_mbe (unsigned long, int, int *);
+static unsigned long insert_mb6 (unsigned long, long, int, const char **);
+static long extract_mb6 (unsigned long, int, int *);
+static unsigned long insert_nb (unsigned long, long, int, const char **);
+static long extract_nb (unsigned long, int, int *);
+static unsigned long insert_nsi (unsigned long, long, int, const char **);
+static long extract_nsi (unsigned long, int, int *);
+static unsigned long insert_ral (unsigned long, long, int, const char **);
+static unsigned long insert_ram (unsigned long, long, int, const char **);
+static unsigned long insert_raq (unsigned long, long, int, const char **);
+static unsigned long insert_ras (unsigned long, long, int, const char **);
+static unsigned long insert_rbs (unsigned long, long, int, const char **);
+static long extract_rbs (unsigned long, int, int *);
+static unsigned long insert_rsq (unsigned long, long, int, const char **);
+static unsigned long insert_rtq (unsigned long, long, int, const char **);
+static unsigned long insert_sh6 (unsigned long, long, int, const char **);
+static long extract_sh6 (unsigned long, int, int *);
+static unsigned long insert_spr (unsigned long, long, int, const char **);
+static long extract_spr (unsigned long, int, int *);
+static unsigned long insert_tbr (unsigned long, long, int, const char **);
+static long extract_tbr (unsigned long, int, int *);
+static unsigned long insert_ev2 (unsigned long, long, int, const char **);
+static long extract_ev2 (unsigned long, int, int *);
+static unsigned long insert_ev4 (unsigned long, long, int, const char **);
+static long extract_ev4 (unsigned long, int, int *);
+static unsigned long insert_ev8 (unsigned long, long, int, const char **);
+static long extract_ev8 (unsigned long, int, int *);
+
+/* The operands table.
+
+   The fields are bits, shift, insert, extract, flags.
+
+   We used to put parens around the various additions, like the one
+   for BA just below.  However, that caused trouble with feeble
+   compilers with a limit on depth of a parenthesized expression, like
+   (reportedly) the compiler in Microsoft Developer Studio 5.  So we
+   omit the parens, since the macros are never used in a context where
+   the addition will be ambiguous.  */
+
+const struct powerpc_operand powerpc_operands[] =
+{
+  /* The zero index is used to indicate the end of the list of
+     operands.  */
+#define UNUSED 0
+  { 0, 0, NULL, NULL, 0 },
+
+  /* The BA field in an XL form instruction.  */
+#define BA UNUSED + 1
+#define BA_MASK (0x1f << 16)
+  { 5, 16, NULL, NULL, PPC_OPERAND_CR },
+
+  /* The BA field in an XL form instruction when it must be the same
+     as the BT field in the same instruction.  */
+#define BAT BA + 1
+  { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
+
+  /* The BB field in an XL form instruction.  */
+#define BB BAT + 1
+#define BB_MASK (0x1f << 11)
+  { 5, 11, NULL, NULL, PPC_OPERAND_CR },
+
+  /* The BB field in an XL form instruction when it must be the same
+     as the BA field in the same instruction.  */
+#define BBA BB + 1
+  { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
+
+  /* The BD field in a B form instruction.  The lower two bits are
+     forced to zero.  */
+#define BD BBA + 1
+  { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
+
+  /* The BD field in a B form instruction when absolute addressing is
+     used.  */
+#define BDA BD + 1
+  { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
+
+  /* The BD field in a B form instruction when the - modifier is used.
+     This sets the y bit of the BO field appropriately.  */
+#define BDM BDA + 1
+  { 16, 0, insert_bdm, extract_bdm,
+      PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
+
+  /* The BD field in a B form instruction when the - modifier is used
+     and absolute address is used.  */
+#define BDMA BDM + 1
+  { 16, 0, insert_bdm, extract_bdm,
+      PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
+
+  /* The BD field in a B form instruction when the + modifier is used.
+     This sets the y bit of the BO field appropriately.  */
+#define BDP BDMA + 1
+  { 16, 0, insert_bdp, extract_bdp,
+      PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
+
+  /* The BD field in a B form instruction when the + modifier is used
+     and absolute addressing is used.  */
+#define BDPA BDP + 1
+  { 16, 0, insert_bdp, extract_bdp,
+      PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
+
+  /* The BF field in an X or XL form instruction.  */
+#define BF BDPA + 1
+  { 3, 23, NULL, NULL, PPC_OPERAND_CR },
+
+  /* An optional BF field.  This is used for comparison instructions,
+     in which an omitted BF field is taken as zero.  */
+#define OBF BF + 1
+  { 3, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
+
+  /* The BFA field in an X or XL form instruction.  */
+#define BFA OBF + 1
+  { 3, 18, NULL, NULL, PPC_OPERAND_CR },
+
+  /* The BI field in a B form or XL form instruction.  */
+#define BI BFA + 1
+#define BI_MASK (0x1f << 16)
+  { 5, 16, NULL, NULL, PPC_OPERAND_CR },
+
+  /* The BO field in a B form instruction.  Certain values are
+     illegal.  */
+#define BO BI + 1
+#define BO_MASK (0x1f << 21)
+  { 5, 21, insert_bo, extract_bo, 0 },
+
+  /* The BO field in a B form instruction when the + or - modifier is
+     used.  This is like the BO field, but it must be even.  */
+#define BOE BO + 1
+  { 5, 21, insert_boe, extract_boe, 0 },
+
+  /* The BT field in an X or XL form instruction.  */
+#define BT BOE + 1
+  { 5, 21, NULL, NULL, PPC_OPERAND_CR },
+
+  /* The condition register number portion of the BI field in a B form
+     or XL form instruction.  This is used for the extended
+     conditional branch mnemonics, which set the lower two bits of the
+     BI field.  This field is optional.  */
+#define CR BT + 1
+  { 3, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
+
+  /* The CRB field in an X form instruction.  */
+#define CRB CR + 1
+  { 5, 6, NULL, NULL, 0 },
+
+  /* The CRFD field in an X form instruction.  */
+#define CRFD CRB + 1
+  { 3, 23, NULL, NULL, PPC_OPERAND_CR },
+
+  /* The CRFS field in an X form instruction.  */
+#define CRFS CRFD + 1
+  { 3, 0, NULL, NULL, PPC_OPERAND_CR },
+
+  /* The CT field in an X form instruction.  */
+#define CT CRFS + 1
+  { 5, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
+
+  /* The D field in a D form instruction.  This is a displacement off
+     a register, and implies that the next operand is a register in
+     parentheses.  */
+#define D CT + 1
+  { 16, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
+
+  /* The DE field in a DE form instruction.  This is like D, but is 12
+     bits only.  */
+#define DE D + 1
+  { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS },
+
+  /* The DES field in a DES form instruction.  This is like DS, but is 14
+     bits only (12 stored.)  */
+#define DES DE + 1
+  { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
+
+  /* The DQ field in a DQ form instruction.  This is like D, but the
+     lower four bits are forced to zero. */
+#define DQ DES + 1
+  { 16, 0, insert_dq, extract_dq,
+      PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
+
+  /* The DS field in a DS form instruction.  This is like D, but the
+     lower two bits are forced to zero.  */
+#define DS DQ + 1
+  { 16, 0, insert_ds, extract_ds,
+      PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
+
+  /* The E field in a wrteei instruction.  */
+#define E DS + 1
+  { 1, 15, NULL, NULL, 0 },
+
+  /* The FL1 field in a POWER SC form instruction.  */
+#define FL1 E + 1
+  { 4, 12, NULL, NULL, 0 },
+
+  /* The FL2 field in a POWER SC form instruction.  */
+#define FL2 FL1 + 1
+  { 3, 2, NULL, NULL, 0 },
+
+  /* The FLM field in an XFL form instruction.  */
+#define FLM FL2 + 1
+  { 8, 17, NULL, NULL, 0 },
+
+  /* The FRA field in an X or A form instruction.  */
+#define FRA FLM + 1
+#define FRA_MASK (0x1f << 16)
+  { 5, 16, NULL, NULL, PPC_OPERAND_FPR },
+
+  /* The FRB field in an X or A form instruction.  */
+#define FRB FRA + 1
+#define FRB_MASK (0x1f << 11)
+  { 5, 11, NULL, NULL, PPC_OPERAND_FPR },
+
+  /* The FRC field in an A form instruction.  */
+#define FRC FRB + 1
+#define FRC_MASK (0x1f << 6)
+  { 5, 6, NULL, NULL, PPC_OPERAND_FPR },
+
+  /* The FRS field in an X form instruction or the FRT field in a D, X
+     or A form instruction.  */
+#define FRS FRC + 1
+#define FRT FRS
+  { 5, 21, NULL, NULL, PPC_OPERAND_FPR },
+
+  /* The FXM field in an XFX instruction.  */
+#define FXM FRS + 1
+#define FXM_MASK (0xff << 12)
+  { 8, 12, insert_fxm, extract_fxm, 0 },
+
+  /* Power4 version for mfcr.  */
+#define FXM4 FXM + 1
+  { 8, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
+
+  /* The L field in a D or X form instruction.  */
+#define L FXM4 + 1
+  { 1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
+
+  /* The LEV field in a POWER SC form instruction.  */
+#define LEV L + 1
+  { 7, 5, NULL, NULL, 0 },
+
+  /* The LI field in an I form instruction.  The lower two bits are
+     forced to zero.  */
+#define LI LEV + 1
+  { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
+
+  /* The LI field in an I form instruction when used as an absolute
+     address.  */
+#define LIA LI + 1
+  { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
+
+  /* The LS field in an X (sync) form instruction.  */
+#define LS LIA + 1
+  { 2, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
+
+  /* The MB field in an M form instruction.  */
+#define MB LS + 1
+#define MB_MASK (0x1f << 6)
+  { 5, 6, NULL, NULL, 0 },
+
+  /* The ME field in an M form instruction.  */
+#define ME MB + 1
+#define ME_MASK (0x1f << 1)
+  { 5, 1, NULL, NULL, 0 },
+
+  /* The MB and ME fields in an M form instruction expressed a single
+     operand which is a bitmask indicating which bits to select.  This
+     is a two operand form using PPC_OPERAND_NEXT.  See the
+     description in opcode/ppc.h for what this means.  */
+#define MBE ME + 1
+  { 5, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
+  { 32, 0, insert_mbe, extract_mbe, 0 },
+
+  /* The MB or ME field in an MD or MDS form instruction.  The high
+     bit is wrapped to the low end.  */
+#define MB6 MBE + 2
+#define ME6 MB6
+#define MB6_MASK (0x3f << 5)
+  { 6, 5, insert_mb6, extract_mb6, 0 },
+
+  /* The MO field in an mbar instruction.  */
+#define MO MB6 + 1
+  { 5, 21, NULL, NULL, 0 },
+
+  /* The NB field in an X form instruction.  The value 32 is stored as
+     0.  */
+#define NB MO + 1
+  { 6, 11, insert_nb, extract_nb, 0 },
+
+  /* The NSI field in a D form instruction.  This is the same as the
+     SI field, only negated.  */
+#define NSI NB + 1
+  { 16, 0, insert_nsi, extract_nsi,
+      PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
+
+  /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction.  */
+#define RA NSI + 1
+#define RA_MASK (0x1f << 16)
+  { 5, 16, NULL, NULL, PPC_OPERAND_GPR },
+
+  /* The RA field in the DQ form lq instruction, which has special
+     value restrictions.  */
+#define RAQ RA + 1
+  { 5, 16, insert_raq, NULL, PPC_OPERAND_GPR },
+
+  /* The RA field in a D or X form instruction which is an updating
+     load, which means that the RA field may not be zero and may not
+     equal the RT field.  */
+#define RAL RAQ + 1
+  { 5, 16, insert_ral, NULL, PPC_OPERAND_GPR },
+
+  /* The RA field in an lmw instruction, which has special value
+     restrictions.  */
+#define RAM RAL + 1
+  { 5, 16, insert_ram, NULL, PPC_OPERAND_GPR },
+
+  /* The RA field in a D or X form instruction which is an updating
+     store or an updating floating point load, which means that the RA
+     field may not be zero.  */
+#define RAS RAM + 1
+  { 5, 16, insert_ras, NULL, PPC_OPERAND_GPR },
+
+  /* The RB field in an X, XO, M, or MDS form instruction.  */
+#define RB RAS + 1
+#define RB_MASK (0x1f << 11)
+  { 5, 11, NULL, NULL, PPC_OPERAND_GPR },
+
+  /* The RB field in an X form instruction when it must be the same as
+     the RS field in the instruction.  This is used for extended
+     mnemonics like mr.  */
+#define RBS RB + 1
+  { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
+
+  /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
+     instruction or the RT field in a D, DS, X, XFX or XO form
+     instruction.  */
+#define RS RBS + 1
+#define RT RS
+#define RT_MASK (0x1f << 21)
+  { 5, 21, NULL, NULL, PPC_OPERAND_GPR },
+
+  /* The RS field of the DS form stq instruction, which has special
+     value restrictions.  */
+#define RSQ RS + 1
+  { 5, 21, insert_rsq, NULL, PPC_OPERAND_GPR },
+
+  /* The RT field of the DQ form lq instruction, which has special
+     value restrictions.  */
+#define RTQ RSQ + 1
+  { 5, 21, insert_rtq, NULL, PPC_OPERAND_GPR },
+
+  /* The SH field in an X or M form instruction.  */
+#define SH RTQ + 1
+#define SH_MASK (0x1f << 11)
+  { 5, 11, NULL, NULL, 0 },
+
+  /* The SH field in an MD form instruction.  This is split.  */
+#define SH6 SH + 1
+#define SH6_MASK ((0x1f << 11) | (1 << 1))
+  { 6, 1, insert_sh6, extract_sh6, 0 },
+
+  /* The SI field in a D form instruction.  */
+#define SI SH6 + 1
+  { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED },
+
+  /* The SI field in a D form instruction when we accept a wide range
+     of positive values.  */
+#define SISIGNOPT SI + 1
+  { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
+
+  /* The SPR field in an XFX form instruction.  This is flipped--the
+     lower 5 bits are stored in the upper 5 and vice- versa.  */
+#define SPR SISIGNOPT + 1
+#define PMR SPR
+#define SPR_MASK (0x3ff << 11)
+  { 10, 11, insert_spr, extract_spr, 0 },
+
+  /* The BAT index number in an XFX form m[ft]ibat[lu] instruction.  */
+#define SPRBAT SPR + 1
+#define SPRBAT_MASK (0x3 << 17)
+  { 2, 17, NULL, NULL, 0 },
+
+  /* The SPRG register number in an XFX form m[ft]sprg instruction.  */
+#define SPRG SPRBAT + 1
+#define SPRG_MASK (0x3 << 16)
+  { 2, 16, NULL, NULL, 0 },
+
+  /* The SR field in an X form instruction.  */
+#define SR SPRG + 1
+  { 4, 16, NULL, NULL, 0 },
+
+  /* The STRM field in an X AltiVec form instruction.  */
+#define STRM SR + 1
+#define STRM_MASK (0x3 << 21)
+  { 2, 21, NULL, NULL, 0 },
+
+  /* The SV field in a POWER SC form instruction.  */
+#define SV STRM + 1
+  { 14, 2, NULL, NULL, 0 },
+
+  /* The TBR field in an XFX form instruction.  This is like the SPR
+     field, but it is optional.  */
+#define TBR SV + 1
+  { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
+
+  /* The TO field in a D or X form instruction.  */
+#define TO TBR + 1
+#define TO_MASK (0x1f << 21)
+  { 5, 21, NULL, NULL, 0 },
+
+  /* The U field in an X form instruction.  */
+#define U TO + 1
+  { 4, 12, NULL, NULL, 0 },
+
+  /* The UI field in a D form instruction.  */
+#define UI U + 1
+  { 16, 0, NULL, NULL, 0 },
+
+  /* The VA field in a VA, VX or VXR form instruction.  */
+#define VA UI + 1
+#define VA_MASK (0x1f << 16)
+  { 5, 16, NULL, NULL, PPC_OPERAND_VR },
+
+  /* The VB field in a VA, VX or VXR form instruction.  */
+#define VB VA + 1
+#define VB_MASK (0x1f << 11)
+  { 5, 11, NULL, NULL, PPC_OPERAND_VR },
+
+  /* The VC field in a VA form instruction.  */
+#define VC VB + 1
+#define VC_MASK (0x1f << 6)
+  { 5, 6, NULL, NULL, PPC_OPERAND_VR },
+
+  /* The VD or VS field in a VA, VX, VXR or X form instruction.  */
+#define VD VC + 1
+#define VS VD
+#define VD_MASK (0x1f << 21)
+  { 5, 21, NULL, NULL, PPC_OPERAND_VR },
+
+  /* The SIMM field in a VX form instruction.  */
+#define SIMM VD + 1
+  { 5, 16, NULL, NULL, PPC_OPERAND_SIGNED},
+
+  /* The UIMM field in a VX form instruction.  */
+#define UIMM SIMM + 1
+  { 5, 16, NULL, NULL, 0 },
+
+  /* The SHB field in a VA form instruction.  */
+#define SHB UIMM + 1
+  { 4, 6, NULL, NULL, 0 },
+
+  /* The other UIMM field in a EVX form instruction.  */
+#define EVUIMM SHB + 1
+  { 5, 11, NULL, NULL, 0 },
+
+  /* The other UIMM field in a half word EVX form instruction.  */
+#define EVUIMM_2 EVUIMM + 1
+  { 32, 11, insert_ev2, extract_ev2, PPC_OPERAND_PARENS },
+
+  /* The other UIMM field in a word EVX form instruction.  */
+#define EVUIMM_4 EVUIMM_2 + 1
+  { 32, 11, insert_ev4, extract_ev4, PPC_OPERAND_PARENS },
+
+  /* The other UIMM field in a double EVX form instruction.  */
+#define EVUIMM_8 EVUIMM_4 + 1
+  { 32, 11, insert_ev8, extract_ev8, PPC_OPERAND_PARENS },
+
+  /* The WS field.  */
+#define WS EVUIMM_8 + 1
+#define WS_MASK (0x7 << 11)
+  { 3, 11, NULL, NULL, 0 },
+
+  /* The L field in an mtmsrd instruction */
+#define MTMSRD_L WS + 1
+  { 1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
+
+};
+
+/* The functions used to insert and extract complicated operands.  */
+
+/* The BA field in an XL form instruction when it must be the same as
+   the BT field in the same instruction.  This operand is marked FAKE.
+   The insertion function just copies the BT field into the BA field,
+   and the extraction function just checks that the fields are the
+   same.  */
+
+/*ARGSUSED*/
+static unsigned long
+insert_bat (unsigned long insn,
+            long value ATTRIBUTE_UNUSED,
+            int dialect ATTRIBUTE_UNUSED,
+            const char **errmsg ATTRIBUTE_UNUSED)
+{
+  return insn | (((insn >> 21) & 0x1f) << 16);
+}
+
+static long
+extract_bat (unsigned long insn,
+             int dialect ATTRIBUTE_UNUSED,
+             int *invalid)
+{
+  if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
+    *invalid = 1;
+  return 0;
+}
+
+/* The BB field in an XL form instruction when it must be the same as
+   the BA field in the same instruction.  This operand is marked FAKE.
+   The insertion function just copies the BA field into the BB field,
+   and the extraction function just checks that the fields are the
+   same.  */
+
+/*ARGSUSED*/
+static unsigned long
+insert_bba (unsigned long insn,
+            long value ATTRIBUTE_UNUSED,
+            int dialect ATTRIBUTE_UNUSED,
+            const char **errmsg ATTRIBUTE_UNUSED)
+{
+  return insn | (((insn >> 16) & 0x1f) << 11);
+}
+
+static long
+extract_bba (unsigned long insn,
+             int dialect ATTRIBUTE_UNUSED,
+             int *invalid)
+{
+  if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
+    *invalid = 1;
+  return 0;
+}
+
+/* The BD field in a B form instruction.  The lower two bits are
+   forced to zero.  */
+
+/*ARGSUSED*/
+static unsigned long
+insert_bd (unsigned long insn,
+           long value,
+           int dialect ATTRIBUTE_UNUSED,
+           const char **errmsg ATTRIBUTE_UNUSED)
+{
+  return insn | (value & 0xfffc);
+}
+
+/*ARGSUSED*/
+static long
+extract_bd (unsigned long insn,
+            int dialect ATTRIBUTE_UNUSED,
+            int *invalid ATTRIBUTE_UNUSED)
+{
+  return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
+}
+
+/* The BD field in a B form instruction when the - modifier is used.
+   This modifier means that the branch is not expected to be taken.
+   For chips built to versions of the architecture prior to version 2
+   (ie. not Power4 compatible), we set the y bit of the BO field to 1
+   if the offset is negative.  When extracting, we require that the y
+   bit be 1 and that the offset be positive, since if the y bit is 0
+   we just want to print the normal form of the instruction.
+   Power4 compatible targets use two bits, "a", and "t", instead of
+   the "y" bit.  "at" == 00 => no hint, "at" == 01 => unpredictable,
+   "at" == 10 => not taken, "at" == 11 => taken.  The "t" bit is 00001
+   in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
+   for branch on CTR.  We only handle the taken/not-taken hint here.  */
+
+/*ARGSUSED*/
+static unsigned long
+insert_bdm (unsigned long insn,
+            long value,
+            int dialect,
+            const char **errmsg ATTRIBUTE_UNUSED)
+{
+  if ((dialect & PPC_OPCODE_POWER4) == 0)
+    {
+      if ((value & 0x8000) != 0)
+        insn |= 1 << 21;
+    }
+  else
+    {
+      if ((insn & (0x14 << 21)) == (0x04 << 21))
+        insn |= 0x02 << 21;
+      else if ((insn & (0x14 << 21)) == (0x10 << 21))
+        insn |= 0x08 << 21;
+    }
+  return insn | (value & 0xfffc);
+}
+
+static long
+extract_bdm (unsigned long insn,
+             int dialect,
+             int *invalid)
+{
+  if ((dialect & PPC_OPCODE_POWER4) == 0)
+    {
+      if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
+        *invalid = 1;
+    }
+  else
+    {
+      if ((insn & (0x17 << 21)) != (0x06 << 21)
+          && (insn & (0x1d << 21)) != (0x18 << 21))
+        *invalid = 1;
+    }
+
+  return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
+}
+
+/* The BD field in a B form instruction when the + modifier is used.
+   This is like BDM, above, except that the branch is expected to be
+   taken.  */
+
+/*ARGSUSED*/
+static unsigned long
+insert_bdp (unsigned long insn,
+            long value,
+            int dialect,
+            const char **errmsg ATTRIBUTE_UNUSED)
+{
+  if ((dialect & PPC_OPCODE_POWER4) == 0)
+    {
+      if ((value & 0x8000) == 0)
+        insn |= 1 << 21;
+    }
+  else
+    {
+      if ((insn & (0x14 << 21)) == (0x04 << 21))
+        insn |= 0x03 << 21;
+      else if ((insn & (0x14 << 21)) == (0x10 << 21))
+        insn |= 0x09 << 21;
+    }
+  return insn | (value & 0xfffc);
+}
+
+static long
+extract_bdp (unsigned long insn,
+             int dialect,
+             int *invalid)
+{
+  if ((dialect & PPC_OPCODE_POWER4) == 0)
+    {
+      if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
+        *invalid = 1;
+    }
+  else
+    {
+      if ((insn & (0x17 << 21)) != (0x07 << 21)
+          && (insn & (0x1d << 21)) != (0x19 << 21))
+        *invalid = 1;
+    }
+
+  return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
+}
+
+/* Check for legal values of a BO field.  */
+
+static int
+valid_bo (long value, int dialect)
+{
+  if ((dialect & PPC_OPCODE_POWER4) == 0)
+    {
+      /* Certain encodings have bits that are required to be zero.
+         These are (z must be zero, y may be anything):
+             001zy
+             011zy
+             1z00y
+             1z01y
+             1z1zz
+      */
+      switch (value & 0x14)
+        {
+        default:
+        case 0:
+          return 1;
+        case 0x4:
+          return (value & 0x2) == 0;
+        case 0x10:
+          return (value & 0x8) == 0;
+        case 0x14:
+          return value == 0x14;
+        }
+    }
+  else
+    {
+      /* Certain encodings have bits that are required to be zero.
+         These are (z must be zero, a & t may be anything):
+             0000z
+             0001z
+             0100z
+             0101z
+             001at
+             011at
+             1a00t
+             1a01t
+             1z1zz
+      */
+      if ((value & 0x14) == 0)
+        return (value & 0x1) == 0;
+      else if ((value & 0x14) == 0x14)
+        return value == 0x14;
+      else
+        return 1;
+    }
+}
+
+/* The BO field in a B form instruction.  Warn about attempts to set
+   the field to an illegal value.  */
+
+static unsigned long
+insert_bo (unsigned long insn,
+           long value,
+           int dialect,
+           const char **errmsg)
+{
+  if (!valid_bo (value, dialect))
+    *errmsg = _("invalid conditional option");
+  return insn | ((value & 0x1f) << 21);
+}
+
+static long
+extract_bo (unsigned long insn,
+            int dialect,
+            int *invalid)
+{
+  long value;
+
+  value = (insn >> 21) & 0x1f;
+  if (!valid_bo (value, dialect))
+    *invalid = 1;
+  return value;
+}
+
+/* The BO field in a B form instruction when the + or - modifier is
+   used.  This is like the BO field, but it must be even.  When
+   extracting it, we force it to be even.  */
+
+static unsigned long
+insert_boe (unsigned long insn,
+            long value,
+            int dialect,
+            const char **errmsg)
+{
+  if (!valid_bo (value, dialect))
+    *errmsg = _("invalid conditional option");
+  else if ((value & 1) != 0)
+    *errmsg = _("attempt to set y bit when using + or - modifier");
+
+  return insn | ((value & 0x1f) << 21);
+}
+
+static long
+extract_boe (unsigned long insn,
+             int dialect,
+             int *invalid)
+{
+  long value;
+
+  value = (insn >> 21) & 0x1f;
+  if (!valid_bo (value, dialect))
+    *invalid = 1;
+  return value & 0x1e;
+}
+
+/* The DQ field in a DQ form instruction.  This is like D, but the
+   lower four bits are forced to zero. */
+
+/*ARGSUSED*/
+static unsigned long
+insert_dq (unsigned long insn,
+           long value,
+           int dialect ATTRIBUTE_UNUSED,
+           const char **errmsg)
+{
+  if ((value & 0xf) != 0)
+    *errmsg = _("offset not a multiple of 16");
+  return insn | (value & 0xfff0);
+}
+
+/*ARGSUSED*/
+static long
+extract_dq (unsigned long insn,
+            int dialect ATTRIBUTE_UNUSED,
+            int *invalid ATTRIBUTE_UNUSED)
+{
+  return ((insn & 0xfff0) ^ 0x8000) - 0x8000;
+}
+
+static unsigned long
+insert_ev2 (unsigned long insn,
+            long value,
+            int dialect ATTRIBUTE_UNUSED,
+            const char **errmsg)
+{
+  if ((value & 1) != 0)
+    *errmsg = _("offset not a multiple of 2");
+  if ((value > 62) != 0)
+    *errmsg = _("offset greater than 62");
+  return insn | ((value & 0x3e) << 10);
+}
+
+static long
+extract_ev2 (unsigned long insn,
+             int dialect ATTRIBUTE_UNUSED,
+             int *invalid ATTRIBUTE_UNUSED)
+{
+  return (insn >> 10) & 0x3e;
+}
+
+static unsigned long
+insert_ev4 (unsigned long insn,
+            long value,
+            int dialect ATTRIBUTE_UNUSED,
+            const char **errmsg)
+{
+  if ((value & 3) != 0)
+    *errmsg = _("offset not a multiple of 4");
+  if ((value > 124) != 0)
+    *errmsg = _("offset greater than 124");
+  return insn | ((value & 0x7c) << 9);
+}
+
+static long
+extract_ev4 (unsigned long insn,
+             int dialect ATTRIBUTE_UNUSED,
+             int *invalid ATTRIBUTE_UNUSED)
+{
+  return (insn >> 9) & 0x7c;
+}
+
+static unsigned long
+insert_ev8 (unsigned long insn,
+            long value,
+            int dialect ATTRIBUTE_UNUSED,
+            const char **errmsg)
+{
+  if ((value & 7) != 0)
+    *errmsg = _("offset not a multiple of 8");
+  if ((value > 248) != 0)
+    *errmsg = _("offset greater than 248");
+  return insn | ((value & 0xf8) << 8);
+}
+
+static long
+extract_ev8 (unsigned long insn,
+             int dialect ATTRIBUTE_UNUSED,
+             int *invalid ATTRIBUTE_UNUSED)
+{
+  return (insn >> 8) & 0xf8;
+}
+
+/* The DS field in a DS form instruction.  This is like D, but the
+   lower two bits are forced to zero.  */
+
+/*ARGSUSED*/
+static unsigned long
+insert_ds (unsigned long insn,
+           long value,
+           int dialect ATTRIBUTE_UNUSED,
+           const char **errmsg)
+{
+  if ((value & 3) != 0)
+    *errmsg = _("offset not a multiple of 4");
+  return insn | (value & 0xfffc);
+}
+
+/*ARGSUSED*/
+static long
+extract_ds (unsigned long insn,
+            int dialect ATTRIBUTE_UNUSED,
+            int *invalid ATTRIBUTE_UNUSED)
+{
+  return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
+}
+
+/* The DE field in a DE form instruction.  */
+
+/*ARGSUSED*/
+static unsigned long
+insert_de (unsigned long insn,
+           long value,
+           int dialect ATTRIBUTE_UNUSED,
+           const char **errmsg)
+{
+  if (value > 2047 || value < -2048)
+    *errmsg = _("offset not between -2048 and 2047");
+  return insn | ((value << 4) & 0xfff0);
+}
+
+/*ARGSUSED*/
+static long
+extract_de (unsigned long insn,
+            int dialect ATTRIBUTE_UNUSED,
+            int *invalid ATTRIBUTE_UNUSED)
+{
+  return (insn & 0xfff0) >> 4;
+}
+
+/* The DES field in a DES form instruction.  */
+
+/*ARGSUSED*/
+static unsigned long
+insert_des (unsigned long insn,
+            long value,
+            int dialect ATTRIBUTE_UNUSED,
+            const char **errmsg)
+{
+  if (value > 8191 || value < -8192)
+    *errmsg = _("offset not between -8192 and 8191");
+  else if ((value & 3) != 0)
+    *errmsg = _("offset not a multiple of 4");
+  return insn | ((value << 2) & 0xfff0);
+}
+
+/*ARGSUSED*/
+static long
+extract_des (unsigned long insn,
+             int dialect ATTRIBUTE_UNUSED,
+             int *invalid ATTRIBUTE_UNUSED)
+{
+  return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000;
+}
+
+/* FXM mask in mfcr and mtcrf instructions.  */
+
+static unsigned long
+insert_fxm (unsigned long insn,
+            long value,
+            int dialect,
+            const char **errmsg)
+{
+  /* If the optional field on mfcr is missing that means we want to use
+     the old form of the instruction that moves the whole cr.  In that
+     case we'll have VALUE zero.  There doesn't seem to be a way to
+     distinguish this from the case where someone writes mfcr %r3,0.  */
+  if (value == 0)
+    ;
+
+  /* If only one bit of the FXM field is set, we can use the new form
+     of the instruction, which is faster.  Unlike the Power4 branch hint
+     encoding, this is not backward compatible.  */
+  else if ((dialect & PPC_OPCODE_POWER4) != 0 && (value & -value) == value)
+    insn |= 1 << 20;
+
+  /* Any other value on mfcr is an error.  */
+  else if ((insn & (0x3ff << 1)) == 19 << 1)
+    {
+      *errmsg = _("ignoring invalid mfcr mask");
+      value = 0;
+    }
+
+  return insn | ((value & 0xff) << 12);
+}
+
+static long
+extract_fxm (unsigned long insn,
+             int dialect,
+             int *invalid)
+{
+  long mask = (insn >> 12) & 0xff;
+
+  /* Is this a Power4 insn?  */
+  if ((insn & (1 << 20)) != 0)
+    {
+      if ((dialect & PPC_OPCODE_POWER4) == 0)
+        *invalid = 1;
+      else
+        {
+          /* Exactly one bit of MASK should be set.  */
+          if (mask == 0 || (mask & -mask) != mask)
+            *invalid = 1;
+        }
+    }
+
+  /* Check that non-power4 form of mfcr has a zero MASK.  */
+  else if ((insn & (0x3ff << 1)) == 19 << 1)
+    {
+      if (mask != 0)
+        *invalid = 1;
+    }
+
+  return mask;
+}
+
+/* The LI field in an I form instruction.  The lower two bits are
+   forced to zero.  */
+
+/*ARGSUSED*/
+static unsigned long
+insert_li (unsigned long insn,
+           long value,
+           int dialect ATTRIBUTE_UNUSED,
+           const char **errmsg)
+{
+  if ((value & 3) != 0)
+    *errmsg = _("ignoring least significant bits in branch offset");
+  return insn | (value & 0x3fffffc);
+}
+
+/*ARGSUSED*/
+static long
+extract_li (unsigned long insn,
+            int dialect ATTRIBUTE_UNUSED,
+            int *invalid ATTRIBUTE_UNUSED)
+{
+  return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000;
+}
+
+/* The MB and ME fields in an M form instruction expressed as a single
+   operand which is itself a bitmask.  The extraction function always
+   marks it as invalid, since we never want to recognize an
+   instruction which uses a field of this type.  */
+
+static unsigned long
+insert_mbe (unsigned long insn,
+            long value,
+            int dialect ATTRIBUTE_UNUSED,
+            const char **errmsg)
+{
+  unsigned long uval, mask;
+  int mb, me, mx, count, last;
+
+  uval = value;
+
+  if (uval == 0)
+    {
+      *errmsg = _("illegal bitmask");
+      return insn;
+    }
+
+  mb = 0;
+  me = 32;
+  if ((uval & 1) != 0)
+    last = 1;
+  else
+    last = 0;
+  count = 0;
+
+  /* mb: location of last 0->1 transition */
+  /* me: location of last 1->0 transition */
+  /* count: # transitions */
+
+  for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
+    {
+      if ((uval & mask) && !last)
+        {
+          ++count;
+          mb = mx;
+          last = 1;
+        }
+      else if (!(uval & mask) && last)
+        {
+          ++count;
+          me = mx;
+          last = 0;
+        }
+    }
+  if (me == 0)
+    me = 32;
+
+  if (count != 2 && (count != 0 || ! last))
+    *errmsg = _("illegal bitmask");
+
+  return insn | (mb << 6) | ((me - 1) << 1);
+}
+
+static long
+extract_mbe (unsigned long insn,
+             int dialect ATTRIBUTE_UNUSED,
+             int *invalid)
+{
+  long ret;
+  int mb, me;
+  int i;
+
+  *invalid = 1;
+
+  mb = (insn >> 6) & 0x1f;
+  me = (insn >> 1) & 0x1f;
+  if (mb < me + 1)
+    {
+      ret = 0;
+      for (i = mb; i <= me; i++)
+        ret |= 1L << (31 - i);
+    }
+  else if (mb == me + 1)
+    ret = ~0;
+  else /* (mb > me + 1) */
+    {
+      ret = ~0;
+      for (i = me + 1; i < mb; i++)
+        ret &= ~(1L << (31 - i));
+    }
+  return ret;
+}
+
+/* The MB or ME field in an MD or MDS form instruction.  The high bit
+   is wrapped to the low end.  */
+
+/*ARGSUSED*/
+static unsigned long
+insert_mb6 (unsigned long insn,
+            long value,
+            int dialect ATTRIBUTE_UNUSED,
+            const char **errmsg ATTRIBUTE_UNUSED)
+{
+  return insn | ((value & 0x1f) << 6) | (value & 0x20);
+}
+
+/*ARGSUSED*/
+static long
+extract_mb6 (unsigned long insn,
+             int dialect ATTRIBUTE_UNUSED,
+             int *invalid ATTRIBUTE_UNUSED)
+{
+  return ((insn >> 6) & 0x1f) | (insn & 0x20);
+}
+
+/* The NB field in an X form instruction.  The value 32 is stored as
+   0.  */
+
+static unsigned long
+insert_nb (unsigned long insn,
+           long value,
+           int dialect ATTRIBUTE_UNUSED,
+           const char **errmsg)
+{
+  if (value < 0 || value > 32)
+    *errmsg = _("value out of range");
+  if (value == 32)
+    value = 0;
+  return insn | ((value & 0x1f) << 11);
+}
+
+/*ARGSUSED*/
+static long
+extract_nb (unsigned long insn,
+            int dialect ATTRIBUTE_UNUSED,
+            int *invalid ATTRIBUTE_UNUSED)
+{
+  long ret;
+
+  ret = (insn >> 11) & 0x1f;
+  if (ret == 0)
+    ret = 32;
+  return ret;
+}
+
+/* The NSI field in a D form instruction.  This is the same as the SI
+   field, only negated.  The extraction function always marks it as
+   invalid, since we never want to recognize an instruction which uses
+   a field of this type.  */
+
+/*ARGSUSED*/
+static unsigned long
+insert_nsi (unsigned long insn,
+            long value,
+            int dialect ATTRIBUTE_UNUSED,
+            const char **errmsg ATTRIBUTE_UNUSED)
+{
+  return insn | (-value & 0xffff);
+}
+
+static long
+extract_nsi (unsigned long insn,
+             int dialect ATTRIBUTE_UNUSED,
+             int *invalid)
+{
+  *invalid = 1;
+  return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
+}
+
+/* The RA field in a D or X form instruction which is an updating
+   load, which means that the RA field may not be zero and may not
+   equal the RT field.  */
+
+static unsigned long
+insert_ral (unsigned long insn,
+            long value,
+            int dialect ATTRIBUTE_UNUSED,
+            const char **errmsg)
+{
+  if (value == 0
+      || (unsigned long) value == ((insn >> 21) & 0x1f))
+    *errmsg = "invalid register operand when updating";
+  return insn | ((value & 0x1f) << 16);
+}
+
+/* The RA field in an lmw instruction, which has special value
+   restrictions.  */
+
+static unsigned long
+insert_ram (unsigned long insn,
+            long value,
+            int dialect ATTRIBUTE_UNUSED,
+            const char **errmsg)
+{
+  if ((unsigned long) value >= ((insn >> 21) & 0x1f))
+    *errmsg = _("index register in load range");
+  return insn | ((value & 0x1f) << 16);
+}
+
+/* The RA field in the DQ form lq instruction, which has special
+   value restrictions.  */
+
+/*ARGSUSED*/
+static unsigned long
+insert_raq (unsigned long insn,
+            long value,
+            int dialect ATTRIBUTE_UNUSED,
+            const char **errmsg)
+{
+  long rtvalue = (insn & RT_MASK) >> 21;
+
+  if (value == rtvalue)
+    *errmsg = _("source and target register operands must be different");
+  return insn | ((value & 0x1f) << 16);
+}
+
+/* The RA field in a D or X form instruction which is an updating
+   store or an updating floating point load, which means that the RA
+   field may not be zero.  */
+
+static unsigned long
+insert_ras (unsigned long insn,
+            long value,
+            int dialect ATTRIBUTE_UNUSED,
+            const char **errmsg)
+{
+  if (value == 0)
+    *errmsg = _("invalid register operand when updating");
+  return insn | ((value & 0x1f) << 16);
+}
+
+/* The RB field in an X form instruction when it must be the same as
+   the RS field in the instruction.  This is used for extended
+   mnemonics like mr.  This operand is marked FAKE.  The insertion
+   function just copies the BT field into the BA field, and the
+   extraction function just checks that the fields are the same.  */
+
+/*ARGSUSED*/
+static unsigned long
+insert_rbs (unsigned long insn,
+            long value ATTRIBUTE_UNUSED,
+            int dialect ATTRIBUTE_UNUSED,
+            const char **errmsg ATTRIBUTE_UNUSED)
+{
+  return insn | (((insn >> 21) & 0x1f) << 11);
+}
+
+static long
+extract_rbs (unsigned long insn,
+             int dialect ATTRIBUTE_UNUSED,
+             int *invalid)
+{
+  if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
+    *invalid = 1;
+  return 0;
+}
+
+/* The RT field of the DQ form lq instruction, which has special
+   value restrictions.  */
+
+/*ARGSUSED*/
+static unsigned long
+insert_rtq (unsigned long insn,
+            long value,
+            int dialect ATTRIBUTE_UNUSED,
+            const char **errmsg)
+{
+  if ((value & 1) != 0)
+    *errmsg = _("target register operand must be even");
+  return insn | ((value & 0x1f) << 21);
+}
+
+/* The RS field of the DS form stq instruction, which has special
+   value restrictions.  */
+
+/*ARGSUSED*/
+static unsigned long
+insert_rsq (unsigned long insn,
+            long value ATTRIBUTE_UNUSED,
+            int dialect ATTRIBUTE_UNUSED,
+            const char **errmsg)
+{
+  if ((value & 1) != 0)
+    *errmsg = _("source register operand must be even");
+  return insn | ((value & 0x1f) << 21);
+}
+
+/* The SH field in an MD form instruction.  This is split.  */
+
+/*ARGSUSED*/
+static unsigned long
+insert_sh6 (unsigned long insn,
+            long value,
+            int dialect ATTRIBUTE_UNUSED,
+            const char **errmsg ATTRIBUTE_UNUSED)
+{
+  return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
+}
+
+/*ARGSUSED*/
+static long
+extract_sh6 (unsigned long insn,
+             int dialect ATTRIBUTE_UNUSED,
+             int *invalid ATTRIBUTE_UNUSED)
+{
+  return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
+}
+
+/* The SPR field in an XFX form instruction.  This is flipped--the
+   lower 5 bits are stored in the upper 5 and vice- versa.  */
+
+static unsigned long
+insert_spr (unsigned long insn,
+            long value,
+            int dialect ATTRIBUTE_UNUSED,
+            const char **errmsg ATTRIBUTE_UNUSED)
+{
+  return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
+}
+
+static long
+extract_spr (unsigned long insn,
+             int dialect ATTRIBUTE_UNUSED,
+             int *invalid ATTRIBUTE_UNUSED)
+{
+  return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
+}
+
+/* The TBR field in an XFX instruction.  This is just like SPR, but it
+   is optional.  When TBR is omitted, it must be inserted as 268 (the
+   magic number of the TB register).  These functions treat 0
+   (indicating an omitted optional operand) as 268.  This means that
+   ``mftb 4,0'' is not handled correctly.  This does not matter very
+   much, since the architecture manual does not define mftb as
+   accepting any values other than 268 or 269.  */
+
+#define TB (268)
+
+static unsigned long
+insert_tbr (unsigned long insn,
+            long value,
+            int dialect ATTRIBUTE_UNUSED,
+            const char **errmsg ATTRIBUTE_UNUSED)
+{
+  if (value == 0)
+    value = TB;
+  return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
+}
+
+static long
+extract_tbr (unsigned long insn,
+             int dialect ATTRIBUTE_UNUSED,
+             int *invalid ATTRIBUTE_UNUSED)
+{
+  long ret;
+
+  ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
+  if (ret == TB)
+    ret = 0;
+  return ret;
+}
+
+/* Macros used to form opcodes.  */
+
+/* The main opcode.  */
+#define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
+#define OP_MASK OP (0x3f)
+
+/* The main opcode combined with a trap code in the TO field of a D
+   form instruction.  Used for extended mnemonics for the trap
+   instructions.  */
+#define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
+#define OPTO_MASK (OP_MASK | TO_MASK)
+
+/* The main opcode combined with a comparison size bit in the L field
+   of a D form or X form instruction.  Used for extended mnemonics for
+   the comparison instructions.  */
+#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
+#define OPL_MASK OPL (0x3f,1)
+
+/* An A form instruction.  */
+#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
+#define A_MASK A (0x3f, 0x1f, 1)
+
+/* An A_MASK with the FRB field fixed.  */
+#define AFRB_MASK (A_MASK | FRB_MASK)
+
+/* An A_MASK with the FRC field fixed.  */
+#define AFRC_MASK (A_MASK | FRC_MASK)
+
+/* An A_MASK with the FRA and FRC fields fixed.  */
+#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
+
+/* A B form instruction.  */
+#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
+#define B_MASK B (0x3f, 1, 1)
+
+/* A B form instruction setting the BO field.  */
+#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
+#define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
+
+/* A BBO_MASK with the y bit of the BO field removed.  This permits
+   matching a conditional branch regardless of the setting of the y
+   bit.  Similarly for the 'at' bits used for power4 branch hints.  */
+#define Y_MASK   (((unsigned long) 1) << 21)
+#define AT1_MASK (((unsigned long) 3) << 21)
+#define AT2_MASK (((unsigned long) 9) << 21)
+#define BBOY_MASK  (BBO_MASK &~ Y_MASK)
+#define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
+
+/* A B form instruction setting the BO field and the condition bits of
+   the BI field.  */
+#define BBOCB(op, bo, cb, aa, lk) \
+  (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
+#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
+
+/* A BBOCB_MASK with the y bit of the BO field removed.  */
+#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
+#define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
+#define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
+
+/* A BBOYCB_MASK in which the BI field is fixed.  */
+#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
+#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
+
+/* An Context form instruction.  */
+#define CTX(op, xop)   (OP (op) | (((unsigned long)(xop)) & 0x7))
+#define CTX_MASK       CTX(0x3f, 0x7)
+
+/* An User Context form instruction.  */
+#define UCTX(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
+#define UCTX_MASK      UCTX(0x3f, 0x1f)
+
+/* The main opcode mask with the RA field clear.  */
+#define DRA_MASK (OP_MASK | RA_MASK)
+
+/* A DS form instruction.  */
+#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
+#define DS_MASK DSO (0x3f, 3)
+
+/* A DE form instruction.  */
+#define DEO(op, xop) (OP (op) | ((xop) & 0xf))
+#define DE_MASK DEO (0x3e, 0xf)
+
+/* An EVSEL form instruction.  */
+#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
+#define EVSEL_MASK EVSEL(0x3f, 0xff)
+
+/* An M form instruction.  */
+#define M(op, rc) (OP (op) | ((rc) & 1))
+#define M_MASK M (0x3f, 1)
+
+/* An M form instruction with the ME field specified.  */
+#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
+
+/* An M_MASK with the MB and ME fields fixed.  */
+#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
+
+/* An M_MASK with the SH and ME fields fixed.  */
+#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
+
+/* An MD form instruction.  */
+#define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
+#define MD_MASK MD (0x3f, 0x7, 1)
+
+/* An MD_MASK with the MB field fixed.  */
+#define MDMB_MASK (MD_MASK | MB6_MASK)
+
+/* An MD_MASK with the SH field fixed.  */
+#define MDSH_MASK (MD_MASK | SH6_MASK)
+
+/* An MDS form instruction.  */
+#define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
+#define MDS_MASK MDS (0x3f, 0xf, 1)
+
+/* An MDS_MASK with the MB field fixed.  */
+#define MDSMB_MASK (MDS_MASK | MB6_MASK)
+
+/* An SC form instruction.  */
+#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
+#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
+
+/* An VX form instruction.  */
+#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
+
+/* The mask for an VX form instruction.  */
+#define VX_MASK VX(0x3f, 0x7ff)
+
+/* An VA form instruction.  */
+#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
+
+/* The mask for an VA form instruction.  */
+#define VXA_MASK VXA(0x3f, 0x3f)
+
+/* An VXR form instruction.  */
+#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
+
+/* The mask for a VXR form instruction.  */
+#define VXR_MASK VXR(0x3f, 0x3ff, 1)
+
+/* An X form instruction.  */
+#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
+
+/* An X form instruction with the RC bit specified.  */
+#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
+
+/* The mask for an X form instruction.  */
+#define X_MASK XRC (0x3f, 0x3ff, 1)
+
+/* An X_MASK with the RA field fixed.  */
+#define XRA_MASK (X_MASK | RA_MASK)
+
+/* An X_MASK with the RB field fixed.  */
+#define XRB_MASK (X_MASK | RB_MASK)
+
+/* An X_MASK with the RT field fixed.  */
+#define XRT_MASK (X_MASK | RT_MASK)
+
+/* An X_MASK with the RA and RB fields fixed.  */
+#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
+
+/* An XRARB_MASK, but with the L bit clear.  */
+#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
+
+/* An X_MASK with the RT and RA fields fixed.  */
+#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
+
+/* An XRTRA_MASK, but with L bit clear.  */
+#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
+
+/* An X form comparison instruction.  */
+#define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
+
+/* The mask for an X form comparison instruction.  */
+#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
+
+/* The mask for an X form comparison instruction with the L field
+   fixed.  */
+#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
+
+/* An X form trap instruction with the TO field specified.  */
+#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
+#define XTO_MASK (X_MASK | TO_MASK)
+
+/* An X form tlb instruction with the SH field specified.  */
+#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
+#define XTLB_MASK (X_MASK | SH_MASK)
+
+/* An X form sync instruction.  */
+#define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
+
+/* An X form sync instruction with everything filled in except the LS field.  */
+#define XSYNC_MASK (0xff9fffff)
+
+/* An X form AltiVec dss instruction.  */
+#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
+#define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
+
+/* An XFL form instruction.  */
+#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
+#define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
+
+/* An X form isel instruction.  */
+#define XISEL(op, xop)  (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
+#define XISEL_MASK      XISEL(0x3f, 0x1f)
+
+/* An XL form instruction with the LK field set to 0.  */
+#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
+
+/* An XL form instruction which uses the LK field.  */
+#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
+
+/* The mask for an XL form instruction.  */
+#define XL_MASK XLLK (0x3f, 0x3ff, 1)
+
+/* An XL form instruction which explicitly sets the BO field.  */
+#define XLO(op, bo, xop, lk) \
+  (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
+#define XLO_MASK (XL_MASK | BO_MASK)
+
+/* An XL form instruction which explicitly sets the y bit of the BO
+   field.  */
+#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
+#define XLYLK_MASK (XL_MASK | Y_MASK)
+
+/* An XL form instruction which sets the BO field and the condition
+   bits of the BI field.  */
+#define XLOCB(op, bo, cb, xop, lk) \
+  (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
+#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
+
+/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed.  */
+#define XLBB_MASK (XL_MASK | BB_MASK)
+#define XLYBB_MASK (XLYLK_MASK | BB_MASK)
+#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
+
+/* An XL_MASK with the BO and BB fields fixed.  */
+#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
+
+/* An XL_MASK with the BO, BI and BB fields fixed.  */
+#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
+
+/* An XO form instruction.  */
+#define XO(op, xop, oe, rc) \
+  (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
+#define XO_MASK XO (0x3f, 0x1ff, 1, 1)
+
+/* An XO_MASK with the RB field fixed.  */
+#define XORB_MASK (XO_MASK | RB_MASK)
+
+/* An XS form instruction.  */
+#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
+#define XS_MASK XS (0x3f, 0x1ff, 1)
+
+/* A mask for the FXM version of an XFX form instruction.  */
+#define XFXFXM_MASK (X_MASK | (1 << 11))
+
+/* An XFX form instruction with the FXM field filled in.  */
+#define XFXM(op, xop, fxm) \
+  (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12))
+
+/* An XFX form instruction with the SPR field filled in.  */
+#define XSPR(op, xop, spr) \
+  (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
+#define XSPR_MASK (X_MASK | SPR_MASK)
+
+/* An XFX form instruction with the SPR field filled in except for the
+   SPRBAT field.  */
+#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
+
+/* An XFX form instruction with the SPR field filled in except for the
+   SPRG field.  */
+#define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
+
+/* An X form instruction with everything filled in except the E field.  */
+#define XE_MASK (0xffff7fff)
+
+/* An X form user context instruction.  */
+#define XUC(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
+#define XUC_MASK      XUC(0x3f, 0x1f)
+
+/* The BO encodings used in extended conditional branch mnemonics.  */
+#define BODNZF  (0x0)
+#define BODNZFP (0x1)
+#define BODZF   (0x2)
+#define BODZFP  (0x3)
+#define BODNZT  (0x8)
+#define BODNZTP (0x9)
+#define BODZT   (0xa)
+#define BODZTP  (0xb)
+
+#define BOF     (0x4)
+#define BOFP    (0x5)
+#define BOFM4   (0x6)
+#define BOFP4   (0x7)
+#define BOT     (0xc)
+#define BOTP    (0xd)
+#define BOTM4   (0xe)
+#define BOTP4   (0xf)
+
+#define BODNZ   (0x10)
+#define BODNZP  (0x11)
+#define BODZ    (0x12)
+#define BODZP   (0x13)
+#define BODNZM4 (0x18)
+#define BODNZP4 (0x19)
+#define BODZM4  (0x1a)
+#define BODZP4  (0x1b)
+
+#define BOU     (0x14)
+
+/* The BI condition bit encodings used in extended conditional branch
+   mnemonics.  */
+#define CBLT    (0)
+#define CBGT    (1)
+#define CBEQ    (2)
+#define CBSO    (3)
+
+/* The TO encodings used in extended trap mnemonics.  */
+#define TOLGT   (0x1)
+#define TOLLT   (0x2)
+#define TOEQ    (0x4)
+#define TOLGE   (0x5)
+#define TOLNL   (0x5)
+#define TOLLE   (0x6)
+#define TOLNG   (0x6)
+#define TOGT    (0x8)
+#define TOGE    (0xc)
+#define TONL    (0xc)
+#define TOLT    (0x10)
+#define TOLE    (0x14)
+#define TONG    (0x14)
+#define TONE    (0x18)
+#define TOU     (0x1f)
+
+/* Smaller names for the flags so each entry in the opcodes table will
+   fit on a single line.  */
+#undef  PPC
+#define PPC     PPC_OPCODE_PPC
+#define PPCCOM  PPC_OPCODE_PPC | PPC_OPCODE_COMMON
+#define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
+#define POWER4  PPC_OPCODE_POWER4
+#define PPC32   PPC_OPCODE_32 | PPC_OPCODE_PPC
+#define PPC64   PPC_OPCODE_64 | PPC_OPCODE_PPC
+#define PPC403  PPC_OPCODE_403
+#define PPC405  PPC403
+#define PPC440  PPC_OPCODE_440
+#define PPC750  PPC
+#define PPC860  PPC
+#define PPCVEC  PPC_OPCODE_ALTIVEC | PPC_OPCODE_PPC
+#define POWER   PPC_OPCODE_POWER
+#define POWER2  PPC_OPCODE_POWER | PPC_OPCODE_POWER2
+#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
+#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
+#define COM     PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
+#define COM32   PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
+#define M601    PPC_OPCODE_POWER | PPC_OPCODE_601
+#define PWRCOM  PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
+#define MFDEC1  PPC_OPCODE_POWER
+#define MFDEC2  PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
+#define BOOKE   PPC_OPCODE_BOOKE
+#define BOOKE64 PPC_OPCODE_BOOKE64
+#define CLASSIC PPC_OPCODE_CLASSIC
+#define PPCSPE  PPC_OPCODE_SPE
+#define PPCISEL PPC_OPCODE_ISEL
+#define PPCEFS  PPC_OPCODE_EFS
+#define PPCBRLK PPC_OPCODE_BRLOCK
+#define PPCPMR  PPC_OPCODE_PMR
+#define PPCCHLK PPC_OPCODE_CACHELCK
+#define PPCCHLK64       PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
+#define PPCRFMCI        PPC_OPCODE_RFMCI
+
+/* The opcode table.
+
+   The format of the opcode table is:
+
+   NAME      OPCODE     MASK            FLAGS           { OPERANDS }
+
+   NAME is the name of the instruction.
+   OPCODE is the instruction opcode.
+   MASK is the opcode mask; this is used to tell the disassembler
+     which bits in the actual opcode must match OPCODE.
+   FLAGS are flags indicated what processors support the instruction.
+   OPERANDS is the list of operands.
+
+   The disassembler reads the table in order and prints the first
+   instruction which matches, so this table is sorted to put more
+   specific instructions before more general instructions.  It is also
+   sorted by major opcode.  */
+
+const struct powerpc_opcode powerpc_opcodes[] = {
+{ "attn",    X(0,256), X_MASK,          POWER4,         { 0 } },
+{ "tdlgti",  OPTO(2,TOLGT), OPTO_MASK,  PPC64,          { RA, SI } },
+{ "tdllti",  OPTO(2,TOLLT), OPTO_MASK,  PPC64,          { RA, SI } },
+{ "tdeqi",   OPTO(2,TOEQ), OPTO_MASK,   PPC64,          { RA, SI } },
+{ "tdlgei",  OPTO(2,TOLGE), OPTO_MASK,  PPC64,          { RA, SI } },
+{ "tdlnli",  OPTO(2,TOLNL), OPTO_MASK,  PPC64,          { RA, SI } },
+{ "tdllei",  OPTO(2,TOLLE), OPTO_MASK,  PPC64,          { RA, SI } },
+{ "tdlngi",  OPTO(2,TOLNG), OPTO_MASK,  PPC64,          { RA, SI } },
+{ "tdgti",   OPTO(2,TOGT), OPTO_MASK,   PPC64,          { RA, SI } },
+{ "tdgei",   OPTO(2,TOGE), OPTO_MASK,   PPC64,          { RA, SI } },
+{ "tdnli",   OPTO(2,TONL), OPTO_MASK,   PPC64,          { RA, SI } },
+{ "tdlti",   OPTO(2,TOLT), OPTO_MASK,   PPC64,          { RA, SI } },
+{ "tdlei",   OPTO(2,TOLE), OPTO_MASK,   PPC64,          { RA, SI } },
+{ "tdngi",   OPTO(2,TONG), OPTO_MASK,   PPC64,          { RA, SI } },
+{ "tdnei",   OPTO(2,TONE), OPTO_MASK,   PPC64,          { RA, SI } },
+{ "tdi",     OP(2),     OP_MASK,        PPC64,          { TO, RA, SI } },
+
+{ "twlgti",  OPTO(3,TOLGT), OPTO_MASK,  PPCCOM,         { RA, SI } },
+{ "tlgti",   OPTO(3,TOLGT), OPTO_MASK,  PWRCOM,         { RA, SI } },
+{ "twllti",  OPTO(3,TOLLT), OPTO_MASK,  PPCCOM,         { RA, SI } },
+{ "tllti",   OPTO(3,TOLLT), OPTO_MASK,  PWRCOM,         { RA, SI } },
+{ "tweqi",   OPTO(3,TOEQ), OPTO_MASK,   PPCCOM,         { RA, SI } },
+{ "teqi",    OPTO(3,TOEQ), OPTO_MASK,   PWRCOM,         { RA, SI } },
+{ "twlgei",  OPTO(3,TOLGE), OPTO_MASK,  PPCCOM,         { RA, SI } },
+{ "tlgei",   OPTO(3,TOLGE), OPTO_MASK,  PWRCOM,         { RA, SI } },
+{ "twlnli",  OPTO(3,TOLNL), OPTO_MASK,  PPCCOM,         { RA, SI } },
+{ "tlnli",   OPTO(3,TOLNL), OPTO_MASK,  PWRCOM,         { RA, SI } },
+{ "twllei",  OPTO(3,TOLLE), OPTO_MASK,  PPCCOM,         { RA, SI } },
+{ "tllei",   OPTO(3,TOLLE), OPTO_MASK,  PWRCOM,         { RA, SI } },
+{ "twlngi",  OPTO(3,TOLNG), OPTO_MASK,  PPCCOM,         { RA, SI } },
+{ "tlngi",   OPTO(3,TOLNG), OPTO_MASK,  PWRCOM,         { RA, SI } },
+{ "twgti",   OPTO(3,TOGT), OPTO_MASK,   PPCCOM,         { RA, SI } },
+{ "tgti",    OPTO(3,TOGT), OPTO_MASK,   PWRCOM,         { RA, SI } },
+{ "twgei",   OPTO(3,TOGE), OPTO_MASK,   PPCCOM,         { RA, SI } },
+{ "tgei",    OPTO(3,TOGE), OPTO_MASK,   PWRCOM,         { RA, SI } },
+{ "twnli",   OPTO(3,TONL), OPTO_MASK,   PPCCOM,         { RA, SI } },
+{ "tnli",    OPTO(3,TONL), OPTO_MASK,   PWRCOM,         { RA, SI } },
+{ "twlti",   OPTO(3,TOLT), OPTO_MASK,   PPCCOM,         { RA, SI } },
+{ "tlti",    OPTO(3,TOLT), OPTO_MASK,   PWRCOM,         { RA, SI } },
+{ "twlei",   OPTO(3,TOLE), OPTO_MASK,   PPCCOM,         { RA, SI } },
+{ "tlei",    OPTO(3,TOLE), OPTO_MASK,   PWRCOM,         { RA, SI } },
+{ "twngi",   OPTO(3,TONG), OPTO_MASK,   PPCCOM,         { RA, SI } },
+{ "tngi",    OPTO(3,TONG), OPTO_MASK,   PWRCOM,         { RA, SI } },
+{ "twnei",   OPTO(3,TONE), OPTO_MASK,   PPCCOM,         { RA, SI } },
+{ "tnei",    OPTO(3,TONE), OPTO_MASK,   PWRCOM,         { RA, SI } },
+{ "twi",     OP(3),     OP_MASK,        PPCCOM,         { TO, RA, SI } },
+{ "ti",      OP(3),     OP_MASK,        PWRCOM,         { TO, RA, SI } },
+
+{ "macchw",     XO(4,172,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchw.",    XO(4,172,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchwo",    XO(4,172,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchwo.",   XO(4,172,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchws",    XO(4,236,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchws.",   XO(4,236,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchwso",   XO(4,236,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchwso.",  XO(4,236,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchwsu",   XO(4,204,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchwsu.",  XO(4,204,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchwsuo",  XO(4,204,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchwu",    XO(4,140,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchwu.",   XO(4,140,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchwuo",   XO(4,140,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchwuo.",  XO(4,140,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhw",     XO(4,44,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhw.",    XO(4,44,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhwo",    XO(4,44,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhwo.",   XO(4,44,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhws",    XO(4,108,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhws.",   XO(4,108,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhwso",   XO(4,108,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhwso.",  XO(4,108,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhwsu",   XO(4,76,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhwsu.",  XO(4,76,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhwsuo",  XO(4,76,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhwsuo.", XO(4,76,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhwu",    XO(4,12,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhwu.",   XO(4,12,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhwuo",   XO(4,12,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhwuo.",  XO(4,12,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhw",     XO(4,428,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhw.",    XO(4,428,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhwo",    XO(4,428,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhwo.",   XO(4,428,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhws",    XO(4,492,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhws.",   XO(4,492,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhwso",   XO(4,492,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhwso.",  XO(4,492,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhwsu",   XO(4,460,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhwsu.",  XO(4,460,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhwsuo",  XO(4,460,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhwu",    XO(4,396,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhwu.",   XO(4,396,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhwuo",   XO(4,396,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhwuo.",  XO(4,396,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "mulchw",     XRC(4,168,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
+{ "mulchw.",    XRC(4,168,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
+{ "mulchwu",    XRC(4,136,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
+{ "mulchwu.",   XRC(4,136,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
+{ "mulhhw",     XRC(4,40,0),   X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
+{ "mulhhw.",    XRC(4,40,1),   X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
+{ "mulhhwu",    XRC(4,8,0),    X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
+{ "mulhhwu.",   XRC(4,8,1),    X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
+{ "mullhw",     XRC(4,424,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
+{ "mullhw.",    XRC(4,424,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
+{ "mullhwu",    XRC(4,392,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
+{ "mullhwu.",   XRC(4,392,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
+{ "nmacchw",    XO(4,174,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmacchw.",   XO(4,174,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmacchwo",   XO(4,174,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmacchwo.",  XO(4,174,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmacchws",   XO(4,238,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmacchws.",  XO(4,238,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmacchwso",  XO(4,238,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmachhw",    XO(4,46,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmachhw.",   XO(4,46,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmachhwo",   XO(4,46,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmachhwo.",  XO(4,46,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmachhws",   XO(4,110,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmachhws.",  XO(4,110,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmachhwso",  XO(4,110,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmaclhw",    XO(4,430,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmaclhw.",   XO(4,430,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmaclhwo",   XO(4,430,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmaclhwo.",  XO(4,430,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmaclhws",   XO(4,494,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmaclhws.",  XO(4,494,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmaclhwso",  XO(4,494,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "mfvscr",  VX(4, 1540), VX_MASK,      PPCVEC,         { VD } },
+{ "mtvscr",  VX(4, 1604), VX_MASK,      PPCVEC,         { VB } },
+{ "vaddcuw", VX(4,  384), VX_MASK,      PPCVEC,         { VD, VA, VB } },
+{ "vaddfp",  VX(4,   10), VX_MASK,      PPCVEC,         { VD, VA, VB } },
+{ "vaddsbs", VX(4,  768), VX_MASK,      PPCVEC,         { VD, VA, VB } },
+{ "vaddshs", VX(4,  832), VX_MASK,      PPCVEC,         { VD, VA, VB } },
+{ "vaddsws", VX(4,  896), VX_MASK,      PPCVEC,         { VD, VA, VB } },
+{ "vaddubm", VX(4,    0), VX_MASK,      PPCVEC,         { VD, VA, VB } },
+{ "vaddubs", VX(4,  512), VX_MASK,      PPCVEC,         { VD, VA, VB } },
+{ "vadduhm", VX(4,   64), VX_MASK,      PPCVEC,         { VD, VA, VB } },
+{ "vadduhs", VX(4,  576), VX_MASK,      PPCVEC,         { VD, VA, VB } },
+{ "vadduwm", VX(4,  128), VX_MASK,      PPCVEC,         { VD, VA, VB } },
+{ "vadduws", VX(4,  640), VX_MASK,      PPCVEC,         { VD, VA, VB } },
+{ "vand",    VX(4, 1028), VX_MASK,      PPCVEC,         { VD, VA, VB } },
+{ "vandc",   VX(4, 1092), VX_MASK,      PPCVEC,         { VD, VA, VB } },
+{ "vavgsb",  VX(4, 1282), VX_MASK,      PPCVEC,         { VD, VA, VB } },
+{ "vavgsh",  VX(4, 1346), VX_MASK,      PPCVEC,         { VD, VA, VB } },
+{ "vavgsw",  VX(4, 1410), VX_MASK,      PPCVEC,         { VD, VA, VB } },
+{ "vavgub",  VX(4, 1026), VX_MASK,      PPCVEC,         { VD, VA, VB } },
+{ "vavguh",  VX(4, 1090), VX_MASK,      PPCVEC,         { VD, VA, VB } },
+{ "vavguw",  VX(4, 1154), VX_MASK,      PPCVEC,         { VD, VA, VB } },
+{ "vcfsx",   VX(4,  842), VX_MASK,      PPCVEC,         { VD, VB, UIMM } },
+{ "vcfux",   VX(4,  778), VX_MASK,      PPCVEC,         { VD, VB, UIMM } },
+{ "vcmpbfp",   VXR(4, 966, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
+{ "vcmpbfp.",  VXR(4, 966, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
+{ "vcmpeqfp",  VXR(4, 198, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
+{ "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
+{ "vcmpequb",  VXR(4,   6, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
+{ "vcmpequb.", VXR(4,   6, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
+{ "vcmpequh",  VXR(4,  70, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
+{ "vcmpequh.", VXR(4,  70, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
+{ "vcmpequw",  VXR(4, 134, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
+{ "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
+{ "vcmpgefp",  VXR(4, 454, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
+{ "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
+{ "vcmpgtfp",  VXR(4, 710, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
+{ "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
+{ "vcmpgtsb",  VXR(4, 774, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
+{ "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
+{ "vcmpgtsh",  VXR(4, 838, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
+{ "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
+{ "vcmpgtsw",  VXR(4, 902, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
+{ "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
+{ "vcmpgtub",  VXR(4, 518, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
+{ "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
+{ "vcmpgtuh",  VXR(4, 582, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
+{ "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
+{ "vcmpgtuw",  VXR(4, 646, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
+{ "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
+{ "vctsxs",    VX(4,  970), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
+{ "vctuxs",    VX(4,  906), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
+{ "vexptefp",  VX(4,  394), VX_MASK,    PPCVEC,         { VD, VB } },
+{ "vlogefp",   VX(4,  458), VX_MASK,    PPCVEC,         { VD, VB } },
+{ "vmaddfp",   VXA(4,  46), VXA_MASK,   PPCVEC,         { VD, VA, VC, VB } },
+{ "vmaxfp",    VX(4, 1034), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vmaxsb",    VX(4,  258), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vmaxsh",    VX(4,  322), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vmaxsw",    VX(4,  386), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vmaxub",    VX(4,    2), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vmaxuh",    VX(4,   66), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vmaxuw",    VX(4,  130), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vmhaddshs", VXA(4,  32), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
+{ "vmhraddshs", VXA(4, 33), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
+{ "vminfp",    VX(4, 1098), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vminsb",    VX(4,  770), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vminsh",    VX(4,  834), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vminsw",    VX(4,  898), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vminub",    VX(4,  514), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vminuh",    VX(4,  578), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vminuw",    VX(4,  642), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vmladduhm", VXA(4,  34), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
+{ "vmrghb",    VX(4,   12), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vmrghh",    VX(4,   76), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vmrghw",    VX(4,  140), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vmrglb",    VX(4,  268), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vmrglh",    VX(4,  332), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vmrglw",    VX(4,  396), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vmsummbm",  VXA(4,  37), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
+{ "vmsumshm",  VXA(4,  40), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
+{ "vmsumshs",  VXA(4,  41), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
+{ "vmsumubm",  VXA(4,  36), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
+{ "vmsumuhm",  VXA(4,  38), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
+{ "vmsumuhs",  VXA(4,  39), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
+{ "vmulesb",   VX(4,  776), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vmulesh",   VX(4,  840), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vmuleub",   VX(4,  520), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vmuleuh",   VX(4,  584), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vmulosb",   VX(4,  264), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vmulosh",   VX(4,  328), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vmuloub",   VX(4,    8), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vmulouh",   VX(4,   72), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vnmsubfp",  VXA(4,  47), VXA_MASK,   PPCVEC,         { VD, VA, VC, VB } },
+{ "vnor",      VX(4, 1284), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vor",       VX(4, 1156), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vperm",     VXA(4,  43), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
+{ "vpkpx",     VX(4,  782), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vpkshss",   VX(4,  398), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vpkshus",   VX(4,  270), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vpkswss",   VX(4,  462), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vpkswus",   VX(4,  334), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vpkuhum",   VX(4,   14), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vpkuhus",   VX(4,  142), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vpkuwum",   VX(4,   78), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vpkuwus",   VX(4,  206), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vrefp",     VX(4,  266), VX_MASK,    PPCVEC,         { VD, VB } },
+{ "vrfim",     VX(4,  714), VX_MASK,    PPCVEC,         { VD, VB } },
+{ "vrfin",     VX(4,  522), VX_MASK,    PPCVEC,         { VD, VB } },
+{ "vrfip",     VX(4,  650), VX_MASK,    PPCVEC,         { VD, VB } },
+{ "vrfiz",     VX(4,  586), VX_MASK,    PPCVEC,         { VD, VB } },
+{ "vrlb",      VX(4,    4), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vrlh",      VX(4,   68), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vrlw",      VX(4,  132), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vrsqrtefp", VX(4,  330), VX_MASK,    PPCVEC,         { VD, VB } },
+{ "vsel",      VXA(4,  42), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
+{ "vsl",       VX(4,  452), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vslb",      VX(4,  260), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vsldoi",    VXA(4,  44), VXA_MASK,   PPCVEC,         { VD, VA, VB, SHB } },
+{ "vslh",      VX(4,  324), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vslo",      VX(4, 1036), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vslw",      VX(4,  388), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vspltb",    VX(4,  524), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
+{ "vsplth",    VX(4,  588), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
+{ "vspltisb",  VX(4,  780), VX_MASK,    PPCVEC,         { VD, SIMM } },
+{ "vspltish",  VX(4,  844), VX_MASK,    PPCVEC,         { VD, SIMM } },
+{ "vspltisw",  VX(4,  908), VX_MASK,    PPCVEC,         { VD, SIMM } },
+{ "vspltw",    VX(4,  652), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
+{ "vsr",       VX(4,  708), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vsrab",     VX(4,  772), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vsrah",     VX(4,  836), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vsraw",     VX(4,  900), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vsrb",      VX(4,  516), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vsrh",      VX(4,  580), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vsro",      VX(4, 1100), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vsrw",      VX(4,  644), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vsubcuw",   VX(4, 1408), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vsubfp",    VX(4,   74), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vsubsbs",   VX(4, 1792), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vsubshs",   VX(4, 1856), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vsubsws",   VX(4, 1920), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vsububm",   VX(4, 1024), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vsububs",   VX(4, 1536), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vsubuhm",   VX(4, 1088), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vsubuhs",   VX(4, 1600), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vsubuwm",   VX(4, 1152), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vsubuws",   VX(4, 1664), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vsumsws",   VX(4, 1928), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vsum2sws",  VX(4, 1672), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vsum4sbs",  VX(4, 1800), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vsum4shs",  VX(4, 1608), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vsum4ubs",  VX(4, 1544), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+{ "vupkhpx",   VX(4,  846), VX_MASK,    PPCVEC,         { VD, VB } },
+{ "vupkhsb",   VX(4,  526), VX_MASK,    PPCVEC,         { VD, VB } },
+{ "vupkhsh",   VX(4,  590), VX_MASK,    PPCVEC,         { VD, VB } },
+{ "vupklpx",   VX(4,  974), VX_MASK,    PPCVEC,         { VD, VB } },
+{ "vupklsb",   VX(4,  654), VX_MASK,    PPCVEC,         { VD, VB } },
+{ "vupklsh",   VX(4,  718), VX_MASK,    PPCVEC,         { VD, VB } },
+{ "vxor",      VX(4, 1220), VX_MASK,    PPCVEC,         { VD, VA, VB } },
+
+{ "evaddw",    VX(4, 512), VX_MASK,     PPCSPE,         { RS, RA, RB } },
+{ "evaddiw",   VX(4, 514), VX_MASK,     PPCSPE,         { RS, RB, UIMM } },
+{ "evsubfw",   VX(4, 516), VX_MASK,     PPCSPE,         { RS, RA, RB } },
+{ "evsubw",    VX(4, 516), VX_MASK,     PPCSPE,         { RS, RB, RA } },
+{ "evsubifw",  VX(4, 518), VX_MASK,     PPCSPE,         { RS, UIMM, RB } },
+{ "evsubiw",   VX(4, 518), VX_MASK,     PPCSPE,         { RS, RB, UIMM } },
+{ "evabs",     VX(4, 520), VX_MASK,     PPCSPE,         { RS, RA } },
+{ "evneg",     VX(4, 521), VX_MASK,     PPCSPE,         { RS, RA } },
+{ "evextsb",   VX(4, 522), VX_MASK,     PPCSPE,         { RS, RA } },
+{ "evextsh",   VX(4, 523), VX_MASK,     PPCSPE,         { RS, RA } },
+{ "evrndw",    VX(4, 524), VX_MASK,     PPCSPE,         { RS, RA } },
+{ "evcntlzw",  VX(4, 525), VX_MASK,     PPCSPE,         { RS, RA } },
+{ "evcntlsw",  VX(4, 526), VX_MASK,     PPCSPE,         { RS, RA } },
+
+{ "brinc",     VX(4, 527), VX_MASK,     PPCSPE,         { RS, RA, RB } },
+
+{ "evand",     VX(4, 529), VX_MASK,     PPCSPE,         { RS, RA, RB } },
+{ "evandc",    VX(4, 530), VX_MASK,     PPCSPE,         { RS, RA, RB } },
+{ "evmr",      VX(4, 535), VX_MASK,     PPCSPE,         { RS, RA, BBA } },
+{ "evor",      VX(4, 535), VX_MASK,     PPCSPE,         { RS, RA, RB } },
+{ "evorc",     VX(4, 539), VX_MASK,     PPCSPE,         { RS, RA, RB } },
+{ "evxor",     VX(4, 534), VX_MASK,     PPCSPE,         { RS, RA, RB } },
+{ "eveqv",     VX(4, 537), VX_MASK,     PPCSPE,         { RS, RA, RB } },
+{ "evnand",    VX(4, 542), VX_MASK,     PPCSPE,         { RS, RA, RB } },
+{ "evnot",     VX(4, 536), VX_MASK,     PPCSPE,         { RS, RA, BBA } },
+{ "evnor",     VX(4, 536), VX_MASK,     PPCSPE,         { RS, RA, RB } },
+
+{ "evrlw",     VX(4, 552), VX_MASK,     PPCSPE,         { RS, RA, RB } },
+{ "evrlwi",    VX(4, 554), VX_MASK,     PPCSPE,         { RS, RA, EVUIMM } },
+{ "evslw",     VX(4, 548), VX_MASK,     PPCSPE,         { RS, RA, RB } },
+{ "evslwi",    VX(4, 550), VX_MASK,     PPCSPE,         { RS, RA, EVUIMM } },
+{ "evsrws",    VX(4, 545), VX_MASK,     PPCSPE,         { RS, RA, RB } },
+{ "evsrwu",    VX(4, 544), VX_MASK,     PPCSPE,         { RS, RA, RB } },
+{ "evsrwis",   VX(4, 547), VX_MASK,     PPCSPE,         { RS, RA, EVUIMM } },
+{ "evsrwiu",   VX(4, 546), VX_MASK,     PPCSPE,         { RS, RA, EVUIMM } },
+{ "evsplati",  VX(4, 553), VX_MASK,     PPCSPE,         { RS, SIMM } },
+{ "evsplatfi", VX(4, 555), VX_MASK,     PPCSPE,         { RS, SIMM } },
+{ "evmergehi", VX(4, 556), VX_MASK,     PPCSPE,         { RS, RA, RB } },
+{ "evmergelo", VX(4, 557), VX_MASK,     PPCSPE,         { RS, RA, RB } },
+{ "evmergehilo",VX(4,558), VX_MASK,     PPCSPE,         { RS, RA, RB } },
+{ "evmergelohi",VX(4,559), VX_MASK,     PPCSPE,         { RS, RA, RB } },
+
+{ "evcmpgts",  VX(4, 561), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
+{ "evcmpgtu",  VX(4, 560), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
+{ "evcmplts",  VX(4, 563), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
+{ "evcmpltu",  VX(4, 562), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
+{ "evcmpeq",   VX(4, 564), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
+{ "evsel",     EVSEL(4,79),EVSEL_MASK,  PPCSPE,         { RS, RA, RB, CRFS } },
+
+{ "evldd",     VX(4, 769), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
+{ "evlddx",    VX(4, 768), VX_MASK,     PPCSPE,         { RS, RA, RB } },
+{ "evldw",     VX(4, 771), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
+{ "evldwx",    VX(4, 770), VX_MASK,     PPCSPE,         { RS, RA, RB } },
+{ "evldh",     VX(4, 773), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
+{ "evldhx",    VX(4, 772), VX_MASK,     PPCSPE,         { RS, RA, RB } },
+{ "evlwhe",    VX(4, 785), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
+{ "evlwhex",   VX(4, 784), VX_MASK,     PPCSPE,         { RS, RA, RB } },
+{ "evlwhou",   VX(4, 789), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
+{ "evlwhoux",  VX(4, 788), VX_MASK,     PPCSPE,         { RS, RA, RB } },
+{ "evlwhos",   VX(4, 791), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
+{ "evlwhosx",  VX(4, 790), VX_MASK,     PPCSPE,         { RS, RA, RB } },
+{ "evlwwsplat",VX(4, 793), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
+{ "evlwwsplatx",VX(4, 792), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evlwhsplat",VX(4, 797), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
+{ "evlwhsplatx",VX(4, 796), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evlhhesplat",VX(4, 777), VX_MASK,    PPCSPE,         { RS, EVUIMM_2, RA } },
+{ "evlhhesplatx",VX(4, 776), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evlhhousplat",VX(4, 781), VX_MASK,   PPCSPE,         { RS, EVUIMM_2, RA } },
+{ "evlhhousplatx",VX(4, 780), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+{ "evlhhossplat",VX(4, 783), VX_MASK,   PPCSPE,         { RS, EVUIMM_2, RA } },
+{ "evlhhossplatx",VX(4, 782), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+
+{ "evstdd",    VX(4, 801), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
+{ "evstddx",   VX(4, 800), VX_MASK,     PPCSPE,         { RS, RA, RB } },
+{ "evstdw",    VX(4, 803), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
+{ "evstdwx",   VX(4, 802), VX_MASK,     PPCSPE,         { RS, RA, RB } },
+{ "evstdh",    VX(4, 805), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
+{ "evstdhx",   VX(4, 804), VX_MASK,     PPCSPE,         { RS, RA, RB } },
+{ "evstwwe",   VX(4, 825), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
+{ "evstwwex",  VX(4, 824), VX_MASK,     PPCSPE,         { RS, RA, RB } },
+{ "evstwwo",   VX(4, 829), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
+{ "evstwwox",  VX(4, 828), VX_MASK,     PPCSPE,         { RS, RA, RB } },
+{ "evstwhe",   VX(4, 817), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
+{ "evstwhex",  VX(4, 816), VX_MASK,     PPCSPE,         { RS, RA, RB } },
+{ "evstwho",   VX(4, 821), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
+{ "evstwhox",  VX(4, 820), VX_MASK,     PPCSPE,         { RS, RA, RB } },
+
+{ "evfsabs",   VX(4, 644), VX_MASK,     PPCSPE,         { RS, RA } },
+{ "evfsnabs",  VX(4, 645), VX_MASK,     PPCSPE,         { RS, RA } },
+{ "evfsneg",   VX(4, 646), VX_MASK,     PPCSPE,         { RS, RA } },
+{ "evfsadd",   VX(4, 640), VX_MASK,     PPCSPE,         { RS, RA, RB } },
+{ "evfssub",   VX(4, 641), VX_MASK,     PPCSPE,         { RS, RA, RB } },
+{ "evfsmul",   VX(4, 648), VX_MASK,     PPCSPE,         { RS, RA, RB } },
+{ "evfsdiv",   VX(4, 649), VX_MASK,     PPCSPE,         { RS, RA, RB } },
+{ "evfscmpgt", VX(4, 652), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
+{ "evfscmplt", VX(4, 653), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
+{ "evfscmpeq", VX(4, 654), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
+{ "evfststgt", VX(4, 668), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
+{ "evfststlt", VX(4, 669), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
+{ "evfststeq", VX(4, 670), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
+{ "evfscfui",  VX(4, 656), VX_MASK,     PPCSPE,         { RS, RB } },
+{ "evfsctuiz", VX(4, 664), VX_MASK,     PPCSPE,         { RS, RB } },
+{ "evfscfsi",  VX(4, 657), VX_MASK,     PPCSPE,         { RS, RB } },
+{ "evfscfuf",  VX(4, 658), VX_MASK,     PPCSPE,         { RS, RB } },
+{ "evfscfsf",  VX(4, 659), VX_MASK,     PPCSPE,         { RS, RB } },
+{ "evfsctui",  VX(4, 660), VX_MASK,     PPCSPE,         { RS, RB } },
+{ "evfsctsi",  VX(4, 661), VX_MASK,     PPCSPE,         { RS, RB } },
+{ "evfsctsiz", VX(4, 666), VX_MASK,     PPCSPE,         { RS, RB } },
+{ "evfsctuf",  VX(4, 662), VX_MASK,     PPCSPE,         { RS, RB } },
+{ "evfsctsf",  VX(4, 663), VX_MASK,     PPCSPE,         { RS, RB } },
+
+{ "efsabs",   VX(4, 708), VX_MASK,      PPCEFS,         { RS, RA } },
+{ "efsnabs",  VX(4, 709), VX_MASK,      PPCEFS,         { RS, RA } },
+{ "efsneg",   VX(4, 710), VX_MASK,      PPCEFS,         { RS, RA } },
+{ "efsadd",   VX(4, 704), VX_MASK,      PPCEFS,         { RS, RA, RB } },
+{ "efssub",   VX(4, 705), VX_MASK,      PPCEFS,         { RS, RA, RB } },
+{ "efsmul",   VX(4, 712), VX_MASK,      PPCEFS,         { RS, RA, RB } },
+{ "efsdiv",   VX(4, 713), VX_MASK,      PPCEFS,         { RS, RA, RB } },
+{ "efscmpgt", VX(4, 716), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
+{ "efscmplt", VX(4, 717), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
+{ "efscmpeq", VX(4, 718), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
+{ "efststgt", VX(4, 732), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
+{ "efststlt", VX(4, 733), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
+{ "efststeq", VX(4, 734), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
+{ "efscfui",  VX(4, 720), VX_MASK,      PPCEFS,         { RS, RB } },
+{ "efsctuiz", VX(4, 728), VX_MASK,      PPCEFS,         { RS, RB } },
+{ "efscfsi",  VX(4, 721), VX_MASK,      PPCEFS,         { RS, RB } },
+{ "efscfuf",  VX(4, 722), VX_MASK,      PPCEFS,         { RS, RB } },
+{ "efscfsf",  VX(4, 723), VX_MASK,      PPCEFS,         { RS, RB } },
+{ "efsctui",  VX(4, 724), VX_MASK,      PPCEFS,         { RS, RB } },
+{ "efsctsi",  VX(4, 725), VX_MASK,      PPCEFS,         { RS, RB } },
+{ "efsctsiz", VX(4, 730), VX_MASK,      PPCEFS,         { RS, RB } },
+{ "efsctuf",  VX(4, 726), VX_MASK,      PPCEFS,         { RS, RB } },
+{ "efsctsf",  VX(4, 727), VX_MASK,      PPCEFS,         { RS, RB } },
+
+{ "evmhossf",  VX(4, 1031), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evmhossfa", VX(4, 1063), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evmhosmf",  VX(4, 1039), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evmhosmfa", VX(4, 1071), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evmhosmi",  VX(4, 1037), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evmhosmia", VX(4, 1069), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evmhoumi",  VX(4, 1036), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evmhoumia", VX(4, 1068), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evmhessf",  VX(4, 1027), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evmhessfa", VX(4, 1059), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evmhesmf",  VX(4, 1035), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evmhesmfa", VX(4, 1067), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evmhesmi",  VX(4, 1033), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evmhesmia", VX(4, 1065), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evmheumi",  VX(4, 1032), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evmheumia", VX(4, 1064), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+
+{ "evmhossfaaw",VX(4, 1287), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmhossiaaw",VX(4, 1285), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmhosmfaaw",VX(4, 1295), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmhosmiaaw",VX(4, 1293), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmhousiaaw",VX(4, 1284), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmhoumiaaw",VX(4, 1292), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmhessfaaw",VX(4, 1283), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmhessiaaw",VX(4, 1281), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmhesmfaaw",VX(4, 1291), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmhesmiaaw",VX(4, 1289), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmheusiaaw",VX(4, 1280), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmheumiaaw",VX(4, 1288), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+
+{ "evmhossfanw",VX(4, 1415), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmhossianw",VX(4, 1413), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmhosmfanw",VX(4, 1423), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmhosmianw",VX(4, 1421), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmhousianw",VX(4, 1412), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmhoumianw",VX(4, 1420), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmhessfanw",VX(4, 1411), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmhessianw",VX(4, 1409), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmhesmfanw",VX(4, 1419), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmhesmianw",VX(4, 1417), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmheusianw",VX(4, 1408), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmheumianw",VX(4, 1416), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+
+{ "evmhogsmfaa",VX(4, 1327), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmhogsmiaa",VX(4, 1325), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmhogumiaa",VX(4, 1324), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmhegsmfaa",VX(4, 1323), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmhegsmiaa",VX(4, 1321), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmhegumiaa",VX(4, 1320), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+
+{ "evmhogsmfan",VX(4, 1455), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmhogsmian",VX(4, 1453), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmhogumian",VX(4, 1452), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmhegsmfan",VX(4, 1451), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmhegsmian",VX(4, 1449), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmhegumian",VX(4, 1448), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+
+{ "evmwhssf",  VX(4, 1095), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evmwhssfa", VX(4, 1127), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evmwhsmf",  VX(4, 1103), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evmwhsmfa", VX(4, 1135), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evmwhsmi",  VX(4, 1101), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evmwhsmia", VX(4, 1133), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evmwhumi",  VX(4, 1100), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evmwhumia", VX(4, 1132), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+
+{ "evmwlumi",  VX(4, 1096), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evmwlumia", VX(4, 1128), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+
+{ "evmwlssiaaw",VX(4, 1345), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmwlsmiaaw",VX(4, 1353), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmwlusiaaw",VX(4, 1344), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmwlumiaaw",VX(4, 1352), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+
+{ "evmwlssianw",VX(4, 1473), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmwlsmianw",VX(4, 1481), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmwlusianw",VX(4, 1472), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmwlumianw",VX(4, 1480), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+
+{ "evmwssf",   VX(4, 1107), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evmwssfa",  VX(4, 1139), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evmwsmf",   VX(4, 1115), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evmwsmfa",  VX(4, 1147), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evmwsmi",   VX(4, 1113), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evmwsmia",  VX(4, 1145), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evmwumi",   VX(4, 1112), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evmwumia",  VX(4, 1144), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+
+{ "evmwssfaa", VX(4, 1363), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evmwsmfaa", VX(4, 1371), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evmwsmiaa", VX(4, 1369), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evmwumiaa", VX(4, 1368), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+
+{ "evmwssfan", VX(4, 1491), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evmwsmfan", VX(4, 1499), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evmwsmian", VX(4, 1497), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evmwumian", VX(4, 1496), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+
+{ "evaddssiaaw",VX(4, 1217), VX_MASK,   PPCSPE,         { RS, RA } },
+{ "evaddsmiaaw",VX(4, 1225), VX_MASK,   PPCSPE,         { RS, RA } },
+{ "evaddusiaaw",VX(4, 1216), VX_MASK,   PPCSPE,         { RS, RA } },
+{ "evaddumiaaw",VX(4, 1224), VX_MASK,   PPCSPE,         { RS, RA } },
+
+{ "evsubfssiaaw",VX(4, 1219), VX_MASK,  PPCSPE,         { RS, RA } },
+{ "evsubfsmiaaw",VX(4, 1227), VX_MASK,  PPCSPE,         { RS, RA } },
+{ "evsubfusiaaw",VX(4, 1218), VX_MASK,  PPCSPE,         { RS, RA } },
+{ "evsubfumiaaw",VX(4, 1226), VX_MASK,  PPCSPE,         { RS, RA } },
+
+{ "evmra",    VX(4, 1220), VX_MASK,     PPCSPE,         { RS, RA } },
+
+{ "evdivws",  VX(4, 1222), VX_MASK,     PPCSPE,         { RS, RA, RB } },
+{ "evdivwu",  VX(4, 1223), VX_MASK,     PPCSPE,         { RS, RA, RB } },
+
+{ "mulli",   OP(7),     OP_MASK,        PPCCOM,         { RT, RA, SI } },
+{ "muli",    OP(7),     OP_MASK,        PWRCOM,         { RT, RA, SI } },
+
+{ "subfic",  OP(8),     OP_MASK,        PPCCOM,         { RT, RA, SI } },
+{ "sfi",     OP(8),     OP_MASK,        PWRCOM,         { RT, RA, SI } },
+
+{ "dozi",    OP(9),     OP_MASK,        M601,           { RT, RA, SI } },
+
+{ "bce",     B(9,0,0),  B_MASK,         BOOKE64,        { BO, BI, BD } },
+{ "bcel",    B(9,0,1),  B_MASK,         BOOKE64,        { BO, BI, BD } },
+{ "bcea",    B(9,1,0),  B_MASK,         BOOKE64,        { BO, BI, BDA } },
+{ "bcela",   B(9,1,1),  B_MASK,         BOOKE64,        { BO, BI, BDA } },
+
+{ "cmplwi",  OPL(10,0), OPL_MASK,       PPCCOM,         { OBF, RA, UI } },
+{ "cmpldi",  OPL(10,1), OPL_MASK,       PPC64,          { OBF, RA, UI } },
+{ "cmpli",   OP(10),    OP_MASK,        PPC,            { BF, L, RA, UI } },
+{ "cmpli",   OP(10),    OP_MASK,        PWRCOM,         { BF, RA, UI } },
+
+{ "cmpwi",   OPL(11,0), OPL_MASK,       PPCCOM,         { OBF, RA, SI } },
+{ "cmpdi",   OPL(11,1), OPL_MASK,       PPC64,          { OBF, RA, SI } },
+{ "cmpi",    OP(11),    OP_MASK,        PPC,            { BF, L, RA, SI } },
+{ "cmpi",    OP(11),    OP_MASK,        PWRCOM,         { BF, RA, SI } },
+
+{ "addic",   OP(12),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
+{ "ai",      OP(12),    OP_MASK,        PWRCOM,         { RT, RA, SI } },
+{ "subic",   OP(12),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
+
+{ "addic.",  OP(13),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
+{ "ai.",     OP(13),    OP_MASK,        PWRCOM,         { RT, RA, SI } },
+{ "subic.",  OP(13),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
+
+{ "li",      OP(14),    DRA_MASK,       PPCCOM,         { RT, SI } },
+{ "lil",     OP(14),    DRA_MASK,       PWRCOM,         { RT, SI } },
+{ "addi",    OP(14),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
+{ "cal",     OP(14),    OP_MASK,        PWRCOM,         { RT, D, RA } },
+{ "subi",    OP(14),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
+{ "la",      OP(14),    OP_MASK,        PPCCOM,         { RT, D, RA } },
+
+{ "lis",     OP(15),    DRA_MASK,       PPCCOM,         { RT, SISIGNOPT } },
+{ "liu",     OP(15),    DRA_MASK,       PWRCOM,         { RT, SISIGNOPT } },
+{ "addis",   OP(15),    OP_MASK,        PPCCOM,         { RT,RA,SISIGNOPT } },
+{ "cau",     OP(15),    OP_MASK,        PWRCOM,         { RT,RA,SISIGNOPT } },
+{ "subis",   OP(15),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
+
+{ "bdnz-",   BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,      { BDM } },
+{ "bdnz+",   BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,      { BDP } },
+{ "bdnz",    BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,      { BD } },
+{ "bdn",     BBO(16,BODNZ,0,0),      BBOATBI_MASK, PWRCOM,      { BD } },
+{ "bdnzl-",  BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,      { BDM } },
+{ "bdnzl+",  BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,      { BDP } },
+{ "bdnzl",   BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,      { BD } },
+{ "bdnl",    BBO(16,BODNZ,0,1),      BBOATBI_MASK, PWRCOM,      { BD } },
+{ "bdnza-",  BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,      { BDMA } },
+{ "bdnza+",  BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,      { BDPA } },
+{ "bdnza",   BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,      { BDA } },
+{ "bdna",    BBO(16,BODNZ,1,0),      BBOATBI_MASK, PWRCOM,      { BDA } },
+{ "bdnzla-", BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,      { BDMA } },
+{ "bdnzla+", BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,      { BDPA } },
+{ "bdnzla",  BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,      { BDA } },
+{ "bdnla",   BBO(16,BODNZ,1,1),      BBOATBI_MASK, PWRCOM,      { BDA } },
+{ "bdz-",    BBO(16,BODZ,0,0),       BBOATBI_MASK, PPCCOM,      { BDM } },
+{ "bdz+",    BBO(16,BODZ,0,0),       BBOATBI_MASK, PPCCOM,      { BDP } },
+{ "bdz",     BBO(16,BODZ,0,0),       BBOATBI_MASK, COM,         { BD } },
+{ "bdzl-",   BBO(16,BODZ,0,1),       BBOATBI_MASK, PPCCOM,      { BDM } },
+{ "bdzl+",   BBO(16,BODZ,0,1),       BBOATBI_MASK, PPCCOM,      { BDP } },
+{ "bdzl",    BBO(16,BODZ,0,1),       BBOATBI_MASK, COM,         { BD } },
+{ "bdza-",   BBO(16,BODZ,1,0),       BBOATBI_MASK, PPCCOM,      { BDMA } },
+{ "bdza+",   BBO(16,BODZ,1,0),       BBOATBI_MASK, PPCCOM,      { BDPA } },
+{ "bdza",    BBO(16,BODZ,1,0),       BBOATBI_MASK, COM,         { BDA } },
+{ "bdzla-",  BBO(16,BODZ,1,1),       BBOATBI_MASK, PPCCOM,      { BDMA } },
+{ "bdzla+",  BBO(16,BODZ,1,1),       BBOATBI_MASK, PPCCOM,      { BDPA } },
+{ "bdzla",   BBO(16,BODZ,1,1),       BBOATBI_MASK, COM,         { BDA } },
+{ "blt-",    BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
+{ "blt+",    BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
+{ "blt",     BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
+{ "bltl-",   BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
+{ "bltl+",   BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
+{ "bltl",    BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
+{ "blta-",   BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
+{ "blta+",   BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
+{ "blta",    BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
+{ "bltla-",  BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
+{ "bltla+",  BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
+{ "bltla",   BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
+{ "bgt-",    BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
+{ "bgt+",    BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
+{ "bgt",     BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
+{ "bgtl-",   BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
+{ "bgtl+",   BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
+{ "bgtl",    BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
+{ "bgta-",   BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
+{ "bgta+",   BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
+{ "bgta",    BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
+{ "bgtla-",  BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
+{ "bgtla+",  BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
+{ "bgtla",   BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
+{ "beq-",    BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
+{ "beq+",    BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
+{ "beq",     BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM,         { CR, BD } },
+{ "beql-",   BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
+{ "beql+",   BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
+{ "beql",    BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM,         { CR, BD } },
+{ "beqa-",   BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
+{ "beqa+",   BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
+{ "beqa",    BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
+{ "beqla-",  BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
+{ "beqla+",  BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
+{ "beqla",   BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
+{ "bso-",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
+{ "bso+",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
+{ "bso",     BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM,         { CR, BD } },
+{ "bsol-",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
+{ "bsol+",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
+{ "bsol",    BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM,         { CR, BD } },
+{ "bsoa-",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
+{ "bsoa+",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
+{ "bsoa",    BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
+{ "bsola-",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
+{ "bsola+",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
+{ "bsola",   BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
+{ "bun-",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
+{ "bun+",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
+{ "bun",     BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BD } },
+{ "bunl-",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
+{ "bunl+",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
+{ "bunl",    BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BD } },
+{ "buna-",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
+{ "buna+",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
+{ "buna",    BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
+{ "bunla-",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
+{ "bunla+",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
+{ "bunla",   BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
+{ "bge-",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
+{ "bge+",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
+{ "bge",     BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
+{ "bgel-",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
+{ "bgel+",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
+{ "bgel",    BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
+{ "bgea-",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
+{ "bgea+",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
+{ "bgea",    BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
+{ "bgela-",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
+{ "bgela+",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
+{ "bgela",   BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
+{ "bnl-",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
+{ "bnl+",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
+{ "bnl",     BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
+{ "bnll-",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
+{ "bnll+",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
+{ "bnll",    BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
+{ "bnla-",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
+{ "bnla+",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
+{ "bnla",    BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
+{ "bnlla-",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
+{ "bnlla+",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
+{ "bnlla",   BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
+{ "ble-",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
+{ "ble+",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
+{ "ble",     BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
+{ "blel-",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
+{ "blel+",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
+{ "blel",    BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
+{ "blea-",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
+{ "blea+",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
+{ "blea",    BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
+{ "blela-",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
+{ "blela+",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
+{ "blela",   BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
+{ "bng-",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
+{ "bng+",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
+{ "bng",     BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
+{ "bngl-",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
+{ "bngl+",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
+{ "bngl",    BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
+{ "bnga-",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
+{ "bnga+",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
+{ "bnga",    BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
+{ "bngla-",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
+{ "bngla+",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
+{ "bngla",   BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
+{ "bne-",    BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
+{ "bne+",    BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
+{ "bne",     BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM,         { CR, BD } },
+{ "bnel-",   BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
+{ "bnel+",   BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
+{ "bnel",    BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM,         { CR, BD } },
+{ "bnea-",   BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
+{ "bnea+",   BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
+{ "bnea",    BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
+{ "bnela-",  BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
+{ "bnela+",  BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
+{ "bnela",   BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
+{ "bns-",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
+{ "bns+",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
+{ "bns",     BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM,         { CR, BD } },
+{ "bnsl-",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
+{ "bnsl+",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
+{ "bnsl",    BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM,         { CR, BD } },
+{ "bnsa-",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
+{ "bnsa+",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
+{ "bnsa",    BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
+{ "bnsla-",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
+{ "bnsla+",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
+{ "bnsla",   BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
+{ "bnu-",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
+{ "bnu+",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
+{ "bnu",     BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BD } },
+{ "bnul-",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
+{ "bnul+",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
+{ "bnul",    BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BD } },
+{ "bnua-",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
+{ "bnua+",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
+{ "bnua",    BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
+{ "bnula-",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
+{ "bnula+",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
+{ "bnula",   BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
+{ "bdnzt-",  BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4,   { BI, BDM } },
+{ "bdnzt+",  BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4,   { BI, BDP } },
+{ "bdnzt",   BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM,     { BI, BD } },
+{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4,   { BI, BDM } },
+{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4,   { BI, BDP } },
+{ "bdnztl",  BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM,     { BI, BD } },
+{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
+{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
+{ "bdnzta",  BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM,     { BI, BDA } },
+{ "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
+{ "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
+{ "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM,     { BI, BDA } },
+{ "bdnzf-",  BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4,   { BI, BDM } },
+{ "bdnzf+",  BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4,   { BI, BDP } },
+{ "bdnzf",   BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM,     { BI, BD } },
+{ "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4,   { BI, BDM } },
+{ "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4,   { BI, BDP } },
+{ "bdnzfl",  BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM,     { BI, BD } },
+{ "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
+{ "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
+{ "bdnzfa",  BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM,     { BI, BDA } },
+{ "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
+{ "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
+{ "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM,     { BI, BDA } },
+{ "bt-",     BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM,       { BI, BDM } },
+{ "bt+",     BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM,       { BI, BDP } },
+{ "bt",      BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM,       { BI, BD } },
+{ "bbt",     BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM,       { BI, BD } },
+{ "btl-",    BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM,       { BI, BDM } },
+{ "btl+",    BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM,       { BI, BDP } },
+{ "btl",     BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM,       { BI, BD } },
+{ "bbtl",    BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM,       { BI, BD } },
+{ "bta-",    BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
+{ "bta+",    BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
+{ "bta",     BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM,       { BI, BDA } },
+{ "bbta",    BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM,       { BI, BDA } },
+{ "btla-",   BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
+{ "btla+",   BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
+{ "btla",    BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM,       { BI, BDA } },
+{ "bbtla",   BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM,       { BI, BDA } },
+{ "bf-",     BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM,       { BI, BDM } },
+{ "bf+",     BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM,       { BI, BDP } },
+{ "bf",      BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM,       { BI, BD } },
+{ "bbf",     BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM,       { BI, BD } },
+{ "bfl-",    BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM,       { BI, BDM } },
+{ "bfl+",    BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM,       { BI, BDP } },
+{ "bfl",     BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM,       { BI, BD } },
+{ "bbfl",    BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM,       { BI, BD } },
+{ "bfa-",    BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
+{ "bfa+",    BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
+{ "bfa",     BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM,       { BI, BDA } },
+{ "bbfa",    BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM,       { BI, BDA } },
+{ "bfla-",   BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
+{ "bfla+",   BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
+{ "bfla",    BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM,       { BI, BDA } },
+{ "bbfla",   BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM,       { BI, BDA } },
+{ "bdzt-",   BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4,    { BI, BDM } },
+{ "bdzt+",   BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4,    { BI, BDP } },
+{ "bdzt",    BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM,      { BI, BD } },
+{ "bdztl-",  BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4,    { BI, BDM } },
+{ "bdztl+",  BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4,    { BI, BDP } },
+{ "bdztl",   BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM,      { BI, BD } },
+{ "bdzta-",  BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
+{ "bdzta+",  BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
+{ "bdzta",   BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM,      { BI, BDA } },
+{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
+{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
+{ "bdztla",  BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM,      { BI, BDA } },
+{ "bdzf-",   BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4,    { BI, BDM } },
+{ "bdzf+",   BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4,    { BI, BDP } },
+{ "bdzf",    BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM,      { BI, BD } },
+{ "bdzfl-",  BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4,    { BI, BDM } },
+{ "bdzfl+",  BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4,    { BI, BDP } },
+{ "bdzfl",   BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM,      { BI, BD } },
+{ "bdzfa-",  BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
+{ "bdzfa+",  BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
+{ "bdzfa",   BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM,      { BI, BDA } },
+{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
+{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
+{ "bdzfla",  BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM,      { BI, BDA } },
+{ "bc-",     B(16,0,0), B_MASK,         PPCCOM,         { BOE, BI, BDM } },
+{ "bc+",     B(16,0,0), B_MASK,         PPCCOM,         { BOE, BI, BDP } },
+{ "bc",      B(16,0,0), B_MASK,         COM,            { BO, BI, BD } },
+{ "bcl-",    B(16,0,1), B_MASK,         PPCCOM,         { BOE, BI, BDM } },
+{ "bcl+",    B(16,0,1), B_MASK,         PPCCOM,         { BOE, BI, BDP } },
+{ "bcl",     B(16,0,1), B_MASK,         COM,            { BO, BI, BD } },
+{ "bca-",    B(16,1,0), B_MASK,         PPCCOM,         { BOE, BI, BDMA } },
+{ "bca+",    B(16,1,0), B_MASK,         PPCCOM,         { BOE, BI, BDPA } },
+{ "bca",     B(16,1,0), B_MASK,         COM,            { BO, BI, BDA } },
+{ "bcla-",   B(16,1,1), B_MASK,         PPCCOM,         { BOE, BI, BDMA } },
+{ "bcla+",   B(16,1,1), B_MASK,         PPCCOM,         { BOE, BI, BDPA } },
+{ "bcla",    B(16,1,1), B_MASK,         COM,            { BO, BI, BDA } },
+
+{ "sc",      SC(17,1,0), 0xffffffff,    PPC,            { 0 } },
+{ "svc",     SC(17,0,0), SC_MASK,       POWER,          { LEV, FL1, FL2 } },
+{ "svcl",    SC(17,0,1), SC_MASK,       POWER,          { LEV, FL1, FL2 } },
+{ "svca",    SC(17,1,0), SC_MASK,       PWRCOM,         { SV } },
+{ "svcla",   SC(17,1,1), SC_MASK,       POWER,          { SV } },
+
+{ "b",       B(18,0,0), B_MASK,         COM,            { LI } },
+{ "bl",      B(18,0,1), B_MASK,         COM,            { LI } },
+{ "ba",      B(18,1,0), B_MASK,         COM,            { LIA } },
+{ "bla",     B(18,1,1), B_MASK,         COM,            { LIA } },
+
+{ "mcrf",    XL(19,0),  XLBB_MASK|(3 << 21)|(3 << 16), COM,     { BF, BFA } },
+
+{ "blr",     XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM,   { 0 } },
+{ "br",      XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM,   { 0 } },
+{ "blrl",    XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM,   { 0 } },
+{ "brl",     XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM,   { 0 } },
+{ "bdnzlr",  XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
+{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
+{ "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4,       { 0 } },
+{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4,      { 0 } },
+{ "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4,       { 0 } },
+{ "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
+{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
+{ "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4,       { 0 } },
+{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4,      { 0 } },
+{ "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4,       { 0 } },
+{ "bdzlr",   XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM,  { 0 } },
+{ "bdzlr-",  XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4,        { 0 } },
+{ "bdzlr-",  XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4,        { 0 } },
+{ "bdzlr+",  XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
+{ "bdzlr+",  XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4,        { 0 } },
+{ "bdzlrl",  XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM,  { 0 } },
+{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4,        { 0 } },
+{ "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4,        { 0 } },
+{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
+{ "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4,        { 0 } },
+{ "bltlr",   XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "bltlr-",  XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bltlr-",  XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bltlr+",  XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bltlr+",  XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bltr",    XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
+{ "bltlrl",  XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bltrl",   XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
+{ "bgtlr",   XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "bgtlr-",  XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bgtlr-",  XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bgtlr+",  XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bgtlr+",  XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bgtr",    XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
+{ "bgtlrl",  XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bgtrl",   XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
+{ "beqlr",   XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "beqlr-",  XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "beqlr-",  XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "beqlr+",  XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "beqlr+",  XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "beqr",    XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
+{ "beqlrl",  XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "beqrl",   XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
+{ "bsolr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "bsolr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bsolr-",  XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bsolr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bsolr+",  XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bsor",    XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
+{ "bsolrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bsorl",   XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
+{ "bunlr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "bunlr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bunlr-",  XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bunlr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bunlr+",  XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bunlrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bgelr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "bgelr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bgelr-",  XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bgelr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bgelr+",  XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bger",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
+{ "bgelrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bgerl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
+{ "bnllr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "bnllr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bnllr-",  XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnllr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bnllr+",  XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnlr",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
+{ "bnllrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnlrl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
+{ "blelr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "blelr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "blelr-",  XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "blelr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "blelr+",  XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bler",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
+{ "blelrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "blerl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
+{ "bnglr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "bnglr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bnglr-",  XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnglr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bnglr+",  XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bngr",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
+{ "bnglrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bngrl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
+{ "bnelr",   XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "bnelr-",  XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bnelr-",  XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnelr+",  XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bnelr+",  XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bner",    XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
+{ "bnelrl",  XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnerl",   XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
+{ "bnslr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "bnslr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bnslr-",  XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnslr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bnslr+",  XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnsr",    XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
+{ "bnslrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnsrl",   XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
+{ "bnulr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "bnulr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bnulr-",  XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnulr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bnulr+",  XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnulrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
+{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "btlr",    XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM,     { BI } },
+{ "btlr-",   XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4,   { BI } },
+{ "btlr-",   XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4,   { BI } },
+{ "btlr+",   XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4,  { BI } },
+{ "btlr+",   XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4,   { BI } },
+{ "bbtr",    XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM,     { BI } },
+{ "btlrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM,     { BI } },
+{ "btlrl-",  XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4,   { BI } },
+{ "btlrl-",  XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4,   { BI } },
+{ "btlrl+",  XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4,  { BI } },
+{ "btlrl+",  XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4,   { BI } },
+{ "bbtrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM,     { BI } },
+{ "bflr",    XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM,     { BI } },
+{ "bflr-",   XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4,   { BI } },
+{ "bflr-",   XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4,   { BI } },
+{ "bflr+",   XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4,  { BI } },
+{ "bflr+",   XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4,   { BI } },
+{ "bbfr",    XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM,     { BI } },
+{ "bflrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM,     { BI } },
+{ "bflrl-",  XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4,   { BI } },
+{ "bflrl-",  XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4,   { BI } },
+{ "bflrl+",  XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4,  { BI } },
+{ "bflrl+",  XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4,   { BI } },
+{ "bbfrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM,     { BI } },
+{ "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
+{ "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
+{ "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
+{ "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
+{ "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
+{ "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
+{ "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
+{ "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
+{ "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
+{ "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
+{ "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
+{ "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
+{ "bdztlr",  XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM,   { BI } },
+{ "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
+{ "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
+{ "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM,   { BI } },
+{ "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
+{ "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
+{ "bdzflr",  XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM,   { BI } },
+{ "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
+{ "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
+{ "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM,   { BI } },
+{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
+{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
+{ "bclr",    XLLK(19,16,0), XLYBB_MASK, PPCCOM,         { BO, BI } },
+{ "bclrl",   XLLK(19,16,1), XLYBB_MASK, PPCCOM,         { BO, BI } },
+{ "bclr+",   XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM,      { BOE, BI } },
+{ "bclrl+",  XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM,      { BOE, BI } },
+{ "bclr-",   XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM,      { BOE, BI } },
+{ "bclrl-",  XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM,      { BOE, BI } },
+{ "bcr",     XLLK(19,16,0), XLBB_MASK,  PWRCOM,         { BO, BI } },
+{ "bcrl",    XLLK(19,16,1), XLBB_MASK,  PWRCOM,         { BO, BI } },
+{ "bclre",   XLLK(19,17,0), XLBB_MASK,  BOOKE64,        { BO, BI } },
+{ "bclrel",  XLLK(19,17,1), XLBB_MASK,  BOOKE64,        { BO, BI } },
+
+{ "rfid",    XL(19,18), 0xffffffff,     PPC64,          { 0 } },
+
+{ "crnot",   XL(19,33), XL_MASK,        PPCCOM,         { BT, BA, BBA } },
+{ "crnor",   XL(19,33), XL_MASK,        COM,            { BT, BA, BB } },
+{ "rfmci",    X(19,38), 0xffffffff,     PPCRFMCI,       { 0 } },
+
+{ "rfi",     XL(19,50), 0xffffffff,     COM,            { 0 } },
+{ "rfci",    XL(19,51), 0xffffffff,     PPC403 | BOOKE, { 0 } },
+
+{ "rfsvc",   XL(19,82), 0xffffffff,     POWER,          { 0 } },
+
+{ "crandc",  XL(19,129), XL_MASK,       COM,            { BT, BA, BB } },
+
+{ "isync",   XL(19,150), 0xffffffff,    PPCCOM,         { 0 } },
+{ "ics",     XL(19,150), 0xffffffff,    PWRCOM,         { 0 } },
+
+{ "crclr",   XL(19,193), XL_MASK,       PPCCOM,         { BT, BAT, BBA } },
+{ "crxor",   XL(19,193), XL_MASK,       COM,            { BT, BA, BB } },
+
+{ "crnand",  XL(19,225), XL_MASK,       COM,            { BT, BA, BB } },
+
+{ "crand",   XL(19,257), XL_MASK,       COM,            { BT, BA, BB } },
+
+{ "crset",   XL(19,289), XL_MASK,       PPCCOM,         { BT, BAT, BBA } },
+{ "creqv",   XL(19,289), XL_MASK,       COM,            { BT, BA, BB } },
+
+{ "crorc",   XL(19,417), XL_MASK,       COM,            { BT, BA, BB } },
+
+{ "crmove",  XL(19,449), XL_MASK,       PPCCOM,         { BT, BA, BBA } },
+{ "cror",    XL(19,449), XL_MASK,       COM,            { BT, BA, BB } },
+
+{ "bctr",    XLO(19,BOU,528,0), XLBOBIBB_MASK, COM,     { 0 } },
+{ "bctrl",   XLO(19,BOU,528,1), XLBOBIBB_MASK, COM,     { 0 } },
+{ "bltctr",  XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
+{ "bltctr-", XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bltctrl", XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
+{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bgtctr",  XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
+{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bgtctrl", XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
+{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "beqctr",  XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
+{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "beqctrl", XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
+{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bsoctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
+{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bsoctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
+{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bunctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
+{ "bunctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bunctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
+{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bgectr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
+{ "bgectr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bgectrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
+{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnlctr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
+{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnlctrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
+{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "blectr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
+{ "blectr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "blectrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
+{ "blectrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bngctr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
+{ "bngctr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bngctrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
+{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnectr",  XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
+{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnectrl", XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
+{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnsctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
+{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnsctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
+{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnuctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
+{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnuctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
+{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
+{ "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
+{ "btctr",   XLO(19,BOT,528,0),  XLBOBB_MASK, PPCCOM,   { BI } },
+{ "btctr-",  XLO(19,BOT,528,0),  XLBOBB_MASK, NOPOWER4, { BI } },
+{ "btctr-",  XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
+{ "btctr+",  XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
+{ "btctr+",  XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
+{ "btctrl",  XLO(19,BOT,528,1),  XLBOBB_MASK, PPCCOM,   { BI } },
+{ "btctrl-", XLO(19,BOT,528,1),  XLBOBB_MASK, NOPOWER4, { BI } },
+{ "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
+{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
+{ "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
+{ "bfctr",   XLO(19,BOF,528,0),  XLBOBB_MASK, PPCCOM,   { BI } },
+{ "bfctr-",  XLO(19,BOF,528,0),  XLBOBB_MASK, NOPOWER4, { BI } },
+{ "bfctr-",  XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
+{ "bfctr+",  XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
+{ "bfctr+",  XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
+{ "bfctrl",  XLO(19,BOF,528,1),  XLBOBB_MASK, PPCCOM,   { BI } },
+{ "bfctrl-", XLO(19,BOF,528,1),  XLBOBB_MASK, NOPOWER4, { BI } },
+{ "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
+{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
+{ "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
+{ "bcctr",   XLLK(19,528,0),     XLYBB_MASK,  PPCCOM,   { BO, BI } },
+{ "bcctr-",  XLYLK(19,528,0,0),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
+{ "bcctr+",  XLYLK(19,528,1,0),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
+{ "bcctrl",  XLLK(19,528,1),     XLYBB_MASK,  PPCCOM,   { BO, BI } },
+{ "bcctrl-", XLYLK(19,528,0,1),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
+{ "bcctrl+", XLYLK(19,528,1,1),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
+{ "bcc",     XLLK(19,528,0),     XLBB_MASK,   PWRCOM,   { BO, BI } },
+{ "bccl",    XLLK(19,528,1),     XLBB_MASK,   PWRCOM,   { BO, BI } },
+{ "bcctre",  XLLK(19,529,0),     XLYBB_MASK,  BOOKE64,  { BO, BI } },
+{ "bcctrel", XLLK(19,529,1),     XLYBB_MASK,  BOOKE64,  { BO, BI } },
+
+{ "rlwimi",  M(20,0),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
+{ "rlimi",   M(20,0),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
+
+{ "rlwimi.", M(20,1),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
+{ "rlimi.",  M(20,1),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
+
+{ "rotlwi",  MME(21,31,0), MMBME_MASK,  PPCCOM,         { RA, RS, SH } },
+{ "clrlwi",  MME(21,31,0), MSHME_MASK,  PPCCOM,         { RA, RS, MB } },
+{ "rlwinm",  M(21,0),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
+{ "rlinm",   M(21,0),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
+{ "rotlwi.", MME(21,31,1), MMBME_MASK,  PPCCOM,         { RA,RS,SH } },
+{ "clrlwi.", MME(21,31,1), MSHME_MASK,  PPCCOM,         { RA, RS, MB } },
+{ "rlwinm.", M(21,1),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
+{ "rlinm.",  M(21,1),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
+
+{ "rlmi",    M(22,0),   M_MASK,         M601,           { RA,RS,RB,MBE,ME } },
+{ "rlmi.",   M(22,1),   M_MASK,         M601,           { RA,RS,RB,MBE,ME } },
+
+{ "be",      B(22,0,0), B_MASK,         BOOKE64,        { LI } },
+{ "bel",     B(22,0,1), B_MASK,         BOOKE64,        { LI } },
+{ "bea",     B(22,1,0), B_MASK,         BOOKE64,        { LIA } },
+{ "bela",    B(22,1,1), B_MASK,         BOOKE64,        { LIA } },
+
+{ "rotlw",   MME(23,31,0), MMBME_MASK,  PPCCOM,         { RA, RS, RB } },
+{ "rlwnm",   M(23,0),   M_MASK,         PPCCOM,         { RA,RS,RB,MBE,ME } },
+{ "rlnm",    M(23,0),   M_MASK,         PWRCOM,         { RA,RS,RB,MBE,ME } },
+{ "rotlw.",  MME(23,31,1), MMBME_MASK,  PPCCOM,         { RA, RS, RB } },
+{ "rlwnm.",  M(23,1),   M_MASK,         PPCCOM,         { RA,RS,RB,MBE,ME } },
+{ "rlnm.",   M(23,1),   M_MASK,         PWRCOM,         { RA,RS,RB,MBE,ME } },
+
+{ "nop",     OP(24),    0xffffffff,     PPCCOM,         { 0 } },
+{ "ori",     OP(24),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
+{ "oril",    OP(24),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
+
+{ "oris",    OP(25),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
+{ "oriu",    OP(25),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
+
+{ "xori",    OP(26),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
+{ "xoril",   OP(26),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
+
+{ "xoris",   OP(27),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
+{ "xoriu",   OP(27),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
+
+{ "andi.",   OP(28),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
+{ "andil.",  OP(28),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
+
+{ "andis.",  OP(29),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
+{ "andiu.",  OP(29),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
+
+{ "rotldi",  MD(30,0,0), MDMB_MASK,     PPC64,          { RA, RS, SH6 } },
+{ "clrldi",  MD(30,0,0), MDSH_MASK,     PPC64,          { RA, RS, MB6 } },
+{ "rldicl",  MD(30,0,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
+{ "rotldi.", MD(30,0,1), MDMB_MASK,     PPC64,          { RA, RS, SH6 } },
+{ "clrldi.", MD(30,0,1), MDSH_MASK,     PPC64,          { RA, RS, MB6 } },
+{ "rldicl.", MD(30,0,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
+
+{ "rldicr",  MD(30,1,0), MD_MASK,       PPC64,          { RA, RS, SH6, ME6 } },
+{ "rldicr.", MD(30,1,1), MD_MASK,       PPC64,          { RA, RS, SH6, ME6 } },
+
+{ "rldic",   MD(30,2,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
+{ "rldic.",  MD(30,2,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
+
+{ "rldimi",  MD(30,3,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
+{ "rldimi.", MD(30,3,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
+
+{ "rotld",   MDS(30,8,0), MDSMB_MASK,   PPC64,          { RA, RS, RB } },
+{ "rldcl",   MDS(30,8,0), MDS_MASK,     PPC64,          { RA, RS, RB, MB6 } },
+{ "rotld.",  MDS(30,8,1), MDSMB_MASK,   PPC64,          { RA, RS, RB } },
+{ "rldcl.",  MDS(30,8,1), MDS_MASK,     PPC64,          { RA, RS, RB, MB6 } },
+
+{ "rldcr",   MDS(30,9,0), MDS_MASK,     PPC64,          { RA, RS, RB, ME6 } },
+{ "rldcr.",  MDS(30,9,1), MDS_MASK,     PPC64,          { RA, RS, RB, ME6 } },
+
+{ "cmpw",    XCMPL(31,0,0), XCMPL_MASK, PPCCOM,         { OBF, RA, RB } },
+{ "cmpd",    XCMPL(31,0,1), XCMPL_MASK, PPC64,          { OBF, RA, RB } },
+{ "cmp",     X(31,0),   XCMP_MASK,      PPC,            { BF, L, RA, RB } },
+{ "cmp",     X(31,0),   XCMPL_MASK,     PWRCOM,         { BF, RA, RB } },
+
+{ "twlgt",   XTO(31,4,TOLGT), XTO_MASK, PPCCOM,         { RA, RB } },
+{ "tlgt",    XTO(31,4,TOLGT), XTO_MASK, PWRCOM,         { RA, RB } },
+{ "twllt",   XTO(31,4,TOLLT), XTO_MASK, PPCCOM,         { RA, RB } },
+{ "tllt",    XTO(31,4,TOLLT), XTO_MASK, PWRCOM,         { RA, RB } },
+{ "tweq",    XTO(31,4,TOEQ), XTO_MASK,  PPCCOM,         { RA, RB } },
+{ "teq",     XTO(31,4,TOEQ), XTO_MASK,  PWRCOM,         { RA, RB } },
+{ "twlge",   XTO(31,4,TOLGE), XTO_MASK, PPCCOM,         { RA, RB } },
+{ "tlge",    XTO(31,4,TOLGE), XTO_MASK, PWRCOM,         { RA, RB } },
+{ "twlnl",   XTO(31,4,TOLNL), XTO_MASK, PPCCOM,         { RA, RB } },
+{ "tlnl",    XTO(31,4,TOLNL), XTO_MASK, PWRCOM,         { RA, RB } },
+{ "twlle",   XTO(31,4,TOLLE), XTO_MASK, PPCCOM,         { RA, RB } },
+{ "tlle",    XTO(31,4,TOLLE), XTO_MASK, PWRCOM,         { RA, RB } },
+{ "twlng",   XTO(31,4,TOLNG), XTO_MASK, PPCCOM,         { RA, RB } },
+{ "tlng",    XTO(31,4,TOLNG), XTO_MASK, PWRCOM,         { RA, RB } },
+{ "twgt",    XTO(31,4,TOGT), XTO_MASK,  PPCCOM,         { RA, RB } },
+{ "tgt",     XTO(31,4,TOGT), XTO_MASK,  PWRCOM,         { RA, RB } },
+{ "twge",    XTO(31,4,TOGE), XTO_MASK,  PPCCOM,         { RA, RB } },
+{ "tge",     XTO(31,4,TOGE), XTO_MASK,  PWRCOM,         { RA, RB } },
+{ "twnl",    XTO(31,4,TONL), XTO_MASK,  PPCCOM,         { RA, RB } },
+{ "tnl",     XTO(31,4,TONL), XTO_MASK,  PWRCOM,         { RA, RB } },
+{ "twlt",    XTO(31,4,TOLT), XTO_MASK,  PPCCOM,         { RA, RB } },
+{ "tlt",     XTO(31,4,TOLT), XTO_MASK,  PWRCOM,         { RA, RB } },
+{ "twle",    XTO(31,4,TOLE), XTO_MASK,  PPCCOM,         { RA, RB } },
+{ "tle",     XTO(31,4,TOLE), XTO_MASK,  PWRCOM,         { RA, RB } },
+{ "twng",    XTO(31,4,TONG), XTO_MASK,  PPCCOM,         { RA, RB } },
+{ "tng",     XTO(31,4,TONG), XTO_MASK,  PWRCOM,         { RA, RB } },
+{ "twne",    XTO(31,4,TONE), XTO_MASK,  PPCCOM,         { RA, RB } },
+{ "tne",     XTO(31,4,TONE), XTO_MASK,  PWRCOM,         { RA, RB } },
+{ "trap",    XTO(31,4,TOU), 0xffffffff, PPCCOM,         { 0 } },
+{ "tw",      X(31,4),   X_MASK,         PPCCOM,         { TO, RA, RB } },
+{ "t",       X(31,4),   X_MASK,         PWRCOM,         { TO, RA, RB } },
+
+{ "subfc",   XO(31,8,0,0), XO_MASK,     PPCCOM,         { RT, RA, RB } },
+{ "sf",      XO(31,8,0,0), XO_MASK,     PWRCOM,         { RT, RA, RB } },
+{ "subc",    XO(31,8,0,0), XO_MASK,     PPC,            { RT, RB, RA } },
+{ "subfc.",  XO(31,8,0,1), XO_MASK,     PPCCOM,         { RT, RA, RB } },
+{ "sf.",     XO(31,8,0,1), XO_MASK,     PWRCOM,         { RT, RA, RB } },
+{ "subc.",   XO(31,8,0,1), XO_MASK,     PPCCOM,         { RT, RB, RA } },
+{ "subfco",  XO(31,8,1,0), XO_MASK,     PPCCOM,         { RT, RA, RB } },
+{ "sfo",     XO(31,8,1,0), XO_MASK,     PWRCOM,         { RT, RA, RB } },
+{ "subco",   XO(31,8,1,0), XO_MASK,     PPC,            { RT, RB, RA } },
+{ "subfco.", XO(31,8,1,1), XO_MASK,     PPCCOM,         { RT, RA, RB } },
+{ "sfo.",    XO(31,8,1,1), XO_MASK,     PWRCOM,         { RT, RA, RB } },
+{ "subco.",  XO(31,8,1,1), XO_MASK,     PPC,            { RT, RB, RA } },
+
+{ "mulhdu",  XO(31,9,0,0), XO_MASK,     PPC64,          { RT, RA, RB } },
+{ "mulhdu.", XO(31,9,0,1), XO_MASK,     PPC64,          { RT, RA, RB } },
+
+{ "addc",    XO(31,10,0,0), XO_MASK,    PPCCOM,         { RT, RA, RB } },
+{ "a",       XO(31,10,0,0), XO_MASK,    PWRCOM,         { RT, RA, RB } },
+{ "addc.",   XO(31,10,0,1), XO_MASK,    PPCCOM,         { RT, RA, RB } },
+{ "a.",      XO(31,10,0,1), XO_MASK,    PWRCOM,         { RT, RA, RB } },
+{ "addco",   XO(31,10,1,0), XO_MASK,    PPCCOM,         { RT, RA, RB } },
+{ "ao",      XO(31,10,1,0), XO_MASK,    PWRCOM,         { RT, RA, RB } },
+{ "addco.",  XO(31,10,1,1), XO_MASK,    PPCCOM,         { RT, RA, RB } },
+{ "ao.",     XO(31,10,1,1), XO_MASK,    PWRCOM,         { RT, RA, RB } },
+
+{ "mulhwu",  XO(31,11,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
+{ "mulhwu.", XO(31,11,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
+
+{ "isellt",  X(31,15),      X_MASK,     PPCISEL,        { RT, RA, RB } },
+{ "iselgt",  X(31,47),      X_MASK,     PPCISEL,        { RT, RA, RB } },
+{ "iseleq",  X(31,79),      X_MASK,     PPCISEL,        { RT, RA, RB } },
+{ "isel",    XISEL(31,15),  XISEL_MASK, PPCISEL,        { RT, RA, RB, CRB } },
+
+{ "mfcr",    X(31,19),  XRARB_MASK,     NOPOWER4,       { RT } },
+{ "mfcr",    X(31,19),  XFXFXM_MASK,    POWER4,         { RT, FXM4 } },
+
+{ "lwarx",   X(31,20),  X_MASK,         PPC,            { RT, RA, RB } },
+
+{ "ldx",     X(31,21),  X_MASK,         PPC64,          { RT, RA, RB } },
+
+{ "icbt",    X(31,22),  X_MASK,         BOOKE,          { CT, RA, RB } },
+{ "icbt",    X(31,262), XRT_MASK,       PPC403,         { RA, RB } },
+
+{ "lwzx",    X(31,23),  X_MASK,         PPCCOM,         { RT, RA, RB } },
+{ "lx",      X(31,23),  X_MASK,         PWRCOM,         { RT, RA, RB } },
+
+{ "slw",     XRC(31,24,0), X_MASK,      PPCCOM,         { RA, RS, RB } },
+{ "sl",      XRC(31,24,0), X_MASK,      PWRCOM,         { RA, RS, RB } },
+{ "slw.",    XRC(31,24,1), X_MASK,      PPCCOM,         { RA, RS, RB } },
+{ "sl.",     XRC(31,24,1), X_MASK,      PWRCOM,         { RA, RS, RB } },
+
+{ "cntlzw",  XRC(31,26,0), XRB_MASK,    PPCCOM,         { RA, RS } },
+{ "cntlz",   XRC(31,26,0), XRB_MASK,    PWRCOM,         { RA, RS } },
+{ "cntlzw.", XRC(31,26,1), XRB_MASK,    PPCCOM,         { RA, RS } },
+{ "cntlz.",  XRC(31,26,1), XRB_MASK,    PWRCOM,         { RA, RS } },
+
+{ "sld",     XRC(31,27,0), X_MASK,      PPC64,          { RA, RS, RB } },
+{ "sld.",    XRC(31,27,1), X_MASK,      PPC64,          { RA, RS, RB } },
+
+{ "and",     XRC(31,28,0), X_MASK,      COM,            { RA, RS, RB } },
+{ "and.",    XRC(31,28,1), X_MASK,      COM,            { RA, RS, RB } },
+
+{ "maskg",   XRC(31,29,0), X_MASK,      M601,           { RA, RS, RB } },
+{ "maskg.",  XRC(31,29,1), X_MASK,      M601,           { RA, RS, RB } },
+
+{ "icbte",   X(31,30),  X_MASK,         BOOKE64,        { CT, RA, RB } },
+
+{ "lwzxe",   X(31,31),  X_MASK,         BOOKE64,        { RT, RA, RB } },
+
+{ "cmplw",   XCMPL(31,32,0), XCMPL_MASK, PPCCOM,        { OBF, RA, RB } },
+{ "cmpld",   XCMPL(31,32,1), XCMPL_MASK, PPC64,         { OBF, RA, RB } },
+{ "cmpl",    X(31,32),  XCMP_MASK,       PPC,           { BF, L, RA, RB } },
+{ "cmpl",    X(31,32),  XCMPL_MASK,      PWRCOM,        { BF, RA, RB } },
+
+{ "subf",    XO(31,40,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
+{ "sub",     XO(31,40,0,0), XO_MASK,    PPC,            { RT, RB, RA } },
+{ "subf.",   XO(31,40,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
+{ "sub.",    XO(31,40,0,1), XO_MASK,    PPC,            { RT, RB, RA } },
+{ "subfo",   XO(31,40,1,0), XO_MASK,    PPC,            { RT, RA, RB } },
+{ "subo",    XO(31,40,1,0), XO_MASK,    PPC,            { RT, RB, RA } },
+{ "subfo.",  XO(31,40,1,1), XO_MASK,    PPC,            { RT, RA, RB } },
+{ "subo.",   XO(31,40,1,1), XO_MASK,    PPC,            { RT, RB, RA } },
+
+{ "ldux",    X(31,53),  X_MASK,         PPC64,          { RT, RAL, RB } },
+
+{ "dcbst",   X(31,54),  XRT_MASK,       PPC,            { RA, RB } },
+
+{ "lwzux",   X(31,55),  X_MASK,         PPCCOM,         { RT, RAL, RB } },
+{ "lux",     X(31,55),  X_MASK,         PWRCOM,         { RT, RA, RB } },
+
+{ "dcbste",  X(31,62),  XRT_MASK,       BOOKE64,        { RA, RB } },
+
+{ "lwzuxe",  X(31,63),  X_MASK,         BOOKE64,        { RT, RAL, RB } },
+
+{ "cntlzd",  XRC(31,58,0), XRB_MASK,    PPC64,          { RA, RS } },
+{ "cntlzd.", XRC(31,58,1), XRB_MASK,    PPC64,          { RA, RS } },
+
+{ "andc",    XRC(31,60,0), X_MASK,      COM,            { RA, RS, RB } },
+{ "andc.",   XRC(31,60,1), X_MASK,      COM,            { RA, RS, RB } },
+
+{ "tdlgt",   XTO(31,68,TOLGT), XTO_MASK, PPC64,         { RA, RB } },
+{ "tdllt",   XTO(31,68,TOLLT), XTO_MASK, PPC64,         { RA, RB } },
+{ "tdeq",    XTO(31,68,TOEQ), XTO_MASK,  PPC64,         { RA, RB } },
+{ "tdlge",   XTO(31,68,TOLGE), XTO_MASK, PPC64,         { RA, RB } },
+{ "tdlnl",   XTO(31,68,TOLNL), XTO_MASK, PPC64,         { RA, RB } },
+{ "tdlle",   XTO(31,68,TOLLE), XTO_MASK, PPC64,         { RA, RB } },
+{ "tdlng",   XTO(31,68,TOLNG), XTO_MASK, PPC64,         { RA, RB } },
+{ "tdgt",    XTO(31,68,TOGT), XTO_MASK,  PPC64,         { RA, RB } },
+{ "tdge",    XTO(31,68,TOGE), XTO_MASK,  PPC64,         { RA, RB } },
+{ "tdnl",    XTO(31,68,TONL), XTO_MASK,  PPC64,         { RA, RB } },
+{ "tdlt",    XTO(31,68,TOLT), XTO_MASK,  PPC64,         { RA, RB } },
+{ "tdle",    XTO(31,68,TOLE), XTO_MASK,  PPC64,         { RA, RB } },
+{ "tdng",    XTO(31,68,TONG), XTO_MASK,  PPC64,         { RA, RB } },
+{ "tdne",    XTO(31,68,TONE), XTO_MASK,  PPC64,         { RA, RB } },
+{ "td",      X(31,68),  X_MASK,          PPC64,         { TO, RA, RB } },
+
+{ "mulhd",   XO(31,73,0,0), XO_MASK,     PPC64,         { RT, RA, RB } },
+{ "mulhd.",  XO(31,73,0,1), XO_MASK,     PPC64,         { RT, RA, RB } },
+
+{ "mulhw",   XO(31,75,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
+{ "mulhw.",  XO(31,75,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
+
+{ "dlmzb",   XRC(31,78,0),  X_MASK,     PPC403|PPC440,  { RA, RS, RB } },
+{ "dlmzb.",  XRC(31,78,1),  X_MASK,     PPC403|PPC440,  { RA, RS, RB } },
+
+{ "mtsrd",   X(31,82),  XRB_MASK|(1<<20), PPC64,        { SR, RS } },
+
+{ "mfmsr",   X(31,83),  XRARB_MASK,     COM,            { RT } },
+
+{ "ldarx",   X(31,84),  X_MASK,         PPC64,          { RT, RA, RB } },
+
+{ "dcbf",    X(31,86),  XRT_MASK,       PPC,            { RA, RB } },
+
+{ "lbzx",    X(31,87),  X_MASK,         COM,            { RT, RA, RB } },
+
+{ "dcbfe",   X(31,94),  XRT_MASK,       BOOKE64,        { RA, RB } },
+
+{ "lbzxe",   X(31,95),  X_MASK,         BOOKE64,        { RT, RA, RB } },
+
+{ "neg",     XO(31,104,0,0), XORB_MASK, COM,            { RT, RA } },
+{ "neg.",    XO(31,104,0,1), XORB_MASK, COM,            { RT, RA } },
+{ "nego",    XO(31,104,1,0), XORB_MASK, COM,            { RT, RA } },
+{ "nego.",   XO(31,104,1,1), XORB_MASK, COM,            { RT, RA } },
+
+{ "mul",     XO(31,107,0,0), XO_MASK,   M601,           { RT, RA, RB } },
+{ "mul.",    XO(31,107,0,1), XO_MASK,   M601,           { RT, RA, RB } },
+{ "mulo",    XO(31,107,1,0), XO_MASK,   M601,           { RT, RA, RB } },
+{ "mulo.",   XO(31,107,1,1), XO_MASK,   M601,           { RT, RA, RB } },
+
+{ "mtsrdin", X(31,114), XRA_MASK,       PPC64,          { RS, RB } },
+
+{ "clf",     X(31,118), XTO_MASK,       POWER,          { RA, RB } },
+
+{ "lbzux",   X(31,119), X_MASK,         COM,            { RT, RAL, RB } },
+
+{ "not",     XRC(31,124,0), X_MASK,     COM,            { RA, RS, RBS } },
+{ "nor",     XRC(31,124,0), X_MASK,     COM,            { RA, RS, RB } },
+{ "not.",    XRC(31,124,1), X_MASK,     COM,            { RA, RS, RBS } },
+{ "nor.",    XRC(31,124,1), X_MASK,     COM,            { RA, RS, RB } },
+
+{ "lwarxe",  X(31,126), X_MASK,         BOOKE64,        { RT, RA, RB } },
+
+{ "lbzuxe",  X(31,127), X_MASK,         BOOKE64,        { RT, RAL, RB } },
+
+{ "wrtee",   X(31,131), XRARB_MASK,     PPC403 | BOOKE, { RS } },
+
+{ "dcbtstls",X(31,134), X_MASK,         PPCCHLK,        { CT, RA, RB }},
+
+{ "subfe",   XO(31,136,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
+{ "sfe",     XO(31,136,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
+{ "subfe.",  XO(31,136,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
+{ "sfe.",    XO(31,136,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
+{ "subfeo",  XO(31,136,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
+{ "sfeo",    XO(31,136,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
+{ "subfeo.", XO(31,136,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
+{ "sfeo.",   XO(31,136,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
+
+{ "adde",    XO(31,138,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
+{ "ae",      XO(31,138,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
+{ "adde.",   XO(31,138,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
+{ "ae.",     XO(31,138,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
+{ "addeo",   XO(31,138,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
+{ "aeo",     XO(31,138,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
+{ "addeo.",  XO(31,138,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
+{ "aeo.",    XO(31,138,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
+
+{ "dcbtstlse",X(31,142),X_MASK,         PPCCHLK64,      { CT, RA, RB }},
+
+{ "mtcr",    XFXM(31,144,0xff), XRARB_MASK, COM,        { RS }},
+{ "mtcrf",   X(31,144), XFXFXM_MASK,    COM,            { FXM, RS } },
+
+{ "mtmsr",   X(31,146), XRARB_MASK,     COM,            { RS } },
+
+{ "stdx",    X(31,149), X_MASK,         PPC64,          { RS, RA, RB } },
+
+{ "stwcx.",  XRC(31,150,1), X_MASK,     PPC,            { RS, RA, RB } },
+
+{ "stwx",    X(31,151), X_MASK,         PPCCOM,         { RS, RA, RB } },
+{ "stx",     X(31,151), X_MASK,         PWRCOM,         { RS, RA, RB } },
+
+{ "stwcxe.", XRC(31,158,1), X_MASK,     BOOKE64,        { RS, RA, RB } },
+
+{ "stwxe",   X(31,159), X_MASK,         BOOKE64,        { RS, RA, RB } },
+
+{ "slq",     XRC(31,152,0), X_MASK,     M601,           { RA, RS, RB } },
+{ "slq.",    XRC(31,152,1), X_MASK,     M601,           { RA, RS, RB } },
+
+{ "sle",     XRC(31,153,0), X_MASK,     M601,           { RA, RS, RB } },
+{ "sle.",    XRC(31,153,1), X_MASK,     M601,           { RA, RS, RB } },
+
+{ "wrteei",  X(31,163), XE_MASK,        PPC403 | BOOKE, { E } },
+
+{ "dcbtls",  X(31,166), X_MASK,         PPCCHLK,        { CT, RA, RB }},
+{ "dcbtlse", X(31,174), X_MASK,         PPCCHLK64,      { CT, RA, RB }},
+
+{ "mtmsrd",  X(31,178), XRLARB_MASK,    PPC64,          { RS, MTMSRD_L } },
+
+{ "stdux",   X(31,181), X_MASK,         PPC64,          { RS, RAS, RB } },
+
+{ "stwux",   X(31,183), X_MASK,         PPCCOM,         { RS, RAS, RB } },
+{ "stux",    X(31,183), X_MASK,         PWRCOM,         { RS, RA, RB } },
+
+{ "sliq",    XRC(31,184,0), X_MASK,     M601,           { RA, RS, SH } },
+{ "sliq.",   XRC(31,184,1), X_MASK,     M601,           { RA, RS, SH } },
+
+{ "stwuxe",  X(31,191), X_MASK,         BOOKE64,        { RS, RAS, RB } },
+
+{ "subfze",  XO(31,200,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
+{ "sfze",    XO(31,200,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
+{ "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
+{ "sfze.",   XO(31,200,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
+{ "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
+{ "sfzeo",   XO(31,200,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
+{ "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
+{ "sfzeo.",  XO(31,200,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
+
+{ "addze",   XO(31,202,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
+{ "aze",     XO(31,202,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
+{ "addze.",  XO(31,202,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
+{ "aze.",    XO(31,202,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
+{ "addzeo",  XO(31,202,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
+{ "azeo",    XO(31,202,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
+{ "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
+{ "azeo.",   XO(31,202,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
+
+{ "mtsr",    X(31,210), XRB_MASK|(1<<20), COM32,        { SR, RS } },
+
+{ "stdcx.",  XRC(31,214,1), X_MASK,     PPC64,          { RS, RA, RB } },
+
+{ "stbx",    X(31,215), X_MASK,         COM,            { RS, RA, RB } },
+
+{ "sllq",    XRC(31,216,0), X_MASK,     M601,           { RA, RS, RB } },
+{ "sllq.",   XRC(31,216,1), X_MASK,     M601,           { RA, RS, RB } },
+
+{ "sleq",    XRC(31,217,0), X_MASK,     M601,           { RA, RS, RB } },
+{ "sleq.",   XRC(31,217,1), X_MASK,     M601,           { RA, RS, RB } },
+
+{ "stbxe",   X(31,223), X_MASK,         BOOKE64,        { RS, RA, RB } },
+
+{ "icblc",   X(31,230), X_MASK,         PPCCHLK,        { CT, RA, RB }},
+
+{ "subfme",  XO(31,232,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
+{ "sfme",    XO(31,232,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
+{ "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
+{ "sfme.",   XO(31,232,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
+{ "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
+{ "sfmeo",   XO(31,232,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
+{ "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
+{ "sfmeo.",  XO(31,232,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
+
+{ "mulld",   XO(31,233,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
+{ "mulld.",  XO(31,233,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
+{ "mulldo",  XO(31,233,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
+{ "mulldo.", XO(31,233,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
+
+{ "addme",   XO(31,234,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
+{ "ame",     XO(31,234,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
+{ "addme.",  XO(31,234,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
+{ "ame.",    XO(31,234,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
+{ "addmeo",  XO(31,234,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
+{ "ameo",    XO(31,234,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
+{ "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
+{ "ameo.",   XO(31,234,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
+
+{ "mullw",   XO(31,235,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
+{ "muls",    XO(31,235,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
+{ "mullw.",  XO(31,235,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
+{ "muls.",   XO(31,235,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
+{ "mullwo",  XO(31,235,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
+{ "mulso",   XO(31,235,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
+{ "mullwo.", XO(31,235,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
+{ "mulso.",  XO(31,235,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
+
+{ "icblce",  X(31,238), X_MASK,         PPCCHLK64,      { CT, RA, RB }},
+{ "mtsrin",  X(31,242), XRA_MASK,       PPC32,          { RS, RB } },
+{ "mtsri",   X(31,242), XRA_MASK,       POWER32,        { RS, RB } },
+
+{ "dcbtst",  X(31,246), XRT_MASK,       PPC,            { CT, RA, RB } },
+
+{ "stbux",   X(31,247), X_MASK,         COM,            { RS, RAS, RB } },
+
+{ "slliq",   XRC(31,248,0), X_MASK,     M601,           { RA, RS, SH } },
+{ "slliq.",  XRC(31,248,1), X_MASK,     M601,           { RA, RS, SH } },
+
+{ "dcbtste", X(31,253), X_MASK,         BOOKE64,        { CT, RA, RB } },
+
+{ "stbuxe",  X(31,255), X_MASK,         BOOKE64,        { RS, RAS, RB } },
+
+{ "mfdcrx",  X(31,259), X_MASK,         BOOKE,          { RS, RA } },
+
+{ "doz",     XO(31,264,0,0), XO_MASK,   M601,           { RT, RA, RB } },
+{ "doz.",    XO(31,264,0,1), XO_MASK,   M601,           { RT, RA, RB } },
+{ "dozo",    XO(31,264,1,0), XO_MASK,   M601,           { RT, RA, RB } },
+{ "dozo.",   XO(31,264,1,1), XO_MASK,   M601,           { RT, RA, RB } },
+
+{ "add",     XO(31,266,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
+{ "cax",     XO(31,266,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
+{ "add.",    XO(31,266,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
+{ "cax.",    XO(31,266,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
+{ "addo",    XO(31,266,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
+{ "caxo",    XO(31,266,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
+{ "addo.",   XO(31,266,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
+{ "caxo.",   XO(31,266,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
+
+{ "tlbiel",  X(31,274), XRTRA_MASK,     POWER4,         { RB } },
+
+{ "mfapidi", X(31,275), X_MASK,         BOOKE,          { RT, RA } },
+
+{ "lscbx",   XRC(31,277,0), X_MASK,     M601,           { RT, RA, RB } },
+{ "lscbx.",  XRC(31,277,1), X_MASK,     M601,           { RT, RA, RB } },
+
+{ "dcbt",    X(31,278), XRT_MASK,       PPC,            { CT, RA, RB } },
+
+{ "lhzx",    X(31,279), X_MASK,         COM,            { RT, RA, RB } },
+
+{ "eqv",     XRC(31,284,0), X_MASK,     COM,            { RA, RS, RB } },
+{ "eqv.",    XRC(31,284,1), X_MASK,     COM,            { RA, RS, RB } },
+
+{ "dcbte",   X(31,286), X_MASK,         BOOKE64,        { CT, RA, RB } },
+
+{ "lhzxe",   X(31,287), X_MASK,         BOOKE64,        { RT, RA, RB } },
+
+{ "tlbie",   X(31,306), XRTLRA_MASK,    PPC,            { RB, L } },
+{ "tlbi",    X(31,306), XRT_MASK,       POWER,          { RA, RB } },
+
+{ "eciwx",   X(31,310), X_MASK,         PPC,            { RT, RA, RB } },
+
+{ "lhzux",   X(31,311), X_MASK,         COM,            { RT, RAL, RB } },
+
+{ "xor",     XRC(31,316,0), X_MASK,     COM,            { RA, RS, RB } },
+{ "xor.",    XRC(31,316,1), X_MASK,     COM,            { RA, RS, RB } },
+
+{ "lhzuxe",  X(31,319), X_MASK,         BOOKE64,        { RT, RAL, RB } },
+
+{ "mfexisr",  XSPR(31,323,64),  XSPR_MASK, PPC403,      { RT } },
+{ "mfexier",  XSPR(31,323,66),  XSPR_MASK, PPC403,      { RT } },
+{ "mfbr0",    XSPR(31,323,128), XSPR_MASK, PPC403,      { RT } },
+{ "mfbr1",    XSPR(31,323,129), XSPR_MASK, PPC403,      { RT } },
+{ "mfbr2",    XSPR(31,323,130), XSPR_MASK, PPC403,      { RT } },
+{ "mfbr3",    XSPR(31,323,131), XSPR_MASK, PPC403,      { RT } },
+{ "mfbr4",    XSPR(31,323,132), XSPR_MASK, PPC403,      { RT } },
+{ "mfbr5",    XSPR(31,323,133), XSPR_MASK, PPC403,      { RT } },
+{ "mfbr6",    XSPR(31,323,134), XSPR_MASK, PPC403,      { RT } },
+{ "mfbr7",    XSPR(31,323,135), XSPR_MASK, PPC403,      { RT } },
+{ "mfbear",   XSPR(31,323,144), XSPR_MASK, PPC403,      { RT } },
+{ "mfbesr",   XSPR(31,323,145), XSPR_MASK, PPC403,      { RT } },
+{ "mfiocr",   XSPR(31,323,160), XSPR_MASK, PPC403,      { RT } },
+{ "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403,      { RT } },
+{ "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403,      { RT } },
+{ "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403,      { RT } },
+{ "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403,      { RT } },
+{ "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403,      { RT } },
+{ "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403,      { RT } },
+{ "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403,      { RT } },
+{ "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403,      { RT } },
+{ "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403,      { RT } },
+{ "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403,      { RT } },
+{ "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403,      { RT } },
+{ "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403,      { RT } },
+{ "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403,      { RT } },
+{ "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403,      { RT } },
+{ "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403,      { RT } },
+{ "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403,      { RT } },
+{ "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403,      { RT } },
+{ "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403,      { RT } },
+{ "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403,      { RT } },
+{ "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403,      { RT } },
+{ "mfdmasr",  XSPR(31,323,224), XSPR_MASK, PPC403,      { RT } },
+{ "mfdcr",    X(31,323),        X_MASK, PPC403 | BOOKE, { RT, SPR } },
+
+{ "div",     XO(31,331,0,0), XO_MASK,   M601,           { RT, RA, RB } },
+{ "div.",    XO(31,331,0,1), XO_MASK,   M601,           { RT, RA, RB } },
+{ "divo",    XO(31,331,1,0), XO_MASK,   M601,           { RT, RA, RB } },
+{ "divo.",   XO(31,331,1,1), XO_MASK,   M601,           { RT, RA, RB } },
+
+{ "mfpmr",   X(31,334), X_MASK,         PPCPMR,         { RT, PMR }},
+
+{ "mfmq",       XSPR(31,339,0),    XSPR_MASK, M601,     { RT } },
+{ "mfxer",      XSPR(31,339,1),    XSPR_MASK, COM,      { RT } },
+{ "mfrtcu",     XSPR(31,339,4),    XSPR_MASK, COM,      { RT } },
+{ "mfrtcl",     XSPR(31,339,5),    XSPR_MASK, COM,      { RT } },
+{ "mfdec",      XSPR(31,339,6),    XSPR_MASK, MFDEC1,   { RT } },
+{ "mfdec",      XSPR(31,339,22),   XSPR_MASK, MFDEC2,   { RT } },
+{ "mflr",       XSPR(31,339,8),    XSPR_MASK, COM,      { RT } },
+{ "mfctr",      XSPR(31,339,9),    XSPR_MASK, COM,      { RT } },
+{ "mftid",      XSPR(31,339,17),   XSPR_MASK, POWER,    { RT } },
+{ "mfdsisr",    XSPR(31,339,18),   XSPR_MASK, COM,      { RT } },
+{ "mfdar",      XSPR(31,339,19),   XSPR_MASK, COM,      { RT } },
+{ "mfsdr0",     XSPR(31,339,24),   XSPR_MASK, POWER,    { RT } },
+{ "mfsdr1",     XSPR(31,339,25),   XSPR_MASK, COM,      { RT } },
+{ "mfsrr0",     XSPR(31,339,26),   XSPR_MASK, COM,      { RT } },
+{ "mfsrr1",     XSPR(31,339,27),   XSPR_MASK, COM,      { RT } },
+{ "mfpid",      XSPR(31,339,48),   XSPR_MASK, BOOKE,    { RT } },
+{ "mfpid",      XSPR(31,339,945),  XSPR_MASK, PPC403,   { RT } },
+{ "mfcsrr0",    XSPR(31,339,58),   XSPR_MASK, BOOKE,    { RT } },
+{ "mfcsrr1",    XSPR(31,339,59),   XSPR_MASK, BOOKE,    { RT } },
+{ "mfdear",     XSPR(31,339,61),   XSPR_MASK, BOOKE,    { RT } },
+{ "mfdear",     XSPR(31,339,981),  XSPR_MASK, PPC403,   { RT } },
+{ "mfesr",      XSPR(31,339,62),   XSPR_MASK, BOOKE,    { RT } },
+{ "mfesr",      XSPR(31,339,980),  XSPR_MASK, PPC403,   { RT } },
+{ "mfivpr",     XSPR(31,339,63),   XSPR_MASK, BOOKE,    { RT } },
+{ "mfcmpa",     XSPR(31,339,144),  XSPR_MASK, PPC860,   { RT } },
+{ "mfcmpb",     XSPR(31,339,145),  XSPR_MASK, PPC860,   { RT } },
+{ "mfcmpc",     XSPR(31,339,146),  XSPR_MASK, PPC860,   { RT } },
+{ "mfcmpd",     XSPR(31,339,147),  XSPR_MASK, PPC860,   { RT } },
+{ "mficr",      XSPR(31,339,148),  XSPR_MASK, PPC860,   { RT } },
+{ "mfder",      XSPR(31,339,149),  XSPR_MASK, PPC860,   { RT } },
+{ "mfcounta",   XSPR(31,339,150),  XSPR_MASK, PPC860,   { RT } },
+{ "mfcountb",   XSPR(31,339,151),  XSPR_MASK, PPC860,   { RT } },
+{ "mfcmpe",     XSPR(31,339,152),  XSPR_MASK, PPC860,   { RT } },
+{ "mfcmpf",     XSPR(31,339,153),  XSPR_MASK, PPC860,   { RT } },
+{ "mfcmpg",     XSPR(31,339,154),  XSPR_MASK, PPC860,   { RT } },
+{ "mfcmph",     XSPR(31,339,155),  XSPR_MASK, PPC860,   { RT } },
+{ "mflctrl1",   XSPR(31,339,156),  XSPR_MASK, PPC860,   { RT } },
+{ "mflctrl2",   XSPR(31,339,157),  XSPR_MASK, PPC860,   { RT } },
+{ "mfictrl",    XSPR(31,339,158),  XSPR_MASK, PPC860,   { RT } },
+{ "mfbar",      XSPR(31,339,159),  XSPR_MASK, PPC860,   { RT } },
+{ "mfvrsave",   XSPR(31,339,256),  XSPR_MASK, PPCVEC,   { RT } },
+{ "mfusprg0",   XSPR(31,339,256),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfsprg4",    XSPR(31,339,260),  XSPR_MASK, PPC405,   { RT } },
+{ "mfsprg5",    XSPR(31,339,261),  XSPR_MASK, PPC405,   { RT } },
+{ "mfsprg6",    XSPR(31,339,262),  XSPR_MASK, PPC405,   { RT } },
+{ "mfsprg7",    XSPR(31,339,263),  XSPR_MASK, PPC405,   { RT } },
+{ "mftb",       X(31,371),         X_MASK,    CLASSIC,  { RT, TBR } },
+{ "mftb",       XSPR(31,339,268),  XSPR_MASK, BOOKE,    { RT } },
+{ "mftbl",      XSPR(31,371,268),  XSPR_MASK, CLASSIC,  { RT } },
+{ "mftbl",      XSPR(31,339,268),  XSPR_MASK, BOOKE,    { RT } },
+{ "mftbu",      XSPR(31,371,269),  XSPR_MASK, CLASSIC,  { RT } },
+{ "mftbu",      XSPR(31,339,269),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfsprg",     XSPR(31,339,272),  XSPRG_MASK, PPC,     { RT, SPRG } },
+{ "mfsprg0",    XSPR(31,339,272),  XSPR_MASK, PPC,      { RT } },
+{ "mfsprg1",    XSPR(31,339,273),  XSPR_MASK, PPC,      { RT } },
+{ "mfsprg2",    XSPR(31,339,274),  XSPR_MASK, PPC,      { RT } },
+{ "mfsprg3",    XSPR(31,339,275),  XSPR_MASK, PPC,      { RT } },
+{ "mfasr",      XSPR(31,339,280),  XSPR_MASK, PPC64,    { RT } },
+{ "mfear",      XSPR(31,339,282),  XSPR_MASK, PPC,      { RT } },
+{ "mfpir",      XSPR(31,339,286),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfpvr",      XSPR(31,339,287),  XSPR_MASK, PPC,      { RT } },
+{ "mfdbsr",     XSPR(31,339,304),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfdbsr",     XSPR(31,339,1008), XSPR_MASK, PPC403,   { RT } },
+{ "mfdbcr0",    XSPR(31,339,308),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfdbcr0",    XSPR(31,339,1010), XSPR_MASK, PPC405,   { RT } },
+{ "mfdbcr1",    XSPR(31,339,309),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfdbcr1",    XSPR(31,339,957),  XSPR_MASK, PPC405,   { RT } },
+{ "mfdbcr2",    XSPR(31,339,310),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfiac1",     XSPR(31,339,312),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfiac1",     XSPR(31,339,1012), XSPR_MASK, PPC403,   { RT } },
+{ "mfiac2",     XSPR(31,339,313),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfiac2",     XSPR(31,339,1013), XSPR_MASK, PPC403,   { RT } },
+{ "mfiac3",     XSPR(31,339,314),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfiac3",     XSPR(31,339,948),  XSPR_MASK, PPC405,   { RT } },
+{ "mfiac4",     XSPR(31,339,315),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfiac4",     XSPR(31,339,949),  XSPR_MASK, PPC405,   { RT } },
+{ "mfdac1",     XSPR(31,339,316),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfdac1",     XSPR(31,339,1014), XSPR_MASK, PPC403,   { RT } },
+{ "mfdac2",     XSPR(31,339,317),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfdac2",     XSPR(31,339,1015), XSPR_MASK, PPC403,   { RT } },
+{ "mfdvc1",     XSPR(31,339,318),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfdvc1",     XSPR(31,339,950),  XSPR_MASK, PPC405,   { RT } },
+{ "mfdvc2",     XSPR(31,339,319),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfdvc2",     XSPR(31,339,951),  XSPR_MASK, PPC405,   { RT } },
+{ "mftsr",      XSPR(31,339,336),  XSPR_MASK, BOOKE,    { RT } },
+{ "mftsr",      XSPR(31,339,984),  XSPR_MASK, PPC403,   { RT } },
+{ "mftcr",      XSPR(31,339,340),  XSPR_MASK, BOOKE,    { RT } },
+{ "mftcr",      XSPR(31,339,986),  XSPR_MASK, PPC403,   { RT } },
+{ "mfivor0",    XSPR(31,339,400),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor1",    XSPR(31,339,401),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor2",    XSPR(31,339,402),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor3",    XSPR(31,339,403),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor4",    XSPR(31,339,404),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor5",    XSPR(31,339,405),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor6",    XSPR(31,339,406),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor7",    XSPR(31,339,407),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor8",    XSPR(31,339,408),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor9",    XSPR(31,339,409),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor10",   XSPR(31,339,410),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor11",   XSPR(31,339,411),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor12",   XSPR(31,339,412),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor13",   XSPR(31,339,413),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor14",   XSPR(31,339,414),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor15",   XSPR(31,339,415),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfspefscr",  XSPR(31,339,512),  XSPR_MASK, PPCSPE,   { RT } },
+{ "mfbbear",    XSPR(31,339,513),  XSPR_MASK, PPCBRLK,  { RT } },
+{ "mfbbtar",    XSPR(31,339,514),  XSPR_MASK, PPCBRLK,  { RT } },
+{ "mfibatu",    XSPR(31,339,528),  XSPRBAT_MASK, PPC,   { RT, SPRBAT } },
+{ "mfibatl",    XSPR(31,339,529),  XSPRBAT_MASK, PPC,   { RT, SPRBAT } },
+{ "mfdbatu",    XSPR(31,339,536),  XSPRBAT_MASK, PPC,   { RT, SPRBAT } },
+{ "mfdbatl",    XSPR(31,339,537),  XSPRBAT_MASK, PPC,   { RT, SPRBAT } },
+{ "mfic_cst",   XSPR(31,339,560),  XSPR_MASK, PPC860,   { RT } },
+{ "mfic_adr",   XSPR(31,339,561),  XSPR_MASK, PPC860,   { RT } },
+{ "mfic_dat",   XSPR(31,339,562),  XSPR_MASK, PPC860,   { RT } },
+{ "mfdc_cst",   XSPR(31,339,568),  XSPR_MASK, PPC860,   { RT } },
+{ "mfdc_adr",   XSPR(31,339,569),  XSPR_MASK, PPC860,   { RT } },
+{ "mfdc_dat",   XSPR(31,339,570),  XSPR_MASK, PPC860,   { RT } },
+{ "mfmcsrr0",   XSPR(31,339,570),  XSPR_MASK, PPCRFMCI, { RT } },
+{ "mfmcsrr1",   XSPR(31,339,571),  XSPR_MASK, PPCRFMCI, { RT } },
+{ "mfmcsr",     XSPR(31,339,572),  XSPR_MASK, PPCRFMCI, { RT } },
+{ "mfdpdr",     XSPR(31,339,630),  XSPR_MASK, PPC860,   { RT } },
+{ "mfdpir",     XSPR(31,339,631),  XSPR_MASK, PPC860,   { RT } },
+{ "mfimmr",     XSPR(31,339,638),  XSPR_MASK, PPC860,   { RT } },
+{ "mfmi_ctr",   XSPR(31,339,784),  XSPR_MASK, PPC860,   { RT } },
+{ "mfmi_ap",    XSPR(31,339,786),  XSPR_MASK, PPC860,   { RT } },
+{ "mfmi_epn",   XSPR(31,339,787),  XSPR_MASK, PPC860,   { RT } },
+{ "mfmi_twc",   XSPR(31,339,789),  XSPR_MASK, PPC860,   { RT } },
+{ "mfmi_rpn",   XSPR(31,339,790),  XSPR_MASK, PPC860,   { RT } },
+{ "mfmd_ctr",   XSPR(31,339,792),  XSPR_MASK, PPC860,   { RT } },
+{ "mfm_casid",  XSPR(31,339,793),  XSPR_MASK, PPC860,   { RT } },
+{ "mfmd_ap",    XSPR(31,339,794),  XSPR_MASK, PPC860,   { RT } },
+{ "mfmd_epn",   XSPR(31,339,795),  XSPR_MASK, PPC860,   { RT } },
+{ "mfmd_twb",   XSPR(31,339,796),  XSPR_MASK, PPC860,   { RT } },
+{ "mfmd_twc",   XSPR(31,339,797),  XSPR_MASK, PPC860,   { RT } },
+{ "mfmd_rpn",   XSPR(31,339,798),  XSPR_MASK, PPC860,   { RT } },
+{ "mfm_tw",     XSPR(31,339,799),  XSPR_MASK, PPC860,   { RT } },
+{ "mfmi_dbcam", XSPR(31,339,816),  XSPR_MASK, PPC860,   { RT } },
+{ "mfmi_dbram0",XSPR(31,339,817),  XSPR_MASK, PPC860,   { RT } },
+{ "mfmi_dbram1",XSPR(31,339,818),  XSPR_MASK, PPC860,   { RT } },
+{ "mfmd_dbcam", XSPR(31,339,824),  XSPR_MASK, PPC860,   { RT } },
+{ "mfmd_dbram0",XSPR(31,339,825),  XSPR_MASK, PPC860,   { RT } },
+{ "mfmd_dbram1",XSPR(31,339,826),  XSPR_MASK, PPC860,   { RT } },
+{ "mfummcr0",   XSPR(31,339,936),  XSPR_MASK, PPC750,   { RT } },
+{ "mfupmc1",    XSPR(31,339,937),  XSPR_MASK, PPC750,   { RT } },
+{ "mfupmc2",    XSPR(31,339,938),  XSPR_MASK, PPC750,   { RT } },
+{ "mfusia",     XSPR(31,339,939),  XSPR_MASK, PPC750,   { RT } },
+{ "mfummcr1",   XSPR(31,339,940),  XSPR_MASK, PPC750,   { RT } },
+{ "mfupmc3",    XSPR(31,339,941),  XSPR_MASK, PPC750,   { RT } },
+{ "mfupmc4",    XSPR(31,339,942),  XSPR_MASK, PPC750,   { RT } },
+{ "mfzpr",      XSPR(31,339,944),  XSPR_MASK, PPC403,   { RT } },
+{ "mfccr0",     XSPR(31,339,947),  XSPR_MASK, PPC405,   { RT } },
+{ "mfmmcr0",    XSPR(31,339,952),  XSPR_MASK, PPC750,   { RT } },
+{ "mfpmc1",     XSPR(31,339,953),  XSPR_MASK, PPC750,   { RT } },
+{ "mfsgr",      XSPR(31,339,953),  XSPR_MASK, PPC403,   { RT } },
+{ "mfpmc2",     XSPR(31,339,954),  XSPR_MASK, PPC750,   { RT } },
+{ "mfdcwr",     XSPR(31,339,954),  XSPR_MASK, PPC403,   { RT } },
+{ "mfsia",      XSPR(31,339,955),  XSPR_MASK, PPC750,   { RT } },
+{ "mfsler",     XSPR(31,339,955),  XSPR_MASK, PPC405,   { RT } },
+{ "mfmmcr1",    XSPR(31,339,956),  XSPR_MASK, PPC750,   { RT } },
+{ "mfsu0r",     XSPR(31,339,956),  XSPR_MASK, PPC405,   { RT } },
+{ "mfpmc3",     XSPR(31,339,957),  XSPR_MASK, PPC750,   { RT } },
+{ "mfpmc4",     XSPR(31,339,958),  XSPR_MASK, PPC750,   { RT } },
+{ "mficdbdr",   XSPR(31,339,979),  XSPR_MASK, PPC403,   { RT } },
+{ "mfevpr",     XSPR(31,339,982),  XSPR_MASK, PPC403,   { RT } },
+{ "mfcdbcr",    XSPR(31,339,983),  XSPR_MASK, PPC403,   { RT } },
+{ "mfpit",      XSPR(31,339,987),  XSPR_MASK, PPC403,   { RT } },
+{ "mftbhi",     XSPR(31,339,988),  XSPR_MASK, PPC403,   { RT } },
+{ "mftblo",     XSPR(31,339,989),  XSPR_MASK, PPC403,   { RT } },
+{ "mfsrr2",     XSPR(31,339,990),  XSPR_MASK, PPC403,   { RT } },
+{ "mfsrr3",     XSPR(31,339,991),  XSPR_MASK, PPC403,   { RT } },
+{ "mfl2cr",     XSPR(31,339,1017), XSPR_MASK, PPC750,   { RT } },
+{ "mfdccr",     XSPR(31,339,1018), XSPR_MASK, PPC403,   { RT } },
+{ "mficcr",     XSPR(31,339,1019), XSPR_MASK, PPC403,   { RT } },
+{ "mfictc",     XSPR(31,339,1019), XSPR_MASK, PPC750,   { RT } },
+{ "mfpbl1",     XSPR(31,339,1020), XSPR_MASK, PPC403,   { RT } },
+{ "mfthrm1",    XSPR(31,339,1020), XSPR_MASK, PPC750,   { RT } },
+{ "mfpbu1",     XSPR(31,339,1021), XSPR_MASK, PPC403,   { RT } },
+{ "mfthrm2",    XSPR(31,339,1021), XSPR_MASK, PPC750,   { RT } },
+{ "mfpbl2",     XSPR(31,339,1022), XSPR_MASK, PPC403,   { RT } },
+{ "mfthrm3",    XSPR(31,339,1022), XSPR_MASK, PPC750,   { RT } },
+{ "mfpbu2",     XSPR(31,339,1023), XSPR_MASK, PPC403,   { RT } },
+{ "mfspr",      X(31,339),         X_MASK,    COM,      { RT, SPR } },
+
+{ "lwax",    X(31,341), X_MASK,         PPC64,          { RT, RA, RB } },
+
+{ "dst",     XDSS(31,342,0), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
+{ "dstt",    XDSS(31,342,1), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
+
+{ "lhax",    X(31,343), X_MASK,         COM,            { RT, RA, RB } },
+
+{ "lhaxe",   X(31,351), X_MASK,         BOOKE64,        { RT, RA, RB } },
+
+{ "dstst",   XDSS(31,374,0), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
+{ "dststt",  XDSS(31,374,1), XDSS_MASK, PPCVEC,         { RA, RB, STRM } },
+
+{ "dccci",   X(31,454), XRT_MASK,       PPC403|PPC440,  { RA, RB } },
+
+{ "abs",     XO(31,360,0,0), XORB_MASK, M601,           { RT, RA } },
+{ "abs.",    XO(31,360,0,1), XORB_MASK, M601,           { RT, RA } },
+{ "abso",    XO(31,360,1,0), XORB_MASK, M601,           { RT, RA } },
+{ "abso.",   XO(31,360,1,1), XORB_MASK, M601,           { RT, RA } },
+
+{ "divs",    XO(31,363,0,0), XO_MASK,   M601,           { RT, RA, RB } },
+{ "divs.",   XO(31,363,0,1), XO_MASK,   M601,           { RT, RA, RB } },
+{ "divso",   XO(31,363,1,0), XO_MASK,   M601,           { RT, RA, RB } },
+{ "divso.",  XO(31,363,1,1), XO_MASK,   M601,           { RT, RA, RB } },
+
+{ "tlbia",   X(31,370), 0xffffffff,     PPC,            { 0 } },
+
+{ "lwaux",   X(31,373), X_MASK,         PPC64,          { RT, RAL, RB } },
+
+{ "lhaux",   X(31,375), X_MASK,         COM,            { RT, RAL, RB } },
+
+{ "lhauxe",  X(31,383), X_MASK,         BOOKE64,        { RT, RAL, RB } },
+
+{ "mtdcrx",  X(31,387), X_MASK,         BOOKE,          { RA, RS } },
+
+{ "dcblc",   X(31,390), X_MASK,         PPCCHLK,        { CT, RA, RB }},
+
+{ "subfe64", XO(31,392,0,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
+{ "subfe64o",XO(31,392,1,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
+
+{ "adde64",  XO(31,394,0,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
+{ "adde64o", XO(31,394,1,0), XO_MASK,   BOOKE64,        { RT, RA, RB } },
+
+{ "dcblce",  X(31,398), X_MASK,         PPCCHLK64,      { CT, RA, RB }},
+
+{ "slbmte",  X(31,402), XRA_MASK,       PPC64,          { RS, RB } },
+
+{ "sthx",    X(31,407), X_MASK,         COM,            { RS, RA, RB } },
+
+{ "lfqx",    X(31,791), X_MASK,         POWER2,         { FRT, RA, RB } },
+
+{ "lfqux",   X(31,823), X_MASK,         POWER2,         { FRT, RA, RB } },
+
+{ "stfqx",   X(31,919), X_MASK,         POWER2,         { FRS, RA, RB } },
+
+{ "stfqux",  X(31,951), X_MASK,         POWER2,         { FRS, RA, RB } },
+
+{ "orc",     XRC(31,412,0), X_MASK,     COM,            { RA, RS, RB } },
+{ "orc.",    XRC(31,412,1), X_MASK,     COM,            { RA, RS, RB } },
+
+{ "sradi",   XS(31,413,0), XS_MASK,     PPC64,          { RA, RS, SH6 } },
+{ "sradi.",  XS(31,413,1), XS_MASK,     PPC64,          { RA, RS, SH6 } },
+
+{ "sthxe",   X(31,415), X_MASK,         BOOKE64,        { RS, RA, RB } },
+
+{ "slbie",   X(31,434), XRTRA_MASK,     PPC64,          { RB } },
+
+{ "ecowx",   X(31,438), X_MASK,         PPC,            { RT, RA, RB } },
+
+{ "sthux",   X(31,439), X_MASK,         COM,            { RS, RAS, RB } },
+
+{ "sthuxe",  X(31,447), X_MASK,         BOOKE64,        { RS, RAS, RB } },
+
+{ "mr",      XRC(31,444,0), X_MASK,     COM,            { RA, RS, RBS } },
+{ "or",      XRC(31,444,0), X_MASK,     COM,            { RA, RS, RB } },
+{ "mr.",     XRC(31,444,1), X_MASK,     COM,            { RA, RS, RBS } },
+{ "or.",     XRC(31,444,1), X_MASK,     COM,            { RA, RS, RB } },
+
+{ "mtexisr",  XSPR(31,451,64),  XSPR_MASK, PPC403,      { RS } },
+{ "mtexier",  XSPR(31,451,66),  XSPR_MASK, PPC403,      { RS } },
+{ "mtbr0",    XSPR(31,451,128), XSPR_MASK, PPC403,      { RS } },
+{ "mtbr1",    XSPR(31,451,129), XSPR_MASK, PPC403,      { RS } },
+{ "mtbr2",    XSPR(31,451,130), XSPR_MASK, PPC403,      { RS } },
+{ "mtbr3",    XSPR(31,451,131), XSPR_MASK, PPC403,      { RS } },
+{ "mtbr4",    XSPR(31,451,132), XSPR_MASK, PPC403,      { RS } },
+{ "mtbr5",    XSPR(31,451,133), XSPR_MASK, PPC403,      { RS } },
+{ "mtbr6",    XSPR(31,451,134), XSPR_MASK, PPC403,      { RS } },
+{ "mtbr7",    XSPR(31,451,135), XSPR_MASK, PPC403,      { RS } },
+{ "mtbear",   XSPR(31,451,144), XSPR_MASK, PPC403,      { RS } },
+{ "mtbesr",   XSPR(31,451,145), XSPR_MASK, PPC403,      { RS } },
+{ "mtiocr",   XSPR(31,451,160), XSPR_MASK, PPC403,      { RS } },
+{ "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403,      { RS } },
+{ "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403,      { RS } },
+{ "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403,      { RS } },
+{ "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403,      { RS } },
+{ "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403,      { RS } },
+{ "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403,      { RS } },
+{ "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403,      { RS } },
+{ "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403,      { RS } },
+{ "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403,      { RS } },
+{ "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403,      { RS } },
+{ "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403,      { RS } },
+{ "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403,      { RS } },
+{ "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403,      { RS } },
+{ "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403,      { RS } },
+{ "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403,      { RS } },
+{ "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403,      { RS } },
+{ "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403,      { RS } },
+{ "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403,      { RS } },
+{ "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403,      { RS } },
+{ "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403,      { RS } },
+{ "mtdmasr",  XSPR(31,451,224), XSPR_MASK, PPC403,      { RS } },
+{ "mtdcr",    X(31,451),        X_MASK, PPC403 | BOOKE, { SPR, RS } },
+
+{ "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
+{ "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64,       { RT, RA } },
+
+{ "divdu",   XO(31,457,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
+{ "divdu.",  XO(31,457,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
+{ "divduo",  XO(31,457,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
+{ "divduo.", XO(31,457,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
+
+{ "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
+{ "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64,        { RT, RA } },
+
+{ "divwu",   XO(31,459,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
+{ "divwu.",  XO(31,459,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
+{ "divwuo",  XO(31,459,1,0), XO_MASK,   PPC,            { RT, RA, RB } },
+{ "divwuo.", XO(31,459,1,1), XO_MASK,   PPC,            { RT, RA, RB } },
+
+{ "mtmq",      XSPR(31,467,0),    XSPR_MASK, M601,      { RS } },
+{ "mtxer",     XSPR(31,467,1),    XSPR_MASK, COM,       { RS } },
+{ "mtlr",      XSPR(31,467,8),    XSPR_MASK, COM,       { RS } },
+{ "mtctr",     XSPR(31,467,9),    XSPR_MASK, COM,       { RS } },
+{ "mttid",     XSPR(31,467,17),   XSPR_MASK, POWER,     { RS } },
+{ "mtdsisr",   XSPR(31,467,18),   XSPR_MASK, COM,       { RS } },
+{ "mtdar",     XSPR(31,467,19),   XSPR_MASK, COM,       { RS } },
+{ "mtrtcu",    XSPR(31,467,20),   XSPR_MASK, COM,       { RS } },
+{ "mtrtcl",    XSPR(31,467,21),   XSPR_MASK, COM,       { RS } },
+{ "mtdec",     XSPR(31,467,22),   XSPR_MASK, COM,       { RS } },
+{ "mtsdr0",    XSPR(31,467,24),   XSPR_MASK, POWER,     { RS } },
+{ "mtsdr1",    XSPR(31,467,25),   XSPR_MASK, COM,       { RS } },
+{ "mtsrr0",    XSPR(31,467,26),   XSPR_MASK, COM,       { RS } },
+{ "mtsrr1",    XSPR(31,467,27),   XSPR_MASK, COM,       { RS } },
+{ "mtpid",     XSPR(31,467,48),   XSPR_MASK, BOOKE,     { RS } },
+{ "mtpid",     XSPR(31,467,945),  XSPR_MASK, PPC403,    { RS } },
+{ "mtdecar",   XSPR(31,467,54),   XSPR_MASK, BOOKE,     { RS } },
+{ "mtcsrr0",   XSPR(31,467,58),   XSPR_MASK, BOOKE,     { RS } },
+{ "mtcsrr1",   XSPR(31,467,59),   XSPR_MASK, BOOKE,     { RS } },
+{ "mtdear",    XSPR(31,467,61),   XSPR_MASK, BOOKE,     { RS } },
+{ "mtdear",    XSPR(31,467,981),  XSPR_MASK, PPC403,    { RS } },
+{ "mtesr",     XSPR(31,467,62),   XSPR_MASK, BOOKE,     { RS } },
+{ "mtesr",     XSPR(31,467,980),  XSPR_MASK, PPC403,    { RS } },
+{ "mtivpr",    XSPR(31,467,63),   XSPR_MASK, BOOKE,     { RS } },
+{ "mtcmpa",    XSPR(31,467,144),  XSPR_MASK, PPC860,    { RS } },
+{ "mtcmpb",    XSPR(31,467,145),  XSPR_MASK, PPC860,    { RS } },
+{ "mtcmpc",    XSPR(31,467,146),  XSPR_MASK, PPC860,    { RS } },
+{ "mtcmpd",    XSPR(31,467,147),  XSPR_MASK, PPC860,    { RS } },
+{ "mticr",     XSPR(31,467,148),  XSPR_MASK, PPC860,    { RS } },
+{ "mtder",     XSPR(31,467,149),  XSPR_MASK, PPC860,    { RS } },
+{ "mtcounta",  XSPR(31,467,150),  XSPR_MASK, PPC860,    { RS } },
+{ "mtcountb",  XSPR(31,467,151),  XSPR_MASK, PPC860,    { RS } },
+{ "mtcmpe",    XSPR(31,467,152),  XSPR_MASK, PPC860,    { RS } },
+{ "mtcmpf",    XSPR(31,467,153),  XSPR_MASK, PPC860,    { RS } },
+{ "mtcmpg",    XSPR(31,467,154),  XSPR_MASK, PPC860,    { RS } },
+{ "mtcmph",    XSPR(31,467,155),  XSPR_MASK, PPC860,    { RS } },
+{ "mtlctrl1",  XSPR(31,467,156),  XSPR_MASK, PPC860,    { RS } },
+{ "mtlctrl2",  XSPR(31,467,157),  XSPR_MASK, PPC860,    { RS } },
+{ "mtictrl",   XSPR(31,467,158),  XSPR_MASK, PPC860,    { RS } },
+{ "mtbar",     XSPR(31,467,159),  XSPR_MASK, PPC860,    { RS } },
+{ "mtvrsave",  XSPR(31,467,256),  XSPR_MASK, PPCVEC,    { RS } },
+{ "mtusprg0",  XSPR(31,467,256),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtsprg",    XSPR(31,467,272),  XSPRG_MASK,PPC,       { SPRG, RS } },
+{ "mtsprg0",   XSPR(31,467,272),  XSPR_MASK, PPC,       { RS } },
+{ "mtsprg1",   XSPR(31,467,273),  XSPR_MASK, PPC,       { RS } },
+{ "mtsprg2",   XSPR(31,467,274),  XSPR_MASK, PPC,       { RS } },
+{ "mtsprg3",   XSPR(31,467,275),  XSPR_MASK, PPC,       { RS } },
+{ "mtsprg4",   XSPR(31,467,276),  XSPR_MASK, PPC405 | BOOKE, { RS } },
+{ "mtsprg5",   XSPR(31,467,277),  XSPR_MASK, PPC405 | BOOKE, { RS } },
+{ "mtsprg6",   XSPR(31,467,278),  XSPR_MASK, PPC405 | BOOKE, { RS } },
+{ "mtsprg7",   XSPR(31,467,279),  XSPR_MASK, PPC405 | BOOKE, { RS } },
+{ "mtasr",     XSPR(31,467,280),  XSPR_MASK, PPC64,     { RS } },
+{ "mtear",     XSPR(31,467,282),  XSPR_MASK, PPC,       { RS } },
+{ "mttbl",     XSPR(31,467,284),  XSPR_MASK, PPC,       { RS } },
+{ "mttbu",     XSPR(31,467,285),  XSPR_MASK, PPC,       { RS } },
+{ "mtdbsr",    XSPR(31,467,304),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtdbsr",    XSPR(31,467,1008), XSPR_MASK, PPC403,    { RS } },
+{ "mtdbcr0",   XSPR(31,467,308),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtdbcr0",   XSPR(31,467,1010), XSPR_MASK, PPC405,    { RS } },
+{ "mtdbcr1",   XSPR(31,467,309),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtdbcr1",   XSPR(31,467,957),  XSPR_MASK, PPC405,    { RS } },
+{ "mtdbcr2",   XSPR(31,467,310),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtiac1",    XSPR(31,467,312),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtiac1",    XSPR(31,467,1012), XSPR_MASK, PPC403,    { RS } },
+{ "mtiac2",    XSPR(31,467,313),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtiac2",    XSPR(31,467,1013), XSPR_MASK, PPC403,    { RS } },
+{ "mtiac3",    XSPR(31,467,314),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtiac3",    XSPR(31,467,948),  XSPR_MASK, PPC405,    { RS } },
+{ "mtiac4",    XSPR(31,467,315),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtiac4",    XSPR(31,467,949),  XSPR_MASK, PPC405,    { RS } },
+{ "mtdac1",    XSPR(31,467,316),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtdac1",    XSPR(31,467,1014), XSPR_MASK, PPC403,    { RS } },
+{ "mtdac2",    XSPR(31,467,317),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtdac2",    XSPR(31,467,1015), XSPR_MASK, PPC403,    { RS } },
+{ "mtdvc1",    XSPR(31,467,318),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtdvc1",    XSPR(31,467,950),  XSPR_MASK, PPC405,    { RS } },
+{ "mtdvc2",    XSPR(31,467,319),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtdvc2",    XSPR(31,467,951),  XSPR_MASK, PPC405,    { RS } },
+{ "mttsr",     XSPR(31,467,336),  XSPR_MASK, BOOKE,     { RS } },
+{ "mttsr",     XSPR(31,467,984),  XSPR_MASK, PPC403,    { RS } },
+{ "mttcr",     XSPR(31,467,340),  XSPR_MASK, BOOKE,     { RS } },
+{ "mttcr",     XSPR(31,467,986),  XSPR_MASK, PPC403,    { RS } },
+{ "mtivor0",   XSPR(31,467,400),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor1",   XSPR(31,467,401),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor2",   XSPR(31,467,402),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor3",   XSPR(31,467,403),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor4",   XSPR(31,467,404),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor5",   XSPR(31,467,405),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor6",   XSPR(31,467,406),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor7",   XSPR(31,467,407),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor8",   XSPR(31,467,408),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor9",   XSPR(31,467,409),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor10",  XSPR(31,467,410),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor11",  XSPR(31,467,411),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor12",  XSPR(31,467,412),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor13",  XSPR(31,467,413),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor14",  XSPR(31,467,414),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor15",  XSPR(31,467,415),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtspefscr",  XSPR(31,467,512),  XSPR_MASK, PPCSPE,   { RS } },
+{ "mtbbear",   XSPR(31,467,513),  XSPR_MASK, PPCBRLK,   { RS } },
+{ "mtbbtar",   XSPR(31,467,514),  XSPR_MASK, PPCBRLK,  { RS } },
+{ "mtibatu",   XSPR(31,467,528),  XSPRBAT_MASK, PPC,    { SPRBAT, RS } },
+{ "mtibatl",   XSPR(31,467,529),  XSPRBAT_MASK, PPC,    { SPRBAT, RS } },
+{ "mtdbatu",   XSPR(31,467,536),  XSPRBAT_MASK, PPC,    { SPRBAT, RS } },
+{ "mtdbatl",   XSPR(31,467,537),  XSPRBAT_MASK, PPC,    { SPRBAT, RS } },
+{ "mtmcsrr0",  XSPR(31,467,570),  XSPR_MASK, PPCRFMCI,  { RS } },
+{ "mtmcsrr1",  XSPR(31,467,571),  XSPR_MASK, PPCRFMCI,  { RS } },
+{ "mtmcsr",    XSPR(31,467,572),  XSPR_MASK, PPCRFMCI,  { RS } },
+{ "mtummcr0",  XSPR(31,467,936),  XSPR_MASK, PPC750,    { RS } },
+{ "mtupmc1",   XSPR(31,467,937),  XSPR_MASK, PPC750,    { RS } },
+{ "mtupmc2",   XSPR(31,467,938),  XSPR_MASK, PPC750,    { RS } },
+{ "mtusia",    XSPR(31,467,939),  XSPR_MASK, PPC750,    { RS } },
+{ "mtummcr1",  XSPR(31,467,940),  XSPR_MASK, PPC750,    { RS } },
+{ "mtupmc3",   XSPR(31,467,941),  XSPR_MASK, PPC750,    { RS } },
+{ "mtupmc4",   XSPR(31,467,942),  XSPR_MASK, PPC750,    { RS } },
+{ "mtzpr",     XSPR(31,467,944),  XSPR_MASK, PPC403,    { RS } },
+{ "mtccr0",    XSPR(31,467,947),  XSPR_MASK, PPC405,    { RS } },
+{ "mtmmcr0",   XSPR(31,467,952),  XSPR_MASK, PPC750,    { RS } },
+{ "mtsgr",     XSPR(31,467,953),  XSPR_MASK, PPC403,    { RS } },
+{ "mtpmc1",    XSPR(31,467,953),  XSPR_MASK, PPC750,    { RS } },
+{ "mtdcwr",    XSPR(31,467,954),  XSPR_MASK, PPC403,    { RS } },
+{ "mtpmc2",    XSPR(31,467,954),  XSPR_MASK, PPC750,    { RS } },
+{ "mtsler",    XSPR(31,467,955),  XSPR_MASK, PPC405,    { RS } },
+{ "mtsia",     XSPR(31,467,955),  XSPR_MASK, PPC750,    { RS } },
+{ "mtsu0r",    XSPR(31,467,956),  XSPR_MASK, PPC405,    { RS } },
+{ "mtmmcr1",   XSPR(31,467,956),  XSPR_MASK, PPC750,    { RS } },
+{ "mtpmc3",    XSPR(31,467,957),  XSPR_MASK, PPC750,    { RS } },
+{ "mtpmc4",    XSPR(31,467,958),  XSPR_MASK, PPC750,    { RS } },
+{ "mticdbdr",  XSPR(31,467,979),  XSPR_MASK, PPC403,    { RS } },
+{ "mtevpr",    XSPR(31,467,982),  XSPR_MASK, PPC403,    { RS } },
+{ "mtcdbcr",   XSPR(31,467,983),  XSPR_MASK, PPC403,    { RS } },
+{ "mtpit",     XSPR(31,467,987),  XSPR_MASK, PPC403,    { RS } },
+{ "mttbhi",    XSPR(31,467,988),  XSPR_MASK, PPC403,    { RS } },
+{ "mttblo",    XSPR(31,467,989),  XSPR_MASK, PPC403,    { RS } },
+{ "mtsrr2",    XSPR(31,467,990),  XSPR_MASK, PPC403,    { RS } },
+{ "mtsrr3",    XSPR(31,467,991),  XSPR_MASK, PPC403,    { RS } },
+{ "mtl2cr",    XSPR(31,467,1017), XSPR_MASK, PPC750,    { RS } },
+{ "mtdccr",    XSPR(31,467,1018), XSPR_MASK, PPC403,    { RS } },
+{ "mticcr",    XSPR(31,467,1019), XSPR_MASK, PPC403,    { RS } },
+{ "mtictc",    XSPR(31,467,1019), XSPR_MASK, PPC750,    { RS } },
+{ "mtpbl1",    XSPR(31,467,1020), XSPR_MASK, PPC403,    { RS } },
+{ "mtthrm1",   XSPR(31,467,1020), XSPR_MASK, PPC750,    { RS } },
+{ "mtpbu1",    XSPR(31,467,1021), XSPR_MASK, PPC403,    { RS } },
+{ "mtthrm2",   XSPR(31,467,1021), XSPR_MASK, PPC750,    { RS } },
+{ "mtpbl2",    XSPR(31,467,1022), XSPR_MASK, PPC403,    { RS } },
+{ "mtthrm3",   XSPR(31,467,1022), XSPR_MASK, PPC750,    { RS } },
+{ "mtpbu2",    XSPR(31,467,1023), XSPR_MASK, PPC403,    { RS } },
+{ "mtspr",     X(31,467),         X_MASK,    COM,       { SPR, RS } },
+
+{ "dcbi",    X(31,470), XRT_MASK,       PPC,            { RA, RB } },
+
+{ "nand",    XRC(31,476,0), X_MASK,     COM,            { RA, RS, RB } },
+{ "nand.",   XRC(31,476,1), X_MASK,     COM,            { RA, RS, RB } },
+
+{ "dcbie",   X(31,478), XRT_MASK,       BOOKE64,        { RA, RB } },
+
+{ "dcread",  X(31,486), X_MASK,         PPC403|PPC440,  { RT, RA, RB }},
+
+{ "mtpmr",   X(31,462), X_MASK,         PPCPMR,         { PMR, RS }},
+
+{ "icbtls",  X(31,486), X_MASK,         PPCCHLK,        { CT, RA, RB }},
+
+{ "nabs",    XO(31,488,0,0), XORB_MASK, M601,           { RT, RA } },
+{ "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
+{ "nabs.",   XO(31,488,0,1), XORB_MASK, M601,           { RT, RA } },
+{ "nabso",   XO(31,488,1,0), XORB_MASK, M601,           { RT, RA } },
+{ "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64,       { RT, RA } },
+{ "nabso.",  XO(31,488,1,1), XORB_MASK, M601,           { RT, RA } },
+
+{ "divd",    XO(31,489,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
+{ "divd.",   XO(31,489,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
+{ "divdo",   XO(31,489,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
+{ "divdo.",  XO(31,489,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
+
+{ "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64,        { RT, RA } },
+{ "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64,        { RT, RA } },
+
+{ "divw",    XO(31,491,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
+{ "divw.",   XO(31,491,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
+{ "divwo",   XO(31,491,1,0), XO_MASK,   PPC,            { RT, RA, RB } },
+{ "divwo.",  XO(31,491,1,1), XO_MASK,   PPC,            { RT, RA, RB } },
+
+{ "icbtlse", X(31,494), X_MASK,         PPCCHLK64,      { CT, RA, RB }},
+
+{ "slbia",   X(31,498), 0xffffffff,     PPC64,          { 0 } },
+
+{ "cli",     X(31,502), XRB_MASK,       POWER,          { RT, RA } },
+
+{ "stdcxe.", XRC(31,511,1), X_MASK,     BOOKE64,        { RS, RA, RB } },
+
+{ "mcrxr",   X(31,512), XRARB_MASK|(3<<21), COM,        { BF } },
+
+{ "bblels",  X(31,518), X_MASK,         PPCBRLK,        { 0 }},
+{ "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64,    { BF } },
+
+{ "clcs",    X(31,531), XRB_MASK,       M601,           { RT, RA } },
+
+{ "lswx",    X(31,533), X_MASK,         PPCCOM,         { RT, RA, RB } },
+{ "lsx",     X(31,533), X_MASK,         PWRCOM,         { RT, RA, RB } },
+
+{ "lwbrx",   X(31,534), X_MASK,         PPCCOM,         { RT, RA, RB } },
+{ "lbrx",    X(31,534), X_MASK,         PWRCOM,         { RT, RA, RB } },
+
+{ "lfsx",    X(31,535), X_MASK,         COM,            { FRT, RA, RB } },
+
+{ "srw",     XRC(31,536,0), X_MASK,     PPCCOM,         { RA, RS, RB } },
+{ "sr",      XRC(31,536,0), X_MASK,     PWRCOM,         { RA, RS, RB } },
+{ "srw.",    XRC(31,536,1), X_MASK,     PPCCOM,         { RA, RS, RB } },
+{ "sr.",     XRC(31,536,1), X_MASK,     PWRCOM,         { RA, RS, RB } },
+
+{ "rrib",    XRC(31,537,0), X_MASK,     M601,           { RA, RS, RB } },
+{ "rrib.",   XRC(31,537,1), X_MASK,     M601,           { RA, RS, RB } },
+
+{ "srd",     XRC(31,539,0), X_MASK,     PPC64,          { RA, RS, RB } },
+{ "srd.",    XRC(31,539,1), X_MASK,     PPC64,          { RA, RS, RB } },
+
+{ "maskir",  XRC(31,541,0), X_MASK,     M601,           { RA, RS, RB } },
+{ "maskir.", XRC(31,541,1), X_MASK,     M601,           { RA, RS, RB } },
+
+{ "lwbrxe",  X(31,542), X_MASK,         BOOKE64,        { RT, RA, RB } },
+
+{ "lfsxe",   X(31,543), X_MASK,         BOOKE64,        { FRT, RA, RB } },
+
+{ "bbelr",   X(31,550), X_MASK,         PPCBRLK,        { 0 }},
+{ "tlbsync", X(31,566), 0xffffffff,     PPC,            { 0 } },
+
+{ "lfsux",   X(31,567), X_MASK,         COM,            { FRT, RAS, RB } },
+
+{ "lfsuxe",  X(31,575), X_MASK,         BOOKE64,        { FRT, RAS, RB } },
+
+{ "mfsr",    X(31,595), XRB_MASK|(1<<20), COM32,        { RT, SR } },
+
+{ "lswi",    X(31,597), X_MASK,         PPCCOM,         { RT, RA, NB } },
+{ "lsi",     X(31,597), X_MASK,         PWRCOM,         { RT, RA, NB } },
+
+{ "lwsync",  XSYNC(31,598,1), 0xffffffff, PPC,          { 0 } },
+{ "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64,        { 0 } },
+{ "msync",   X(31,598), 0xffffffff,     BOOKE,          { 0 } },
+{ "sync",    X(31,598), XSYNC_MASK,     PPCCOM,         { LS } },
+{ "dcs",     X(31,598), 0xffffffff,     PWRCOM,         { 0 } },
+
+{ "lfdx",    X(31,599), X_MASK,         COM,            { FRT, RA, RB } },
+
+{ "lfdxe",   X(31,607), X_MASK,         BOOKE64,        { FRT, RA, RB } },
+
+{ "mfsri",   X(31,627), X_MASK,         PWRCOM,         { RT, RA, RB } },
+
+{ "dclst",   X(31,630), XRB_MASK,       PWRCOM,         { RS, RA } },
+
+{ "lfdux",   X(31,631), X_MASK,         COM,            { FRT, RAS, RB } },
+
+{ "lfduxe",  X(31,639), X_MASK,         BOOKE64,        { FRT, RAS, RB } },
+
+{ "mfsrin",  X(31,659), XRA_MASK,       PPC32,          { RT, RB } },
+
+{ "stswx",   X(31,661), X_MASK,         PPCCOM,         { RS, RA, RB } },
+{ "stsx",    X(31,661), X_MASK,         PWRCOM,         { RS, RA, RB } },
+
+{ "stwbrx",  X(31,662), X_MASK,         PPCCOM,         { RS, RA, RB } },
+{ "stbrx",   X(31,662), X_MASK,         PWRCOM,         { RS, RA, RB } },
+
+{ "stfsx",   X(31,663), X_MASK,         COM,            { FRS, RA, RB } },
+
+{ "srq",     XRC(31,664,0), X_MASK,     M601,           { RA, RS, RB } },
+{ "srq.",    XRC(31,664,1), X_MASK,     M601,           { RA, RS, RB } },
+
+{ "sre",     XRC(31,665,0), X_MASK,     M601,           { RA, RS, RB } },
+{ "sre.",    XRC(31,665,1), X_MASK,     M601,           { RA, RS, RB } },
+
+{ "stwbrxe", X(31,670), X_MASK,         BOOKE64,        { RS, RA, RB } },
+
+{ "stfsxe",  X(31,671), X_MASK,         BOOKE64,        { FRS, RA, RB } },
+
+{ "stfsux",  X(31,695), X_MASK,         COM,            { FRS, RAS, RB } },
+
+{ "sriq",    XRC(31,696,0), X_MASK,     M601,           { RA, RS, SH } },
+{ "sriq.",   XRC(31,696,1), X_MASK,     M601,           { RA, RS, SH } },
+
+{ "stfsuxe", X(31,703), X_MASK,         BOOKE64,        { FRS, RAS, RB } },
+
+{ "stswi",   X(31,725), X_MASK,         PPCCOM,         { RS, RA, NB } },
+{ "stsi",    X(31,725), X_MASK,         PWRCOM,         { RS, RA, NB } },
+
+{ "stfdx",   X(31,727), X_MASK,         COM,            { FRS, RA, RB } },
+
+{ "srlq",    XRC(31,728,0), X_MASK,     M601,           { RA, RS, RB } },
+{ "srlq.",   XRC(31,728,1), X_MASK,     M601,           { RA, RS, RB } },
+
+{ "sreq",    XRC(31,729,0), X_MASK,     M601,           { RA, RS, RB } },
+{ "sreq.",   XRC(31,729,1), X_MASK,     M601,           { RA, RS, RB } },
+
+{ "stfdxe",  X(31,735), X_MASK,         BOOKE64,        { FRS, RA, RB } },
+
+{ "dcba",    X(31,758), XRT_MASK,       PPC405 | BOOKE, { RA, RB } },
+
+{ "stfdux",  X(31,759), X_MASK,         COM,            { FRS, RAS, RB } },
+
+{ "srliq",   XRC(31,760,0), X_MASK,     M601,           { RA, RS, SH } },
+{ "srliq.",  XRC(31,760,1), X_MASK,     M601,           { RA, RS, SH } },
+
+{ "dcbae",   X(31,766), XRT_MASK,       BOOKE64,        { RA, RB } },
+
+{ "stfduxe", X(31,767), X_MASK,         BOOKE64,        { FRS, RAS, RB } },
+
+{ "tlbivax", X(31,786), XRT_MASK,       BOOKE,          { RA, RB } },
+{ "tlbivaxe",X(31,787), XRT_MASK,       BOOKE64,        { RA, RB } },
+
+{ "lhbrx",   X(31,790), X_MASK,         COM,            { RT, RA, RB } },
+
+{ "sraw",    XRC(31,792,0), X_MASK,     PPCCOM,         { RA, RS, RB } },
+{ "sra",     XRC(31,792,0), X_MASK,     PWRCOM,         { RA, RS, RB } },
+{ "sraw.",   XRC(31,792,1), X_MASK,     PPCCOM,         { RA, RS, RB } },
+{ "sra.",    XRC(31,792,1), X_MASK,     PWRCOM,         { RA, RS, RB } },
+
+{ "srad",    XRC(31,794,0), X_MASK,     PPC64,          { RA, RS, RB } },
+{ "srad.",   XRC(31,794,1), X_MASK,     PPC64,          { RA, RS, RB } },
+
+{ "lhbrxe",  X(31,798), X_MASK,         BOOKE64,        { RT, RA, RB } },
+
+{ "ldxe",    X(31,799), X_MASK,         BOOKE64,        { RT, RA, RB } },
+{ "lduxe",   X(31,831), X_MASK,         BOOKE64,        { RT, RA, RB } },
+
+{ "rac",     X(31,818), X_MASK,         PWRCOM,         { RT, RA, RB } },
+
+{ "dss",     XDSS(31,822,0), XDSS_MASK, PPCVEC,         { STRM } },
+{ "dssall",  XDSS(31,822,1), XDSS_MASK, PPCVEC,         { 0 } },
+
+{ "srawi",   XRC(31,824,0), X_MASK,     PPCCOM,         { RA, RS, SH } },
+{ "srai",    XRC(31,824,0), X_MASK,     PWRCOM,         { RA, RS, SH } },
+{ "srawi.",  XRC(31,824,1), X_MASK,     PPCCOM,         { RA, RS, SH } },
+{ "srai.",   XRC(31,824,1), X_MASK,     PWRCOM,         { RA, RS, SH } },
+
+{ "slbmfev", X(31,851), XRA_MASK,       PPC64,          { RT, RB } },
+
+{ "mbar",    X(31,854), X_MASK,         BOOKE,          { MO } },
+{ "eieio",   X(31,854), 0xffffffff,     PPC,            { 0 } },
+
+{ "tlbsx",   XRC(31,914,0), X_MASK,     BOOKE,          { RA, RB } },
+{ "tlbsx",   XRC(31,914,0), X_MASK,     PPC403,         { RT, RA, RB } },
+{ "tlbsx.",  XRC(31,914,1), X_MASK,     BOOKE,          { RA, RB } },
+{ "tlbsx.",  XRC(31,914,1), X_MASK,     PPC403,         { RT, RA, RB } },
+{ "tlbsxe",  XRC(31,915,0), X_MASK,     BOOKE64,        { RA, RB } },
+{ "tlbsxe.", XRC(31,915,1), X_MASK,     BOOKE64,        { RA, RB } },
+
+{ "slbmfee", X(31,915), XRA_MASK,       PPC64,          { RT, RB } },
+
+{ "sthbrx",  X(31,918), X_MASK,         COM,            { RS, RA, RB } },
+
+{ "sraq",    XRC(31,920,0), X_MASK,     M601,           { RA, RS, RB } },
+{ "sraq.",   XRC(31,920,1), X_MASK,     M601,           { RA, RS, RB } },
+
+{ "srea",    XRC(31,921,0), X_MASK,     M601,           { RA, RS, RB } },
+{ "srea.",   XRC(31,921,1), X_MASK,     M601,           { RA, RS, RB } },
+
+{ "extsh",   XRC(31,922,0), XRB_MASK,   PPCCOM,         { RA, RS } },
+{ "exts",    XRC(31,922,0), XRB_MASK,   PWRCOM,         { RA, RS } },
+{ "extsh.",  XRC(31,922,1), XRB_MASK,   PPCCOM,         { RA, RS } },
+{ "exts.",   XRC(31,922,1), XRB_MASK,   PWRCOM,         { RA, RS } },
+
+{ "sthbrxe", X(31,926), X_MASK,         BOOKE64,        { RS, RA, RB } },
+
+{ "stdxe",   X(31,927), X_MASK,         BOOKE64,        { RS, RA, RB } },
+
+{ "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403,         { RT, RA } },
+{ "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403,         { RT, RA } },
+{ "tlbre",   X(31,946), X_MASK,         BOOKE,          { 0 } },
+{ "tlbre",   X(31,946), X_MASK,         PPC403,         { RS, RA, SH } },
+
+{ "sraiq",   XRC(31,952,0), X_MASK,     M601,           { RA, RS, SH } },
+{ "sraiq.",  XRC(31,952,1), X_MASK,     M601,           { RA, RS, SH } },
+
+{ "extsb",   XRC(31,954,0), XRB_MASK,   PPC,            { RA, RS} },
+{ "extsb.",  XRC(31,954,1), XRB_MASK,   PPC,            { RA, RS} },
+
+{ "stduxe",  X(31,959), X_MASK,         BOOKE64,        { RS, RAS, RB } },
+
+{ "iccci",   X(31,966), XRT_MASK,       PPC403|PPC440,  { RA, RB } },
+
+{ "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403,         { RT, RA } },
+{ "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403,         { RT, RA } },
+{ "tlbwe",   X(31,978), X_MASK,         BOOKE,          { 0 } },
+{ "tlbwe",   X(31,978), X_MASK,         PPC403,         { RS, RA, SH } },
+{ "tlbld",   X(31,978), XRTRA_MASK,     PPC,            { RB } },
+
+{ "icbi",    X(31,982), XRT_MASK,       PPC,            { RA, RB } },
+
+{ "stfiwx",  X(31,983), X_MASK,         PPC,            { FRS, RA, RB } },
+
+{ "extsw",   XRC(31,986,0), XRB_MASK,   PPC64 | BOOKE64,{ RA, RS } },
+{ "extsw.",  XRC(31,986,1), XRB_MASK,   PPC64,          { RA, RS } },
+
+{ "icread",  X(31,998), XRT_MASK,       PPC403|PPC440,  { RA, RB } },
+
+{ "icbie",   X(31,990), XRT_MASK,       BOOKE64,        { RA, RB } },
+{ "stfiwxe", X(31,991), X_MASK,         BOOKE64,        { FRS, RA, RB } },
+
+{ "tlbli",   X(31,1010), XRTRA_MASK,    PPC,            { RB } },
+
+{ "dcbz",    X(31,1014), XRT_MASK,      PPC,            { RA, RB } },
+{ "dclz",    X(31,1014), XRT_MASK,      PPC,            { RA, RB } },
+
+{ "dcbze",   X(31,1022), XRT_MASK,      BOOKE64,        { RA, RB } },
+
+{ "lvebx",   X(31,   7), X_MASK,        PPCVEC,         { VD, RA, RB } },
+{ "lvehx",   X(31,  39), X_MASK,        PPCVEC,         { VD, RA, RB } },
+{ "lvewx",   X(31,  71), X_MASK,        PPCVEC,         { VD, RA, RB } },
+{ "lvsl",    X(31,   6), X_MASK,        PPCVEC,         { VD, RA, RB } },
+{ "lvsr",    X(31,  38), X_MASK,        PPCVEC,         { VD, RA, RB } },
+{ "lvx",     X(31, 103), X_MASK,        PPCVEC,         { VD, RA, RB } },
+{ "lvxl",    X(31, 359), X_MASK,        PPCVEC,         { VD, RA, RB } },
+{ "stvebx",  X(31, 135), X_MASK,        PPCVEC,         { VS, RA, RB } },
+{ "stvehx",  X(31, 167), X_MASK,        PPCVEC,         { VS, RA, RB } },
+{ "stvewx",  X(31, 199), X_MASK,        PPCVEC,         { VS, RA, RB } },
+{ "stvx",    X(31, 231), X_MASK,        PPCVEC,         { VS, RA, RB } },
+{ "stvxl",   X(31, 487), X_MASK,        PPCVEC,         { VS, RA, RB } },
+
+{ "lwz",     OP(32),    OP_MASK,        PPCCOM,         { RT, D, RA } },
+{ "l",       OP(32),    OP_MASK,        PWRCOM,         { RT, D, RA } },
+
+{ "lwzu",    OP(33),    OP_MASK,        PPCCOM,         { RT, D, RAL } },
+{ "lu",      OP(33),    OP_MASK,        PWRCOM,         { RT, D, RA } },
+
+{ "lbz",     OP(34),    OP_MASK,        COM,            { RT, D, RA } },
+
+{ "lbzu",    OP(35),    OP_MASK,        COM,            { RT, D, RAL } },
+
+{ "stw",     OP(36),    OP_MASK,        PPCCOM,         { RS, D, RA } },
+{ "st",      OP(36),    OP_MASK,        PWRCOM,         { RS, D, RA } },
+
+{ "stwu",    OP(37),    OP_MASK,        PPCCOM,         { RS, D, RAS } },
+{ "stu",     OP(37),    OP_MASK,        PWRCOM,         { RS, D, RA } },
+
+{ "stb",     OP(38),    OP_MASK,        COM,            { RS, D, RA } },
+
+{ "stbu",    OP(39),    OP_MASK,        COM,            { RS, D, RAS } },
+
+{ "lhz",     OP(40),    OP_MASK,        COM,            { RT, D, RA } },
+
+{ "lhzu",    OP(41),    OP_MASK,        COM,            { RT, D, RAL } },
+
+{ "lha",     OP(42),    OP_MASK,        COM,            { RT, D, RA } },
+
+{ "lhau",    OP(43),    OP_MASK,        COM,            { RT, D, RAL } },
+
+{ "sth",     OP(44),    OP_MASK,        COM,            { RS, D, RA } },
+
+{ "sthu",    OP(45),    OP_MASK,        COM,            { RS, D, RAS } },
+
+{ "lmw",     OP(46),    OP_MASK,        PPCCOM,         { RT, D, RAM } },
+{ "lm",      OP(46),    OP_MASK,        PWRCOM,         { RT, D, RA } },
+
+{ "stmw",    OP(47),    OP_MASK,        PPCCOM,         { RS, D, RA } },
+{ "stm",     OP(47),    OP_MASK,        PWRCOM,         { RS, D, RA } },
+
+{ "lfs",     OP(48),    OP_MASK,        COM,            { FRT, D, RA } },
+
+{ "lfsu",    OP(49),    OP_MASK,        COM,            { FRT, D, RAS } },
+
+{ "lfd",     OP(50),    OP_MASK,        COM,            { FRT, D, RA } },
+
+{ "lfdu",    OP(51),    OP_MASK,        COM,            { FRT, D, RAS } },
+
+{ "stfs",    OP(52),    OP_MASK,        COM,            { FRS, D, RA } },
+
+{ "stfsu",   OP(53),    OP_MASK,        COM,            { FRS, D, RAS } },
+
+{ "stfd",    OP(54),    OP_MASK,        COM,            { FRS, D, RA } },
+
+{ "stfdu",   OP(55),    OP_MASK,        COM,            { FRS, D, RAS } },
+
+{ "lq",      OP(56),    OP_MASK,        POWER4,         { RTQ, DQ, RAQ } },
+
+{ "lfq",     OP(56),    OP_MASK,        POWER2,         { FRT, D, RA } },
+
+{ "lfqu",    OP(57),    OP_MASK,        POWER2,         { FRT, D, RA } },
+
+{ "lbze",    DEO(58,0), DE_MASK,        BOOKE64,        { RT, DE, RA } },
+{ "lbzue",   DEO(58,1), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
+{ "lhze",    DEO(58,2), DE_MASK,        BOOKE64,        { RT, DE, RA } },
+{ "lhzue",   DEO(58,3), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
+{ "lhae",    DEO(58,4), DE_MASK,        BOOKE64,        { RT, DE, RA } },
+{ "lhaue",   DEO(58,5), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
+{ "lwze",    DEO(58,6), DE_MASK,        BOOKE64,        { RT, DE, RA } },
+{ "lwzue",   DEO(58,7), DE_MASK,        BOOKE64,        { RT, DE, RAL } },
+{ "stbe",    DEO(58,8), DE_MASK,        BOOKE64,        { RS, DE, RA } },
+{ "stbue",   DEO(58,9), DE_MASK,        BOOKE64,        { RS, DE, RAS } },
+{ "sthe",    DEO(58,10), DE_MASK,       BOOKE64,        { RS, DE, RA } },
+{ "sthue",   DEO(58,11), DE_MASK,       BOOKE64,        { RS, DE, RAS } },
+{ "stwe",    DEO(58,14), DE_MASK,       BOOKE64,        { RS, DE, RA } },
+{ "stwue",   DEO(58,15), DE_MASK,       BOOKE64,        { RS, DE, RAS } },
+
+{ "ld",      DSO(58,0), DS_MASK,        PPC64,          { RT, DS, RA } },
+
+{ "ldu",     DSO(58,1), DS_MASK,        PPC64,          { RT, DS, RAL } },
+
+{ "lwa",     DSO(58,2), DS_MASK,        PPC64,          { RT, DS, RA } },
+
+{ "fdivs",   A(59,18,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
+{ "fdivs.",  A(59,18,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
+
+{ "fsubs",   A(59,20,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
+{ "fsubs.",  A(59,20,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
+
+{ "fadds",   A(59,21,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
+{ "fadds.",  A(59,21,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
+
+{ "fsqrts",  A(59,22,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
+{ "fsqrts.", A(59,22,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
+
+{ "fres",    A(59,24,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
+{ "fres.",   A(59,24,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
+
+{ "fmuls",   A(59,25,0), AFRB_MASK,     PPC,            { FRT, FRA, FRC } },
+{ "fmuls.",  A(59,25,1), AFRB_MASK,     PPC,            { FRT, FRA, FRC } },
+
+{ "fmsubs",  A(59,28,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
+{ "fmsubs.", A(59,28,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
+
+{ "fmadds",  A(59,29,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
+{ "fmadds.", A(59,29,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
+
+{ "fnmsubs", A(59,30,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
+{ "fnmsubs.",A(59,30,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
+
+{ "fnmadds", A(59,31,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
+{ "fnmadds.",A(59,31,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
+
+{ "stfq",    OP(60),    OP_MASK,        POWER2,         { FRS, D, RA } },
+
+{ "stfqu",   OP(61),    OP_MASK,        POWER2,         { FRS, D, RA } },
+
+{ "lde",     DEO(62,0), DE_MASK,        BOOKE64,        { RT, DES, RA } },
+{ "ldue",    DEO(62,1), DE_MASK,        BOOKE64,        { RT, DES, RA } },
+{ "lfse",    DEO(62,4), DE_MASK,        BOOKE64,        { FRT, DES, RA } },
+{ "lfsue",   DEO(62,5), DE_MASK,        BOOKE64,        { FRT, DES, RAS } },
+{ "lfde",    DEO(62,6), DE_MASK,        BOOKE64,        { FRT, DES, RA } },
+{ "lfdue",   DEO(62,7), DE_MASK,        BOOKE64,        { FRT, DES, RAS } },
+{ "stde",    DEO(62,8), DE_MASK,        BOOKE64,        { RS, DES, RA } },
+{ "stdue",   DEO(62,9), DE_MASK,        BOOKE64,        { RS, DES, RAS } },
+{ "stfse",   DEO(62,12), DE_MASK,       BOOKE64,        { FRS, DES, RA } },
+{ "stfsue",  DEO(62,13), DE_MASK,       BOOKE64,        { FRS, DES, RAS } },
+{ "stfde",   DEO(62,14), DE_MASK,       BOOKE64,        { FRS, DES, RA } },
+{ "stfdue",  DEO(62,15), DE_MASK,       BOOKE64,        { FRS, DES, RAS } },
+
+{ "std",     DSO(62,0), DS_MASK,        PPC64,          { RS, DS, RA } },
+
+{ "stdu",    DSO(62,1), DS_MASK,        PPC64,          { RS, DS, RAS } },
+
+{ "stq",     DSO(62,2), DS_MASK,        POWER4,         { RSQ, DS, RA } },
+
+{ "fcmpu",   X(63,0),   X_MASK|(3<<21), COM,            { BF, FRA, FRB } },
+
+{ "frsp",    XRC(63,12,0), XRA_MASK,    COM,            { FRT, FRB } },
+{ "frsp.",   XRC(63,12,1), XRA_MASK,    COM,            { FRT, FRB } },
+
+{ "fctiw",   XRC(63,14,0), XRA_MASK,    PPCCOM,         { FRT, FRB } },
+{ "fcir",    XRC(63,14,0), XRA_MASK,    POWER2,         { FRT, FRB } },
+{ "fctiw.",  XRC(63,14,1), XRA_MASK,    PPCCOM,         { FRT, FRB } },
+{ "fcir.",   XRC(63,14,1), XRA_MASK,    POWER2,         { FRT, FRB } },
+
+{ "fctiwz",  XRC(63,15,0), XRA_MASK,    PPCCOM,         { FRT, FRB } },
+{ "fcirz",   XRC(63,15,0), XRA_MASK,    POWER2,         { FRT, FRB } },
+{ "fctiwz.", XRC(63,15,1), XRA_MASK,    PPCCOM,         { FRT, FRB } },
+{ "fcirz.",  XRC(63,15,1), XRA_MASK,    POWER2,         { FRT, FRB } },
+
+{ "fdiv",    A(63,18,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
+{ "fd",      A(63,18,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
+{ "fdiv.",   A(63,18,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
+{ "fd.",     A(63,18,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
+
+{ "fsub",    A(63,20,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
+{ "fs",      A(63,20,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
+{ "fsub.",   A(63,20,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
+{ "fs.",     A(63,20,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
+
+{ "fadd",    A(63,21,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
+{ "fa",      A(63,21,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
+{ "fadd.",   A(63,21,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
+{ "fa.",     A(63,21,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
+
+{ "fsqrt",   A(63,22,0), AFRAFRC_MASK,  PPCPWR2,        { FRT, FRB } },
+{ "fsqrt.",  A(63,22,1), AFRAFRC_MASK,  PPCPWR2,        { FRT, FRB } },
+
+{ "fsel",    A(63,23,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
+{ "fsel.",   A(63,23,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
+
+{ "fmul",    A(63,25,0), AFRB_MASK,     PPCCOM,         { FRT, FRA, FRC } },
+{ "fm",      A(63,25,0), AFRB_MASK,     PWRCOM,         { FRT, FRA, FRC } },
+{ "fmul.",   A(63,25,1), AFRB_MASK,     PPCCOM,         { FRT, FRA, FRC } },
+{ "fm.",     A(63,25,1), AFRB_MASK,     PWRCOM,         { FRT, FRA, FRC } },
+
+{ "frsqrte", A(63,26,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
+{ "frsqrte.",A(63,26,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
+
+{ "fmsub",   A(63,28,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
+{ "fms",     A(63,28,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
+{ "fmsub.",  A(63,28,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
+{ "fms.",    A(63,28,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
+
+{ "fmadd",   A(63,29,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
+{ "fma",     A(63,29,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
+{ "fmadd.",  A(63,29,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
+{ "fma.",    A(63,29,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
+
+{ "fnmsub",  A(63,30,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
+{ "fnms",    A(63,30,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
+{ "fnmsub.", A(63,30,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
+{ "fnms.",   A(63,30,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
+
+{ "fnmadd",  A(63,31,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
+{ "fnma",    A(63,31,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
+{ "fnmadd.", A(63,31,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
+{ "fnma.",   A(63,31,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
+
+{ "fcmpo",   X(63,32),  X_MASK|(3<<21), COM,            { BF, FRA, FRB } },
+
+{ "mtfsb1",  XRC(63,38,0), XRARB_MASK,  COM,            { BT } },
+{ "mtfsb1.", XRC(63,38,1), XRARB_MASK,  COM,            { BT } },
+
+{ "fneg",    XRC(63,40,0), XRA_MASK,    COM,            { FRT, FRB } },
+{ "fneg.",   XRC(63,40,1), XRA_MASK,    COM,            { FRT, FRB } },
+
+{ "mcrfs",   X(63,64),  XRB_MASK|(3<<21)|(3<<16), COM,  { BF, BFA } },
+
+{ "mtfsb0",  XRC(63,70,0), XRARB_MASK,  COM,            { BT } },
+{ "mtfsb0.", XRC(63,70,1), XRARB_MASK,  COM,            { BT } },
+
+{ "fmr",     XRC(63,72,0), XRA_MASK,    COM,            { FRT, FRB } },
+{ "fmr.",    XRC(63,72,1), XRA_MASK,    COM,            { FRT, FRB } },
+
+{ "mtfsfi",  XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
+{ "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
+
+{ "fnabs",   XRC(63,136,0), XRA_MASK,   COM,            { FRT, FRB } },
+{ "fnabs.",  XRC(63,136,1), XRA_MASK,   COM,            { FRT, FRB } },
+
+{ "fabs",    XRC(63,264,0), XRA_MASK,   COM,            { FRT, FRB } },
+{ "fabs.",   XRC(63,264,1), XRA_MASK,   COM,            { FRT, FRB } },
+
+{ "mffs",    XRC(63,583,0), XRARB_MASK, COM,            { FRT } },
+{ "mffs.",   XRC(63,583,1), XRARB_MASK, COM,            { FRT } },
+
+{ "mtfsf",   XFL(63,711,0), XFL_MASK,   COM,            { FLM, FRB } },
+{ "mtfsf.",  XFL(63,711,1), XFL_MASK,   COM,            { FLM, FRB } },
+
+{ "fctid",   XRC(63,814,0), XRA_MASK,   PPC64,          { FRT, FRB } },
+{ "fctid.",  XRC(63,814,1), XRA_MASK,   PPC64,          { FRT, FRB } },
+
+{ "fctidz",  XRC(63,815,0), XRA_MASK,   PPC64,          { FRT, FRB } },
+{ "fctidz.", XRC(63,815,1), XRA_MASK,   PPC64,          { FRT, FRB } },
+
+{ "fcfid",   XRC(63,846,0), XRA_MASK,   PPC64,          { FRT, FRB } },
+{ "fcfid.",  XRC(63,846,1), XRA_MASK,   PPC64,          { FRT, FRB } },
+
+};
+
+const int powerpc_num_opcodes =
+  sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
+
+/* The macro table.  This is only used by the assembler.  */
+
+/* The expressions of the form (-x ! 31) & (x | 31) have the value 0
+   when x=0; 32-x when x is between 1 and 31; are negative if x is
+   negative; and are 32 or more otherwise.  This is what you want
+   when, for instance, you are emulating a right shift by a
+   rotate-left-and-mask, because the underlying instructions support
+   shifts of size 0 but not shifts of size 32.  By comparison, when
+   extracting x bits from some word you want to use just 32-x, because
+   the underlying instructions don't support extracting 0 bits but do
+   support extracting the whole word (32 bits in this case).  */
+
+const struct powerpc_macro powerpc_macros[] = {
+{ "extldi",  4,   PPC64,        "rldicr %0,%1,%3,(%2)-1" },
+{ "extldi.", 4,   PPC64,        "rldicr. %0,%1,%3,(%2)-1" },
+{ "extrdi",  4,   PPC64,        "rldicl %0,%1,(%2)+(%3),64-(%2)" },
+{ "extrdi.", 4,   PPC64,        "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
+{ "insrdi",  4,   PPC64,        "rldimi %0,%1,64-((%2)+(%3)),%3" },
+{ "insrdi.", 4,   PPC64,        "rldimi. %0,%1,64-((%2)+(%3)),%3" },
+{ "rotrdi",  3,   PPC64,        "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
+{ "rotrdi.", 3,   PPC64,        "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
+{ "sldi",    3,   PPC64,        "rldicr %0,%1,%2,63-(%2)" },
+{ "sldi.",   3,   PPC64,        "rldicr. %0,%1,%2,63-(%2)" },
+{ "srdi",    3,   PPC64,        "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
+{ "srdi.",   3,   PPC64,        "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
+{ "clrrdi",  3,   PPC64,        "rldicr %0,%1,0,63-(%2)" },
+{ "clrrdi.", 3,   PPC64,        "rldicr. %0,%1,0,63-(%2)" },
+{ "clrlsldi",4,   PPC64,        "rldic %0,%1,%3,(%2)-(%3)" },
+{ "clrlsldi.",4,  PPC64,        "rldic. %0,%1,%3,(%2)-(%3)" },
+
+{ "extlwi",  4,   PPCCOM,       "rlwinm %0,%1,%3,0,(%2)-1" },
+{ "extlwi.", 4,   PPCCOM,       "rlwinm. %0,%1,%3,0,(%2)-1" },
+{ "extrwi",  4,   PPCCOM,       "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
+{ "extrwi.", 4,   PPCCOM,       "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
+{ "inslwi",  4,   PPCCOM,       "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
+{ "inslwi.", 4,   PPCCOM,       "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
+{ "insrwi",  4,   PPCCOM,       "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
+{ "insrwi.", 4,   PPCCOM,       "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
+{ "rotrwi",  3,   PPCCOM,       "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
+{ "rotrwi.", 3,   PPCCOM,       "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
+{ "slwi",    3,   PPCCOM,       "rlwinm %0,%1,%2,0,31-(%2)" },
+{ "sli",     3,   PWRCOM,       "rlinm %0,%1,%2,0,31-(%2)" },
+{ "slwi.",   3,   PPCCOM,       "rlwinm. %0,%1,%2,0,31-(%2)" },
+{ "sli.",    3,   PWRCOM,       "rlinm. %0,%1,%2,0,31-(%2)" },
+{ "srwi",    3,   PPCCOM,       "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
+{ "sri",     3,   PWRCOM,       "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
+{ "srwi.",   3,   PPCCOM,       "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
+{ "sri.",    3,   PWRCOM,       "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
+{ "clrrwi",  3,   PPCCOM,       "rlwinm %0,%1,0,0,31-(%2)" },
+{ "clrrwi.", 3,   PPCCOM,       "rlwinm. %0,%1,0,0,31-(%2)" },
+{ "clrlslwi",4,   PPCCOM,       "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
+{ "clrlslwi.",4,  PPCCOM,       "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
+};
+
+const int powerpc_num_macros =
+  sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
diff --git a/arch/powerpc/xmon/ppc.h b/arch/powerpc/xmon/ppc.h
new file mode 100644
index 000000000000..342237e8dd69
--- /dev/null
+++ b/arch/powerpc/xmon/ppc.h
@@ -0,0 +1,307 @@
+/* ppc.h -- Header file for PowerPC opcode table
+   Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003
+   Free Software Foundation, Inc.
+   Written by Ian Lance Taylor, Cygnus Support
+
+This file is part of GDB, GAS, and the GNU binutils.
+
+GDB, GAS, and the GNU binutils are free software; you can redistribute
+them and/or modify them under the terms of the GNU General Public
+License as published by the Free Software Foundation; either version
+1, or (at your option) any later version.
+
+GDB, GAS, and the GNU binutils are distributed in the hope that they
+will be useful, but WITHOUT ANY WARRANTY; without even the implied
+warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+the GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this file; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#ifndef PPC_H
+#define PPC_H
+
+/* The opcode table is an array of struct powerpc_opcode.  */
+
+struct powerpc_opcode
+{
+  /* The opcode name.  */
+  const char *name;
+
+  /* The opcode itself.  Those bits which will be filled in with
+     operands are zeroes.  */
+  unsigned long opcode;
+
+  /* The opcode mask.  This is used by the disassembler.  This is a
+     mask containing ones indicating those bits which must match the
+     opcode field, and zeroes indicating those bits which need not
+     match (and are presumably filled in by operands).  */
+  unsigned long mask;
+
+  /* One bit flags for the opcode.  These are used to indicate which
+     specific processors support the instructions.  The defined values
+     are listed below.  */
+  unsigned long flags;
+
+  /* An array of operand codes.  Each code is an index into the
+     operand table.  They appear in the order which the operands must
+     appear in assembly code, and are terminated by a zero.  */
+  unsigned char operands[8];
+};
+
+/* The table itself is sorted by major opcode number, and is otherwise
+   in the order in which the disassembler should consider
+   instructions.  */
+extern const struct powerpc_opcode powerpc_opcodes[];
+extern const int powerpc_num_opcodes;
+
+/* Values defined for the flags field of a struct powerpc_opcode.  */
+
+/* Opcode is defined for the PowerPC architecture.  */
+#define PPC_OPCODE_PPC                   1
+
+/* Opcode is defined for the POWER (RS/6000) architecture.  */
+#define PPC_OPCODE_POWER                 2
+
+/* Opcode is defined for the POWER2 (Rios 2) architecture.  */
+#define PPC_OPCODE_POWER2                4
+
+/* Opcode is only defined on 32 bit architectures.  */
+#define PPC_OPCODE_32                    8
+
+/* Opcode is only defined on 64 bit architectures.  */
+#define PPC_OPCODE_64                 0x10
+
+/* Opcode is supported by the Motorola PowerPC 601 processor.  The 601
+   is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
+   but it also supports many additional POWER instructions.  */
+#define PPC_OPCODE_601                0x20
+
+/* Opcode is supported in both the Power and PowerPC architectures
+   (ie, compiler's -mcpu=common or assembler's -mcom).  */
+#define PPC_OPCODE_COMMON             0x40
+
+/* Opcode is supported for any Power or PowerPC platform (this is
+   for the assembler's -many option, and it eliminates duplicates).  */
+#define PPC_OPCODE_ANY                0x80
+
+/* Opcode is supported as part of the 64-bit bridge.  */
+#define PPC_OPCODE_64_BRIDGE         0x100
+
+/* Opcode is supported by Altivec Vector Unit */
+#define PPC_OPCODE_ALTIVEC           0x200
+
+/* Opcode is supported by PowerPC 403 processor.  */
+#define PPC_OPCODE_403               0x400
+
+/* Opcode is supported by PowerPC BookE processor.  */
+#define PPC_OPCODE_BOOKE             0x800
+
+/* Opcode is only supported by 64-bit PowerPC BookE processor.  */
+#define PPC_OPCODE_BOOKE64          0x1000
+
+/* Opcode is supported by PowerPC 440 processor.  */
+#define PPC_OPCODE_440              0x2000
+
+/* Opcode is only supported by Power4 architecture.  */
+#define PPC_OPCODE_POWER4           0x4000
+
+/* Opcode isn't supported by Power4 architecture.  */
+#define PPC_OPCODE_NOPOWER4         0x8000
+
+/* Opcode is only supported by POWERPC Classic architecture.  */
+#define PPC_OPCODE_CLASSIC         0x10000
+
+/* Opcode is only supported by e500x2 Core.  */
+#define PPC_OPCODE_SPE             0x20000
+
+/* Opcode is supported by e500x2 Integer select APU.  */
+#define PPC_OPCODE_ISEL            0x40000
+
+/* Opcode is an e500 SPE floating point instruction.  */
+#define PPC_OPCODE_EFS             0x80000
+
+/* Opcode is supported by branch locking APU.  */
+#define PPC_OPCODE_BRLOCK         0x100000
+
+/* Opcode is supported by performance monitor APU.  */
+#define PPC_OPCODE_PMR            0x200000
+
+/* Opcode is supported by cache locking APU.  */
+#define PPC_OPCODE_CACHELCK       0x400000
+
+/* Opcode is supported by machine check APU.  */
+#define PPC_OPCODE_RFMCI          0x800000
+
+/* A macro to extract the major opcode from an instruction.  */
+#define PPC_OP(i) (((i) >> 26) & 0x3f)
+
+/* The operands table is an array of struct powerpc_operand.  */
+
+struct powerpc_operand
+{
+  /* The number of bits in the operand.  */
+  int bits;
+
+  /* How far the operand is left shifted in the instruction.  */
+  int shift;
+
+  /* Insertion function.  This is used by the assembler.  To insert an
+     operand value into an instruction, check this field.
+
+     If it is NULL, execute
+         i |= (op & ((1 << o->bits) - 1)) << o->shift;
+     (i is the instruction which we are filling in, o is a pointer to
+     this structure, and op is the opcode value; this assumes twos
+     complement arithmetic).
+
+     If this field is not NULL, then simply call it with the
+     instruction and the operand value.  It will return the new value
+     of the instruction.  If the ERRMSG argument is not NULL, then if
+     the operand value is illegal, *ERRMSG will be set to a warning
+     string (the operand will be inserted in any case).  If the
+     operand value is legal, *ERRMSG will be unchanged (most operands
+     can accept any value).  */
+  unsigned long (*insert)
+    (unsigned long instruction, long op, int dialect, const char **errmsg);
+
+  /* Extraction function.  This is used by the disassembler.  To
+     extract this operand type from an instruction, check this field.
+
+     If it is NULL, compute
+         op = ((i) >> o->shift) & ((1 << o->bits) - 1);
+         if ((o->flags & PPC_OPERAND_SIGNED) != 0
+             && (op & (1 << (o->bits - 1))) != 0)
+           op -= 1 << o->bits;
+     (i is the instruction, o is a pointer to this structure, and op
+     is the result; this assumes twos complement arithmetic).
+
+     If this field is not NULL, then simply call it with the
+     instruction value.  It will return the value of the operand.  If
+     the INVALID argument is not NULL, *INVALID will be set to
+     non-zero if this operand type can not actually be extracted from
+     this operand (i.e., the instruction does not match).  If the
+     operand is valid, *INVALID will not be changed.  */
+  long (*extract) (unsigned long instruction, int dialect, int *invalid);
+
+  /* One bit syntax flags.  */
+  unsigned long flags;
+};
+
+/* Elements in the table are retrieved by indexing with values from
+   the operands field of the powerpc_opcodes table.  */
+
+extern const struct powerpc_operand powerpc_operands[];
+
+/* Values defined for the flags field of a struct powerpc_operand.  */
+
+/* This operand takes signed values.  */
+#define PPC_OPERAND_SIGNED (01)
+
+/* This operand takes signed values, but also accepts a full positive
+   range of values when running in 32 bit mode.  That is, if bits is
+   16, it takes any value from -0x8000 to 0xffff.  In 64 bit mode,
+   this flag is ignored.  */
+#define PPC_OPERAND_SIGNOPT (02)
+
+/* This operand does not actually exist in the assembler input.  This
+   is used to support extended mnemonics such as mr, for which two
+   operands fields are identical.  The assembler should call the
+   insert function with any op value.  The disassembler should call
+   the extract function, ignore the return value, and check the value
+   placed in the valid argument.  */
+#define PPC_OPERAND_FAKE (04)
+
+/* The next operand should be wrapped in parentheses rather than
+   separated from this one by a comma.  This is used for the load and
+   store instructions which want their operands to look like
+       reg,displacement(reg)
+   */
+#define PPC_OPERAND_PARENS (010)
+
+/* This operand may use the symbolic names for the CR fields, which
+   are
+       lt  0    gt  1   eq  2   so  3   un  3
+       cr0 0    cr1 1   cr2 2   cr3 3
+       cr4 4    cr5 5   cr6 6   cr7 7
+   These may be combined arithmetically, as in cr2*4+gt.  These are
+   only supported on the PowerPC, not the POWER.  */
+#define PPC_OPERAND_CR (020)
+
+/* This operand names a register.  The disassembler uses this to print
+   register names with a leading 'r'.  */
+#define PPC_OPERAND_GPR (040)
+
+/* This operand names a floating point register.  The disassembler
+   prints these with a leading 'f'.  */
+#define PPC_OPERAND_FPR (0100)
+
+/* This operand is a relative branch displacement.  The disassembler
+   prints these symbolically if possible.  */
+#define PPC_OPERAND_RELATIVE (0200)
+
+/* This operand is an absolute branch address.  The disassembler
+   prints these symbolically if possible.  */
+#define PPC_OPERAND_ABSOLUTE (0400)
+
+/* This operand is optional, and is zero if omitted.  This is used for
+   the optional BF and L fields in the comparison instructions.  The
+   assembler must count the number of operands remaining on the line,
+   and the number of operands remaining for the opcode, and decide
+   whether this operand is present or not.  The disassembler should
+   print this operand out only if it is not zero.  */
+#define PPC_OPERAND_OPTIONAL (01000)
+
+/* This flag is only used with PPC_OPERAND_OPTIONAL.  If this operand
+   is omitted, then for the next operand use this operand value plus
+   1, ignoring the next operand field for the opcode.  This wretched
+   hack is needed because the Power rotate instructions can take
+   either 4 or 5 operands.  The disassembler should print this operand
+   out regardless of the PPC_OPERAND_OPTIONAL field.  */
+#define PPC_OPERAND_NEXT (02000)
+
+/* This operand should be regarded as a negative number for the
+   purposes of overflow checking (i.e., the normal most negative
+   number is disallowed and one more than the normal most positive
+   number is allowed).  This flag will only be set for a signed
+   operand.  */
+#define PPC_OPERAND_NEGATIVE (04000)
+
+/* This operand names a vector unit register.  The disassembler
+   prints these with a leading 'v'.  */
+#define PPC_OPERAND_VR (010000)
+
+/* This operand is for the DS field in a DS form instruction.  */
+#define PPC_OPERAND_DS (020000)
+
+/* This operand is for the DQ field in a DQ form instruction.  */
+#define PPC_OPERAND_DQ (040000)
+
+/* The POWER and PowerPC assemblers use a few macros.  We keep them
+   with the operands table for simplicity.  The macro table is an
+   array of struct powerpc_macro.  */
+
+struct powerpc_macro
+{
+  /* The macro name.  */
+  const char *name;
+
+  /* The number of operands the macro takes.  */
+  unsigned int operands;
+
+  /* One bit flags for the opcode.  These are used to indicate which
+     specific processors support the instructions.  The values are the
+     same as those for the struct powerpc_opcode flags field.  */
+  unsigned long flags;
+
+  /* A format string to turn the macro into a normal instruction.
+     Each %N in the string is replaced with operand number N (zero
+     based).  */
+  const char *format;
+};
+
+extern const struct powerpc_macro powerpc_macros[];
+extern const int powerpc_num_macros;
+
+#endif /* PPC_H */
diff --git a/arch/powerpc/xmon/setjmp.S b/arch/powerpc/xmon/setjmp.S
new file mode 100644
index 000000000000..f8e40dfd2bff
--- /dev/null
+++ b/arch/powerpc/xmon/setjmp.S
@@ -0,0 +1,135 @@
+/*
+ * Copyright (C) 1996 Paul Mackerras.
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ *
+ * NOTE: assert(sizeof(buf) > 23 * sizeof(long))
+ */
+#include <asm/processor.h>
+#include <asm/ppc_asm.h>
+#include <asm/asm-offsets.h>
+
+_GLOBAL(xmon_setjmp)
+        mflr    r0
+        STL     r0,0(r3)
+        STL     r1,SZL(r3)
+        STL     r2,2*SZL(r3)
+        mfcr    r0
+        STL     r0,3*SZL(r3)
+        STL     r13,4*SZL(r3)
+        STL     r14,5*SZL(r3)
+        STL     r15,6*SZL(r3)
+        STL     r16,7*SZL(r3)
+        STL     r17,8*SZL(r3)
+        STL     r18,9*SZL(r3)
+        STL     r19,10*SZL(r3)
+        STL     r20,11*SZL(r3)
+        STL     r21,12*SZL(r3)
+        STL     r22,13*SZL(r3)
+        STL     r23,14*SZL(r3)
+        STL     r24,15*SZL(r3)
+        STL     r25,16*SZL(r3)
+        STL     r26,17*SZL(r3)
+        STL     r27,18*SZL(r3)
+        STL     r28,19*SZL(r3)
+        STL     r29,20*SZL(r3)
+        STL     r30,21*SZL(r3)
+        STL     r31,22*SZL(r3)
+        li      r3,0
+        blr
+
+_GLOBAL(xmon_longjmp)
+        CMPI    r4,0
+        bne     1f
+        li      r4,1
+1:      LDL     r13,4*SZL(r3)
+        LDL     r14,5*SZL(r3)
+        LDL     r15,6*SZL(r3)
+        LDL     r16,7*SZL(r3)
+        LDL     r17,8*SZL(r3)
+        LDL     r18,9*SZL(r3)
+        LDL     r19,10*SZL(r3)
+        LDL     r20,11*SZL(r3)
+        LDL     r21,12*SZL(r3)
+        LDL     r22,13*SZL(r3)
+        LDL     r23,14*SZL(r3)
+        LDL     r24,15*SZL(r3)
+        LDL     r25,16*SZL(r3)
+        LDL     r26,17*SZL(r3)
+        LDL     r27,18*SZL(r3)
+        LDL     r28,19*SZL(r3)
+        LDL     r29,20*SZL(r3)
+        LDL     r30,21*SZL(r3)
+        LDL     r31,22*SZL(r3)
+        LDL     r0,3*SZL(r3)
+        mtcrf   0x38,r0
+        LDL     r0,0(r3)
+        LDL     r1,SZL(r3)
+        LDL     r2,2*SZL(r3)
+        mtlr    r0
+        mr      r3,r4
+        blr
+
+/*
+ * Grab the register values as they are now.
+ * This won't do a particularily good job because we really
+ * want our caller's caller's registers, and our caller has
+ * already executed its prologue.
+ * ToDo: We could reach back into the caller's save area to do
+ * a better job of representing the caller's state (note that
+ * that will be different for 32-bit and 64-bit, because of the
+ * different ABIs, though).
+ */
+_GLOBAL(xmon_save_regs)
+        STL     r0,0*SZL(r3)
+        STL     r2,2*SZL(r3)
+        STL     r3,3*SZL(r3)
+        STL     r4,4*SZL(r3)
+        STL     r5,5*SZL(r3)
+        STL     r6,6*SZL(r3)
+        STL     r7,7*SZL(r3)
+        STL     r8,8*SZL(r3)
+        STL     r9,9*SZL(r3)
+        STL     r10,10*SZL(r3)
+        STL     r11,11*SZL(r3)
+        STL     r12,12*SZL(r3)
+        STL     r13,13*SZL(r3)
+        STL     r14,14*SZL(r3)
+        STL     r15,15*SZL(r3)
+        STL     r16,16*SZL(r3)
+        STL     r17,17*SZL(r3)
+        STL     r18,18*SZL(r3)
+        STL     r19,19*SZL(r3)
+        STL     r20,20*SZL(r3)
+        STL     r21,21*SZL(r3)
+        STL     r22,22*SZL(r3)
+        STL     r23,23*SZL(r3)
+        STL     r24,24*SZL(r3)
+        STL     r25,25*SZL(r3)
+        STL     r26,26*SZL(r3)
+        STL     r27,27*SZL(r3)
+        STL     r28,28*SZL(r3)
+        STL     r29,29*SZL(r3)
+        STL     r30,30*SZL(r3)
+        STL     r31,31*SZL(r3)
+        /* go up one stack frame for SP */
+        LDL     r4,0(r1)
+        STL     r4,1*SZL(r3)
+        /* get caller's LR */
+        LDL     r0,LRSAVE(r4)
+        STL     r0,_NIP-STACK_FRAME_OVERHEAD(r3)
+        STL     r0,_LINK-STACK_FRAME_OVERHEAD(r3)
+        mfmsr   r0
+        STL     r0,_MSR-STACK_FRAME_OVERHEAD(r3)
+        mfctr   r0
+        STL     r0,_CTR-STACK_FRAME_OVERHEAD(r3)
+        mfxer   r0
+        STL     r0,_XER-STACK_FRAME_OVERHEAD(r3)
+        mfcr    r0
+        STL     r0,_CCR-STACK_FRAME_OVERHEAD(r3)
+        li      r0,0
+        STL     r0,_TRAP-STACK_FRAME_OVERHEAD(r3)
+        blr
diff --git a/arch/powerpc/xmon/start_32.c b/arch/powerpc/xmon/start_32.c
new file mode 100644
index 000000000000..69b658c0f760
--- /dev/null
+++ b/arch/powerpc/xmon/start_32.c
@@ -0,0 +1,624 @@
+/*
+ * Copyright (C) 1996 Paul Mackerras.
+ */
+#include <linux/config.h>
+#include <linux/string.h>
+#include <asm/machdep.h>
+#include <asm/io.h>
+#include <asm/page.h>
+#include <linux/adb.h>
+#include <linux/pmu.h>
+#include <linux/cuda.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/sysrq.h>
+#include <linux/bitops.h>
+#include <asm/xmon.h>
+#include <asm/prom.h>
+#include <asm/bootx.h>
+#include <asm/machdep.h>
+#include <asm/errno.h>
+#include <asm/pmac_feature.h>
+#include <asm/processor.h>
+#include <asm/delay.h>
+#include <asm/btext.h>
+
+static volatile unsigned char __iomem *sccc, *sccd;
+unsigned int TXRDY, RXRDY, DLAB;
+static int xmon_expect(const char *str, unsigned int timeout);
+
+static int use_serial;
+static int use_screen;
+static int via_modem;
+static int xmon_use_sccb;
+static struct device_node *channel_node;
+
+#define TB_SPEED        25000000
+
+static inline unsigned int readtb(void)
+{
+        unsigned int ret;
+
+        asm volatile("mftb %0" : "=r" (ret) :);
+        return ret;
+}
+
+void buf_access(void)
+{
+        if (DLAB)
+                sccd[3] &= ~DLAB;       /* reset DLAB */
+}
+
+extern int adb_init(void);
+
+#ifdef CONFIG_PPC_CHRP
+/*
+ * This looks in the "ranges" property for the primary PCI host bridge
+ * to find the physical address of the start of PCI/ISA I/O space.
+ * It is basically a cut-down version of pci_process_bridge_OF_ranges.
+ */
+static unsigned long chrp_find_phys_io_base(void)
+{
+        struct device_node *node;
+        unsigned int *ranges;
+        unsigned long base = CHRP_ISA_IO_BASE;
+        int rlen = 0;
+        int np;
+
+        node = find_devices("isa");
+        if (node != NULL) {
+                node = node->parent;
+                if (node == NULL || node->type == NULL
+                    || strcmp(node->type, "pci") != 0)
+                        node = NULL;
+        }
+        if (node == NULL)
+                node = find_devices("pci");
+        if (node == NULL)
+                return base;
+
+        ranges = (unsigned int *) get_property(node, "ranges", &rlen);
+        np = prom_n_addr_cells(node) + 5;
+        while ((rlen -= np * sizeof(unsigned int)) >= 0) {
+                if ((ranges[0] >> 24) == 1 && ranges[2] == 0) {
+                        /* I/O space starting at 0, grab the phys base */
+                        base = ranges[np - 3];
+                        break;
+                }
+                ranges += np;
+        }
+        return base;
+}
+#endif /* CONFIG_PPC_CHRP */
+
+#ifdef CONFIG_MAGIC_SYSRQ
+static void sysrq_handle_xmon(int key, struct pt_regs *regs,
+                              struct tty_struct *tty)
+{
+        xmon(regs);
+}
+
+static struct sysrq_key_op sysrq_xmon_op =
+{
+        .handler =      sysrq_handle_xmon,
+        .help_msg =     "Xmon",
+        .action_msg =   "Entering xmon",
+};
+#endif
+
+void
+xmon_map_scc(void)
+{
+#ifdef CONFIG_PPC_MULTIPLATFORM
+        volatile unsigned char __iomem *base;
+
+        if (_machine == _MACH_Pmac) {
+                struct device_node *np;
+                unsigned long addr;
+#ifdef CONFIG_BOOTX_TEXT
+                if (!use_screen && !use_serial
+                    && !machine_is_compatible("iMac")) {
+                        /* see if there is a keyboard in the device tree
+                           with a parent of type "adb" */
+                        for (np = find_devices("keyboard"); np; np = np->next)
+                                if (np->parent && np->parent->type
+                                    && strcmp(np->parent->type, "adb") == 0)
+                                        break;
+
+                        /* needs to be hacked if xmon_printk is to be used
+                           from within find_via_pmu() */
+#ifdef CONFIG_ADB_PMU
+                        if (np != NULL && boot_text_mapped && find_via_pmu())
+                                use_screen = 1;
+#endif
+#ifdef CONFIG_ADB_CUDA
+                        if (np != NULL && boot_text_mapped && find_via_cuda())
+                                use_screen = 1;
+#endif
+                }
+                if (!use_screen && (np = find_devices("escc")) != NULL) {
+                        /*
+                         * look for the device node for the serial port
+                         * we're using and see if it says it has a modem
+                         */
+                        char *name = xmon_use_sccb? "ch-b": "ch-a";
+                        char *slots;
+                        int l;
+
+                        np = np->child;
+                        while (np != NULL && strcmp(np->name, name) != 0)
+                                np = np->sibling;
+                        if (np != NULL) {
+                                /* XXX should parse this properly */
+                                channel_node = np;
+                                slots = get_property(np, "slot-names", &l);
+                                if (slots != NULL && l >= 10
+                                    && strcmp(slots+4, "Modem") == 0)
+                                        via_modem = 1;
+                        }
+                }
+                btext_drawstring("xmon uses ");
+                if (use_screen)
+                        btext_drawstring("screen and keyboard\n");
+                else {
+                        if (via_modem)
+                                btext_drawstring("modem on ");
+                        btext_drawstring(xmon_use_sccb? "printer": "modem");
+                        btext_drawstring(" port\n");
+                }
+
+#endif /* CONFIG_BOOTX_TEXT */
+
+#ifdef CHRP_ESCC
+                addr = 0xc1013020;
+#else
+                addr = 0xf3013020;
+#endif
+                TXRDY = 4;
+                RXRDY = 1;
+        
+                np = find_devices("mac-io");
+                if (np && np->n_addrs)
+                        addr = np->addrs[0].address + 0x13020;
+                base = (volatile unsigned char *) ioremap(addr & PAGE_MASK, PAGE_SIZE);
+                sccc = base + (addr & ~PAGE_MASK);
+                sccd = sccc + 0x10;
+
+        } else {
+                base = (volatile unsigned char *) isa_io_base;
+
+#ifdef CONFIG_PPC_CHRP
+                if (_machine == _MACH_chrp)
+                        base = (volatile unsigned char __iomem *)
+                                ioremap(chrp_find_phys_io_base(), 0x1000);
+#endif
+
+                sccc = base + 0x3fd;
+                sccd = base + 0x3f8;
+                if (xmon_use_sccb) {
+                        sccc -= 0x100;
+                        sccd -= 0x100;
+                }
+                TXRDY = 0x20;
+                RXRDY = 1;
+                DLAB = 0x80;
+        }
+#elif defined(CONFIG_GEMINI)
+        /* should already be mapped by the kernel boot */
+        sccc = (volatile unsigned char __iomem *) 0xffeffb0d;
+        sccd = (volatile unsigned char __iomem *) 0xffeffb08;
+        TXRDY = 0x20;
+        RXRDY = 1;
+        DLAB = 0x80;
+#elif defined(CONFIG_405GP)
+        sccc = (volatile unsigned char __iomem *)0xef600305;
+        sccd = (volatile unsigned char __iomem *)0xef600300;
+        TXRDY = 0x20;
+        RXRDY = 1;
+        DLAB = 0x80;
+#endif /* platform */
+
+        register_sysrq_key('x', &sysrq_xmon_op);
+}
+
+static int scc_initialized = 0;
+
+void xmon_init_scc(void);
+extern void cuda_poll(void);
+
+static inline void do_poll_adb(void)
+{
+#ifdef CONFIG_ADB_PMU
+        if (sys_ctrler == SYS_CTRLER_PMU)
+                pmu_poll_adb();
+#endif /* CONFIG_ADB_PMU */
+#ifdef CONFIG_ADB_CUDA
+        if (sys_ctrler == SYS_CTRLER_CUDA)
+                cuda_poll();
+#endif /* CONFIG_ADB_CUDA */
+}
+
+int
+xmon_write(void *handle, void *ptr, int nb)
+{
+        char *p = ptr;
+        int i, c, ct;
+
+#ifdef CONFIG_SMP
+        static unsigned long xmon_write_lock;
+        int lock_wait = 1000000;
+        int locked;
+
+        while ((locked = test_and_set_bit(0, &xmon_write_lock)) != 0)
+                if (--lock_wait == 0)
+                        break;
+#endif
+
+#ifdef CONFIG_BOOTX_TEXT
+        if (use_screen) {
+                /* write it on the screen */
+                for (i = 0; i < nb; ++i)
+                        btext_drawchar(*p++);
+                goto out;
+        }
+#endif
+        if (!scc_initialized)
+                xmon_init_scc();
+        ct = 0;
+        for (i = 0; i < nb; ++i) {
+                while ((*sccc & TXRDY) == 0)
+                        do_poll_adb();
+                c = p[i];
+                if (c == '\n' && !ct) {
+                        c = '\r';
+                        ct = 1;
+                        --i;
+                } else {
+                        ct = 0;
+                }
+                buf_access();
+                *sccd = c;
+                eieio();
+        }
+
+ out:
+#ifdef CONFIG_SMP
+        if (!locked)
+                clear_bit(0, &xmon_write_lock);
+#endif
+        return nb;
+}
+
+int xmon_wants_key;
+int xmon_adb_keycode;
+
+#ifdef CONFIG_BOOTX_TEXT
+static int xmon_adb_shiftstate;
+
+static unsigned char xmon_keytab[128] =
+        "asdfhgzxcv\000bqwer"                           /* 0x00 - 0x0f */
+        "yt123465=97-80]o"                              /* 0x10 - 0x1f */
+        "u[ip\rlj'k;\\,/nm."                            /* 0x20 - 0x2f */
+        "\t `\177\0\033\0\0\0\0\0\0\0\0\0\0"            /* 0x30 - 0x3f */
+        "\0.\0*\0+\0\0\0\0\0/\r\0-\0"                   /* 0x40 - 0x4f */
+        "\0\0000123456789\0\0\0";                       /* 0x50 - 0x5f */
+
+static unsigned char xmon_shift_keytab[128] =
+        "ASDFHGZXCV\000BQWER"                           /* 0x00 - 0x0f */
+        "YT!@#$^%+(&_*)}O"                              /* 0x10 - 0x1f */
+        "U{IP\rLJ\"K:|<?NM>"                            /* 0x20 - 0x2f */
+        "\t ~\177\0\033\0\0\0\0\0\0\0\0\0\0"            /* 0x30 - 0x3f */
+        "\0.\0*\0+\0\0\0\0\0/\r\0-\0"                   /* 0x40 - 0x4f */
+        "\0\0000123456789\0\0\0";                       /* 0x50 - 0x5f */
+
+static int
+xmon_get_adb_key(void)
+{
+        int k, t, on;
+
+        xmon_wants_key = 1;
+        for (;;) {
+                xmon_adb_keycode = -1;
+                t = 0;
+                on = 0;
+                do {
+                        if (--t < 0) {
+                                on = 1 - on;
+                                btext_drawchar(on? 0xdb: 0x20);
+                                btext_drawchar('\b');
+                                t = 200000;
+                        }
+                        do_poll_adb();
+                } while (xmon_adb_keycode == -1);
+                k = xmon_adb_keycode;
+                if (on)
+                        btext_drawstring(" \b");
+
+                /* test for shift keys */
+                if ((k & 0x7f) == 0x38 || (k & 0x7f) == 0x7b) {
+                        xmon_adb_shiftstate = (k & 0x80) == 0;
+                        continue;
+                }
+                if (k >= 0x80)
+                        continue;       /* ignore up transitions */
+                k = (xmon_adb_shiftstate? xmon_shift_keytab: xmon_keytab)[k];
+                if (k != 0)
+                        break;
+        }
+        xmon_wants_key = 0;
+        return k;
+}
+#endif /* CONFIG_BOOTX_TEXT */
+
+int
+xmon_read(void *handle, void *ptr, int nb)
+{
+    char *p = ptr;
+    int i;
+
+#ifdef CONFIG_BOOTX_TEXT
+    if (use_screen) {
+        for (i = 0; i < nb; ++i)
+            *p++ = xmon_get_adb_key();
+        return i;
+    }
+#endif
+    if (!scc_initialized)
+        xmon_init_scc();
+    for (i = 0; i < nb; ++i) {
+        while ((*sccc & RXRDY) == 0)
+            do_poll_adb();
+        buf_access();
+        *p++ = *sccd;
+    }
+    return i;
+}
+
+int
+xmon_read_poll(void)
+{
+        if ((*sccc & RXRDY) == 0) {
+                do_poll_adb();
+                return -1;
+        }
+        buf_access();
+        return *sccd;
+}
+
+static unsigned char scc_inittab[] = {
+    13, 0,              /* set baud rate divisor */
+    12, 1,
+    14, 1,              /* baud rate gen enable, src=rtxc */
+    11, 0x50,           /* clocks = br gen */
+    5,  0xea,           /* tx 8 bits, assert DTR & RTS */
+    4,  0x46,           /* x16 clock, 1 stop */
+    3,  0xc1,           /* rx enable, 8 bits */
+};
+
+void
+xmon_init_scc(void)
+{
+        if ( _machine == _MACH_chrp )
+        {
+                sccd[3] = 0x83; eieio();        /* LCR = 8N1 + DLAB */
+                sccd[0] = 12; eieio();          /* DLL = 9600 baud */
+                sccd[1] = 0; eieio();
+                sccd[2] = 0; eieio();           /* FCR = 0 */
+                sccd[3] = 3; eieio();           /* LCR = 8N1 */
+                sccd[1] = 0; eieio();           /* IER = 0 */
+        }
+        else if ( _machine == _MACH_Pmac )
+        {
+                int i, x;
+
+                if (channel_node != 0)
+                        pmac_call_feature(
+                                PMAC_FTR_SCC_ENABLE,
+                                channel_node,
+                                PMAC_SCC_ASYNC | PMAC_SCC_FLAG_XMON, 1);
+                        printk(KERN_INFO "Serial port locked ON by debugger !\n");
+                if (via_modem && channel_node != 0) {
+                        unsigned int t0;
+
+                        pmac_call_feature(
+                                PMAC_FTR_MODEM_ENABLE,
+                                channel_node, 0, 1);
+                        printk(KERN_INFO "Modem powered up by debugger !\n");
+                        t0 = readtb();
+                        while (readtb() - t0 < 3*TB_SPEED)
+                                eieio();
+                }
+                /* use the B channel if requested */
+                if (xmon_use_sccb) {
+                        sccc = (volatile unsigned char *)
+                                ((unsigned long)sccc & ~0x20);
+                        sccd = sccc + 0x10;
+                }
+                for (i = 20000; i != 0; --i) {
+                        x = *sccc; eieio();
+                }
+                *sccc = 9; eieio();             /* reset A or B side */
+                *sccc = ((unsigned long)sccc & 0x20)? 0x80: 0x40; eieio();
+                for (i = 0; i < sizeof(scc_inittab); ++i) {
+                        *sccc = scc_inittab[i];
+                        eieio();
+                }
+        }
+        scc_initialized = 1;
+        if (via_modem) {
+                for (;;) {
+                        xmon_write(NULL, "ATE1V1\r", 7);
+                        if (xmon_expect("OK", 5)) {
+                                xmon_write(NULL, "ATA\r", 4);
+                                if (xmon_expect("CONNECT", 40))
+                                        break;
+                        }
+                        xmon_write(NULL, "+++", 3);
+                        xmon_expect("OK", 3);
+                }
+        }
+}
+
+void *xmon_stdin;
+void *xmon_stdout;
+void *xmon_stderr;
+
+int xmon_putc(int c, void *f)
+{
+    char ch = c;
+
+    if (c == '\n')
+        xmon_putc('\r', f);
+    return xmon_write(f, &ch, 1) == 1? c: -1;
+}
+
+int xmon_putchar(int c)
+{
+        return xmon_putc(c, xmon_stdout);
+}
+
+int xmon_fputs(char *str, void *f)
+{
+        int n = strlen(str);
+
+        return xmon_write(f, str, n) == n? 0: -1;
+}
+
+int
+xmon_readchar(void)
+{
+        char ch;
+
+        for (;;) {
+                switch (xmon_read(xmon_stdin, &ch, 1)) {
+                case 1:
+                        return ch;
+                case -1:
+                        xmon_printf("read(stdin) returned -1\r\n", 0, 0);
+                        return -1;
+                }
+        }
+}
+
+static char line[256];
+static char *lineptr;
+static int lineleft;
+
+int xmon_expect(const char *str, unsigned int timeout)
+{
+        int c;
+        unsigned int t0;
+
+        timeout *= TB_SPEED;
+        t0 = readtb();
+        do {
+                lineptr = line;
+                for (;;) {
+                        c = xmon_read_poll();
+                        if (c == -1) {
+                                if (readtb() - t0 > timeout)
+                                        return 0;
+                                continue;
+                        }
+                        if (c == '\n')
+                                break;
+                        if (c != '\r' && lineptr < &line[sizeof(line) - 1])
+                                *lineptr++ = c;
+                }
+                *lineptr = 0;
+        } while (strstr(line, str) == NULL);
+        return 1;
+}
+
+int
+xmon_getchar(void)
+{
+    int c;
+
+    if (lineleft == 0) {
+        lineptr = line;
+        for (;;) {
+            c = xmon_readchar();
+            if (c == -1 || c == 4)
+                break;
+            if (c == '\r' || c == '\n') {
+                *lineptr++ = '\n';
+                xmon_putchar('\n');
+                break;
+            }
+            switch (c) {
+            case 0177:
+            case '\b':
+                if (lineptr > line) {
+                    xmon_putchar('\b');
+                    xmon_putchar(' ');
+                    xmon_putchar('\b');
+                    --lineptr;
+                }
+                break;
+            case 'U' & 0x1F:
+                while (lineptr > line) {
+                    xmon_putchar('\b');
+                    xmon_putchar(' ');
+                    xmon_putchar('\b');
+                    --lineptr;
+                }
+                break;
+            default:
+                if (lineptr >= &line[sizeof(line) - 1])
+                    xmon_putchar('\a');
+                else {
+                    xmon_putchar(c);
+                    *lineptr++ = c;
+                }
+            }
+        }
+        lineleft = lineptr - line;
+        lineptr = line;
+    }
+    if (lineleft == 0)
+        return -1;
+    --lineleft;
+    return *lineptr++;
+}
+
+char *
+xmon_fgets(char *str, int nb, void *f)
+{
+    char *p;
+    int c;
+
+    for (p = str; p < str + nb - 1; ) {
+        c = xmon_getchar();
+        if (c == -1) {
+            if (p == str)
+                return NULL;
+            break;
+        }
+        *p++ = c;
+        if (c == '\n')
+            break;
+    }
+    *p = 0;
+    return str;
+}
+
+void
+xmon_enter(void)
+{
+#ifdef CONFIG_ADB_PMU
+        if (_machine == _MACH_Pmac) {
+                pmu_suspend();
+        }
+#endif
+}
+
+void
+xmon_leave(void)
+{
+#ifdef CONFIG_ADB_PMU
+        if (_machine == _MACH_Pmac) {
+                pmu_resume();
+        }
+#endif
+}
diff --git a/arch/powerpc/xmon/start_64.c b/arch/powerpc/xmon/start_64.c
new file mode 100644
index 000000000000..e50c158191e1
--- /dev/null
+++ b/arch/powerpc/xmon/start_64.c
@@ -0,0 +1,187 @@
+/*
+ * Copyright (C) 1996 Paul Mackerras.
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+#include <linux/config.h>
+#include <linux/string.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/sysrq.h>
+#include <linux/init.h>
+#include <asm/machdep.h>
+#include <asm/io.h>
+#include <asm/page.h>
+#include <asm/prom.h>
+#include <asm/processor.h>
+#include <asm/udbg.h>
+#include <asm/system.h>
+#include "nonstdio.h"
+
+#ifdef CONFIG_MAGIC_SYSRQ
+
+static void sysrq_handle_xmon(int key, struct pt_regs *pt_regs,
+                              struct tty_struct *tty) 
+{
+        /* ensure xmon is enabled */
+        xmon_init(1);
+        debugger(pt_regs);
+}
+
+static struct sysrq_key_op sysrq_xmon_op = 
+{
+        .handler =      sysrq_handle_xmon,
+        .help_msg =     "Xmon",
+        .action_msg =   "Entering xmon",
+};
+
+static int __init setup_xmon_sysrq(void)
+{
+        register_sysrq_key('x', &sysrq_xmon_op);
+        return 0;
+}
+__initcall(setup_xmon_sysrq);
+#endif /* CONFIG_MAGIC_SYSRQ */
+
+int
+xmon_write(void *handle, void *ptr, int nb)
+{
+        return udbg_write(ptr, nb);
+}
+
+int
+xmon_read(void *handle, void *ptr, int nb)
+{
+        return udbg_read(ptr, nb);
+}
+
+int
+xmon_read_poll(void)
+{
+        if (udbg_getc_poll)
+                return udbg_getc_poll();
+        return -1;
+}
+ 
+FILE *xmon_stdin;
+FILE *xmon_stdout;
+
+int
+xmon_putc(int c, void *f)
+{
+        char ch = c;
+
+        if (c == '\n')
+                xmon_putc('\r', f);
+        return xmon_write(f, &ch, 1) == 1? c: -1;
+}
+
+int
+xmon_putchar(int c)
+{
+        return xmon_putc(c, xmon_stdout);
+}
+
+int
+xmon_fputs(char *str, void *f)
+{
+        int n = strlen(str);
+
+        return xmon_write(f, str, n) == n? 0: -1;
+}
+
+int
+xmon_readchar(void)
+{
+        char ch;
+
+        for (;;) {
+                switch (xmon_read(xmon_stdin, &ch, 1)) {
+                case 1:
+                        return ch;
+                case -1:
+                        xmon_printf("read(stdin) returned -1\r\n", 0, 0);
+                        return -1;
+                }
+        }
+}
+
+static char line[256];
+static char *lineptr;
+static int lineleft;
+
+int
+xmon_getchar(void)
+{
+        int c;
+
+        if (lineleft == 0) {
+                lineptr = line;
+                for (;;) {
+                        c = xmon_readchar();
+                        if (c == -1 || c == 4)
+                                break;
+                        if (c == '\r' || c == '\n') {
+                                *lineptr++ = '\n';
+                                xmon_putchar('\n');
+                                break;
+                        }
+                        switch (c) {
+                        case 0177:
+                        case '\b':
+                                if (lineptr > line) {
+                                        xmon_putchar('\b');
+                                        xmon_putchar(' ');
+                                        xmon_putchar('\b');
+                                        --lineptr;
+                                }
+                                break;
+                        case 'U' & 0x1F:
+                                while (lineptr > line) {
+                                        xmon_putchar('\b');
+                                        xmon_putchar(' ');
+                                        xmon_putchar('\b');
+                                        --lineptr;
+                                }
+                                break;
+                        default:
+                                if (lineptr >= &line[sizeof(line) - 1])
+                                        xmon_putchar('\a');
+                                else {
+                                        xmon_putchar(c);
+                                        *lineptr++ = c;
+                                }
+                        }
+                }
+                lineleft = lineptr - line;
+                lineptr = line;
+        }
+        if (lineleft == 0)
+                return -1;
+        --lineleft;
+        return *lineptr++;
+}
+
+char *
+xmon_fgets(char *str, int nb, void *f)
+{
+        char *p;
+        int c;
+
+        for (p = str; p < str + nb - 1; ) {
+                c = xmon_getchar();
+                if (c == -1) {
+                        if (p == str)
+                                return NULL;
+                        break;
+                }
+                *p++ = c;
+                if (c == '\n')
+                        break;
+        }
+        *p = 0;
+        return str;
+}
diff --git a/arch/powerpc/xmon/start_8xx.c b/arch/powerpc/xmon/start_8xx.c
new file mode 100644
index 000000000000..a48bd594cf61
--- /dev/null
+++ b/arch/powerpc/xmon/start_8xx.c
@@ -0,0 +1,287 @@
+/*
+ * Copyright (C) 1996 Paul Mackerras.
+ * Copyright (C) 2000 Dan Malek.
+ * Quick hack of Paul's code to make XMON work on 8xx processors.  Lots
+ * of assumptions, like the SMC1 is used, it has been initialized by the
+ * loader at some point, and we can just stuff and suck bytes.
+ * We rely upon the 8xx uart driver to support us, as the interface
+ * changes between boot up and operational phases of the kernel.
+ */
+#include <linux/string.h>
+#include <asm/machdep.h>
+#include <asm/io.h>
+#include <asm/page.h>
+#include <linux/kernel.h>
+#include <asm/8xx_immap.h>
+#include <asm/mpc8xx.h>
+#include <asm/commproc.h>
+
+extern void xmon_printf(const char *fmt, ...);
+extern int xmon_8xx_write(char *str, int nb);
+extern int xmon_8xx_read_poll(void);
+extern int xmon_8xx_read_char(void);
+void prom_drawhex(uint);
+void prom_drawstring(const char *str);
+
+static int use_screen = 1; /* default */
+
+#define TB_SPEED        25000000
+
+static inline unsigned int readtb(void)
+{
+        unsigned int ret;
+
+        asm volatile("mftb %0" : "=r" (ret) :);
+        return ret;
+}
+
+void buf_access(void)
+{
+}
+
+void
+xmon_map_scc(void)
+{
+
+        cpmp = (cpm8xx_t *)&(((immap_t *)IMAP_ADDR)->im_cpm);
+        use_screen = 0;
+        
+        prom_drawstring("xmon uses serial port\n");
+}
+
+static int scc_initialized = 0;
+
+void xmon_init_scc(void);
+
+int
+xmon_write(void *handle, void *ptr, int nb)
+{
+        char *p = ptr;
+        int i, c, ct;
+
+        if (!scc_initialized)
+                xmon_init_scc();
+
+        return(xmon_8xx_write(ptr, nb));
+}
+
+int xmon_wants_key;
+
+int
+xmon_read(void *handle, void *ptr, int nb)
+{
+        char *p = ptr;
+        int i;
+
+        if (!scc_initialized)
+                xmon_init_scc();
+
+        for (i = 0; i < nb; ++i) {
+                *p++ = xmon_8xx_read_char();
+        }
+        return i;
+}
+
+int
+xmon_read_poll(void)
+{
+        return(xmon_8xx_read_poll());
+}
+
+void
+xmon_init_scc()
+{
+        scc_initialized = 1;
+}
+
+#if 0
+extern int (*prom_entry)(void *);
+
+int
+xmon_exit(void)
+{
+    struct prom_args {
+        char *service;
+    } args;
+
+    for (;;) {
+        args.service = "exit";
+        (*prom_entry)(&args);
+    }
+}
+#endif
+
+void *xmon_stdin;
+void *xmon_stdout;
+void *xmon_stderr;
+
+void
+xmon_init(void)
+{
+}
+
+int
+xmon_putc(int c, void *f)
+{
+    char ch = c;
+
+    if (c == '\n')
+        xmon_putc('\r', f);
+    return xmon_write(f, &ch, 1) == 1? c: -1;
+}
+
+int
+xmon_putchar(int c)
+{
+    return xmon_putc(c, xmon_stdout);
+}
+
+int
+xmon_fputs(char *str, void *f)
+{
+    int n = strlen(str);
+
+    return xmon_write(f, str, n) == n? 0: -1;
+}
+
+int
+xmon_readchar(void)
+{
+    char ch;
+
+    for (;;) {
+        switch (xmon_read(xmon_stdin, &ch, 1)) {
+        case 1:
+            return ch;
+        case -1:
+            xmon_printf("read(stdin) returned -1\r\n", 0, 0);
+            return -1;
+        }
+    }
+}
+
+static char line[256];
+static char *lineptr;
+static int lineleft;
+
+#if 0
+int xmon_expect(const char *str, unsigned int timeout)
+{
+        int c;
+        unsigned int t0;
+
+        timeout *= TB_SPEED;
+        t0 = readtb();
+        do {
+                lineptr = line;
+                for (;;) {
+                        c = xmon_read_poll();
+                        if (c == -1) {
+                                if (readtb() - t0 > timeout)
+                                        return 0;
+                                continue;
+                        }
+                        if (c == '\n')
+                                break;
+                        if (c != '\r' && lineptr < &line[sizeof(line) - 1])
+                                *lineptr++ = c;
+                }
+                *lineptr = 0;
+        } while (strstr(line, str) == NULL);
+        return 1;
+}
+#endif
+
+int
+xmon_getchar(void)
+{
+    int c;
+
+    if (lineleft == 0) {
+        lineptr = line;
+        for (;;) {
+            c = xmon_readchar();
+            if (c == -1 || c == 4)
+                break;
+            if (c == '\r' || c == '\n') {
+                *lineptr++ = '\n';
+                xmon_putchar('\n');
+                break;
+            }
+            switch (c) {
+            case 0177:
+            case '\b':
+                if (lineptr > line) {
+                    xmon_putchar('\b');
+                    xmon_putchar(' ');
+                    xmon_putchar('\b');
+                    --lineptr;
+                }
+                break;
+            case 'U' & 0x1F:
+                while (lineptr > line) {
+                    xmon_putchar('\b');
+                    xmon_putchar(' ');
+                    xmon_putchar('\b');
+                    --lineptr;
+                }
+                break;
+            default:
+                if (lineptr >= &line[sizeof(line) - 1])
+                    xmon_putchar('\a');
+                else {
+                    xmon_putchar(c);
+                    *lineptr++ = c;
+                }
+            }
+        }
+        lineleft = lineptr - line;
+        lineptr = line;
+    }
+    if (lineleft == 0)
+        return -1;
+    --lineleft;
+    return *lineptr++;
+}
+
+char *
+xmon_fgets(char *str, int nb, void *f)
+{
+    char *p;
+    int c;
+
+    for (p = str; p < str + nb - 1; ) {
+        c = xmon_getchar();
+        if (c == -1) {
+            if (p == str)
+                return 0;
+            break;
+        }
+        *p++ = c;
+        if (c == '\n')
+            break;
+    }
+    *p = 0;
+    return str;
+}
+
+void
+prom_drawhex(uint val)
+{
+        unsigned char buf[10];
+
+        int i;
+        for (i = 7;  i >= 0;  i--)
+        {
+                buf[i] = "0123456789abcdef"[val & 0x0f];
+                val >>= 4;
+        }
+        buf[8] = '\0';
+        xmon_fputs(buf, xmon_stdout);
+}
+
+void
+prom_drawstring(const char *str)
+{
+        xmon_fputs(str, xmon_stdout);
+}
diff --git a/arch/powerpc/xmon/subr_prf.c b/arch/powerpc/xmon/subr_prf.c
new file mode 100644
index 000000000000..b48738c6dd33
--- /dev/null
+++ b/arch/powerpc/xmon/subr_prf.c
@@ -0,0 +1,54 @@
+/*
+ * Written by Cort Dougan to replace the version originally used
+ * by Paul Mackerras, which came from NetBSD and thus had copyright
+ * conflicts with Linux.
+ *
+ * This file makes liberal use of the standard linux utility
+ * routines to reduce the size of the binary.  We assume we can
+ * trust some parts of Linux inside the debugger.
+ *   -- Cort (cort@cs.nmt.edu)
+ *
+ * Copyright (C) 1999 Cort Dougan.
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/module.h>
+#include <stdarg.h>
+#include "nonstdio.h"
+
+extern int xmon_write(void *, void *, int);
+
+void xmon_vfprintf(void *f, const char *fmt, va_list ap)
+{
+        static char xmon_buf[2048];
+        int n;
+
+        n = vsprintf(xmon_buf, fmt, ap);
+        xmon_write(f, xmon_buf, n);
+}
+
+void xmon_printf(const char *fmt, ...)
+{
+        va_list ap;
+
+        va_start(ap, fmt);
+        xmon_vfprintf(stdout, fmt, ap);
+        va_end(ap);
+}
+EXPORT_SYMBOL(xmon_printf);
+
+void xmon_fprintf(void *f, const char *fmt, ...)
+{
+        va_list ap;
+
+        va_start(ap, fmt);
+        xmon_vfprintf(f, fmt, ap);
+        va_end(ap);
+}
+
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
new file mode 100644
index 000000000000..1124f1146202
--- /dev/null
+++ b/arch/powerpc/xmon/xmon.c
@@ -0,0 +1,2529 @@
+/*
+ * Routines providing a simple monitor for use on the PowerMac.
+ *
+ * Copyright (C) 1996 Paul Mackerras.
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+#include <linux/config.h>
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <linux/smp.h>
+#include <linux/mm.h>
+#include <linux/reboot.h>
+#include <linux/delay.h>
+#include <linux/kallsyms.h>
+#include <linux/cpumask.h>
+#include <linux/module.h>
+
+#include <asm/ptrace.h>
+#include <asm/string.h>
+#include <asm/prom.h>
+#include <asm/machdep.h>
+#include <asm/xmon.h>
+#ifdef CONFIG_PMAC_BACKLIGHT
+#include <asm/backlight.h>
+#endif
+#include <asm/processor.h>
+#include <asm/pgtable.h>
+#include <asm/mmu.h>
+#include <asm/mmu_context.h>
+#include <asm/cputable.h>
+#include <asm/rtas.h>
+#include <asm/sstep.h>
+#include <asm/bug.h>
+
+#ifdef CONFIG_PPC64
+#include <asm/hvcall.h>
+#include <asm/paca.h>
+#endif
+
+#include "nonstdio.h"
+
+#define scanhex xmon_scanhex
+#define skipbl  xmon_skipbl
+
+#ifdef CONFIG_SMP
+cpumask_t cpus_in_xmon = CPU_MASK_NONE;
+static unsigned long xmon_taken = 1;
+static int xmon_owner;
+static int xmon_gate;
+#endif /* CONFIG_SMP */
+
+static unsigned long in_xmon = 0;
+
+static unsigned long adrs;
+static int size = 1;
+#define MAX_DUMP (128 * 1024)
+static unsigned long ndump = 64;
+static unsigned long nidump = 16;
+static unsigned long ncsum = 4096;
+static int termch;
+static char tmpstr[128];
+
+#define JMP_BUF_LEN     23
+static long bus_error_jmp[JMP_BUF_LEN];
+static int catch_memory_errors;
+static long *xmon_fault_jmp[NR_CPUS];
+#define setjmp xmon_setjmp
+#define longjmp xmon_longjmp
+
+/* Breakpoint stuff */
+struct bpt {
+        unsigned long   address;
+        unsigned int    instr[2];
+        atomic_t        ref_count;
+        int             enabled;
+        unsigned long   pad;
+};
+
+/* Bits in bpt.enabled */
+#define BP_IABR_TE      1               /* IABR translation enabled */
+#define BP_IABR         2
+#define BP_TRAP         8
+#define BP_DABR         0x10
+
+#define NBPTS   256
+static struct bpt bpts[NBPTS];
+static struct bpt dabr;
+static struct bpt *iabr;
+static unsigned bpinstr = 0x7fe00008;   /* trap */
+
+#define BP_NUM(bp)      ((bp) - bpts + 1)
+
+/* Prototypes */
+static int cmds(struct pt_regs *);
+static int mread(unsigned long, void *, int);
+static int mwrite(unsigned long, void *, int);
+static int handle_fault(struct pt_regs *);
+static void byterev(unsigned char *, int);
+static void memex(void);
+static int bsesc(void);
+static void dump(void);
+static void prdump(unsigned long, long);
+static int ppc_inst_dump(unsigned long, long, int);
+void print_address(unsigned long);
+static void backtrace(struct pt_regs *);
+static void excprint(struct pt_regs *);
+static void prregs(struct pt_regs *);
+static void memops(int);
+static void memlocate(void);
+static void memzcan(void);
+static void memdiffs(unsigned char *, unsigned char *, unsigned, unsigned);
+int skipbl(void);
+int scanhex(unsigned long *valp);
+static void scannl(void);
+static int hexdigit(int);
+void getstring(char *, int);
+static void flush_input(void);
+static int inchar(void);
+static void take_input(char *);
+static unsigned long read_spr(int);
+static void write_spr(int, unsigned long);
+static void super_regs(void);
+static void remove_bpts(void);
+static void insert_bpts(void);
+static void remove_cpu_bpts(void);
+static void insert_cpu_bpts(void);
+static struct bpt *at_breakpoint(unsigned long pc);
+static struct bpt *in_breakpoint_table(unsigned long pc, unsigned long *offp);
+static int  do_step(struct pt_regs *);
+static void bpt_cmds(void);
+static void cacheflush(void);
+static int  cpu_cmd(void);
+static void csum(void);
+static void bootcmds(void);
+static void proccall(void);
+void dump_segments(void);
+static void symbol_lookup(void);
+static void xmon_print_symbol(unsigned long address, const char *mid,
+                              const char *after);
+static const char *getvecname(unsigned long vec);
+
+extern int print_insn_powerpc(unsigned long, unsigned long, int);
+extern void printf(const char *fmt, ...);
+extern void xmon_vfprintf(void *f, const char *fmt, va_list ap);
+extern int xmon_putc(int c, void *f);
+extern int putchar(int ch);
+
+extern void xmon_enter(void);
+extern void xmon_leave(void);
+
+extern int xmon_read_poll(void);
+extern long setjmp(long *);
+extern void longjmp(long *, long);
+extern void xmon_save_regs(struct pt_regs *);
+
+#ifdef CONFIG_PPC64
+#define REG             "%.16lx"
+#define REGS_PER_LINE   4
+#define LAST_VOLATILE   13
+#else
+#define REG             "%.8lx"
+#define REGS_PER_LINE   8
+#define LAST_VOLATILE   12
+#endif
+
+#define GETWORD(v)      (((v)[0] << 24) + ((v)[1] << 16) + ((v)[2] << 8) + (v)[3])
+
+#define isxdigit(c)     (('0' <= (c) && (c) <= '9') \
+                         || ('a' <= (c) && (c) <= 'f') \
+                         || ('A' <= (c) && (c) <= 'F'))
+#define isalnum(c)      (('0' <= (c) && (c) <= '9') \
+                         || ('a' <= (c) && (c) <= 'z') \
+                         || ('A' <= (c) && (c) <= 'Z'))
+#define isspace(c)      (c == ' ' || c == '\t' || c == 10 || c == 13 || c == 0)
+
+static char *help_string = "\
+Commands:\n\
+  b     show breakpoints\n\
+  bd    set data breakpoint\n\
+  bi    set instruction breakpoint\n\
+  bc    clear breakpoint\n"
+#ifdef CONFIG_SMP
+  "\
+  c     print cpus stopped in xmon\n\
+  c#    try to switch to cpu number h (in hex)\n"
+#endif
+  "\
+  C     checksum\n\
+  d     dump bytes\n\
+  di    dump instructions\n\
+  df    dump float values\n\
+  dd    dump double values\n\
+  e     print exception information\n\
+  f     flush cache\n\
+  la    lookup symbol+offset of specified address\n\
+  ls    lookup address of specified symbol\n\
+  m     examine/change memory\n\
+  mm    move a block of memory\n\
+  ms    set a block of memory\n\
+  md    compare two blocks of memory\n\
+  ml    locate a block of memory\n\
+  mz    zero a block of memory\n\
+  mi    show information about memory allocation\n\
+  p     call a procedure\n\
+  r     print registers\n\
+  s     single step\n\
+  S     print special registers\n\
+  t     print backtrace\n\
+  x     exit monitor and recover\n\
+  X     exit monitor and dont recover\n"
+#ifdef CONFIG_PPC64
+"  u    dump segment table or SLB\n"
+#endif
+#ifdef CONFIG_PPC_STD_MMU_32
+"  u    dump segment registers\n"
+#endif
+"  ?    help\n"
+"  zr   reboot\n\
+  zh    halt\n"
+;
+
+static struct pt_regs *xmon_regs;
+
+static inline void sync(void)
+{
+        asm volatile("sync; isync");
+}
+
+static inline void store_inst(void *p)
+{
+        asm volatile ("dcbst 0,%0; sync; icbi 0,%0; isync" : : "r" (p));
+}
+
+static inline void cflush(void *p)
+{
+        asm volatile ("dcbf 0,%0; icbi 0,%0" : : "r" (p));
+}
+
+static inline void cinval(void *p)
+{
+        asm volatile ("dcbi 0,%0; icbi 0,%0" : : "r" (p));
+}
+
+/*
+ * Disable surveillance (the service processor watchdog function)
+ * while we are in xmon.
+ * XXX we should re-enable it when we leave. :)
+ */
+#define SURVEILLANCE_TOKEN      9000
+
+static inline void disable_surveillance(void)
+{
+#ifdef CONFIG_PPC_PSERIES
+        /* Since this can't be a module, args should end up below 4GB. */
+        static struct rtas_args args;
+
+        /*
+         * At this point we have got all the cpus we can into
+         * xmon, so there is hopefully no other cpu calling RTAS
+         * at the moment, even though we don't take rtas.lock.
+         * If we did try to take rtas.lock there would be a
+         * real possibility of deadlock.
+         */
+        args.token = rtas_token("set-indicator");
+        if (args.token == RTAS_UNKNOWN_SERVICE)
+                return;
+        args.nargs = 3;
+        args.nret = 1;
+        args.rets = &args.args[3];
+        args.args[0] = SURVEILLANCE_TOKEN;
+        args.args[1] = 0;
+        args.args[2] = 0;
+        enter_rtas(__pa(&args));
+#endif /* CONFIG_PPC_PSERIES */
+}
+
+#ifdef CONFIG_SMP
+static int xmon_speaker;
+
+static void get_output_lock(void)
+{
+        int me = smp_processor_id() + 0x100;
+        int last_speaker = 0, prev;
+        long timeout;
+
+        if (xmon_speaker == me)
+                return;
+        for (;;) {
+                if (xmon_speaker == 0) {
+                        last_speaker = cmpxchg(&xmon_speaker, 0, me);
+                        if (last_speaker == 0)
+                                return;
+                }
+                timeout = 10000000;
+                while (xmon_speaker == last_speaker) {
+                        if (--timeout > 0)
+                                continue;
+                        /* hostile takeover */
+                        prev = cmpxchg(&xmon_speaker, last_speaker, me);
+                        if (prev == last_speaker)
+                                return;
+                        break;
+                }
+        }
+}
+
+static void release_output_lock(void)
+{
+        xmon_speaker = 0;
+}
+#endif
+
+int xmon_core(struct pt_regs *regs, int fromipi)
+{
+        int cmd = 0;
+        unsigned long msr;
+        struct bpt *bp;
+        long recurse_jmp[JMP_BUF_LEN];
+        unsigned long offset;
+#ifdef CONFIG_SMP
+        int cpu;
+        int secondary;
+        unsigned long timeout;
+#endif
+
+        msr = mfmsr();
+        mtmsr(msr & ~MSR_EE);   /* disable interrupts */
+
+        bp = in_breakpoint_table(regs->nip, &offset);
+        if (bp != NULL) {
+                regs->nip = bp->address + offset;
+                atomic_dec(&bp->ref_count);
+        }
+
+        remove_cpu_bpts();
+
+#ifdef CONFIG_SMP
+        cpu = smp_processor_id();
+        if (cpu_isset(cpu, cpus_in_xmon)) {
+                get_output_lock();
+                excprint(regs);
+                printf("cpu 0x%x: Exception %lx %s in xmon, "
+                       "returning to main loop\n",
+                       cpu, regs->trap, getvecname(TRAP(regs)));
+                release_output_lock();
+                longjmp(xmon_fault_jmp[cpu], 1);
+        }
+
+        if (setjmp(recurse_jmp) != 0) {
+                if (!in_xmon || !xmon_gate) {
+                        get_output_lock();
+                        printf("xmon: WARNING: bad recursive fault "
+                               "on cpu 0x%x\n", cpu);
+                        release_output_lock();
+                        goto waiting;
+                }
+                secondary = !(xmon_taken && cpu == xmon_owner);
+                goto cmdloop;
+        }
+
+        xmon_fault_jmp[cpu] = recurse_jmp;
+        cpu_set(cpu, cpus_in_xmon);
+
+        bp = NULL;
+        if ((regs->msr & (MSR_IR|MSR_PR|MSR_SF)) == (MSR_IR|MSR_SF))
+                bp = at_breakpoint(regs->nip);
+        if (bp || (regs->msr & MSR_RI) == 0)
+                fromipi = 0;
+
+        if (!fromipi) {
+                get_output_lock();
+                excprint(regs);
+                if (bp) {
+                        printf("cpu 0x%x stopped at breakpoint 0x%x (",
+                               cpu, BP_NUM(bp));
+                        xmon_print_symbol(regs->nip, " ", ")\n");
+                }
+                if ((regs->msr & MSR_RI) == 0)
+                        printf("WARNING: exception is not recoverable, "
+                               "can't continue\n");
+                release_output_lock();
+        }
+
+ waiting:
+        secondary = 1;
+        while (secondary && !xmon_gate) {
+                if (in_xmon == 0) {
+                        if (fromipi)
+                                goto leave;
+                        secondary = test_and_set_bit(0, &in_xmon);
+                }
+                barrier();
+        }
+
+        if (!secondary && !xmon_gate) {
+                /* we are the first cpu to come in */
+                /* interrupt other cpu(s) */
+                int ncpus = num_online_cpus();
+
+                xmon_owner = cpu;
+                mb();
+                if (ncpus > 1) {
+                        smp_send_debugger_break(MSG_ALL_BUT_SELF);
+                        /* wait for other cpus to come in */
+                        for (timeout = 100000000; timeout != 0; --timeout) {
+                                if (cpus_weight(cpus_in_xmon) >= ncpus)
+                                        break;
+                                barrier();
+                        }
+                }
+                remove_bpts();
+                disable_surveillance();
+                /* for breakpoint or single step, print the current instr. */
+                if (bp || TRAP(regs) == 0xd00)
+                        ppc_inst_dump(regs->nip, 1, 0);
+                printf("enter ? for help\n");
+                mb();
+                xmon_gate = 1;
+                barrier();
+        }
+
+ cmdloop:
+        while (in_xmon) {
+                if (secondary) {
+                        if (cpu == xmon_owner) {
+                                if (!test_and_set_bit(0, &xmon_taken)) {
+                                        secondary = 0;
+                                        continue;
+                                }
+                                /* missed it */
+                                while (cpu == xmon_owner)
+                                        barrier();
+                        }
+                        barrier();
+                } else {
+                        cmd = cmds(regs);
+                        if (cmd != 0) {
+                                /* exiting xmon */
+                                insert_bpts();
+                                xmon_gate = 0;
+                                wmb();
+                                in_xmon = 0;
+                                break;
+                        }
+                        /* have switched to some other cpu */
+                        secondary = 1;
+                }
+        }
+ leave:
+        cpu_clear(cpu, cpus_in_xmon);
+        xmon_fault_jmp[cpu] = NULL;
+
+#else
+        /* UP is simple... */
+        if (in_xmon) {
+                printf("Exception %lx %s in xmon, returning to main loop\n",
+                       regs->trap, getvecname(TRAP(regs)));
+                longjmp(xmon_fault_jmp[0], 1);
+        }
+        if (setjmp(recurse_jmp) == 0) {
+                xmon_fault_jmp[0] = recurse_jmp;
+                in_xmon = 1;
+
+                excprint(regs);
+                bp = at_breakpoint(regs->nip);
+                if (bp) {
+                        printf("Stopped at breakpoint %x (", BP_NUM(bp));
+                        xmon_print_symbol(regs->nip, " ", ")\n");
+                }
+                if ((regs->msr & MSR_RI) == 0)
+                        printf("WARNING: exception is not recoverable, "
+                               "can't continue\n");
+                remove_bpts();
+                disable_surveillance();
+                /* for breakpoint or single step, print the current instr. */
+                if (bp || TRAP(regs) == 0xd00)
+                        ppc_inst_dump(regs->nip, 1, 0);
+                printf("enter ? for help\n");
+        }
+
+        cmd = cmds(regs);
+
+        insert_bpts();
+        in_xmon = 0;
+#endif
+
+        if ((regs->msr & (MSR_IR|MSR_PR|MSR_SF)) == (MSR_IR|MSR_SF)) {
+                bp = at_breakpoint(regs->nip);
+                if (bp != NULL) {
+                        int stepped = emulate_step(regs, bp->instr[0]);
+                        if (stepped == 0) {
+                                regs->nip = (unsigned long) &bp->instr[0];
+                                atomic_inc(&bp->ref_count);
+                        } else if (stepped < 0) {
+                                printf("Couldn't single-step %s instruction\n",
+                                    (IS_RFID(bp->instr[0])? "rfid": "mtmsrd"));
+                        }
+                }
+        }
+
+        insert_cpu_bpts();
+
+        mtmsr(msr);             /* restore interrupt enable */
+
+        return cmd != 'X';
+}
+
+int xmon(struct pt_regs *excp)
+{
+        struct pt_regs regs;
+
+        if (excp == NULL) {
+                xmon_save_regs(&regs);
+                excp = &regs;
+        }
+        return xmon_core(excp, 0);
+}
+EXPORT_SYMBOL(xmon);
+
+irqreturn_t
+xmon_irq(int irq, void *d, struct pt_regs *regs)
+{
+        unsigned long flags;
+        local_irq_save(flags);
+        printf("Keyboard interrupt\n");
+        xmon(regs);
+        local_irq_restore(flags);
+        return IRQ_HANDLED;
+}
+
+int xmon_bpt(struct pt_regs *regs)
+{
+        struct bpt *bp;
+        unsigned long offset;
+
+        if ((regs->msr & (MSR_IR|MSR_PR|MSR_SF)) != (MSR_IR|MSR_SF))
+                return 0;
+
+        /* Are we at the trap at bp->instr[1] for some bp? */
+        bp = in_breakpoint_table(regs->nip, &offset);
+        if (bp != NULL && offset == 4) {
+                regs->nip = bp->address + 4;
+                atomic_dec(&bp->ref_count);
+                return 1;
+        }
+
+        /* Are we at a breakpoint? */
+        bp = at_breakpoint(regs->nip);
+        if (!bp)
+                return 0;
+
+        xmon_core(regs, 0);
+
+        return 1;
+}
+
+int xmon_sstep(struct pt_regs *regs)
+{
+        if (user_mode(regs))
+                return 0;
+        xmon_core(regs, 0);
+        return 1;
+}
+
+int xmon_dabr_match(struct pt_regs *regs)
+{
+        if ((regs->msr & (MSR_IR|MSR_PR|MSR_SF)) != (MSR_IR|MSR_SF))
+                return 0;
+        if (dabr.enabled == 0)
+                return 0;
+        xmon_core(regs, 0);
+        return 1;
+}
+
+int xmon_iabr_match(struct pt_regs *regs)
+{
+        if ((regs->msr & (MSR_IR|MSR_PR|MSR_SF)) != (MSR_IR|MSR_SF))
+                return 0;
+        if (iabr == 0)
+                return 0;
+        xmon_core(regs, 0);
+        return 1;
+}
+
+int xmon_ipi(struct pt_regs *regs)
+{
+#ifdef CONFIG_SMP
+        if (in_xmon && !cpu_isset(smp_processor_id(), cpus_in_xmon))
+                xmon_core(regs, 1);
+#endif
+        return 0;
+}
+
+int xmon_fault_handler(struct pt_regs *regs)
+{
+        struct bpt *bp;
+        unsigned long offset;
+
+        if (in_xmon && catch_memory_errors)
+                handle_fault(regs);     /* doesn't return */
+
+        if ((regs->msr & (MSR_IR|MSR_PR|MSR_SF)) == (MSR_IR|MSR_SF)) {
+                bp = in_breakpoint_table(regs->nip, &offset);
+                if (bp != NULL) {
+                        regs->nip = bp->address + offset;
+                        atomic_dec(&bp->ref_count);
+                }
+        }
+
+        return 0;
+}
+
+static struct bpt *at_breakpoint(unsigned long pc)
+{
+        int i;
+        struct bpt *bp;
+
+        bp = bpts;
+        for (i = 0; i < NBPTS; ++i, ++bp)
+                if (bp->enabled && pc == bp->address)
+                        return bp;
+        return NULL;
+}
+
+static struct bpt *in_breakpoint_table(unsigned long nip, unsigned long *offp)
+{
+        unsigned long off;
+
+        off = nip - (unsigned long) bpts;
+        if (off >= sizeof(bpts))
+                return NULL;
+        off %= sizeof(struct bpt);
+        if (off != offsetof(struct bpt, instr[0])
+            && off != offsetof(struct bpt, instr[1]))
+                return NULL;
+        *offp = off - offsetof(struct bpt, instr[0]);
+        return (struct bpt *) (nip - off);
+}
+
+static struct bpt *new_breakpoint(unsigned long a)
+{
+        struct bpt *bp;
+
+        a &= ~3UL;
+        bp = at_breakpoint(a);
+        if (bp)
+                return bp;
+
+        for (bp = bpts; bp < &bpts[NBPTS]; ++bp) {
+                if (!bp->enabled && atomic_read(&bp->ref_count) == 0) {
+                        bp->address = a;
+                        bp->instr[1] = bpinstr;
+                        store_inst(&bp->instr[1]);
+                        return bp;
+                }
+        }
+
+        printf("Sorry, no free breakpoints.  Please clear one first.\n");
+        return NULL;
+}
+
+static void insert_bpts(void)
+{
+        int i;
+        struct bpt *bp;
+
+        bp = bpts;
+        for (i = 0; i < NBPTS; ++i, ++bp) {
+                if ((bp->enabled & (BP_TRAP|BP_IABR)) == 0)
+                        continue;
+                if (mread(bp->address, &bp->instr[0], 4) != 4) {
+                        printf("Couldn't read instruction at %lx, "
+                               "disabling breakpoint there\n", bp->address);
+                        bp->enabled = 0;
+                        continue;
+                }
+                if (IS_MTMSRD(bp->instr[0]) || IS_RFID(bp->instr[0])) {
+                        printf("Breakpoint at %lx is on an mtmsrd or rfid "
+                               "instruction, disabling it\n", bp->address);
+                        bp->enabled = 0;
+                        continue;
+                }
+                store_inst(&bp->instr[0]);
+                if (bp->enabled & BP_IABR)
+                        continue;
+                if (mwrite(bp->address, &bpinstr, 4) != 4) {
+                        printf("Couldn't write instruction at %lx, "
+                               "disabling breakpoint there\n", bp->address);
+                        bp->enabled &= ~BP_TRAP;
+                        continue;
+                }
+                store_inst((void *)bp->address);
+        }
+}
+
+static void insert_cpu_bpts(void)
+{
+        if (dabr.enabled)
+                set_dabr(dabr.address | (dabr.enabled & 7));
+        if (iabr && cpu_has_feature(CPU_FTR_IABR))
+                mtspr(SPRN_IABR, iabr->address
+                         | (iabr->enabled & (BP_IABR|BP_IABR_TE)));
+}
+
+static void remove_bpts(void)
+{
+        int i;
+        struct bpt *bp;
+        unsigned instr;
+
+        bp = bpts;
+        for (i = 0; i < NBPTS; ++i, ++bp) {
+                if ((bp->enabled & (BP_TRAP|BP_IABR)) != BP_TRAP)
+                        continue;
+                if (mread(bp->address, &instr, 4) == 4
+                    && instr == bpinstr
+                    && mwrite(bp->address, &bp->instr, 4) != 4)
+                        printf("Couldn't remove breakpoint at %lx\n",
+                               bp->address);
+                else
+                        store_inst((void *)bp->address);
+        }
+}
+
+static void remove_cpu_bpts(void)
+{
+        set_dabr(0);
+        if (cpu_has_feature(CPU_FTR_IABR))
+                mtspr(SPRN_IABR, 0);
+}
+
+/* Command interpreting routine */
+static char *last_cmd;
+
+static int
+cmds(struct pt_regs *excp)
+{
+        int cmd = 0;
+
+        last_cmd = NULL;
+        xmon_regs = excp;
+        for(;;) {
+#ifdef CONFIG_SMP
+                printf("%x:", smp_processor_id());
+#endif /* CONFIG_SMP */
+                printf("mon> ");
+                fflush(stdout);
+                flush_input();
+                termch = 0;
+                cmd = skipbl();
+                if( cmd == '\n' ) {
+                        if (last_cmd == NULL)
+                                continue;
+                        take_input(last_cmd);
+                        last_cmd = NULL;
+                        cmd = inchar();
+                }
+                switch (cmd) {
+                case 'm':
+                        cmd = inchar();
+                        switch (cmd) {
+                        case 'm':
+                        case 's':
+                        case 'd':
+                                memops(cmd);
+                                break;
+                        case 'l':
+                                memlocate();
+                                break;
+                        case 'z':
+                                memzcan();
+                                break;
+                        case 'i':
+                                show_mem();
+                                break;
+                        default:
+                                termch = cmd;
+                                memex();
+                        }
+                        break;
+                case 'd':
+                        dump();
+                        break;
+                case 'l':
+                        symbol_lookup();
+                        break;
+                case 'r':
+                        prregs(excp);   /* print regs */
+                        break;
+                case 'e':
+                        excprint(excp);
+                        break;
+                case 'S':
+                        super_regs();
+                        break;
+                case 't':
+                        backtrace(excp);
+                        break;
+                case 'f':
+                        cacheflush();
+                        break;
+                case 's':
+                        if (do_step(excp))
+                                return cmd;
+                        break;
+                case 'x':
+                case 'X':
+                case EOF:
+                        return cmd;
+                case '?':
+                        printf(help_string);
+                        break;
+                case 'b':
+                        bpt_cmds();
+                        break;
+                case 'C':
+                        csum();
+                        break;
+                case 'c':
+                        if (cpu_cmd())
+                                return 0;
+                        break;
+                case 'z':
+                        bootcmds();
+                        break;
+                case 'p':
+                        proccall();
+                        break;
+#ifdef CONFIG_PPC_STD_MMU
+                case 'u':
+                        dump_segments();
+                        break;
+#endif
+                default:
+                        printf("Unrecognized command: ");
+                        do {
+                                if (' ' < cmd && cmd <= '~')
+                                        putchar(cmd);
+                                else
+                                        printf("\\x%x", cmd);
+                                cmd = inchar();
+                        } while (cmd != '\n'); 
+                        printf(" (type ? for help)\n");
+                        break;
+                }
+        }
+}
+
+/*
+ * Step a single instruction.
+ * Some instructions we emulate, others we execute with MSR_SE set.
+ */
+static int do_step(struct pt_regs *regs)
+{
+        unsigned int instr;
+        int stepped;
+
+        /* check we are in 64-bit kernel mode, translation enabled */
+        if ((regs->msr & (MSR_SF|MSR_PR|MSR_IR)) == (MSR_SF|MSR_IR)) {
+                if (mread(regs->nip, &instr, 4) == 4) {
+                        stepped = emulate_step(regs, instr);
+                        if (stepped < 0) {
+                                printf("Couldn't single-step %s instruction\n",
+                                       (IS_RFID(instr)? "rfid": "mtmsrd"));
+                                return 0;
+                        }
+                        if (stepped > 0) {
+                                regs->trap = 0xd00 | (regs->trap & 1);
+                                printf("stepped to ");
+                                xmon_print_symbol(regs->nip, " ", "\n");
+                                ppc_inst_dump(regs->nip, 1, 0);
+                                return 0;
+                        }
+                }
+        }
+        regs->msr |= MSR_SE;
+        return 1;
+}
+
+static void bootcmds(void)
+{
+        int cmd;
+
+        cmd = inchar();
+        if (cmd == 'r')
+                ppc_md.restart(NULL);
+        else if (cmd == 'h')
+                ppc_md.halt();
+        else if (cmd == 'p')
+                ppc_md.power_off();
+}
+
+static int cpu_cmd(void)
+{
+#ifdef CONFIG_SMP
+        unsigned long cpu;
+        int timeout;
+        int count;
+
+        if (!scanhex(&cpu)) {
+                /* print cpus waiting or in xmon */
+                printf("cpus stopped:");
+                count = 0;
+                for (cpu = 0; cpu < NR_CPUS; ++cpu) {
+                        if (cpu_isset(cpu, cpus_in_xmon)) {
+                                if (count == 0)
+                                        printf(" %x", cpu);
+                                ++count;
+                        } else {
+                                if (count > 1)
+                                        printf("-%x", cpu - 1);
+                                count = 0;
+                        }
+                }
+                if (count > 1)
+                        printf("-%x", NR_CPUS - 1);
+                printf("\n");
+                return 0;
+        }
+        /* try to switch to cpu specified */
+        if (!cpu_isset(cpu, cpus_in_xmon)) {
+                printf("cpu 0x%x isn't in xmon\n", cpu);
+                return 0;
+        }
+        xmon_taken = 0;
+        mb();
+        xmon_owner = cpu;
+        timeout = 10000000;
+        while (!xmon_taken) {
+                if (--timeout == 0) {
+                        if (test_and_set_bit(0, &xmon_taken))
+                                break;
+                        /* take control back */
+                        mb();
+                        xmon_owner = smp_processor_id();
+                        printf("cpu %u didn't take control\n", cpu);
+                        return 0;
+                }
+                barrier();
+        }
+        return 1;
+#else
+        return 0;
+#endif /* CONFIG_SMP */
+}
+
+static unsigned short fcstab[256] = {
+        0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf,
+        0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7,
+        0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e,
+        0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876,
+        0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd,
+        0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5,
+        0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c,
+        0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974,
+        0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb,
+        0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3,
+        0x5285, 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a,
+        0xdecd, 0xcf44, 0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72,
+        0x6306, 0x728f, 0x4014, 0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9,
+        0xef4e, 0xfec7, 0xcc5c, 0xddd5, 0xa96a, 0xb8e3, 0x8a78, 0x9bf1,
+        0x7387, 0x620e, 0x5095, 0x411c, 0x35a3, 0x242a, 0x16b1, 0x0738,
+        0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862, 0x9af9, 0x8b70,
+        0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e, 0xf0b7,
+        0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff,
+        0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036,
+        0x18c1, 0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e,
+        0xa50a, 0xb483, 0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5,
+        0x2942, 0x38cb, 0x0a50, 0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd,
+        0xb58b, 0xa402, 0x9699, 0x8710, 0xf3af, 0xe226, 0xd0bd, 0xc134,
+        0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7, 0x6e6e, 0x5cf5, 0x4d7c,
+        0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1, 0xa33a, 0xb2b3,
+        0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72, 0x3efb,
+        0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232,
+        0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a,
+        0xe70e, 0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1,
+        0x6b46, 0x7acf, 0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9,
+        0xf78f, 0xe606, 0xd49d, 0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330,
+        0x7bc7, 0x6a4e, 0x58d5, 0x495c, 0x3de3, 0x2c6a, 0x1ef1, 0x0f78
+};
+
+#define FCS(fcs, c)     (((fcs) >> 8) ^ fcstab[((fcs) ^ (c)) & 0xff])
+
+static void
+csum(void)
+{
+        unsigned int i;
+        unsigned short fcs;
+        unsigned char v;
+
+        if (!scanhex(&adrs))
+                return;
+        if (!scanhex(&ncsum))
+                return;
+        fcs = 0xffff;
+        for (i = 0; i < ncsum; ++i) {
+                if (mread(adrs+i, &v, 1) == 0) {
+                        printf("csum stopped at %x\n", adrs+i);
+                        break;
+                }
+                fcs = FCS(fcs, v);
+        }
+        printf("%x\n", fcs);
+}
+
+/*
+ * Check if this is a suitable place to put a breakpoint.
+ */
+static long check_bp_loc(unsigned long addr)
+{
+        unsigned int instr;
+
+        addr &= ~3;
+        if (addr < KERNELBASE) {
+                printf("Breakpoints may only be placed at kernel addresses\n");
+                return 0;
+        }
+        if (!mread(addr, &instr, sizeof(instr))) {
+                printf("Can't read instruction at address %lx\n", addr);
+                return 0;
+        }
+        if (IS_MTMSRD(instr) || IS_RFID(instr)) {
+                printf("Breakpoints may not be placed on mtmsrd or rfid "
+                       "instructions\n");
+                return 0;
+        }
+        return 1;
+}
+
+static char *breakpoint_help_string = 
+    "Breakpoint command usage:\n"
+    "b                show breakpoints\n"
+    "b <addr> [cnt]   set breakpoint at given instr addr\n"
+    "bc               clear all breakpoints\n"
+    "bc <n/addr>      clear breakpoint number n or at addr\n"
+    "bi <addr> [cnt]  set hardware instr breakpoint (POWER3/RS64 only)\n"
+    "bd <addr> [cnt]  set hardware data breakpoint\n"
+    "";
+
+static void
+bpt_cmds(void)
+{
+        int cmd;
+        unsigned long a;
+        int mode, i;
+        struct bpt *bp;
+        const char badaddr[] = "Only kernel addresses are permitted "
+                "for breakpoints\n";
+
+        cmd = inchar();
+        switch (cmd) {
+#ifndef CONFIG_8xx
+        case 'd':       /* bd - hardware data breakpoint */
+                mode = 7;
+                cmd = inchar();
+                if (cmd == 'r')
+                        mode = 5;
+                else if (cmd == 'w')
+                        mode = 6;
+                else
+                        termch = cmd;
+                dabr.address = 0;
+                dabr.enabled = 0;
+                if (scanhex(&dabr.address)) {
+                        if (dabr.address < KERNELBASE) {
+                                printf(badaddr);
+                                break;
+                        }
+                        dabr.address &= ~7;
+                        dabr.enabled = mode | BP_DABR;
+                }
+                break;
+
+        case 'i':       /* bi - hardware instr breakpoint */
+                if (!cpu_has_feature(CPU_FTR_IABR)) {
+                        printf("Hardware instruction breakpoint "
+                               "not supported on this cpu\n");
+                        break;
+                }
+                if (iabr) {
+                        iabr->enabled &= ~(BP_IABR | BP_IABR_TE);
+                        iabr = NULL;
+                }
+                if (!scanhex(&a))
+                        break;
+                if (!check_bp_loc(a))
+                        break;
+                bp = new_breakpoint(a);
+                if (bp != NULL) {
+                        bp->enabled |= BP_IABR | BP_IABR_TE;
+                        iabr = bp;
+                }
+                break;
+#endif
+
+        case 'c':
+                if (!scanhex(&a)) {
+                        /* clear all breakpoints */
+                        for (i = 0; i < NBPTS; ++i)
+                                bpts[i].enabled = 0;
+                        iabr = NULL;
+                        dabr.enabled = 0;
+                        printf("All breakpoints cleared\n");
+                        break;
+                }
+
+                if (a <= NBPTS && a >= 1) {
+                        /* assume a breakpoint number */
+                        bp = &bpts[a-1];        /* bp nums are 1 based */
+                } else {
+                        /* assume a breakpoint address */
+                        bp = at_breakpoint(a);
+                        if (bp == 0) {
+                                printf("No breakpoint at %x\n", a);
+                                break;
+                        }
+                }
+
+                printf("Cleared breakpoint %x (", BP_NUM(bp));
+                xmon_print_symbol(bp->address, " ", ")\n");
+                bp->enabled = 0;
+                break;
+
+        default:
+                termch = cmd;
+                cmd = skipbl();
+                if (cmd == '?') {
+                        printf(breakpoint_help_string);
+                        break;
+                }
+                termch = cmd;
+                if (!scanhex(&a)) {
+                        /* print all breakpoints */
+                        printf("   type            address\n");
+                        if (dabr.enabled) {
+                                printf("   data   "REG"  [", dabr.address);
+                                if (dabr.enabled & 1)
+                                        printf("r");
+                                if (dabr.enabled & 2)
+                                        printf("w");
+                                printf("]\n");
+                        }
+                        for (bp = bpts; bp < &bpts[NBPTS]; ++bp) {
+                                if (!bp->enabled)
+                                        continue;
+                                printf("%2x %s   ", BP_NUM(bp),
+                                    (bp->enabled & BP_IABR)? "inst": "trap");
+                                xmon_print_symbol(bp->address, "  ", "\n");
+                        }
+                        break;
+                }
+
+                if (!check_bp_loc(a))
+                        break;
+                bp = new_breakpoint(a);
+                if (bp != NULL)
+                        bp->enabled |= BP_TRAP;
+                break;
+        }
+}
+
+/* Very cheap human name for vector lookup. */
+static
+const char *getvecname(unsigned long vec)
+{
+        char *ret;
+
+        switch (vec) {
+        case 0x100:     ret = "(System Reset)"; break;
+        case 0x200:     ret = "(Machine Check)"; break;
+        case 0x300:     ret = "(Data Access)"; break;
+        case 0x380:     ret = "(Data SLB Access)"; break;
+        case 0x400:     ret = "(Instruction Access)"; break;
+        case 0x480:     ret = "(Instruction SLB Access)"; break;
+        case 0x500:     ret = "(Hardware Interrupt)"; break;
+        case 0x600:     ret = "(Alignment)"; break;
+        case 0x700:     ret = "(Program Check)"; break;
+        case 0x800:     ret = "(FPU Unavailable)"; break;
+        case 0x900:     ret = "(Decrementer)"; break;
+        case 0xc00:     ret = "(System Call)"; break;
+        case 0xd00:     ret = "(Single Step)"; break;
+        case 0xf00:     ret = "(Performance Monitor)"; break;
+        case 0xf20:     ret = "(Altivec Unavailable)"; break;
+        case 0x1300:    ret = "(Instruction Breakpoint)"; break;
+        default: ret = "";
+        }
+        return ret;
+}
+
+static void get_function_bounds(unsigned long pc, unsigned long *startp,
+                                unsigned long *endp)
+{
+        unsigned long size, offset;
+        const char *name;
+        char *modname;
+
+        *startp = *endp = 0;
+        if (pc == 0)
+                return;
+        if (setjmp(bus_error_jmp) == 0) {
+                catch_memory_errors = 1;
+                sync();
+                name = kallsyms_lookup(pc, &size, &offset, &modname, tmpstr);
+                if (name != NULL) {
+                        *startp = pc - offset;
+                        *endp = pc - offset + size;
+                }
+                sync();
+        }
+        catch_memory_errors = 0;
+}
+
+static int xmon_depth_to_print = 64;
+
+#ifdef CONFIG_PPC64
+#define LRSAVE_OFFSET           0x10
+#define REG_FRAME_MARKER        0x7265677368657265ul    /* "regshere" */
+#define MARKER_OFFSET           0x60
+#define REGS_OFFSET             0x70
+#else
+#define LRSAVE_OFFSET           4
+#define REG_FRAME_MARKER        0x72656773
+#define MARKER_OFFSET           8
+#define REGS_OFFSET             16
+#endif
+
+static void xmon_show_stack(unsigned long sp, unsigned long lr,
+                            unsigned long pc)
+{
+        unsigned long ip;
+        unsigned long newsp;
+        unsigned long marker;
+        int count = 0;
+        struct pt_regs regs;
+
+        do {
+                if (sp < PAGE_OFFSET) {
+                        if (sp != 0)
+                                printf("SP (%lx) is in userspace\n", sp);
+                        break;
+                }
+
+                if (!mread(sp + LRSAVE_OFFSET, &ip, sizeof(unsigned long))
+                    || !mread(sp, &newsp, sizeof(unsigned long))) {
+                        printf("Couldn't read stack frame at %lx\n", sp);
+                        break;
+                }
+
+                /*
+                 * For the first stack frame, try to work out if
+                 * LR and/or the saved LR value in the bottommost
+                 * stack frame are valid.
+                 */
+                if ((pc | lr) != 0) {
+                        unsigned long fnstart, fnend;
+                        unsigned long nextip;
+                        int printip = 1;
+
+                        get_function_bounds(pc, &fnstart, &fnend);
+                        nextip = 0;
+                        if (newsp > sp)
+                                mread(newsp + LRSAVE_OFFSET, &nextip,
+                                      sizeof(unsigned long));
+                        if (lr == ip) {
+                                if (lr < PAGE_OFFSET
+                                    || (fnstart <= lr && lr < fnend))
+                                        printip = 0;
+                        } else if (lr == nextip) {
+                                printip = 0;
+                        } else if (lr >= PAGE_OFFSET
+                                   && !(fnstart <= lr && lr < fnend)) {
+                                printf("[link register   ] ");
+                                xmon_print_symbol(lr, " ", "\n");
+                        }
+                        if (printip) {
+                                printf("["REG"] ", sp);
+                                xmon_print_symbol(ip, " ", " (unreliable)\n");
+                        }
+                        pc = lr = 0;
+
+                } else {
+                        printf("["REG"] ", sp);
+                        xmon_print_symbol(ip, " ", "\n");
+                }
+
+                /* Look for "regshere" marker to see if this is
+                   an exception frame. */
+                if (mread(sp + MARKER_OFFSET, &marker, sizeof(unsigned long))
+                    && marker == REG_FRAME_MARKER) {
+                        if (mread(sp + REGS_OFFSET, &regs, sizeof(regs))
+                            != sizeof(regs)) {
+                                printf("Couldn't read registers at %lx\n",
+                                       sp + REGS_OFFSET);
+                                break;
+                        }
+                        printf("--- Exception: %lx %s at ", regs.trap,
+                               getvecname(TRAP(&regs)));
+                        pc = regs.nip;
+                        lr = regs.link;
+                        xmon_print_symbol(pc, " ", "\n");
+                }
+
+                if (newsp == 0)
+                        break;
+
+                sp = newsp;
+        } while (count++ < xmon_depth_to_print);
+}
+
+static void backtrace(struct pt_regs *excp)
+{
+        unsigned long sp;
+
+        if (scanhex(&sp))
+                xmon_show_stack(sp, 0, 0);
+        else
+                xmon_show_stack(excp->gpr[1], excp->link, excp->nip);
+        scannl();
+}
+
+static void print_bug_trap(struct pt_regs *regs)
+{
+        struct bug_entry *bug;
+        unsigned long addr;
+
+        if (regs->msr & MSR_PR)
+                return;         /* not in kernel */
+        addr = regs->nip;       /* address of trap instruction */
+        if (addr < PAGE_OFFSET)
+                return;
+        bug = find_bug(regs->nip);
+        if (bug == NULL)
+                return;
+        if (bug->line & BUG_WARNING_TRAP)
+                return;
+
+        printf("kernel BUG in %s at %s:%d!\n",
+               bug->function, bug->file, (unsigned int)bug->line);
+}
+
+void excprint(struct pt_regs *fp)
+{
+        unsigned long trap;
+
+#ifdef CONFIG_SMP
+        printf("cpu 0x%x: ", smp_processor_id());
+#endif /* CONFIG_SMP */
+
+        trap = TRAP(fp);
+        printf("Vector: %lx %s at [%lx]\n", fp->trap, getvecname(trap), fp);
+        printf("    pc: ");
+        xmon_print_symbol(fp->nip, ": ", "\n");
+
+        printf("    lr: ", fp->link);
+        xmon_print_symbol(fp->link, ": ", "\n");
+
+        printf("    sp: %lx\n", fp->gpr[1]);
+        printf("   msr: %lx\n", fp->msr);
+
+        if (trap == 0x300 || trap == 0x380 || trap == 0x600) {
+                printf("   dar: %lx\n", fp->dar);
+                if (trap != 0x380)
+                        printf(" dsisr: %lx\n", fp->dsisr);
+        }
+
+        printf("  current = 0x%lx\n", current);
+#ifdef CONFIG_PPC64
+        printf("  paca    = 0x%lx\n", get_paca());
+#endif
+        if (current) {
+                printf("    pid   = %ld, comm = %s\n",
+                       current->pid, current->comm);
+        }
+
+        if (trap == 0x700)
+                print_bug_trap(fp);
+}
+
+void prregs(struct pt_regs *fp)
+{
+        int n, trap;
+        unsigned long base;
+        struct pt_regs regs;
+
+        if (scanhex(&base)) {
+                if (setjmp(bus_error_jmp) == 0) {
+                        catch_memory_errors = 1;
+                        sync();
+                        regs = *(struct pt_regs *)base;
+                        sync();
+                        __delay(200);
+                } else {
+                        catch_memory_errors = 0;
+                        printf("*** Error reading registers from "REG"\n",
+                               base);
+                        return;
+                }
+                catch_memory_errors = 0;
+                fp = &regs;
+        }
+
+#ifdef CONFIG_PPC64
+        if (FULL_REGS(fp)) {
+                for (n = 0; n < 16; ++n)
+                        printf("R%.2ld = "REG"   R%.2ld = "REG"\n",
+                               n, fp->gpr[n], n+16, fp->gpr[n+16]);
+        } else {
+                for (n = 0; n < 7; ++n)
+                        printf("R%.2ld = "REG"   R%.2ld = "REG"\n",
+                               n, fp->gpr[n], n+7, fp->gpr[n+7]);
+        }
+#else
+        for (n = 0; n < 32; ++n) {
+                printf("R%.2d = %.8x%s", n, fp->gpr[n],
+                       (n & 3) == 3? "\n": "   ");
+                if (n == 12 && !FULL_REGS(fp)) {
+                        printf("\n");
+                        break;
+                }
+        }
+#endif
+        printf("pc  = ");
+        xmon_print_symbol(fp->nip, " ", "\n");
+        printf("lr  = ");
+        xmon_print_symbol(fp->link, " ", "\n");
+        printf("msr = "REG"   cr  = %.8lx\n", fp->msr, fp->ccr);
+        printf("ctr = "REG"   xer = "REG"   trap = %4lx\n",
+               fp->ctr, fp->xer, fp->trap);
+        trap = TRAP(fp);
+        if (trap == 0x300 || trap == 0x380 || trap == 0x600)
+                printf("dar = "REG"   dsisr = %.8lx\n", fp->dar, fp->dsisr);
+}
+
+void cacheflush(void)
+{
+        int cmd;
+        unsigned long nflush;
+
+        cmd = inchar();
+        if (cmd != 'i')
+                termch = cmd;
+        scanhex((void *)&adrs);
+        if (termch != '\n')
+                termch = 0;
+        nflush = 1;
+        scanhex(&nflush);
+        nflush = (nflush + L1_CACHE_BYTES - 1) / L1_CACHE_BYTES;
+        if (setjmp(bus_error_jmp) == 0) {
+                catch_memory_errors = 1;
+                sync();
+
+                if (cmd != 'i') {
+                        for (; nflush > 0; --nflush, adrs += L1_CACHE_BYTES)
+                                cflush((void *) adrs);
+                } else {
+                        for (; nflush > 0; --nflush, adrs += L1_CACHE_BYTES)
+                                cinval((void *) adrs);
+                }
+                sync();
+                /* wait a little while to see if we get a machine check */
+                __delay(200);
+        }
+        catch_memory_errors = 0;
+}
+
+unsigned long
+read_spr(int n)
+{
+        unsigned int instrs[2];
+        unsigned long (*code)(void);
+        unsigned long opd[3];
+        unsigned long ret = -1UL;
+
+        instrs[0] = 0x7c6002a6 + ((n & 0x1F) << 16) + ((n & 0x3e0) << 6);
+        instrs[1] = 0x4e800020;
+        opd[0] = (unsigned long)instrs;
+        opd[1] = 0;
+        opd[2] = 0;
+        store_inst(instrs);
+        store_inst(instrs+1);
+        code = (unsigned long (*)(void)) opd;
+
+        if (setjmp(bus_error_jmp) == 0) {
+                catch_memory_errors = 1;
+                sync();
+
+                ret = code();
+
+                sync();
+                /* wait a little while to see if we get a machine check */
+                __delay(200);
+                n = size;
+        }
+
+        return ret;
+}
+
+void
+write_spr(int n, unsigned long val)
+{
+        unsigned int instrs[2];
+        unsigned long (*code)(unsigned long);
+        unsigned long opd[3];
+
+        instrs[0] = 0x7c6003a6 + ((n & 0x1F) << 16) + ((n & 0x3e0) << 6);
+        instrs[1] = 0x4e800020;
+        opd[0] = (unsigned long)instrs;
+        opd[1] = 0;
+        opd[2] = 0;
+        store_inst(instrs);
+        store_inst(instrs+1);
+        code = (unsigned long (*)(unsigned long)) opd;
+
+        if (setjmp(bus_error_jmp) == 0) {
+                catch_memory_errors = 1;
+                sync();
+
+                code(val);
+
+                sync();
+                /* wait a little while to see if we get a machine check */
+                __delay(200);
+                n = size;
+        }
+}
+
+static unsigned long regno;
+extern char exc_prolog;
+extern char dec_exc;
+
+void super_regs(void)
+{
+        int cmd;
+        unsigned long val;
+#ifdef CONFIG_PPC_ISERIES
+        struct paca_struct *ptrPaca = NULL;
+        struct lppaca *ptrLpPaca = NULL;
+        struct ItLpRegSave *ptrLpRegSave = NULL;
+#endif
+
+        cmd = skipbl();
+        if (cmd == '\n') {
+                unsigned long sp, toc;
+                asm("mr %0,1" : "=r" (sp) :);
+                asm("mr %0,2" : "=r" (toc) :);
+
+                printf("msr  = "REG"  sprg0= "REG"\n",
+                       mfmsr(), mfspr(SPRN_SPRG0));
+                printf("pvr  = "REG"  sprg1= "REG"\n",
+                       mfspr(SPRN_PVR), mfspr(SPRN_SPRG1)); 
+                printf("dec  = "REG"  sprg2= "REG"\n",
+                       mfspr(SPRN_DEC), mfspr(SPRN_SPRG2));
+                printf("sp   = "REG"  sprg3= "REG"\n", sp, mfspr(SPRN_SPRG3));
+                printf("toc  = "REG"  dar  = "REG"\n", toc, mfspr(SPRN_DAR));
+#ifdef CONFIG_PPC_ISERIES
+                // Dump out relevant Paca data areas.
+                printf("Paca: \n");
+                ptrPaca = get_paca();
+    
+                printf("  Local Processor Control Area (LpPaca): \n");
+                ptrLpPaca = ptrPaca->lppaca_ptr;
+                printf("    Saved Srr0=%.16lx  Saved Srr1=%.16lx \n",
+                       ptrLpPaca->saved_srr0, ptrLpPaca->saved_srr1);
+                printf("    Saved Gpr3=%.16lx  Saved Gpr4=%.16lx \n",
+                       ptrLpPaca->saved_gpr3, ptrLpPaca->saved_gpr4);
+                printf("    Saved Gpr5=%.16lx \n", ptrLpPaca->saved_gpr5);
+    
+                printf("  Local Processor Register Save Area (LpRegSave): \n");
+                ptrLpRegSave = ptrPaca->reg_save_ptr;
+                printf("    Saved Sprg0=%.16lx  Saved Sprg1=%.16lx \n",
+                       ptrLpRegSave->xSPRG0, ptrLpRegSave->xSPRG0);
+                printf("    Saved Sprg2=%.16lx  Saved Sprg3=%.16lx \n",
+                       ptrLpRegSave->xSPRG2, ptrLpRegSave->xSPRG3);
+                printf("    Saved Msr  =%.16lx  Saved Nia  =%.16lx \n",
+                       ptrLpRegSave->xMSR, ptrLpRegSave->xNIA);
+#endif
+
+                return;
+        }
+
+        scanhex(&regno);
+        switch (cmd) {
+        case 'w':
+                val = read_spr(regno);
+                scanhex(&val);
+                write_spr(regno, val);
+                /* fall through */
+        case 'r':
+                printf("spr %lx = %lx\n", regno, read_spr(regno));
+                break;
+        }
+        scannl();
+}
+
+/*
+ * Stuff for reading and writing memory safely
+ */
+int
+mread(unsigned long adrs, void *buf, int size)
+{
+        volatile int n;
+        char *p, *q;
+
+        n = 0;
+        if (setjmp(bus_error_jmp) == 0) {
+                catch_memory_errors = 1;
+                sync();
+                p = (char *)adrs;
+                q = (char *)buf;
+                switch (size) {
+                case 2:
+                        *(u16 *)q = *(u16 *)p;
+                        break;
+                case 4:
+                        *(u32 *)q = *(u32 *)p;
+                        break;
+                case 8:
+                        *(u64 *)q = *(u64 *)p;
+                        break;
+                default:
+                        for( ; n < size; ++n) {
+                                *q++ = *p++;
+                                sync();
+                        }
+                }
+                sync();
+                /* wait a little while to see if we get a machine check */
+                __delay(200);
+                n = size;
+        }
+        catch_memory_errors = 0;
+        return n;
+}
+
+int
+mwrite(unsigned long adrs, void *buf, int size)
+{
+        volatile int n;
+        char *p, *q;
+
+        n = 0;
+        if (setjmp(bus_error_jmp) == 0) {
+                catch_memory_errors = 1;
+                sync();
+                p = (char *) adrs;
+                q = (char *) buf;
+                switch (size) {
+                case 2:
+                        *(u16 *)p = *(u16 *)q;
+                        break;
+                case 4:
+                        *(u32 *)p = *(u32 *)q;
+                        break;
+                case 8:
+                        *(u64 *)p = *(u64 *)q;
+                        break;
+                default:
+                        for ( ; n < size; ++n) {
+                                *p++ = *q++;
+                                sync();
+                        }
+                }
+                sync();
+                /* wait a little while to see if we get a machine check */
+                __delay(200);
+                n = size;
+        } else {
+                printf("*** Error writing address %x\n", adrs + n);
+        }
+        catch_memory_errors = 0;
+        return n;
+}
+
+static int fault_type;
+static int fault_except;
+static char *fault_chars[] = { "--", "**", "##" };
+
+static int handle_fault(struct pt_regs *regs)
+{
+        fault_except = TRAP(regs);
+        switch (TRAP(regs)) {
+        case 0x200:
+                fault_type = 0;
+                break;
+        case 0x300:
+        case 0x380:
+                fault_type = 1;
+                break;
+        default:
+                fault_type = 2;
+        }
+
+        longjmp(bus_error_jmp, 1);
+
+        return 0;
+}
+
+#define SWAP(a, b, t)   ((t) = (a), (a) = (b), (b) = (t))
+
+void
+byterev(unsigned char *val, int size)
+{
+        int t;
+        
+        switch (size) {
+        case 2:
+                SWAP(val[0], val[1], t);
+                break;
+        case 4:
+                SWAP(val[0], val[3], t);
+                SWAP(val[1], val[2], t);
+                break;
+        case 8: /* is there really any use for this? */
+                SWAP(val[0], val[7], t);
+                SWAP(val[1], val[6], t);
+                SWAP(val[2], val[5], t);
+                SWAP(val[3], val[4], t);
+                break;
+        }
+}
+
+static int brev;
+static int mnoread;
+
+static char *memex_help_string = 
+    "Memory examine command usage:\n"
+    "m [addr] [flags] examine/change memory\n"
+    "  addr is optional.  will start where left off.\n"
+    "  flags may include chars from this set:\n"
+    "    b   modify by bytes (default)\n"
+    "    w   modify by words (2 byte)\n"
+    "    l   modify by longs (4 byte)\n"
+    "    d   modify by doubleword (8 byte)\n"
+    "    r   toggle reverse byte order mode\n"
+    "    n   do not read memory (for i/o spaces)\n"
+    "    .   ok to read (default)\n"
+    "NOTE: flags are saved as defaults\n"
+    "";
+
+static char *memex_subcmd_help_string = 
+    "Memory examine subcommands:\n"
+    "  hexval   write this val to current location\n"
+    "  'string' write chars from string to this location\n"
+    "  '        increment address\n"
+    "  ^        decrement address\n"
+    "  /        increment addr by 0x10.  //=0x100, ///=0x1000, etc\n"
+    "  \\        decrement addr by 0x10.  \\\\=0x100, \\\\\\=0x1000, etc\n"
+    "  `        clear no-read flag\n"
+    "  ;        stay at this addr\n"
+    "  v        change to byte mode\n"
+    "  w        change to word (2 byte) mode\n"
+    "  l        change to long (4 byte) mode\n"
+    "  u        change to doubleword (8 byte) mode\n"
+    "  m addr   change current addr\n"
+    "  n        toggle no-read flag\n"
+    "  r        toggle byte reverse flag\n"
+    "  < count  back up count bytes\n"
+    "  > count  skip forward count bytes\n"
+    "  x        exit this mode\n"
+    "";
+
+void
+memex(void)
+{
+        int cmd, inc, i, nslash;
+        unsigned long n;
+        unsigned char val[16];
+
+        scanhex((void *)&adrs);
+        cmd = skipbl();
+        if (cmd == '?') {
+                printf(memex_help_string);
+                return;
+        } else {
+                termch = cmd;
+        }
+        last_cmd = "m\n";
+        while ((cmd = skipbl()) != '\n') {
+                switch( cmd ){
+                case 'b':       size = 1;       break;
+                case 'w':       size = 2;       break;
+                case 'l':       size = 4;       break;
+                case 'd':       size = 8;       break;
+                case 'r':       brev = !brev;   break;
+                case 'n':       mnoread = 1;    break;
+                case '.':       mnoread = 0;    break;
+                }
+        }
+        if( size <= 0 )
+                size = 1;
+        else if( size > 8 )
+                size = 8;
+        for(;;){
+                if (!mnoread)
+                        n = mread(adrs, val, size);
+                printf("%.16x%c", adrs, brev? 'r': ' ');
+                if (!mnoread) {
+                        if (brev)
+                                byterev(val, size);
+                        putchar(' ');
+                        for (i = 0; i < n; ++i)
+                                printf("%.2x", val[i]);
+                        for (; i < size; ++i)
+                                printf("%s", fault_chars[fault_type]);
+                }
+                putchar(' ');
+                inc = size;
+                nslash = 0;
+                for(;;){
+                        if( scanhex(&n) ){
+                                for (i = 0; i < size; ++i)
+                                        val[i] = n >> (i * 8);
+                                if (!brev)
+                                        byterev(val, size);
+                                mwrite(adrs, val, size);
+                                inc = size;
+                        }
+                        cmd = skipbl();
+                        if (cmd == '\n')
+                                break;
+                        inc = 0;
+                        switch (cmd) {
+                        case '\'':
+                                for(;;){
+                                        n = inchar();
+                                        if( n == '\\' )
+                                                n = bsesc();
+                                        else if( n == '\'' )
+                                                break;
+                                        for (i = 0; i < size; ++i)
+                                                val[i] = n >> (i * 8);
+                                        if (!brev)
+                                                byterev(val, size);
+                                        mwrite(adrs, val, size);
+                                        adrs += size;
+                                }
+                                adrs -= size;
+                                inc = size;
+                                break;
+                        case ',':
+                                adrs += size;
+                                break;
+                        case '.':
+                                mnoread = 0;
+                                break;
+                        case ';':
+                                break;
+                        case 'x':
+                        case EOF:
+                                scannl();
+                                return;
+                        case 'b':
+                        case 'v':
+                                size = 1;
+                                break;
+                        case 'w':
+                                size = 2;
+                                break;
+                        case 'l':
+                                size = 4;
+                                break;
+                        case 'u':
+                                size = 8;
+                                break;
+                        case '^':
+                                adrs -= size;
+                                break;
+                                break;
+                        case '/':
+                                if (nslash > 0)
+                                        adrs -= 1 << nslash;
+                                else
+                                        nslash = 0;
+                                nslash += 4;
+                                adrs += 1 << nslash;
+                                break;
+                        case '\\':
+                                if (nslash < 0)
+                                        adrs += 1 << -nslash;
+                                else
+                                        nslash = 0;
+                                nslash -= 4;
+                                adrs -= 1 << -nslash;
+                                break;
+                        case 'm':
+                                scanhex((void *)&adrs);
+                                break;
+                        case 'n':
+                                mnoread = 1;
+                                break;
+                        case 'r':
+                                brev = !brev;
+                                break;
+                        case '<':
+                                n = size;
+                                scanhex(&n);
+                                adrs -= n;
+                                break;
+                        case '>':
+                                n = size;
+                                scanhex(&n);
+                                adrs += n;
+                                break;
+                        case '?':
+                                printf(memex_subcmd_help_string);
+                                break;
+                        }
+                }
+                adrs += inc;
+        }
+}
+
+int
+bsesc(void)
+{
+        int c;
+
+        c = inchar();
+        switch( c ){
+        case 'n':       c = '\n';       break;
+        case 'r':       c = '\r';       break;
+        case 'b':       c = '\b';       break;
+        case 't':       c = '\t';       break;
+        }
+        return c;
+}
+
+#define isxdigit(c)     (('0' <= (c) && (c) <= '9') \
+                         || ('a' <= (c) && (c) <= 'f') \
+                         || ('A' <= (c) && (c) <= 'F'))
+void
+dump(void)
+{
+        int c;
+
+        c = inchar();
+        if ((isxdigit(c) && c != 'f' && c != 'd') || c == '\n')
+                termch = c;
+        scanhex((void *)&adrs);
+        if (termch != '\n')
+                termch = 0;
+        if (c == 'i') {
+                scanhex(&nidump);
+                if (nidump == 0)
+                        nidump = 16;
+                else if (nidump > MAX_DUMP)
+                        nidump = MAX_DUMP;
+                adrs += ppc_inst_dump(adrs, nidump, 1);
+                last_cmd = "di\n";
+        } else {
+                scanhex(&ndump);
+                if (ndump == 0)
+                        ndump = 64;
+                else if (ndump > MAX_DUMP)
+                        ndump = MAX_DUMP;
+                prdump(adrs, ndump);
+                adrs += ndump;
+                last_cmd = "d\n";
+        }
+}
+
+void
+prdump(unsigned long adrs, long ndump)
+{
+        long n, m, c, r, nr;
+        unsigned char temp[16];
+
+        for (n = ndump; n > 0;) {
+                printf(REG, adrs);
+                putchar(' ');
+                r = n < 16? n: 16;
+                nr = mread(adrs, temp, r);
+                adrs += nr;
+                for (m = 0; m < r; ++m) {
+                        if ((m & 7) == 0 && m > 0)
+                            putchar(' ');
+                        if (m < nr)
+                                printf("%.2x", temp[m]);
+                        else
+                                printf("%s", fault_chars[fault_type]);
+                }
+                if (m <= 8)
+                        printf(" ");
+                for (; m < 16; ++m)
+                        printf("  ");
+                printf("  |");
+                for (m = 0; m < r; ++m) {
+                        if (m < nr) {
+                                c = temp[m];
+                                putchar(' ' <= c && c <= '~'? c: '.');
+                        } else
+                                putchar(' ');
+                }
+                n -= r;
+                for (; m < 16; ++m)
+                        putchar(' ');
+                printf("|\n");
+                if (nr < r)
+                        break;
+        }
+}
+
+int
+ppc_inst_dump(unsigned long adr, long count, int praddr)
+{
+        int nr, dotted;
+        unsigned long first_adr;
+        unsigned long inst, last_inst = 0;
+        unsigned char val[4];
+
+        dotted = 0;
+        for (first_adr = adr; count > 0; --count, adr += 4) {
+                nr = mread(adr, val, 4);
+                if (nr == 0) {
+                        if (praddr) {
+                                const char *x = fault_chars[fault_type];
+                                printf(REG"  %s%s%s%s\n", adr, x, x, x, x);
+                        }
+                        break;
+                }
+                inst = GETWORD(val);
+                if (adr > first_adr && inst == last_inst) {
+                        if (!dotted) {
+                                printf(" ...\n");
+                                dotted = 1;
+                        }
+                        continue;
+                }
+                dotted = 0;
+                last_inst = inst;
+                if (praddr)
+                        printf(REG"  %.8x", adr, inst);
+                printf("\t");
+                print_insn_powerpc(inst, adr, 0);       /* always returns 4 */
+                printf("\n");
+        }
+        return adr - first_adr;
+}
+
+void
+print_address(unsigned long addr)
+{
+        xmon_print_symbol(addr, "\t# ", "");
+}
+
+
+/*
+ * Memory operations - move, set, print differences
+ */
+static unsigned long mdest;             /* destination address */
+static unsigned long msrc;              /* source address */
+static unsigned long mval;              /* byte value to set memory to */
+static unsigned long mcount;            /* # bytes to affect */
+static unsigned long mdiffs;            /* max # differences to print */
+
+void
+memops(int cmd)
+{
+        scanhex((void *)&mdest);
+        if( termch != '\n' )
+                termch = 0;
+        scanhex((void *)(cmd == 's'? &mval: &msrc));
+        if( termch != '\n' )
+                termch = 0;
+        scanhex((void *)&mcount);
+        switch( cmd ){
+        case 'm':
+                memmove((void *)mdest, (void *)msrc, mcount);
+                break;
+        case 's':
+                memset((void *)mdest, mval, mcount);
+                break;
+        case 'd':
+                if( termch != '\n' )
+                        termch = 0;
+                scanhex((void *)&mdiffs);
+                memdiffs((unsigned char *)mdest, (unsigned char *)msrc, mcount, mdiffs);
+                break;
+        }
+}
+
+void
+memdiffs(unsigned char *p1, unsigned char *p2, unsigned nb, unsigned maxpr)
+{
+        unsigned n, prt;
+
+        prt = 0;
+        for( n = nb; n > 0; --n )
+                if( *p1++ != *p2++ )
+                        if( ++prt <= maxpr )
+                                printf("%.16x %.2x # %.16x %.2x\n", p1 - 1,
+                                        p1[-1], p2 - 1, p2[-1]);
+        if( prt > maxpr )
+                printf("Total of %d differences\n", prt);
+}
+
+static unsigned mend;
+static unsigned mask;
+
+void
+memlocate(void)
+{
+        unsigned a, n;
+        unsigned char val[4];
+
+        last_cmd = "ml";
+        scanhex((void *)&mdest);
+        if (termch != '\n') {
+                termch = 0;
+                scanhex((void *)&mend);
+                if (termch != '\n') {
+                        termch = 0;
+                        scanhex((void *)&mval);
+                        mask = ~0;
+                        if (termch != '\n') termch = 0;
+                        scanhex((void *)&mask);
+                }
+        }
+        n = 0;
+        for (a = mdest; a < mend; a += 4) {
+                if (mread(a, val, 4) == 4
+                        && ((GETWORD(val) ^ mval) & mask) == 0) {
+                        printf("%.16x:  %.16x\n", a, GETWORD(val));
+                        if (++n >= 10)
+                                break;
+                }
+        }
+}
+
+static unsigned long mskip = 0x1000;
+static unsigned long mlim = 0xffffffff;
+
+void
+memzcan(void)
+{
+        unsigned char v;
+        unsigned a;
+        int ok, ook;
+
+        scanhex(&mdest);
+        if (termch != '\n') termch = 0;
+        scanhex(&mskip);
+        if (termch != '\n') termch = 0;
+        scanhex(&mlim);
+        ook = 0;
+        for (a = mdest; a < mlim; a += mskip) {
+                ok = mread(a, &v, 1);
+                if (ok && !ook) {
+                        printf("%.8x .. ", a);
+                        fflush(stdout);
+                } else if (!ok && ook)
+                        printf("%.8x\n", a - mskip);
+                ook = ok;
+                if (a + mskip < a)
+                        break;
+        }
+        if (ook)
+                printf("%.8x\n", a - mskip);
+}
+
+void proccall(void)
+{
+        unsigned long args[8];
+        unsigned long ret;
+        int i;
+        typedef unsigned long (*callfunc_t)(unsigned long, unsigned long,
+                        unsigned long, unsigned long, unsigned long,
+                        unsigned long, unsigned long, unsigned long);
+        callfunc_t func;
+
+        if (!scanhex(&adrs))
+                return;
+        if (termch != '\n')
+                termch = 0;
+        for (i = 0; i < 8; ++i)
+                args[i] = 0;
+        for (i = 0; i < 8; ++i) {
+                if (!scanhex(&args[i]) || termch == '\n')
+                        break;
+                termch = 0;
+        }
+        func = (callfunc_t) adrs;
+        ret = 0;
+        if (setjmp(bus_error_jmp) == 0) {
+                catch_memory_errors = 1;
+                sync();
+                ret = func(args[0], args[1], args[2], args[3],
+                           args[4], args[5], args[6], args[7]);
+                sync();
+                printf("return value is %x\n", ret);
+        } else {
+                printf("*** %x exception occurred\n", fault_except);
+        }
+        catch_memory_errors = 0;
+}
+
+/* Input scanning routines */
+int
+skipbl(void)
+{
+        int c;
+
+        if( termch != 0 ){
+                c = termch;
+                termch = 0;
+        } else
+                c = inchar();
+        while( c == ' ' || c == '\t' )
+                c = inchar();
+        return c;
+}
+
+#define N_PTREGS        44
+static char *regnames[N_PTREGS] = {
+        "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+        "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
+        "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
+        "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
+        "pc", "msr", "or3", "ctr", "lr", "xer", "ccr",
+#ifdef CONFIG_PPC64
+        "softe",
+#else
+        "mq",
+#endif
+        "trap", "dar", "dsisr", "res"
+};
+
+int
+scanhex(unsigned long *vp)
+{
+        int c, d;
+        unsigned long v;
+
+        c = skipbl();
+        if (c == '%') {
+                /* parse register name */
+                char regname[8];
+                int i;
+
+                for (i = 0; i < sizeof(regname) - 1; ++i) {
+                        c = inchar();
+                        if (!isalnum(c)) {
+                                termch = c;
+                                break;
+                        }
+                        regname[i] = c;
+                }
+                regname[i] = 0;
+                for (i = 0; i < N_PTREGS; ++i) {
+                        if (strcmp(regnames[i], regname) == 0) {
+                                if (xmon_regs == NULL) {
+                                        printf("regs not available\n");
+                                        return 0;
+                                }
+                                *vp = ((unsigned long *)xmon_regs)[i];
+                                return 1;
+                        }
+                }
+                printf("invalid register name '%%%s'\n", regname);
+                return 0;
+        }
+
+        /* skip leading "0x" if any */
+
+        if (c == '0') {
+                c = inchar();
+                if (c == 'x') {
+                        c = inchar();
+                } else {
+                        d = hexdigit(c);
+                        if (d == EOF) {
+                                termch = c;
+                                *vp = 0;
+                                return 1;
+                        }
+                }
+        } else if (c == '$') {
+                int i;
+                for (i=0; i<63; i++) {
+                        c = inchar();
+                        if (isspace(c)) {
+                                termch = c;
+                                break;
+                        }
+                        tmpstr[i] = c;
+                }
+                tmpstr[i++] = 0;
+                *vp = 0;
+                if (setjmp(bus_error_jmp) == 0) {
+                        catch_memory_errors = 1;
+                        sync();
+                        *vp = kallsyms_lookup_name(tmpstr);
+                        sync();
+                }
+                catch_memory_errors = 0;
+                if (!(*vp)) {
+                        printf("unknown symbol '%s'\n", tmpstr);
+                        return 0;
+                }
+                return 1;
+        }
+
+        d = hexdigit(c);
+        if (d == EOF) {
+                termch = c;
+                return 0;
+        }
+        v = 0;
+        do {
+                v = (v << 4) + d;
+                c = inchar();
+                d = hexdigit(c);
+        } while (d != EOF);
+        termch = c;
+        *vp = v;
+        return 1;
+}
+
+void
+scannl(void)
+{
+        int c;
+
+        c = termch;
+        termch = 0;
+        while( c != '\n' )
+                c = inchar();
+}
+
+int hexdigit(int c)
+{
+        if( '0' <= c && c <= '9' )
+                return c - '0';
+        if( 'A' <= c && c <= 'F' )
+                return c - ('A' - 10);
+        if( 'a' <= c && c <= 'f' )
+                return c - ('a' - 10);
+        return EOF;
+}
+
+void
+getstring(char *s, int size)
+{
+        int c;
+
+        c = skipbl();
+        do {
+                if( size > 1 ){
+                        *s++ = c;
+                        --size;
+                }
+                c = inchar();
+        } while( c != ' ' && c != '\t' && c != '\n' );
+        termch = c;
+        *s = 0;
+}
+
+static char line[256];
+static char *lineptr;
+
+void
+flush_input(void)
+{
+        lineptr = NULL;
+}
+
+int
+inchar(void)
+{
+        if (lineptr == NULL || *lineptr == 0) {
+                if (fgets(line, sizeof(line), stdin) == NULL) {
+                        lineptr = NULL;
+                        return EOF;
+                }
+                lineptr = line;
+        }
+        return *lineptr++;
+}
+
+void
+take_input(char *str)
+{
+        lineptr = str;
+}
+
+
+static void
+symbol_lookup(void)
+{
+        int type = inchar();
+        unsigned long addr;
+        static char tmp[64];
+
+        switch (type) {
+        case 'a':
+                if (scanhex(&addr))
+                        xmon_print_symbol(addr, ": ", "\n");
+                termch = 0;
+                break;
+        case 's':
+                getstring(tmp, 64);
+                if (setjmp(bus_error_jmp) == 0) {
+                        catch_memory_errors = 1;
+                        sync();
+                        addr = kallsyms_lookup_name(tmp);
+                        if (addr)
+                                printf("%s: %lx\n", tmp, addr);
+                        else
+                                printf("Symbol '%s' not found.\n", tmp);
+                        sync();
+                }
+                catch_memory_errors = 0;
+                termch = 0;
+                break;
+        }
+}
+
+
+/* Print an address in numeric and symbolic form (if possible) */
+static void xmon_print_symbol(unsigned long address, const char *mid,
+                              const char *after)
+{
+        char *modname;
+        const char *name = NULL;
+        unsigned long offset, size;
+
+        printf(REG, address);
+        if (setjmp(bus_error_jmp) == 0) {
+                catch_memory_errors = 1;
+                sync();
+                name = kallsyms_lookup(address, &size, &offset, &modname,
+                                       tmpstr);
+                sync();
+                /* wait a little while to see if we get a machine check */
+                __delay(200);
+        }
+
+        catch_memory_errors = 0;
+
+        if (name) {
+                printf("%s%s+%#lx/%#lx", mid, name, offset, size);
+                if (modname)
+                        printf(" [%s]", modname);
+        }
+        printf("%s", after);
+}
+
+#ifdef CONFIG_PPC64
+static void dump_slb(void)
+{
+        int i;
+        unsigned long tmp;
+
+        printf("SLB contents of cpu %x\n", smp_processor_id());
+
+        for (i = 0; i < SLB_NUM_ENTRIES; i++) {
+                asm volatile("slbmfee  %0,%1" : "=r" (tmp) : "r" (i));
+                printf("%02d %016lx ", i, tmp);
+
+                asm volatile("slbmfev  %0,%1" : "=r" (tmp) : "r" (i));
+                printf("%016lx\n", tmp);
+        }
+}
+
+static void dump_stab(void)
+{
+        int i;
+        unsigned long *tmp = (unsigned long *)get_paca()->stab_addr;
+
+        printf("Segment table contents of cpu %x\n", smp_processor_id());
+
+        for (i = 0; i < PAGE_SIZE/16; i++) {
+                unsigned long a, b;
+
+                a = *tmp++;
+                b = *tmp++;
+
+                if (a || b) {
+                        printf("%03d %016lx ", i, a);
+                        printf("%016lx\n", b);
+                }
+        }
+}
+
+void dump_segments(void)
+{
+        if (cpu_has_feature(CPU_FTR_SLB))
+                dump_slb();
+        else
+                dump_stab();
+}
+#endif
+
+#ifdef CONFIG_PPC_STD_MMU_32
+void dump_segments(void)
+{
+        int i;
+
+        printf("sr0-15 =");
+        for (i = 0; i < 16; ++i)
+                printf(" %x", mfsrin(i));
+        printf("\n");
+}
+#endif
+
+void xmon_init(int enable)
+{
+        if (enable) {
+                __debugger = xmon;
+                __debugger_ipi = xmon_ipi;
+                __debugger_bpt = xmon_bpt;
+                __debugger_sstep = xmon_sstep;
+                __debugger_iabr_match = xmon_iabr_match;
+                __debugger_dabr_match = xmon_dabr_match;
+                __debugger_fault_handler = xmon_fault_handler;
+        } else {
+                __debugger = NULL;
+                __debugger_ipi = NULL;
+                __debugger_bpt = NULL;
+                __debugger_sstep = NULL;
+                __debugger_iabr_match = NULL;
+                __debugger_dabr_match = NULL;
+                __debugger_fault_handler = NULL;
+        }
+}