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authorWolfgang Grandegger <wg@grandegger.com>2009-03-30 06:02:42 -0400
committerDavid Woodhouse <David.Woodhouse@intel.com>2009-04-06 10:17:09 -0400
commitb6e0e8c07754c8aefd6ff3536463fed5f71405a0 (patch)
tree84233509d5ccf9efea3e92785c101ce3b051eaef /arch/powerpc/sysdev
parentdb99a5523175ba15fef4719c722cea11b94911bb (diff)
[MTD] [NAND] FSL-UPM: add multi chip support
This patch adds support for multi-chip NAND devices to the FSL-UPM driver. This requires support for multiple GPIOs for the RNB pins. The NAND chips are selected through address lines defined by the FDT property "fsl,upm-addr-line-cs-offsets". Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Acked-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'arch/powerpc/sysdev')
-rw-r--r--arch/powerpc/sysdev/fsl_lbc.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/sysdev/fsl_lbc.c b/arch/powerpc/sysdev/fsl_lbc.c
index 0494ee55920f..dceb8d1a843d 100644
--- a/arch/powerpc/sysdev/fsl_lbc.c
+++ b/arch/powerpc/sysdev/fsl_lbc.c
@@ -150,7 +150,7 @@ int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base, u32 mar)
150 150
151 spin_lock_irqsave(&fsl_lbc_lock, flags); 151 spin_lock_irqsave(&fsl_lbc_lock, flags);
152 152
153 out_be32(&fsl_lbc_regs->mar, mar << (32 - upm->width)); 153 out_be32(&fsl_lbc_regs->mar, mar);
154 154
155 switch (upm->width) { 155 switch (upm->width) {
156 case 8: 156 case 8: