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authorThomas Gleixner <tglx@linutronix.de>2011-03-25 11:23:57 -0400
committerThomas Gleixner <tglx@linutronix.de>2011-03-29 08:48:10 -0400
commit1ac06cdadf3f6e9c52cf87304238bffdf4c71566 (patch)
treedab5adc13900cea9ed20c239ff2f6581cb3e0c73 /arch/powerpc/sysdev/uic.c
parent24a3f2e82bc8cf7ed05294008794f842cf170ea2 (diff)
powerpc: uic: Cleanup flow type handling
The core irq_set_type() function updates the flow type when the chip callback returns 0. So setting the type is bogus. The core also updates IRQ_LEVEL. Use irq_data to get the level type information in the chip functions. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/powerpc/sysdev/uic.c')
-rw-r--r--arch/powerpc/sysdev/uic.c27
1 files changed, 10 insertions, 17 deletions
diff --git a/arch/powerpc/sysdev/uic.c b/arch/powerpc/sysdev/uic.c
index a68469ef36d0..02dc40f41bd2 100644
--- a/arch/powerpc/sysdev/uic.c
+++ b/arch/powerpc/sysdev/uic.c
@@ -57,7 +57,6 @@ struct uic {
57 57
58static void uic_unmask_irq(struct irq_data *d) 58static void uic_unmask_irq(struct irq_data *d)
59{ 59{
60 struct irq_desc *desc = irq_to_desc(d->irq);
61 struct uic *uic = irq_data_get_irq_chip_data(d); 60 struct uic *uic = irq_data_get_irq_chip_data(d);
62 unsigned int src = uic_irq_to_hw(d->irq); 61 unsigned int src = uic_irq_to_hw(d->irq);
63 unsigned long flags; 62 unsigned long flags;
@@ -66,7 +65,7 @@ static void uic_unmask_irq(struct irq_data *d)
66 sr = 1 << (31-src); 65 sr = 1 << (31-src);
67 spin_lock_irqsave(&uic->lock, flags); 66 spin_lock_irqsave(&uic->lock, flags);
68 /* ack level-triggered interrupts here */ 67 /* ack level-triggered interrupts here */
69 if (desc->status & IRQ_LEVEL) 68 if (irqd_is_level_type(d))
70 mtdcr(uic->dcrbase + UIC_SR, sr); 69 mtdcr(uic->dcrbase + UIC_SR, sr);
71 er = mfdcr(uic->dcrbase + UIC_ER); 70 er = mfdcr(uic->dcrbase + UIC_ER);
72 er |= sr; 71 er |= sr;
@@ -101,7 +100,6 @@ static void uic_ack_irq(struct irq_data *d)
101 100
102static void uic_mask_ack_irq(struct irq_data *d) 101static void uic_mask_ack_irq(struct irq_data *d)
103{ 102{
104 struct irq_desc *desc = irq_to_desc(d->irq);
105 struct uic *uic = irq_data_get_irq_chip_data(d); 103 struct uic *uic = irq_data_get_irq_chip_data(d);
106 unsigned int src = uic_irq_to_hw(d->irq); 104 unsigned int src = uic_irq_to_hw(d->irq);
107 unsigned long flags; 105 unsigned long flags;
@@ -120,7 +118,7 @@ static void uic_mask_ack_irq(struct irq_data *d)
120 * level interrupts are ack'ed after the actual 118 * level interrupts are ack'ed after the actual
121 * isr call in the uic_unmask_irq() 119 * isr call in the uic_unmask_irq()
122 */ 120 */
123 if (!(desc->status & IRQ_LEVEL)) 121 if (!irqd_is_level_type(d))
124 mtdcr(uic->dcrbase + UIC_SR, sr); 122 mtdcr(uic->dcrbase + UIC_SR, sr);
125 spin_unlock_irqrestore(&uic->lock, flags); 123 spin_unlock_irqrestore(&uic->lock, flags);
126} 124}
@@ -129,7 +127,6 @@ static int uic_set_irq_type(struct irq_data *d, unsigned int flow_type)
129{ 127{
130 struct uic *uic = irq_data_get_irq_chip_data(d); 128 struct uic *uic = irq_data_get_irq_chip_data(d);
131 unsigned int src = uic_irq_to_hw(d->irq); 129 unsigned int src = uic_irq_to_hw(d->irq);
132 struct irq_desc *desc = irq_to_desc(d->irq);
133 unsigned long flags; 130 unsigned long flags;
134 int trigger, polarity; 131 int trigger, polarity;
135 u32 tr, pr, mask; 132 u32 tr, pr, mask;
@@ -166,11 +163,6 @@ static int uic_set_irq_type(struct irq_data *d, unsigned int flow_type)
166 mtdcr(uic->dcrbase + UIC_PR, pr); 163 mtdcr(uic->dcrbase + UIC_PR, pr);
167 mtdcr(uic->dcrbase + UIC_TR, tr); 164 mtdcr(uic->dcrbase + UIC_TR, tr);
168 165
169 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
170 desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
171 if (!trigger)
172 desc->status |= IRQ_LEVEL;
173
174 spin_unlock_irqrestore(&uic->lock, flags); 166 spin_unlock_irqrestore(&uic->lock, flags);
175 167
176 return 0; 168 return 0;
@@ -221,16 +213,17 @@ static struct irq_host_ops uic_host_ops = {
221void uic_irq_cascade(unsigned int virq, struct irq_desc *desc) 213void uic_irq_cascade(unsigned int virq, struct irq_desc *desc)
222{ 214{
223 struct irq_chip *chip = get_irq_desc_chip(desc); 215 struct irq_chip *chip = get_irq_desc_chip(desc);
216 struct irq_data *idata = irq_desc_get_irq_data(desc);
224 struct uic *uic = get_irq_data(virq); 217 struct uic *uic = get_irq_data(virq);
225 u32 msr; 218 u32 msr;
226 int src; 219 int src;
227 int subvirq; 220 int subvirq;
228 221
229 raw_spin_lock(&desc->lock); 222 raw_spin_lock(&desc->lock);
230 if (desc->status & IRQ_LEVEL) 223 if (irqd_is_level_type(idata))
231 chip->irq_mask(&desc->irq_data); 224 chip->irq_mask(idata);
232 else 225 else
233 chip->irq_mask_ack(&desc->irq_data); 226 chip->irq_mask_ack(idata);
234 raw_spin_unlock(&desc->lock); 227 raw_spin_unlock(&desc->lock);
235 228
236 msr = mfdcr(uic->dcrbase + UIC_MSR); 229 msr = mfdcr(uic->dcrbase + UIC_MSR);
@@ -244,10 +237,10 @@ void uic_irq_cascade(unsigned int virq, struct irq_desc *desc)
244 237
245uic_irq_ret: 238uic_irq_ret:
246 raw_spin_lock(&desc->lock); 239 raw_spin_lock(&desc->lock);
247 if (irqd_is_level_type(&desc->irq_data)) 240 if (irqd_is_level_type(idata))
248 chip->irq_ack(&desc->irq_data); 241 chip->irq_ack(idata);
249 if (!(irq_is_disabled(&desc->irq_data) && chip->irq_unmask) 242 if (!irqd_irq_disabled(idata) && chip->irq_unmask)
250 chip->irq_unmask(&desc->irq_data); 243 chip->irq_unmask(idata);
251 raw_spin_unlock(&desc->lock); 244 raw_spin_unlock(&desc->lock);
252} 245}
253 246