Merge branch 'for_paulus' of master.kernel.org:/pub/scm/linux/kernel/git/galak/powerpc

* 'for_paulus' of master.kernel.org:/pub/scm/linux/kernel/git/galak/powerpc: (25 commits)
  [POWERPC] 85xx: Added needed MPC85xx PCI device IDs
  [POWERPC] Add Freescale PCI VENDOR ID and 8641 device IDs
  [POWERPC] 85xxCDS: MPC8548 DTS cleanup.
  [POWERPC] 85xxCDS: Misc 8548 PCI Corrections.
  [POWERPC] 85xxCDS: Delay 8259 cascade hookup.
  [POWERPC] 85xxCDS: Make sure restart resets the PCI bus.
  [POWERPC] 85xxCDS: Allow 8259 cascade to share an MPIC interrupt line.
  [POWERPC] FSL: Add support for PCI-X controllers
  [POWERPC] Make sure virtual P2P bridge registers are setup on PCIe PHB
  [POWERPC] Provide ability to setup P2P bridge registers from struct resource
  [POWERPC] Add basic PCI/PCI Express support for 8544DS board
  [POWERPC] Make endianess of cfg_addr for indirect pci ops runtime
  [POWERPC] Removed setup_indirect_pci_nomap
  [POWERPC] 85xx: Add quirk to ignore bogus FPGA on CDS
  [POWERPC] 85xx: Added 8568 PCIe support
  [POWERPC] Fixup resources on pci_bus for PCIe PHB when no device is connected
  [POWERPC] Add basic PCI node for mpc8568mds board
  [POWERPC] Use Freescale pci/pcie common code for 85xx boards
  [POWERPC] Update PCI nodes in the 83xx/85xx boards device tree
  [POWERPC] Add 8548 CDS PCI express controller node and PCI-X device node
  ...

1 files changed, 88 insertions, 0 deletions

diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
new file mode 100644
index 000000000000..37b04ad26571
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -0,0 +1,88 @@
+/*
+ * MPC85xx/86xx PCI Express structure define
+ *
+ * Copyright 2007 Freescale Semiconductor, Inc
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifdef __KERNEL__
+#ifndef __POWERPC_FSL_PCI_H
+#define __POWERPC_FSL_PCI_H
+
+#define PCIE_LTSSM      0x0404          /* PCIE Link Training and Status */
+#define PCIE_LTSSM_L0   0x16            /* L0 state */
+#define PIWAR_2G        0xa0f5501e      /* Enable, Prefetch, Local Mem, Snoop R/W, 2G */
+
+/* PCI/PCI Express outbound window reg */
+struct pci_outbound_window_regs {
+        __be32  potar;  /* 0x.0 - Outbound translation address register */
+        __be32  potear; /* 0x.4 - Outbound translation extended address register */
+        __be32  powbar; /* 0x.8 - Outbound window base address register */
+        u8      res1[4];
+        __be32  powar;  /* 0x.10 - Outbound window attributes register */
+        u8      res2[12];
+};
+
+/* PCI/PCI Express inbound window reg */
+struct pci_inbound_window_regs {
+        __be32  pitar;  /* 0x.0 - Inbound translation address register */
+        u8      res1[4];
+        __be32  piwbar; /* 0x.8 - Inbound window base address register */
+        __be32  piwbear;        /* 0x.c - Inbound window base extended address register */
+        __be32  piwar;  /* 0x.10 - Inbound window attributes register */
+        u8      res2[12];
+};
+
+/* PCI/PCI Express IO block registers for 85xx/86xx */
+struct ccsr_pci {
+        __be32  config_addr;            /* 0x.000 - PCI/PCIE Configuration Address Register */
+        __be32  config_data;            /* 0x.004 - PCI/PCIE Configuration Data Register */
+        __be32  int_ack;                /* 0x.008 - PCI Interrupt Acknowledge Register */
+        __be32  pex_otb_cpl_tor;        /* 0x.00c - PCIE Outbound completion timeout register */
+        __be32  pex_conf_tor;           /* 0x.010 - PCIE configuration timeout register */
+        u8      res2[12];
+        __be32  pex_pme_mes_dr;         /* 0x.020 - PCIE PME and message detect register */
+        __be32  pex_pme_mes_disr;       /* 0x.024 - PCIE PME and message disable register */
+        __be32  pex_pme_mes_ier;        /* 0x.028 - PCIE PME and message interrupt enable register */
+        __be32  pex_pmcr;               /* 0x.02c - PCIE power management command register */
+        u8      res3[3024];
+
+/* PCI/PCI Express outbound window 0-4
+ * Window 0 is the default window and is the only window enabled upon reset.
+ * The default outbound register set is used when a transaction misses
+ * in all of the other outbound windows.
+ */
+        struct pci_outbound_window_regs pow[5];
+
+        u8      res14[256];
+
+/* PCI/PCI Express inbound window 3-1
+ * inbound window 1 supports only a 32-bit base address and does not
+ * define an inbound window base extended address register.
+ */
+        struct pci_inbound_window_regs piw[3];
+
+        __be32  pex_err_dr;             /* 0x.e00 - PCI/PCIE error detect register */
+        u8      res21[4];
+        __be32  pex_err_en;             /* 0x.e08 - PCI/PCIE error interrupt enable register */
+        u8      res22[4];
+        __be32  pex_err_disr;           /* 0x.e10 - PCI/PCIE error disable register */
+        u8      res23[12];
+        __be32  pex_err_cap_stat;       /* 0x.e20 - PCI/PCIE error capture status register */
+        u8      res24[4];
+        __be32  pex_err_cap_r0;         /* 0x.e28 - PCIE error capture register 0 */
+        __be32  pex_err_cap_r1;         /* 0x.e2c - PCIE error capture register 0 */
+        __be32  pex_err_cap_r2;         /* 0x.e30 - PCIE error capture register 0 */
+        __be32  pex_err_cap_r3;         /* 0x.e34 - PCIE error capture register 0 */
+};
+
+extern int fsl_add_bridge(struct device_node *dev, int is_primary);
+extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
+
+#endif /* __POWERPC_FSL_PCI_H */
+#endif /* __KERNEL__ */