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authorLinus Torvalds <torvalds@linux-foundation.org>2015-04-16 14:53:32 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2015-04-16 14:53:32 -0400
commitd19d5efd8c8840aa4f38a6dfbfe500d8cc27de46 (patch)
tree2e2f4f57de790c7de2ccd6d1afbec8695b2c7a46 /arch/powerpc/platforms
parent34c9a0ffc75ad25b6a60f61e27c4a4b1189b8085 (diff)
parent2fe0753d49402aee325cc39c476b46fd51a8afec (diff)
Merge tag 'powerpc-4.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mpe/linux
Pull powerpc updates from Michael Ellerman: - Numerous minor fixes, cleanups etc. - More EEH work from Gavin to remove its dependency on device_nodes. - Memory hotplug implemented entirely in the kernel from Nathan Fontenot. - Removal of redundant CONFIG_PPC_OF by Kevin Hao. - Rewrite of VPHN parsing logic & tests from Greg Kurz. - A fix from Nish Aravamudan to reduce memory usage by clamping nodes_possible_map. - Support for pstore on powernv from Hari Bathini. - Removal of old powerpc specific byte swap routines by David Gibson. - Fix from Vasant Hegde to prevent the flash driver telling you it was flashing your firmware when it wasn't. - Patch from Ben Herrenschmidt to add an OPAL heartbeat driver. - Fix for an oops causing get/put_cpu_var() imbalance in perf by Jan Stancek. - Some fixes for migration from Tyrel Datwyler. - A new syscall to switch the cpu endian by Michael Ellerman. - Large series from Wei Yang to implement SRIOV, reviewed and acked by Bjorn. - A fix for the OPAL sensor driver from Cédric Le Goater. - Fixes to get STRICT_MM_TYPECHECKS building again by Michael Ellerman. - Large series from Daniel Axtens to make our PCI hooks per PHB rather than per machine. - Small patch from Sam Bobroff to explicitly abort non-suspended transactions on syscalls, plus a test to exercise it. - Numerous reworks and fixes for the 24x7 PMU from Sukadev Bhattiprolu. - Small patch to enable the hard lockup detector from Anton Blanchard. - Fix from Dave Olson for missing L2 cache information on some CPUs. - Some fixes from Michael Ellerman to get Cell machines booting again. - Freescale updates from Scott: Highlights include BMan device tree nodes, an MSI erratum workaround, a couple minor performance improvements, config updates, and misc fixes/cleanup. * tag 'powerpc-4.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mpe/linux: (196 commits) powerpc/powermac: Fix build error seen with powermac smp builds powerpc/pseries: Fix compile of memory hotplug without CONFIG_MEMORY_HOTREMOVE powerpc: Remove PPC32 code from pseries specific find_and_init_phbs() powerpc/cell: Fix iommu breakage caused by controller_ops change powerpc/eeh: Fix crash in eeh_add_device_early() on Cell powerpc/perf: Cap 64bit userspace backtraces to PERF_MAX_STACK_DEPTH powerpc/perf/hv-24x7: Fail 24x7 initcall if create_events_from_catalog() fails powerpc/pseries: Correct memory hotplug locking powerpc: Fix missing L2 cache size in /sys/devices/system/cpu powerpc: Add ppc64 hard lockup detector support oprofile: Disable oprofile NMI timer on ppc64 powerpc/perf/hv-24x7: Add missing put_cpu_var() powerpc/perf/hv-24x7: Break up single_24x7_request powerpc/perf/hv-24x7: Define update_event_count() powerpc/perf/hv-24x7: Whitespace cleanup powerpc/perf/hv-24x7: Define add_event_to_24x7_request() powerpc/perf/hv-24x7: Rename hv_24x7_event_update powerpc/perf/hv-24x7: Move debug prints to separate function powerpc/perf/hv-24x7: Drop event_24x7_request() powerpc/perf/hv-24x7: Use pr_devel() to log message ... Conflicts: tools/testing/selftests/powerpc/Makefile tools/testing/selftests/powerpc/tm/Makefile
Diffstat (limited to 'arch/powerpc/platforms')
-rw-r--r--arch/powerpc/platforms/85xx/common.c1
-rw-r--r--arch/powerpc/platforms/85xx/corenet_generic.c12
-rw-r--r--arch/powerpc/platforms/85xx/smp.c4
-rw-r--r--arch/powerpc/platforms/Kconfig5
-rw-r--r--arch/powerpc/platforms/Kconfig.cputype3
-rw-r--r--arch/powerpc/platforms/cell/Kconfig11
-rw-r--r--arch/powerpc/platforms/cell/Makefile15
-rw-r--r--arch/powerpc/platforms/cell/beat.c264
-rw-r--r--arch/powerpc/platforms/cell/beat.h39
-rw-r--r--arch/powerpc/platforms/cell/beat_htab.c445
-rw-r--r--arch/powerpc/platforms/cell/beat_hvCall.S285
-rw-r--r--arch/powerpc/platforms/cell/beat_interrupt.c253
-rw-r--r--arch/powerpc/platforms/cell/beat_interrupt.h30
-rw-r--r--arch/powerpc/platforms/cell/beat_iommu.c115
-rw-r--r--arch/powerpc/platforms/cell/beat_spu_priv1.c205
-rw-r--r--arch/powerpc/platforms/cell/beat_syscall.h164
-rw-r--r--arch/powerpc/platforms/cell/beat_udbg.c98
-rw-r--r--arch/powerpc/platforms/cell/beat_wrapper.h290
-rw-r--r--arch/powerpc/platforms/cell/cell.h24
-rw-r--r--arch/powerpc/platforms/cell/celleb_pci.c500
-rw-r--r--arch/powerpc/platforms/cell/celleb_pci.h46
-rw-r--r--arch/powerpc/platforms/cell/celleb_scc.h232
-rw-r--r--arch/powerpc/platforms/cell/celleb_scc_epci.c428
-rw-r--r--arch/powerpc/platforms/cell/celleb_scc_pciex.c538
-rw-r--r--arch/powerpc/platforms/cell/celleb_scc_sio.c99
-rw-r--r--arch/powerpc/platforms/cell/celleb_scc_uhc.c95
-rw-r--r--arch/powerpc/platforms/cell/celleb_setup.c243
-rw-r--r--arch/powerpc/platforms/cell/interrupt.c2
-rw-r--r--arch/powerpc/platforms/cell/iommu.c11
-rw-r--r--arch/powerpc/platforms/cell/setup.c5
-rw-r--r--arch/powerpc/platforms/cell/smp.c9
-rw-r--r--arch/powerpc/platforms/cell/spu_callbacks.c1
-rw-r--r--arch/powerpc/platforms/chrp/setup.c2
-rw-r--r--arch/powerpc/platforms/maple/maple.h2
-rw-r--r--arch/powerpc/platforms/maple/pci.c4
-rw-r--r--arch/powerpc/platforms/maple/setup.c2
-rw-r--r--arch/powerpc/platforms/pasemi/iommu.c6
-rw-r--r--arch/powerpc/platforms/pasemi/pasemi.h1
-rw-r--r--arch/powerpc/platforms/pasemi/pci.c5
-rw-r--r--arch/powerpc/platforms/powermac/bootx_init.c2
-rw-r--r--arch/powerpc/platforms/powermac/pci.c38
-rw-r--r--arch/powerpc/platforms/powermac/pic.c3
-rw-r--r--arch/powerpc/platforms/powermac/pmac.h3
-rw-r--r--arch/powerpc/platforms/powermac/setup.c22
-rw-r--r--arch/powerpc/platforms/powermac/smp.c18
-rw-r--r--arch/powerpc/platforms/powernv/Kconfig7
-rw-r--r--arch/powerpc/platforms/powernv/Makefile2
-rw-r--r--arch/powerpc/platforms/powernv/eeh-ioda.c1149
-rw-r--r--arch/powerpc/platforms/powernv/eeh-powernv.c1300
-rw-r--r--arch/powerpc/platforms/powernv/opal-dump.c3
-rw-r--r--arch/powerpc/platforms/powernv/opal-elog.c3
-rw-r--r--arch/powerpc/platforms/powernv/opal-flash.c8
-rw-r--r--arch/powerpc/platforms/powernv/opal-nvram.c10
-rw-r--r--arch/powerpc/platforms/powernv/opal-sensor.c30
-rw-r--r--arch/powerpc/platforms/powernv/opal-wrappers.S5
-rw-r--r--arch/powerpc/platforms/powernv/opal.c92
-rw-r--r--arch/powerpc/platforms/powernv/pci-ioda.c797
-rw-r--r--arch/powerpc/platforms/powernv/pci-p5ioc2.c1
-rw-r--r--arch/powerpc/platforms/powernv/pci.c190
-rw-r--r--arch/powerpc/platforms/powernv/pci.h38
-rw-r--r--arch/powerpc/platforms/powernv/powernv.h2
-rw-r--r--arch/powerpc/platforms/powernv/setup.c54
-rw-r--r--arch/powerpc/platforms/powernv/smp.c13
-rw-r--r--arch/powerpc/platforms/ps3/smp.c4
-rw-r--r--arch/powerpc/platforms/pseries/Kconfig1
-rw-r--r--arch/powerpc/platforms/pseries/dlpar.c118
-rw-r--r--arch/powerpc/platforms/pseries/eeh_pseries.c98
-rw-r--r--arch/powerpc/platforms/pseries/hotplug-memory.c489
-rw-r--r--arch/powerpc/platforms/pseries/iommu.c9
-rw-r--r--arch/powerpc/platforms/pseries/mobility.c26
-rw-r--r--arch/powerpc/platforms/pseries/msi.c6
-rw-r--r--arch/powerpc/platforms/pseries/nvram.c674
-rw-r--r--arch/powerpc/platforms/pseries/pci_dlpar.c5
-rw-r--r--arch/powerpc/platforms/pseries/pseries.h14
-rw-r--r--arch/powerpc/platforms/pseries/setup.c48
-rw-r--r--arch/powerpc/platforms/pseries/smp.c6
76 files changed, 3000 insertions, 6782 deletions
diff --git a/arch/powerpc/platforms/85xx/common.c b/arch/powerpc/platforms/85xx/common.c
index 4a9ad871a168..7bfb9b184dd4 100644
--- a/arch/powerpc/platforms/85xx/common.c
+++ b/arch/powerpc/platforms/85xx/common.c
@@ -40,6 +40,7 @@ static const struct of_device_id mpc85xx_common_ids[] __initconst = {
40 { .compatible = "fsl,qoriq-pcie-v2.4", }, 40 { .compatible = "fsl,qoriq-pcie-v2.4", },
41 { .compatible = "fsl,qoriq-pcie-v2.3", }, 41 { .compatible = "fsl,qoriq-pcie-v2.3", },
42 { .compatible = "fsl,qoriq-pcie-v2.2", }, 42 { .compatible = "fsl,qoriq-pcie-v2.2", },
43 { .compatible = "fsl,fman", },
43 {}, 44 {},
44}; 45};
45 46
diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c b/arch/powerpc/platforms/85xx/corenet_generic.c
index 1f309ccb096e..9824d2cf79bd 100644
--- a/arch/powerpc/platforms/85xx/corenet_generic.c
+++ b/arch/powerpc/platforms/85xx/corenet_generic.c
@@ -88,6 +88,15 @@ static const struct of_device_id of_device_ids[] = {
88 .compatible = "simple-bus" 88 .compatible = "simple-bus"
89 }, 89 },
90 { 90 {
91 .compatible = "mdio-mux-gpio"
92 },
93 {
94 .compatible = "fsl,fpga-ngpixis"
95 },
96 {
97 .compatible = "fsl,fpga-qixis"
98 },
99 {
91 .compatible = "fsl,srio", 100 .compatible = "fsl,srio",
92 }, 101 },
93 { 102 {
@@ -108,6 +117,9 @@ static const struct of_device_id of_device_ids[] = {
108 { 117 {
109 .compatible = "fsl,qe", 118 .compatible = "fsl,qe",
110 }, 119 },
120 {
121 .compatible = "fsl,fman",
122 },
111 /* The following two are for the Freescale hypervisor */ 123 /* The following two are for the Freescale hypervisor */
112 { 124 {
113 .name = "hypervisor", 125 .name = "hypervisor",
diff --git a/arch/powerpc/platforms/85xx/smp.c b/arch/powerpc/platforms/85xx/smp.c
index d7c1e69f3070..8631ac5f0e57 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -360,10 +360,10 @@ static void mpc85xx_smp_kexec_down(void *arg)
360static void map_and_flush(unsigned long paddr) 360static void map_and_flush(unsigned long paddr)
361{ 361{
362 struct page *page = pfn_to_page(paddr >> PAGE_SHIFT); 362 struct page *page = pfn_to_page(paddr >> PAGE_SHIFT);
363 unsigned long kaddr = (unsigned long)kmap(page); 363 unsigned long kaddr = (unsigned long)kmap_atomic(page);
364 364
365 flush_dcache_range(kaddr, kaddr + PAGE_SIZE); 365 flush_dcache_range(kaddr, kaddr + PAGE_SIZE);
366 kunmap(page); 366 kunmap_atomic((void *)kaddr);
367} 367}
368 368
369/** 369/**
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index 391b3f6b54a3..b7f9c408bf24 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -72,11 +72,6 @@ config PPC_SMP_MUXED_IPI
72 cpu. This will enable the generic code to multiplex the 4 72 cpu. This will enable the generic code to multiplex the 4
73 messages on to one ipi. 73 messages on to one ipi.
74 74
75config PPC_UDBG_BEAT
76 bool "BEAT based debug console"
77 depends on PPC_CELLEB
78 default n
79
80config IPIC 75config IPIC
81 bool 76 bool
82 default n 77 default n
diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
index 76483e3acd60..7264e91190be 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++ b/arch/powerpc/platforms/Kconfig.cputype
@@ -2,6 +2,7 @@ config PPC64
2 bool "64-bit kernel" 2 bool "64-bit kernel"
3 default n 3 default n
4 select HAVE_VIRT_CPU_ACCOUNTING 4 select HAVE_VIRT_CPU_ACCOUNTING
5 select ZLIB_DEFLATE
5 help 6 help
6 This option selects whether a 32-bit or a 64-bit kernel 7 This option selects whether a 32-bit or a 64-bit kernel
7 will be built. 8 will be built.
@@ -15,7 +16,7 @@ choice
15 The most common ones are the desktop and server CPUs (601, 603, 16 The most common ones are the desktop and server CPUs (601, 603,
16 604, 740, 750, 74xx) CPUs from Freescale and IBM, with their 17 604, 740, 750, 74xx) CPUs from Freescale and IBM, with their
17 embedded 512x/52xx/82xx/83xx/86xx counterparts. 18 embedded 512x/52xx/82xx/83xx/86xx counterparts.
18 The other embeeded parts, namely 4xx, 8xx, e200 (55xx) and e500 19 The other embedded parts, namely 4xx, 8xx, e200 (55xx) and e500
19 (85xx) each form a family of their own that is not compatible 20 (85xx) each form a family of their own that is not compatible
20 with the others. 21 with the others.
21 22
diff --git a/arch/powerpc/platforms/cell/Kconfig b/arch/powerpc/platforms/cell/Kconfig
index 870b6dbd4d18..2f23133ab3d1 100644
--- a/arch/powerpc/platforms/cell/Kconfig
+++ b/arch/powerpc/platforms/cell/Kconfig
@@ -33,17 +33,6 @@ config PPC_IBM_CELL_BLADE
33 select PPC_UDBG_16550 33 select PPC_UDBG_16550
34 select UDBG_RTAS_CONSOLE 34 select UDBG_RTAS_CONSOLE
35 35
36config PPC_CELLEB
37 bool "Toshiba's Cell Reference Set 'Celleb' Architecture"
38 depends on PPC64 && PPC_BOOK3S
39 select PPC_CELL_NATIVE
40 select PPC_OF_PLATFORM_PCI
41 select PCI
42 select HAS_TXX9_SERIAL
43 select PPC_UDBG_BEAT
44 select USB_OHCI_BIG_ENDIAN_MMIO
45 select USB_EHCI_BIG_ENDIAN_MMIO
46
47config PPC_CELL_QPACE 36config PPC_CELL_QPACE
48 bool "IBM Cell - QPACE" 37 bool "IBM Cell - QPACE"
49 depends on PPC64 && PPC_BOOK3S 38 depends on PPC64 && PPC_BOOK3S
diff --git a/arch/powerpc/platforms/cell/Makefile b/arch/powerpc/platforms/cell/Makefile
index 2d16884f67b9..34699bddfddd 100644
--- a/arch/powerpc/platforms/cell/Makefile
+++ b/arch/powerpc/platforms/cell/Makefile
@@ -29,18 +29,3 @@ obj-$(CONFIG_AXON_MSI) += axon_msi.o
29 29
30# qpace setup 30# qpace setup
31obj-$(CONFIG_PPC_CELL_QPACE) += qpace_setup.o 31obj-$(CONFIG_PPC_CELL_QPACE) += qpace_setup.o
32
33# celleb stuff
34ifeq ($(CONFIG_PPC_CELLEB),y)
35obj-y += celleb_setup.o \
36 celleb_pci.o celleb_scc_epci.o \
37 celleb_scc_pciex.o \
38 celleb_scc_uhc.o \
39 spider-pci.o beat.o beat_htab.o \
40 beat_hvCall.o beat_interrupt.o \
41 beat_iommu.o
42
43obj-$(CONFIG_PPC_UDBG_BEAT) += beat_udbg.o
44obj-$(CONFIG_SERIAL_TXX9) += celleb_scc_sio.o
45obj-$(CONFIG_SPU_BASE) += beat_spu_priv1.o
46endif
diff --git a/arch/powerpc/platforms/cell/beat.c b/arch/powerpc/platforms/cell/beat.c
deleted file mode 100644
index affcf566d460..000000000000
--- a/arch/powerpc/platforms/cell/beat.c
+++ /dev/null
@@ -1,264 +0,0 @@
1/*
2 * Simple routines for Celleb/Beat
3 *
4 * (C) Copyright 2006-2007 TOSHIBA CORPORATION
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <linux/export.h>
22#include <linux/init.h>
23#include <linux/err.h>
24#include <linux/rtc.h>
25#include <linux/interrupt.h>
26#include <linux/irqreturn.h>
27#include <linux/reboot.h>
28
29#include <asm/hvconsole.h>
30#include <asm/time.h>
31#include <asm/machdep.h>
32#include <asm/firmware.h>
33
34#include "beat_wrapper.h"
35#include "beat.h"
36#include "beat_interrupt.h"
37
38static int beat_pm_poweroff_flag;
39
40void beat_restart(char *cmd)
41{
42 beat_shutdown_logical_partition(!beat_pm_poweroff_flag);
43}
44
45void beat_power_off(void)
46{
47 beat_shutdown_logical_partition(0);
48}
49
50u64 beat_halt_code = 0x1000000000000000UL;
51EXPORT_SYMBOL(beat_halt_code);
52
53void beat_halt(void)
54{
55 beat_shutdown_logical_partition(beat_halt_code);
56}
57
58int beat_set_rtc_time(struct rtc_time *rtc_time)
59{
60 u64 tim;
61 tim = mktime(rtc_time->tm_year+1900,
62 rtc_time->tm_mon+1, rtc_time->tm_mday,
63 rtc_time->tm_hour, rtc_time->tm_min, rtc_time->tm_sec);
64 if (beat_rtc_write(tim))
65 return -1;
66 return 0;
67}
68
69void beat_get_rtc_time(struct rtc_time *rtc_time)
70{
71 u64 tim;
72
73 if (beat_rtc_read(&tim))
74 tim = 0;
75 to_tm(tim, rtc_time);
76 rtc_time->tm_year -= 1900;
77 rtc_time->tm_mon -= 1;
78}
79
80#define BEAT_NVRAM_SIZE 4096
81
82ssize_t beat_nvram_read(char *buf, size_t count, loff_t *index)
83{
84 unsigned int i;
85 unsigned long len;
86 char *p = buf;
87
88 if (*index >= BEAT_NVRAM_SIZE)
89 return -ENODEV;
90 i = *index;
91 if (i + count > BEAT_NVRAM_SIZE)
92 count = BEAT_NVRAM_SIZE - i;
93
94 for (; count != 0; count -= len) {
95 len = count;
96 if (len > BEAT_NVRW_CNT)
97 len = BEAT_NVRW_CNT;
98 if (beat_eeprom_read(i, len, p))
99 return -EIO;
100
101 p += len;
102 i += len;
103 }
104 *index = i;
105 return p - buf;
106}
107
108ssize_t beat_nvram_write(char *buf, size_t count, loff_t *index)
109{
110 unsigned int i;
111 unsigned long len;
112 char *p = buf;
113
114 if (*index >= BEAT_NVRAM_SIZE)
115 return -ENODEV;
116 i = *index;
117 if (i + count > BEAT_NVRAM_SIZE)
118 count = BEAT_NVRAM_SIZE - i;
119
120 for (; count != 0; count -= len) {
121 len = count;
122 if (len > BEAT_NVRW_CNT)
123 len = BEAT_NVRW_CNT;
124 if (beat_eeprom_write(i, len, p))
125 return -EIO;
126
127 p += len;
128 i += len;
129 }
130 *index = i;
131 return p - buf;
132}
133
134ssize_t beat_nvram_get_size(void)
135{
136 return BEAT_NVRAM_SIZE;
137}
138
139int beat_set_xdabr(unsigned long dabr, unsigned long dabrx)
140{
141 if (beat_set_dabr(dabr, dabrx))
142 return -1;
143 return 0;
144}
145
146int64_t beat_get_term_char(u64 vterm, u64 *len, u64 *t1, u64 *t2)
147{
148 u64 db[2];
149 s64 ret;
150
151 ret = beat_get_characters_from_console(vterm, len, (u8 *)db);
152 if (ret == 0) {
153 *t1 = db[0];
154 *t2 = db[1];
155 }
156 return ret;
157}
158EXPORT_SYMBOL(beat_get_term_char);
159
160int64_t beat_put_term_char(u64 vterm, u64 len, u64 t1, u64 t2)
161{
162 u64 db[2];
163
164 db[0] = t1;
165 db[1] = t2;
166 return beat_put_characters_to_console(vterm, len, (u8 *)db);
167}
168EXPORT_SYMBOL(beat_put_term_char);
169
170void beat_power_save(void)
171{
172 beat_pause(0);
173}
174
175#ifdef CONFIG_KEXEC
176void beat_kexec_cpu_down(int crash, int secondary)
177{
178 beatic_deinit_IRQ();
179}
180#endif
181
182static irqreturn_t beat_power_event(int virq, void *arg)
183{
184 printk(KERN_DEBUG "Beat: power button pressed\n");
185 beat_pm_poweroff_flag = 1;
186 ctrl_alt_del();
187 return IRQ_HANDLED;
188}
189
190static irqreturn_t beat_reset_event(int virq, void *arg)
191{
192 printk(KERN_DEBUG "Beat: reset button pressed\n");
193 beat_pm_poweroff_flag = 0;
194 ctrl_alt_del();
195 return IRQ_HANDLED;
196}
197
198static struct beat_event_list {
199 const char *typecode;
200 irq_handler_t handler;
201 unsigned int virq;
202} beat_event_list[] = {
203 { "power", beat_power_event, 0 },
204 { "reset", beat_reset_event, 0 },
205};
206
207static int __init beat_register_event(void)
208{
209 u64 path[4], data[2];
210 int rc, i;
211 unsigned int virq;
212
213 for (i = 0; i < ARRAY_SIZE(beat_event_list); i++) {
214 struct beat_event_list *ev = &beat_event_list[i];
215
216 if (beat_construct_event_receive_port(data) != 0) {
217 printk(KERN_ERR "Beat: "
218 "cannot construct event receive port for %s\n",
219 ev->typecode);
220 return -EINVAL;
221 }
222
223 virq = irq_create_mapping(NULL, data[0]);
224 if (virq == NO_IRQ) {
225 printk(KERN_ERR "Beat: failed to get virtual IRQ"
226 " for event receive port for %s\n",
227 ev->typecode);
228 beat_destruct_event_receive_port(data[0]);
229 return -EIO;
230 }
231 ev->virq = virq;
232
233 rc = request_irq(virq, ev->handler, 0,
234 ev->typecode, NULL);
235 if (rc != 0) {
236 printk(KERN_ERR "Beat: failed to request virtual IRQ"
237 " for event receive port for %s\n",
238 ev->typecode);
239 beat_destruct_event_receive_port(data[0]);
240 return rc;
241 }
242
243 path[0] = 0x1000000065780000ul; /* 1,ex */
244 path[1] = 0x627574746f6e0000ul; /* button */
245 path[2] = 0;
246 strncpy((char *)&path[2], ev->typecode, 8);
247 path[3] = 0;
248 data[1] = 0;
249
250 beat_create_repository_node(path, data);
251 }
252 return 0;
253}
254
255static int __init beat_event_init(void)
256{
257 if (!firmware_has_feature(FW_FEATURE_BEAT))
258 return -EINVAL;
259
260 beat_pm_poweroff_flag = 0;
261 return beat_register_event();
262}
263
264device_initcall(beat_event_init);
diff --git a/arch/powerpc/platforms/cell/beat.h b/arch/powerpc/platforms/cell/beat.h
deleted file mode 100644
index bfcb8e351ae5..000000000000
--- a/arch/powerpc/platforms/cell/beat.h
+++ /dev/null
@@ -1,39 +0,0 @@
1/*
2 * Guest OS Interfaces.
3 *
4 * (C) Copyright 2006 TOSHIBA CORPORATION
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#ifndef _CELLEB_BEAT_H
22#define _CELLEB_BEAT_H
23
24int64_t beat_get_term_char(uint64_t, uint64_t *, uint64_t *, uint64_t *);
25int64_t beat_put_term_char(uint64_t, uint64_t, uint64_t, uint64_t);
26int64_t beat_repository_encode(int, const char *, uint64_t[4]);
27void beat_restart(char *);
28void beat_power_off(void);
29void beat_halt(void);
30int beat_set_rtc_time(struct rtc_time *);
31void beat_get_rtc_time(struct rtc_time *);
32ssize_t beat_nvram_get_size(void);
33ssize_t beat_nvram_read(char *, size_t, loff_t *);
34ssize_t beat_nvram_write(char *, size_t, loff_t *);
35int beat_set_xdabr(unsigned long, unsigned long);
36void beat_power_save(void);
37void beat_kexec_cpu_down(int, int);
38
39#endif /* _CELLEB_BEAT_H */
diff --git a/arch/powerpc/platforms/cell/beat_htab.c b/arch/powerpc/platforms/cell/beat_htab.c
deleted file mode 100644
index bee9232fe619..000000000000
--- a/arch/powerpc/platforms/cell/beat_htab.c
+++ /dev/null
@@ -1,445 +0,0 @@
1/*
2 * "Cell Reference Set" HTAB support.
3 *
4 * (C) Copyright 2006-2007 TOSHIBA CORPORATION
5 *
6 * This code is based on arch/powerpc/platforms/pseries/lpar.c:
7 * Copyright (C) 2001 Todd Inglett, IBM Corporation
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
22 */
23
24#undef DEBUG_LOW
25
26#include <linux/kernel.h>
27#include <linux/spinlock.h>
28
29#include <asm/mmu.h>
30#include <asm/page.h>
31#include <asm/pgtable.h>
32#include <asm/machdep.h>
33#include <asm/udbg.h>
34
35#include "beat_wrapper.h"
36
37#ifdef DEBUG_LOW
38#define DBG_LOW(fmt...) do { udbg_printf(fmt); } while (0)
39#else
40#define DBG_LOW(fmt...) do { } while (0)
41#endif
42
43static DEFINE_RAW_SPINLOCK(beat_htab_lock);
44
45static inline unsigned int beat_read_mask(unsigned hpte_group)
46{
47 unsigned long rmask = 0;
48 u64 hpte_v[5];
49
50 beat_read_htab_entries(0, hpte_group + 0, hpte_v);
51 if (!(hpte_v[0] & HPTE_V_BOLTED))
52 rmask |= 0x8000;
53 if (!(hpte_v[1] & HPTE_V_BOLTED))
54 rmask |= 0x4000;
55 if (!(hpte_v[2] & HPTE_V_BOLTED))
56 rmask |= 0x2000;
57 if (!(hpte_v[3] & HPTE_V_BOLTED))
58 rmask |= 0x1000;
59 beat_read_htab_entries(0, hpte_group + 4, hpte_v);
60 if (!(hpte_v[0] & HPTE_V_BOLTED))
61 rmask |= 0x0800;
62 if (!(hpte_v[1] & HPTE_V_BOLTED))
63 rmask |= 0x0400;
64 if (!(hpte_v[2] & HPTE_V_BOLTED))
65 rmask |= 0x0200;
66 if (!(hpte_v[3] & HPTE_V_BOLTED))
67 rmask |= 0x0100;
68 hpte_group = ~hpte_group & (htab_hash_mask * HPTES_PER_GROUP);
69 beat_read_htab_entries(0, hpte_group + 0, hpte_v);
70 if (!(hpte_v[0] & HPTE_V_BOLTED))
71 rmask |= 0x80;
72 if (!(hpte_v[1] & HPTE_V_BOLTED))
73 rmask |= 0x40;
74 if (!(hpte_v[2] & HPTE_V_BOLTED))
75 rmask |= 0x20;
76 if (!(hpte_v[3] & HPTE_V_BOLTED))
77 rmask |= 0x10;
78 beat_read_htab_entries(0, hpte_group + 4, hpte_v);
79 if (!(hpte_v[0] & HPTE_V_BOLTED))
80 rmask |= 0x08;
81 if (!(hpte_v[1] & HPTE_V_BOLTED))
82 rmask |= 0x04;
83 if (!(hpte_v[2] & HPTE_V_BOLTED))
84 rmask |= 0x02;
85 if (!(hpte_v[3] & HPTE_V_BOLTED))
86 rmask |= 0x01;
87 return rmask;
88}
89
90static long beat_lpar_hpte_insert(unsigned long hpte_group,
91 unsigned long vpn, unsigned long pa,
92 unsigned long rflags, unsigned long vflags,
93 int psize, int apsize, int ssize)
94{
95 unsigned long lpar_rc;
96 u64 hpte_v, hpte_r, slot;
97
98 if (vflags & HPTE_V_SECONDARY)
99 return -1;
100
101 if (!(vflags & HPTE_V_BOLTED))
102 DBG_LOW("hpte_insert(group=%lx, va=%016lx, pa=%016lx, "
103 "rflags=%lx, vflags=%lx, psize=%d)\n",
104 hpte_group, va, pa, rflags, vflags, psize);
105
106 hpte_v = hpte_encode_v(vpn, psize, apsize, MMU_SEGSIZE_256M) |
107 vflags | HPTE_V_VALID;
108 hpte_r = hpte_encode_r(pa, psize, apsize) | rflags;
109
110 if (!(vflags & HPTE_V_BOLTED))
111 DBG_LOW(" hpte_v=%016lx, hpte_r=%016lx\n", hpte_v, hpte_r);
112
113 if (rflags & _PAGE_NO_CACHE)
114 hpte_r &= ~HPTE_R_M;
115
116 raw_spin_lock(&beat_htab_lock);
117 lpar_rc = beat_read_mask(hpte_group);
118 if (lpar_rc == 0) {
119 if (!(vflags & HPTE_V_BOLTED))
120 DBG_LOW(" full\n");
121 raw_spin_unlock(&beat_htab_lock);
122 return -1;
123 }
124
125 lpar_rc = beat_insert_htab_entry(0, hpte_group, lpar_rc << 48,
126 hpte_v, hpte_r, &slot);
127 raw_spin_unlock(&beat_htab_lock);
128
129 /*
130 * Since we try and ioremap PHBs we don't own, the pte insert
131 * will fail. However we must catch the failure in hash_page
132 * or we will loop forever, so return -2 in this case.
133 */
134 if (unlikely(lpar_rc != 0)) {
135 if (!(vflags & HPTE_V_BOLTED))
136 DBG_LOW(" lpar err %lx\n", lpar_rc);
137 return -2;
138 }
139 if (!(vflags & HPTE_V_BOLTED))
140 DBG_LOW(" -> slot: %lx\n", slot);
141
142 /* We have to pass down the secondary bucket bit here as well */
143 return (slot ^ hpte_group) & 15;
144}
145
146static long beat_lpar_hpte_remove(unsigned long hpte_group)
147{
148 DBG_LOW("hpte_remove(group=%lx)\n", hpte_group);
149 return -1;
150}
151
152static unsigned long beat_lpar_hpte_getword0(unsigned long slot)
153{
154 unsigned long dword0;
155 unsigned long lpar_rc;
156 u64 dword[5];
157
158 lpar_rc = beat_read_htab_entries(0, slot & ~3UL, dword);
159
160 dword0 = dword[slot&3];
161
162 BUG_ON(lpar_rc != 0);
163
164 return dword0;
165}
166
167static void beat_lpar_hptab_clear(void)
168{
169 unsigned long size_bytes = 1UL << ppc64_pft_size;
170 unsigned long hpte_count = size_bytes >> 4;
171 int i;
172 u64 dummy0, dummy1;
173
174 /* TODO: Use bulk call */
175 for (i = 0; i < hpte_count; i++)
176 beat_write_htab_entry(0, i, 0, 0, -1UL, -1UL, &dummy0, &dummy1);
177}
178
179/*
180 * NOTE: for updatepp ops we are fortunate that the linux "newpp" bits and
181 * the low 3 bits of flags happen to line up. So no transform is needed.
182 * We can probably optimize here and assume the high bits of newpp are
183 * already zero. For now I am paranoid.
184 */
185static long beat_lpar_hpte_updatepp(unsigned long slot,
186 unsigned long newpp,
187 unsigned long vpn,
188 int psize, int apsize,
189 int ssize, unsigned long flags)
190{
191 unsigned long lpar_rc;
192 u64 dummy0, dummy1;
193 unsigned long want_v;
194
195 want_v = hpte_encode_avpn(vpn, psize, MMU_SEGSIZE_256M);
196
197 DBG_LOW(" update: "
198 "avpnv=%016lx, slot=%016lx, psize: %d, newpp %016lx ... ",
199 want_v & HPTE_V_AVPN, slot, psize, newpp);
200
201 raw_spin_lock(&beat_htab_lock);
202 dummy0 = beat_lpar_hpte_getword0(slot);
203 if ((dummy0 & ~0x7FUL) != (want_v & ~0x7FUL)) {
204 DBG_LOW("not found !\n");
205 raw_spin_unlock(&beat_htab_lock);
206 return -1;
207 }
208
209 lpar_rc = beat_write_htab_entry(0, slot, 0, newpp, 0, 7, &dummy0,
210 &dummy1);
211 raw_spin_unlock(&beat_htab_lock);
212 if (lpar_rc != 0 || dummy0 == 0) {
213 DBG_LOW("not found !\n");
214 return -1;
215 }
216
217 DBG_LOW("ok %lx %lx\n", dummy0, dummy1);
218
219 BUG_ON(lpar_rc != 0);
220
221 return 0;
222}
223
224static long beat_lpar_hpte_find(unsigned long vpn, int psize)
225{
226 unsigned long hash;
227 unsigned long i, j;
228 long slot;
229 unsigned long want_v, hpte_v;
230
231 hash = hpt_hash(vpn, mmu_psize_defs[psize].shift, MMU_SEGSIZE_256M);
232 want_v = hpte_encode_avpn(vpn, psize, MMU_SEGSIZE_256M);
233
234 for (j = 0; j < 2; j++) {
235 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
236 for (i = 0; i < HPTES_PER_GROUP; i++) {
237 hpte_v = beat_lpar_hpte_getword0(slot);
238
239 if (HPTE_V_COMPARE(hpte_v, want_v)
240 && (hpte_v & HPTE_V_VALID)
241 && (!!(hpte_v & HPTE_V_SECONDARY) == j)) {
242 /* HPTE matches */
243 if (j)
244 slot = -slot;
245 return slot;
246 }
247 ++slot;
248 }
249 hash = ~hash;
250 }
251
252 return -1;
253}
254
255static void beat_lpar_hpte_updateboltedpp(unsigned long newpp,
256 unsigned long ea,
257 int psize, int ssize)
258{
259 unsigned long vpn;
260 unsigned long lpar_rc, slot, vsid;
261 u64 dummy0, dummy1;
262
263 vsid = get_kernel_vsid(ea, MMU_SEGSIZE_256M);
264 vpn = hpt_vpn(ea, vsid, MMU_SEGSIZE_256M);
265
266 raw_spin_lock(&beat_htab_lock);
267 slot = beat_lpar_hpte_find(vpn, psize);
268 BUG_ON(slot == -1);
269
270 lpar_rc = beat_write_htab_entry(0, slot, 0, newpp, 0, 7,
271 &dummy0, &dummy1);
272 raw_spin_unlock(&beat_htab_lock);
273
274 BUG_ON(lpar_rc != 0);
275}
276
277static void beat_lpar_hpte_invalidate(unsigned long slot, unsigned long vpn,
278 int psize, int apsize,
279 int ssize, int local)
280{
281 unsigned long want_v;
282 unsigned long lpar_rc;
283 u64 dummy1, dummy2;
284 unsigned long flags;
285
286 DBG_LOW(" inval : slot=%lx, va=%016lx, psize: %d, local: %d\n",
287 slot, va, psize, local);
288 want_v = hpte_encode_avpn(vpn, psize, MMU_SEGSIZE_256M);
289
290 raw_spin_lock_irqsave(&beat_htab_lock, flags);
291 dummy1 = beat_lpar_hpte_getword0(slot);
292
293 if ((dummy1 & ~0x7FUL) != (want_v & ~0x7FUL)) {
294 DBG_LOW("not found !\n");
295 raw_spin_unlock_irqrestore(&beat_htab_lock, flags);
296 return;
297 }
298
299 lpar_rc = beat_write_htab_entry(0, slot, 0, 0, HPTE_V_VALID, 0,
300 &dummy1, &dummy2);
301 raw_spin_unlock_irqrestore(&beat_htab_lock, flags);
302
303 BUG_ON(lpar_rc != 0);
304}
305
306void __init hpte_init_beat(void)
307{
308 ppc_md.hpte_invalidate = beat_lpar_hpte_invalidate;
309 ppc_md.hpte_updatepp = beat_lpar_hpte_updatepp;
310 ppc_md.hpte_updateboltedpp = beat_lpar_hpte_updateboltedpp;
311 ppc_md.hpte_insert = beat_lpar_hpte_insert;
312 ppc_md.hpte_remove = beat_lpar_hpte_remove;
313 ppc_md.hpte_clear_all = beat_lpar_hptab_clear;
314}
315
316static long beat_lpar_hpte_insert_v3(unsigned long hpte_group,
317 unsigned long vpn, unsigned long pa,
318 unsigned long rflags, unsigned long vflags,
319 int psize, int apsize, int ssize)
320{
321 unsigned long lpar_rc;
322 u64 hpte_v, hpte_r, slot;
323
324 if (vflags & HPTE_V_SECONDARY)
325 return -1;
326
327 if (!(vflags & HPTE_V_BOLTED))
328 DBG_LOW("hpte_insert(group=%lx, vpn=%016lx, pa=%016lx, "
329 "rflags=%lx, vflags=%lx, psize=%d)\n",
330 hpte_group, vpn, pa, rflags, vflags, psize);
331
332 hpte_v = hpte_encode_v(vpn, psize, apsize, MMU_SEGSIZE_256M) |
333 vflags | HPTE_V_VALID;
334 hpte_r = hpte_encode_r(pa, psize, apsize) | rflags;
335
336 if (!(vflags & HPTE_V_BOLTED))
337 DBG_LOW(" hpte_v=%016lx, hpte_r=%016lx\n", hpte_v, hpte_r);
338
339 if (rflags & _PAGE_NO_CACHE)
340 hpte_r &= ~HPTE_R_M;
341
342 /* insert into not-volted entry */
343 lpar_rc = beat_insert_htab_entry3(0, hpte_group, hpte_v, hpte_r,
344 HPTE_V_BOLTED, 0, &slot);
345 /*
346 * Since we try and ioremap PHBs we don't own, the pte insert
347 * will fail. However we must catch the failure in hash_page
348 * or we will loop forever, so return -2 in this case.
349 */
350 if (unlikely(lpar_rc != 0)) {
351 if (!(vflags & HPTE_V_BOLTED))
352 DBG_LOW(" lpar err %lx\n", lpar_rc);
353 return -2;
354 }
355 if (!(vflags & HPTE_V_BOLTED))
356 DBG_LOW(" -> slot: %lx\n", slot);
357
358 /* We have to pass down the secondary bucket bit here as well */
359 return (slot ^ hpte_group) & 15;
360}
361
362/*
363 * NOTE: for updatepp ops we are fortunate that the linux "newpp" bits and
364 * the low 3 bits of flags happen to line up. So no transform is needed.
365 * We can probably optimize here and assume the high bits of newpp are
366 * already zero. For now I am paranoid.
367 */
368static long beat_lpar_hpte_updatepp_v3(unsigned long slot,
369 unsigned long newpp,
370 unsigned long vpn,
371 int psize, int apsize,
372 int ssize, unsigned long flags)
373{
374 unsigned long lpar_rc;
375 unsigned long want_v;
376 unsigned long pss;
377
378 want_v = hpte_encode_avpn(vpn, psize, MMU_SEGSIZE_256M);
379 pss = (psize == MMU_PAGE_4K) ? -1UL : mmu_psize_defs[psize].penc[psize];
380
381 DBG_LOW(" update: "
382 "avpnv=%016lx, slot=%016lx, psize: %d, newpp %016lx ... ",
383 want_v & HPTE_V_AVPN, slot, psize, newpp);
384
385 lpar_rc = beat_update_htab_permission3(0, slot, want_v, pss, 7, newpp);
386
387 if (lpar_rc == 0xfffffff7) {
388 DBG_LOW("not found !\n");
389 return -1;
390 }
391
392 DBG_LOW("ok\n");
393
394 BUG_ON(lpar_rc != 0);
395
396 return 0;
397}
398
399static void beat_lpar_hpte_invalidate_v3(unsigned long slot, unsigned long vpn,
400 int psize, int apsize,
401 int ssize, int local)
402{
403 unsigned long want_v;
404 unsigned long lpar_rc;
405 unsigned long pss;
406
407 DBG_LOW(" inval : slot=%lx, vpn=%016lx, psize: %d, local: %d\n",
408 slot, vpn, psize, local);
409 want_v = hpte_encode_avpn(vpn, psize, MMU_SEGSIZE_256M);
410 pss = (psize == MMU_PAGE_4K) ? -1UL : mmu_psize_defs[psize].penc[psize];
411
412 lpar_rc = beat_invalidate_htab_entry3(0, slot, want_v, pss);
413
414 /* E_busy can be valid output: page may be already replaced */
415 BUG_ON(lpar_rc != 0 && lpar_rc != 0xfffffff7);
416}
417
418static int64_t _beat_lpar_hptab_clear_v3(void)
419{
420 return beat_clear_htab3(0);
421}
422
423static void beat_lpar_hptab_clear_v3(void)
424{
425 _beat_lpar_hptab_clear_v3();
426}
427
428void __init hpte_init_beat_v3(void)
429{
430 if (_beat_lpar_hptab_clear_v3() == 0) {
431 ppc_md.hpte_invalidate = beat_lpar_hpte_invalidate_v3;
432 ppc_md.hpte_updatepp = beat_lpar_hpte_updatepp_v3;
433 ppc_md.hpte_updateboltedpp = beat_lpar_hpte_updateboltedpp;
434 ppc_md.hpte_insert = beat_lpar_hpte_insert_v3;
435 ppc_md.hpte_remove = beat_lpar_hpte_remove;
436 ppc_md.hpte_clear_all = beat_lpar_hptab_clear_v3;
437 } else {
438 ppc_md.hpte_invalidate = beat_lpar_hpte_invalidate;
439 ppc_md.hpte_updatepp = beat_lpar_hpte_updatepp;
440 ppc_md.hpte_updateboltedpp = beat_lpar_hpte_updateboltedpp;
441 ppc_md.hpte_insert = beat_lpar_hpte_insert;
442 ppc_md.hpte_remove = beat_lpar_hpte_remove;
443 ppc_md.hpte_clear_all = beat_lpar_hptab_clear;
444 }
445}
diff --git a/arch/powerpc/platforms/cell/beat_hvCall.S b/arch/powerpc/platforms/cell/beat_hvCall.S
deleted file mode 100644
index 96c801907126..000000000000
--- a/arch/powerpc/platforms/cell/beat_hvCall.S
+++ /dev/null
@@ -1,285 +0,0 @@
1/*
2 * Beat hypervisor call I/F
3 *
4 * (C) Copyright 2007 TOSHIBA CORPORATION
5 *
6 * This code is based on arch/powerpc/platforms/pseries/hvCall.S.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
21 */
22
23#include <asm/ppc_asm.h>
24
25/* Not implemented on Beat, now */
26#define HCALL_INST_PRECALL
27#define HCALL_INST_POSTCALL
28
29 .text
30
31#define HVSC .long 0x44000022
32
33/* Note: takes only 7 input parameters at maximum */
34_GLOBAL(beat_hcall_norets)
35 HMT_MEDIUM
36
37 mfcr r0
38 stw r0,8(r1)
39
40 HCALL_INST_PRECALL
41
42 mr r11,r3
43 mr r3,r4
44 mr r4,r5
45 mr r5,r6
46 mr r6,r7
47 mr r7,r8
48 mr r8,r9
49
50 HVSC /* invoke the hypervisor */
51
52 HCALL_INST_POSTCALL
53
54 lwz r0,8(r1)
55 mtcrf 0xff,r0
56
57 blr /* return r3 = status */
58
59/* Note: takes 8 input parameters at maximum */
60_GLOBAL(beat_hcall_norets8)
61 HMT_MEDIUM
62
63 mfcr r0
64 stw r0,8(r1)
65
66 HCALL_INST_PRECALL
67
68 mr r11,r3
69 mr r3,r4
70 mr r4,r5
71 mr r5,r6
72 mr r6,r7
73 mr r7,r8
74 mr r8,r9
75 ld r10,STK_PARAM(R10)(r1)
76
77 HVSC /* invoke the hypervisor */
78
79 HCALL_INST_POSTCALL
80
81 lwz r0,8(r1)
82 mtcrf 0xff,r0
83
84 blr /* return r3 = status */
85
86/* Note: takes only 6 input parameters, 1 output parameters at maximum */
87_GLOBAL(beat_hcall1)
88 HMT_MEDIUM
89
90 mfcr r0
91 stw r0,8(r1)
92
93 HCALL_INST_PRECALL
94
95 std r4,STK_PARAM(R4)(r1) /* save ret buffer */
96
97 mr r11,r3
98 mr r3,r5
99 mr r4,r6
100 mr r5,r7
101 mr r6,r8
102 mr r7,r9
103 mr r8,r10
104
105 HVSC /* invoke the hypervisor */
106
107 HCALL_INST_POSTCALL
108
109 ld r12,STK_PARAM(R4)(r1)
110 std r4, 0(r12)
111
112 lwz r0,8(r1)
113 mtcrf 0xff,r0
114
115 blr /* return r3 = status */
116
117/* Note: takes only 6 input parameters, 2 output parameters at maximum */
118_GLOBAL(beat_hcall2)
119 HMT_MEDIUM
120
121 mfcr r0
122 stw r0,8(r1)
123
124 HCALL_INST_PRECALL
125
126 std r4,STK_PARAM(R4)(r1) /* save ret buffer */
127
128 mr r11,r3
129 mr r3,r5
130 mr r4,r6
131 mr r5,r7
132 mr r6,r8
133 mr r7,r9
134 mr r8,r10
135
136 HVSC /* invoke the hypervisor */
137
138 HCALL_INST_POSTCALL
139
140 ld r12,STK_PARAM(R4)(r1)
141 std r4, 0(r12)
142 std r5, 8(r12)
143
144 lwz r0,8(r1)
145 mtcrf 0xff,r0
146
147 blr /* return r3 = status */
148
149/* Note: takes only 6 input parameters, 3 output parameters at maximum */
150_GLOBAL(beat_hcall3)
151 HMT_MEDIUM
152
153 mfcr r0
154 stw r0,8(r1)
155
156 HCALL_INST_PRECALL
157
158 std r4,STK_PARAM(R4)(r1) /* save ret buffer */
159
160 mr r11,r3
161 mr r3,r5
162 mr r4,r6
163 mr r5,r7
164 mr r6,r8
165 mr r7,r9
166 mr r8,r10
167
168 HVSC /* invoke the hypervisor */
169
170 HCALL_INST_POSTCALL
171
172 ld r12,STK_PARAM(R4)(r1)
173 std r4, 0(r12)
174 std r5, 8(r12)
175 std r6, 16(r12)
176
177 lwz r0,8(r1)
178 mtcrf 0xff,r0
179
180 blr /* return r3 = status */
181
182/* Note: takes only 6 input parameters, 4 output parameters at maximum */
183_GLOBAL(beat_hcall4)
184 HMT_MEDIUM
185
186 mfcr r0
187 stw r0,8(r1)
188
189 HCALL_INST_PRECALL
190
191 std r4,STK_PARAM(R4)(r1) /* save ret buffer */
192
193 mr r11,r3
194 mr r3,r5
195 mr r4,r6
196 mr r5,r7
197 mr r6,r8
198 mr r7,r9
199 mr r8,r10
200
201 HVSC /* invoke the hypervisor */
202
203 HCALL_INST_POSTCALL
204
205 ld r12,STK_PARAM(R4)(r1)
206 std r4, 0(r12)
207 std r5, 8(r12)
208 std r6, 16(r12)
209 std r7, 24(r12)
210
211 lwz r0,8(r1)
212 mtcrf 0xff,r0
213
214 blr /* return r3 = status */
215
216/* Note: takes only 6 input parameters, 5 output parameters at maximum */
217_GLOBAL(beat_hcall5)
218 HMT_MEDIUM
219
220 mfcr r0
221 stw r0,8(r1)
222
223 HCALL_INST_PRECALL
224
225 std r4,STK_PARAM(R4)(r1) /* save ret buffer */
226
227 mr r11,r3
228 mr r3,r5
229 mr r4,r6
230 mr r5,r7
231 mr r6,r8
232 mr r7,r9
233 mr r8,r10
234
235 HVSC /* invoke the hypervisor */
236
237 HCALL_INST_POSTCALL
238
239 ld r12,STK_PARAM(R4)(r1)
240 std r4, 0(r12)
241 std r5, 8(r12)
242 std r6, 16(r12)
243 std r7, 24(r12)
244 std r8, 32(r12)
245
246 lwz r0,8(r1)
247 mtcrf 0xff,r0
248
249 blr /* return r3 = status */
250
251/* Note: takes only 6 input parameters, 6 output parameters at maximum */
252_GLOBAL(beat_hcall6)
253 HMT_MEDIUM
254
255 mfcr r0
256 stw r0,8(r1)
257
258 HCALL_INST_PRECALL
259
260 std r4,STK_PARAM(R4)(r1) /* save ret buffer */
261
262 mr r11,r3
263 mr r3,r5
264 mr r4,r6
265 mr r5,r7
266 mr r6,r8
267 mr r7,r9
268 mr r8,r10
269
270 HVSC /* invoke the hypervisor */
271
272 HCALL_INST_POSTCALL
273
274 ld r12,STK_PARAM(R4)(r1)
275 std r4, 0(r12)
276 std r5, 8(r12)
277 std r6, 16(r12)
278 std r7, 24(r12)
279 std r8, 32(r12)
280 std r9, 40(r12)
281
282 lwz r0,8(r1)
283 mtcrf 0xff,r0
284
285 blr /* return r3 = status */
diff --git a/arch/powerpc/platforms/cell/beat_interrupt.c b/arch/powerpc/platforms/cell/beat_interrupt.c
deleted file mode 100644
index 9e5dfbcc00af..000000000000
--- a/arch/powerpc/platforms/cell/beat_interrupt.c
+++ /dev/null
@@ -1,253 +0,0 @@
1/*
2 * Celleb/Beat Interrupt controller
3 *
4 * (C) Copyright 2006-2007 TOSHIBA CORPORATION
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/irq.h>
24#include <linux/percpu.h>
25#include <linux/types.h>
26
27#include <asm/machdep.h>
28
29#include "beat_interrupt.h"
30#include "beat_wrapper.h"
31
32#define MAX_IRQS NR_IRQS
33static DEFINE_RAW_SPINLOCK(beatic_irq_mask_lock);
34static uint64_t beatic_irq_mask_enable[(MAX_IRQS+255)/64];
35static uint64_t beatic_irq_mask_ack[(MAX_IRQS+255)/64];
36
37static struct irq_domain *beatic_host;
38
39/*
40 * In this implementation, "virq" == "IRQ plug number",
41 * "(irq_hw_number_t)hwirq" == "IRQ outlet number".
42 */
43
44/* assumption: locked */
45static inline void beatic_update_irq_mask(unsigned int irq_plug)
46{
47 int off;
48 unsigned long masks[4];
49
50 off = (irq_plug / 256) * 4;
51 masks[0] = beatic_irq_mask_enable[off + 0]
52 & beatic_irq_mask_ack[off + 0];
53 masks[1] = beatic_irq_mask_enable[off + 1]
54 & beatic_irq_mask_ack[off + 1];
55 masks[2] = beatic_irq_mask_enable[off + 2]
56 & beatic_irq_mask_ack[off + 2];
57 masks[3] = beatic_irq_mask_enable[off + 3]
58 & beatic_irq_mask_ack[off + 3];
59 if (beat_set_interrupt_mask(irq_plug&~255UL,
60 masks[0], masks[1], masks[2], masks[3]) != 0)
61 panic("Failed to set mask IRQ!");
62}
63
64static void beatic_mask_irq(struct irq_data *d)
65{
66 unsigned long flags;
67
68 raw_spin_lock_irqsave(&beatic_irq_mask_lock, flags);
69 beatic_irq_mask_enable[d->irq/64] &= ~(1UL << (63 - (d->irq%64)));
70 beatic_update_irq_mask(d->irq);
71 raw_spin_unlock_irqrestore(&beatic_irq_mask_lock, flags);
72}
73
74static void beatic_unmask_irq(struct irq_data *d)
75{
76 unsigned long flags;
77
78 raw_spin_lock_irqsave(&beatic_irq_mask_lock, flags);
79 beatic_irq_mask_enable[d->irq/64] |= 1UL << (63 - (d->irq%64));
80 beatic_update_irq_mask(d->irq);
81 raw_spin_unlock_irqrestore(&beatic_irq_mask_lock, flags);
82}
83
84static void beatic_ack_irq(struct irq_data *d)
85{
86 unsigned long flags;
87
88 raw_spin_lock_irqsave(&beatic_irq_mask_lock, flags);
89 beatic_irq_mask_ack[d->irq/64] &= ~(1UL << (63 - (d->irq%64)));
90 beatic_update_irq_mask(d->irq);
91 raw_spin_unlock_irqrestore(&beatic_irq_mask_lock, flags);
92}
93
94static void beatic_end_irq(struct irq_data *d)
95{
96 s64 err;
97 unsigned long flags;
98
99 err = beat_downcount_of_interrupt(d->irq);
100 if (err != 0) {
101 if ((err & 0xFFFFFFFF) != 0xFFFFFFF5) /* -11: wrong state */
102 panic("Failed to downcount IRQ! Error = %16llx", err);
103
104 printk(KERN_ERR "IRQ over-downcounted, plug %d\n", d->irq);
105 }
106 raw_spin_lock_irqsave(&beatic_irq_mask_lock, flags);
107 beatic_irq_mask_ack[d->irq/64] |= 1UL << (63 - (d->irq%64));
108 beatic_update_irq_mask(d->irq);
109 raw_spin_unlock_irqrestore(&beatic_irq_mask_lock, flags);
110}
111
112static struct irq_chip beatic_pic = {
113 .name = "CELL-BEAT",
114 .irq_unmask = beatic_unmask_irq,
115 .irq_mask = beatic_mask_irq,
116 .irq_eoi = beatic_end_irq,
117};
118
119/*
120 * Dispose binding hardware IRQ number (hw) and Virtuql IRQ number (virq),
121 * update flags.
122 *
123 * Note that the number (virq) is already assigned at upper layer.
124 */
125static void beatic_pic_host_unmap(struct irq_domain *h, unsigned int virq)
126{
127 beat_destruct_irq_plug(virq);
128}
129
130/*
131 * Create or update binding hardware IRQ number (hw) and Virtuql
132 * IRQ number (virq). This is called only once for a given mapping.
133 *
134 * Note that the number (virq) is already assigned at upper layer.
135 */
136static int beatic_pic_host_map(struct irq_domain *h, unsigned int virq,
137 irq_hw_number_t hw)
138{
139 int64_t err;
140
141 err = beat_construct_and_connect_irq_plug(virq, hw);
142 if (err < 0)
143 return -EIO;
144
145 irq_set_status_flags(virq, IRQ_LEVEL);
146 irq_set_chip_and_handler(virq, &beatic_pic, handle_fasteoi_irq);
147 return 0;
148}
149
150/*
151 * Translate device-tree interrupt spec to irq_hw_number_t style (ulong),
152 * to pass away to irq_create_mapping().
153 *
154 * Called from irq_create_of_mapping() only.
155 * Note: We have only 1 entry to translate.
156 */
157static int beatic_pic_host_xlate(struct irq_domain *h, struct device_node *ct,
158 const u32 *intspec, unsigned int intsize,
159 irq_hw_number_t *out_hwirq,
160 unsigned int *out_flags)
161{
162 const u64 *intspec2 = (const u64 *)intspec;
163
164 *out_hwirq = *intspec2;
165 *out_flags |= IRQ_TYPE_LEVEL_LOW;
166 return 0;
167}
168
169static int beatic_pic_host_match(struct irq_domain *h, struct device_node *np)
170{
171 /* Match all */
172 return 1;
173}
174
175static const struct irq_domain_ops beatic_pic_host_ops = {
176 .map = beatic_pic_host_map,
177 .unmap = beatic_pic_host_unmap,
178 .xlate = beatic_pic_host_xlate,
179 .match = beatic_pic_host_match,
180};
181
182/*
183 * Get an IRQ number
184 * Note: returns VIRQ
185 */
186static inline unsigned int beatic_get_irq_plug(void)
187{
188 int i;
189 uint64_t pending[4], ub;
190
191 for (i = 0; i < MAX_IRQS; i += 256) {
192 beat_detect_pending_interrupts(i, pending);
193 __asm__ ("cntlzd %0,%1":"=r"(ub):
194 "r"(pending[0] & beatic_irq_mask_enable[i/64+0]
195 & beatic_irq_mask_ack[i/64+0]));
196 if (ub != 64)
197 return i + ub + 0;
198 __asm__ ("cntlzd %0,%1":"=r"(ub):
199 "r"(pending[1] & beatic_irq_mask_enable[i/64+1]
200 & beatic_irq_mask_ack[i/64+1]));
201 if (ub != 64)
202 return i + ub + 64;
203 __asm__ ("cntlzd %0,%1":"=r"(ub):
204 "r"(pending[2] & beatic_irq_mask_enable[i/64+2]
205 & beatic_irq_mask_ack[i/64+2]));
206 if (ub != 64)
207 return i + ub + 128;
208 __asm__ ("cntlzd %0,%1":"=r"(ub):
209 "r"(pending[3] & beatic_irq_mask_enable[i/64+3]
210 & beatic_irq_mask_ack[i/64+3]));
211 if (ub != 64)
212 return i + ub + 192;
213 }
214
215 return NO_IRQ;
216}
217unsigned int beatic_get_irq(void)
218{
219 unsigned int ret;
220
221 ret = beatic_get_irq_plug();
222 if (ret != NO_IRQ)
223 beatic_ack_irq(irq_get_irq_data(ret));
224 return ret;
225}
226
227/*
228 */
229void __init beatic_init_IRQ(void)
230{
231 int i;
232
233 memset(beatic_irq_mask_enable, 0, sizeof(beatic_irq_mask_enable));
234 memset(beatic_irq_mask_ack, 255, sizeof(beatic_irq_mask_ack));
235 for (i = 0; i < MAX_IRQS; i += 256)
236 beat_set_interrupt_mask(i, 0L, 0L, 0L, 0L);
237
238 /* Set out get_irq function */
239 ppc_md.get_irq = beatic_get_irq;
240
241 /* Allocate an irq host */
242 beatic_host = irq_domain_add_nomap(NULL, ~0, &beatic_pic_host_ops, NULL);
243 BUG_ON(beatic_host == NULL);
244 irq_set_default_host(beatic_host);
245}
246
247void beatic_deinit_IRQ(void)
248{
249 int i;
250
251 for (i = 1; i < nr_irqs; i++)
252 beat_destruct_irq_plug(i);
253}
diff --git a/arch/powerpc/platforms/cell/beat_interrupt.h b/arch/powerpc/platforms/cell/beat_interrupt.h
deleted file mode 100644
index a7e52f91a078..000000000000
--- a/arch/powerpc/platforms/cell/beat_interrupt.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * Celleb/Beat Interrupt controller
3 *
4 * (C) Copyright 2006 TOSHIBA CORPORATION
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#ifndef ASM_BEAT_PIC_H
22#define ASM_BEAT_PIC_H
23#ifdef __KERNEL__
24
25extern void beatic_init_IRQ(void);
26extern unsigned int beatic_get_irq(void);
27extern void beatic_deinit_IRQ(void);
28
29#endif
30#endif /* ASM_BEAT_PIC_H */
diff --git a/arch/powerpc/platforms/cell/beat_iommu.c b/arch/powerpc/platforms/cell/beat_iommu.c
deleted file mode 100644
index 3ce685568935..000000000000
--- a/arch/powerpc/platforms/cell/beat_iommu.c
+++ /dev/null
@@ -1,115 +0,0 @@
1/*
2 * Support for IOMMU on Celleb platform.
3 *
4 * (C) Copyright 2006-2007 TOSHIBA CORPORATION
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/dma-mapping.h>
24#include <linux/pci.h>
25#include <linux/of_platform.h>
26
27#include <asm/machdep.h>
28
29#include "beat_wrapper.h"
30
31#define DMA_FLAGS 0xf800000000000000UL /* r/w permitted, coherency required,
32 strongest order */
33
34static int __init find_dma_window(u64 *io_space_id, u64 *ioid,
35 u64 *base, u64 *size, u64 *io_page_size)
36{
37 struct device_node *dn;
38 const unsigned long *dma_window;
39
40 for_each_node_by_type(dn, "ioif") {
41 dma_window = of_get_property(dn, "toshiba,dma-window", NULL);
42 if (dma_window) {
43 *io_space_id = (dma_window[0] >> 32) & 0xffffffffUL;
44 *ioid = dma_window[0] & 0x7ffUL;
45 *base = dma_window[1];
46 *size = dma_window[2];
47 *io_page_size = 1 << dma_window[3];
48 of_node_put(dn);
49 return 1;
50 }
51 }
52 return 0;
53}
54
55static unsigned long celleb_dma_direct_offset;
56
57static void __init celleb_init_direct_mapping(void)
58{
59 u64 lpar_addr, io_addr;
60 u64 io_space_id, ioid, dma_base, dma_size, io_page_size;
61
62 if (!find_dma_window(&io_space_id, &ioid, &dma_base, &dma_size,
63 &io_page_size)) {
64 pr_info("No dma window found !\n");
65 return;
66 }
67
68 for (lpar_addr = 0; lpar_addr < dma_size; lpar_addr += io_page_size) {
69 io_addr = lpar_addr + dma_base;
70 (void)beat_put_iopte(io_space_id, io_addr, lpar_addr,
71 ioid, DMA_FLAGS);
72 }
73
74 celleb_dma_direct_offset = dma_base;
75}
76
77static void celleb_dma_dev_setup(struct device *dev)
78{
79 set_dma_ops(dev, &dma_direct_ops);
80 set_dma_offset(dev, celleb_dma_direct_offset);
81}
82
83static void celleb_pci_dma_dev_setup(struct pci_dev *pdev)
84{
85 celleb_dma_dev_setup(&pdev->dev);
86}
87
88static int celleb_of_bus_notify(struct notifier_block *nb,
89 unsigned long action, void *data)
90{
91 struct device *dev = data;
92
93 /* We are only intereted in device addition */
94 if (action != BUS_NOTIFY_ADD_DEVICE)
95 return 0;
96
97 celleb_dma_dev_setup(dev);
98
99 return 0;
100}
101
102static struct notifier_block celleb_of_bus_notifier = {
103 .notifier_call = celleb_of_bus_notify
104};
105
106static int __init celleb_init_iommu(void)
107{
108 celleb_init_direct_mapping();
109 ppc_md.pci_dma_dev_setup = celleb_pci_dma_dev_setup;
110 bus_register_notifier(&platform_bus_type, &celleb_of_bus_notifier);
111
112 return 0;
113}
114
115machine_arch_initcall(celleb_beat, celleb_init_iommu);
diff --git a/arch/powerpc/platforms/cell/beat_spu_priv1.c b/arch/powerpc/platforms/cell/beat_spu_priv1.c
deleted file mode 100644
index 13f52589d3a9..000000000000
--- a/arch/powerpc/platforms/cell/beat_spu_priv1.c
+++ /dev/null
@@ -1,205 +0,0 @@
1/*
2 * spu hypervisor abstraction for Beat
3 *
4 * (C) Copyright 2006-2007 TOSHIBA CORPORATION
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <asm/types.h>
22#include <asm/spu.h>
23#include <asm/spu_priv1.h>
24
25#include "beat_wrapper.h"
26
27static inline void _int_mask_set(struct spu *spu, int class, u64 mask)
28{
29 spu->shadow_int_mask_RW[class] = mask;
30 beat_set_irq_mask_for_spe(spu->spe_id, class, mask);
31}
32
33static inline u64 _int_mask_get(struct spu *spu, int class)
34{
35 return spu->shadow_int_mask_RW[class];
36}
37
38static void int_mask_set(struct spu *spu, int class, u64 mask)
39{
40 _int_mask_set(spu, class, mask);
41}
42
43static u64 int_mask_get(struct spu *spu, int class)
44{
45 return _int_mask_get(spu, class);
46}
47
48static void int_mask_and(struct spu *spu, int class, u64 mask)
49{
50 u64 old_mask;
51 old_mask = _int_mask_get(spu, class);
52 _int_mask_set(spu, class, old_mask & mask);
53}
54
55static void int_mask_or(struct spu *spu, int class, u64 mask)
56{
57 u64 old_mask;
58 old_mask = _int_mask_get(spu, class);
59 _int_mask_set(spu, class, old_mask | mask);
60}
61
62static void int_stat_clear(struct spu *spu, int class, u64 stat)
63{
64 beat_clear_interrupt_status_of_spe(spu->spe_id, class, stat);
65}
66
67static u64 int_stat_get(struct spu *spu, int class)
68{
69 u64 int_stat;
70 beat_get_interrupt_status_of_spe(spu->spe_id, class, &int_stat);
71 return int_stat;
72}
73
74static void cpu_affinity_set(struct spu *spu, int cpu)
75{
76 return;
77}
78
79static u64 mfc_dar_get(struct spu *spu)
80{
81 u64 dar;
82 beat_get_spe_privileged_state_1_registers(
83 spu->spe_id,
84 offsetof(struct spu_priv1, mfc_dar_RW), &dar);
85 return dar;
86}
87
88static u64 mfc_dsisr_get(struct spu *spu)
89{
90 u64 dsisr;
91 beat_get_spe_privileged_state_1_registers(
92 spu->spe_id,
93 offsetof(struct spu_priv1, mfc_dsisr_RW), &dsisr);
94 return dsisr;
95}
96
97static void mfc_dsisr_set(struct spu *spu, u64 dsisr)
98{
99 beat_set_spe_privileged_state_1_registers(
100 spu->spe_id,
101 offsetof(struct spu_priv1, mfc_dsisr_RW), dsisr);
102}
103
104static void mfc_sdr_setup(struct spu *spu)
105{
106 return;
107}
108
109static void mfc_sr1_set(struct spu *spu, u64 sr1)
110{
111 beat_set_spe_privileged_state_1_registers(
112 spu->spe_id,
113 offsetof(struct spu_priv1, mfc_sr1_RW), sr1);
114}
115
116static u64 mfc_sr1_get(struct spu *spu)
117{
118 u64 sr1;
119 beat_get_spe_privileged_state_1_registers(
120 spu->spe_id,
121 offsetof(struct spu_priv1, mfc_sr1_RW), &sr1);
122 return sr1;
123}
124
125static void mfc_tclass_id_set(struct spu *spu, u64 tclass_id)
126{
127 beat_set_spe_privileged_state_1_registers(
128 spu->spe_id,
129 offsetof(struct spu_priv1, mfc_tclass_id_RW), tclass_id);
130}
131
132static u64 mfc_tclass_id_get(struct spu *spu)
133{
134 u64 tclass_id;
135 beat_get_spe_privileged_state_1_registers(
136 spu->spe_id,
137 offsetof(struct spu_priv1, mfc_tclass_id_RW), &tclass_id);
138 return tclass_id;
139}
140
141static void tlb_invalidate(struct spu *spu)
142{
143 beat_set_spe_privileged_state_1_registers(
144 spu->spe_id,
145 offsetof(struct spu_priv1, tlb_invalidate_entry_W), 0ul);
146}
147
148static void resource_allocation_groupID_set(struct spu *spu, u64 id)
149{
150 beat_set_spe_privileged_state_1_registers(
151 spu->spe_id,
152 offsetof(struct spu_priv1, resource_allocation_groupID_RW),
153 id);
154}
155
156static u64 resource_allocation_groupID_get(struct spu *spu)
157{
158 u64 id;
159 beat_get_spe_privileged_state_1_registers(
160 spu->spe_id,
161 offsetof(struct spu_priv1, resource_allocation_groupID_RW),
162 &id);
163 return id;
164}
165
166static void resource_allocation_enable_set(struct spu *spu, u64 enable)
167{
168 beat_set_spe_privileged_state_1_registers(
169 spu->spe_id,
170 offsetof(struct spu_priv1, resource_allocation_enable_RW),
171 enable);
172}
173
174static u64 resource_allocation_enable_get(struct spu *spu)
175{
176 u64 enable;
177 beat_get_spe_privileged_state_1_registers(
178 spu->spe_id,
179 offsetof(struct spu_priv1, resource_allocation_enable_RW),
180 &enable);
181 return enable;
182}
183
184const struct spu_priv1_ops spu_priv1_beat_ops = {
185 .int_mask_and = int_mask_and,
186 .int_mask_or = int_mask_or,
187 .int_mask_set = int_mask_set,
188 .int_mask_get = int_mask_get,
189 .int_stat_clear = int_stat_clear,
190 .int_stat_get = int_stat_get,
191 .cpu_affinity_set = cpu_affinity_set,
192 .mfc_dar_get = mfc_dar_get,
193 .mfc_dsisr_get = mfc_dsisr_get,
194 .mfc_dsisr_set = mfc_dsisr_set,
195 .mfc_sdr_setup = mfc_sdr_setup,
196 .mfc_sr1_set = mfc_sr1_set,
197 .mfc_sr1_get = mfc_sr1_get,
198 .mfc_tclass_id_set = mfc_tclass_id_set,
199 .mfc_tclass_id_get = mfc_tclass_id_get,
200 .tlb_invalidate = tlb_invalidate,
201 .resource_allocation_groupID_set = resource_allocation_groupID_set,
202 .resource_allocation_groupID_get = resource_allocation_groupID_get,
203 .resource_allocation_enable_set = resource_allocation_enable_set,
204 .resource_allocation_enable_get = resource_allocation_enable_get,
205};
diff --git a/arch/powerpc/platforms/cell/beat_syscall.h b/arch/powerpc/platforms/cell/beat_syscall.h
deleted file mode 100644
index 8580dc7e1798..000000000000
--- a/arch/powerpc/platforms/cell/beat_syscall.h
+++ /dev/null
@@ -1,164 +0,0 @@
1/*
2 * Beat hypervisor call numbers
3 *
4 * (C) Copyright 2004-2007 TOSHIBA CORPORATION
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#ifndef BEAT_BEAT_syscall_H
22#define BEAT_BEAT_syscall_H
23
24#ifdef __ASSEMBLY__
25#define __BEAT_ADD_VENDOR_ID(__x, __v) ((__v)<<60|(__x))
26#else
27#define __BEAT_ADD_VENDOR_ID(__x, __v) ((u64)(__v)<<60|(__x))
28#endif
29#define HV_allocate_memory __BEAT_ADD_VENDOR_ID(0, 0)
30#define HV_construct_virtual_address_space __BEAT_ADD_VENDOR_ID(2, 0)
31#define HV_destruct_virtual_address_space __BEAT_ADD_VENDOR_ID(10, 0)
32#define HV_get_virtual_address_space_id_of_ppe __BEAT_ADD_VENDOR_ID(4, 0)
33#define HV_query_logical_partition_address_region_info \
34 __BEAT_ADD_VENDOR_ID(6, 0)
35#define HV_release_memory __BEAT_ADD_VENDOR_ID(13, 0)
36#define HV_select_virtual_address_space __BEAT_ADD_VENDOR_ID(7, 0)
37#define HV_load_range_registers __BEAT_ADD_VENDOR_ID(68, 0)
38#define HV_set_ppe_l2cache_rmt_entry __BEAT_ADD_VENDOR_ID(70, 0)
39#define HV_set_ppe_tlb_rmt_entry __BEAT_ADD_VENDOR_ID(71, 0)
40#define HV_set_spe_tlb_rmt_entry __BEAT_ADD_VENDOR_ID(72, 0)
41#define HV_get_io_address_translation_fault_info __BEAT_ADD_VENDOR_ID(14, 0)
42#define HV_get_iopte __BEAT_ADD_VENDOR_ID(16, 0)
43#define HV_preload_iopt_cache __BEAT_ADD_VENDOR_ID(17, 0)
44#define HV_put_iopte __BEAT_ADD_VENDOR_ID(15, 0)
45#define HV_connect_event_ports __BEAT_ADD_VENDOR_ID(21, 0)
46#define HV_construct_event_receive_port __BEAT_ADD_VENDOR_ID(18, 0)
47#define HV_destruct_event_receive_port __BEAT_ADD_VENDOR_ID(19, 0)
48#define HV_destruct_event_send_port __BEAT_ADD_VENDOR_ID(22, 0)
49#define HV_get_state_of_event_send_port __BEAT_ADD_VENDOR_ID(25, 0)
50#define HV_request_to_connect_event_ports __BEAT_ADD_VENDOR_ID(20, 0)
51#define HV_send_event_externally __BEAT_ADD_VENDOR_ID(23, 0)
52#define HV_send_event_locally __BEAT_ADD_VENDOR_ID(24, 0)
53#define HV_construct_and_connect_irq_plug __BEAT_ADD_VENDOR_ID(28, 0)
54#define HV_destruct_irq_plug __BEAT_ADD_VENDOR_ID(29, 0)
55#define HV_detect_pending_interrupts __BEAT_ADD_VENDOR_ID(26, 0)
56#define HV_end_of_interrupt __BEAT_ADD_VENDOR_ID(27, 0)
57#define HV_assign_control_signal_notification_port __BEAT_ADD_VENDOR_ID(45, 0)
58#define HV_end_of_control_signal_processing __BEAT_ADD_VENDOR_ID(48, 0)
59#define HV_get_control_signal __BEAT_ADD_VENDOR_ID(46, 0)
60#define HV_set_irq_mask_for_spe __BEAT_ADD_VENDOR_ID(61, 0)
61#define HV_shutdown_logical_partition __BEAT_ADD_VENDOR_ID(44, 0)
62#define HV_connect_message_ports __BEAT_ADD_VENDOR_ID(35, 0)
63#define HV_destruct_message_port __BEAT_ADD_VENDOR_ID(36, 0)
64#define HV_receive_message __BEAT_ADD_VENDOR_ID(37, 0)
65#define HV_get_message_port_info __BEAT_ADD_VENDOR_ID(34, 0)
66#define HV_request_to_connect_message_ports __BEAT_ADD_VENDOR_ID(33, 0)
67#define HV_send_message __BEAT_ADD_VENDOR_ID(32, 0)
68#define HV_get_logical_ppe_id __BEAT_ADD_VENDOR_ID(69, 0)
69#define HV_pause __BEAT_ADD_VENDOR_ID(9, 0)
70#define HV_destruct_shared_memory_handle __BEAT_ADD_VENDOR_ID(51, 0)
71#define HV_get_shared_memory_info __BEAT_ADD_VENDOR_ID(52, 0)
72#define HV_permit_sharing_memory __BEAT_ADD_VENDOR_ID(50, 0)
73#define HV_request_to_attach_shared_memory __BEAT_ADD_VENDOR_ID(49, 0)
74#define HV_enable_logical_spe_execution __BEAT_ADD_VENDOR_ID(55, 0)
75#define HV_construct_logical_spe __BEAT_ADD_VENDOR_ID(53, 0)
76#define HV_disable_logical_spe_execution __BEAT_ADD_VENDOR_ID(56, 0)
77#define HV_destruct_logical_spe __BEAT_ADD_VENDOR_ID(54, 0)
78#define HV_sense_spe_execution_status __BEAT_ADD_VENDOR_ID(58, 0)
79#define HV_insert_htab_entry __BEAT_ADD_VENDOR_ID(101, 0)
80#define HV_read_htab_entries __BEAT_ADD_VENDOR_ID(95, 0)
81#define HV_write_htab_entry __BEAT_ADD_VENDOR_ID(94, 0)
82#define HV_assign_io_address_translation_fault_port \
83 __BEAT_ADD_VENDOR_ID(100, 0)
84#define HV_set_interrupt_mask __BEAT_ADD_VENDOR_ID(73, 0)
85#define HV_get_logical_partition_id __BEAT_ADD_VENDOR_ID(74, 0)
86#define HV_create_repository_node2 __BEAT_ADD_VENDOR_ID(90, 0)
87#define HV_create_repository_node __BEAT_ADD_VENDOR_ID(90, 0) /* alias */
88#define HV_get_repository_node_value2 __BEAT_ADD_VENDOR_ID(91, 0)
89#define HV_get_repository_node_value __BEAT_ADD_VENDOR_ID(91, 0) /* alias */
90#define HV_modify_repository_node_value2 __BEAT_ADD_VENDOR_ID(92, 0)
91#define HV_modify_repository_node_value __BEAT_ADD_VENDOR_ID(92, 0) /* alias */
92#define HV_remove_repository_node2 __BEAT_ADD_VENDOR_ID(93, 0)
93#define HV_remove_repository_node __BEAT_ADD_VENDOR_ID(93, 0) /* alias */
94#define HV_cancel_shared_memory __BEAT_ADD_VENDOR_ID(104, 0)
95#define HV_clear_interrupt_status_of_spe __BEAT_ADD_VENDOR_ID(206, 0)
96#define HV_construct_spe_irq_outlet __BEAT_ADD_VENDOR_ID(80, 0)
97#define HV_destruct_spe_irq_outlet __BEAT_ADD_VENDOR_ID(81, 0)
98#define HV_disconnect_ipspc_service __BEAT_ADD_VENDOR_ID(88, 0)
99#define HV_execute_ipspc_command __BEAT_ADD_VENDOR_ID(86, 0)
100#define HV_get_interrupt_status_of_spe __BEAT_ADD_VENDOR_ID(205, 0)
101#define HV_get_spe_privileged_state_1_registers __BEAT_ADD_VENDOR_ID(208, 0)
102#define HV_permit_use_of_ipspc_service __BEAT_ADD_VENDOR_ID(85, 0)
103#define HV_reinitialize_logical_spe __BEAT_ADD_VENDOR_ID(82, 0)
104#define HV_request_ipspc_service __BEAT_ADD_VENDOR_ID(84, 0)
105#define HV_stop_ipspc_command __BEAT_ADD_VENDOR_ID(87, 0)
106#define HV_set_spe_privileged_state_1_registers __BEAT_ADD_VENDOR_ID(204, 0)
107#define HV_get_status_of_ipspc_service __BEAT_ADD_VENDOR_ID(203, 0)
108#define HV_put_characters_to_console __BEAT_ADD_VENDOR_ID(0x101, 1)
109#define HV_get_characters_from_console __BEAT_ADD_VENDOR_ID(0x102, 1)
110#define HV_get_base_clock __BEAT_ADD_VENDOR_ID(0x111, 1)
111#define HV_set_base_clock __BEAT_ADD_VENDOR_ID(0x112, 1)
112#define HV_get_frame_cycle __BEAT_ADD_VENDOR_ID(0x114, 1)
113#define HV_disable_console __BEAT_ADD_VENDOR_ID(0x115, 1)
114#define HV_disable_all_console __BEAT_ADD_VENDOR_ID(0x116, 1)
115#define HV_oneshot_timer __BEAT_ADD_VENDOR_ID(0x117, 1)
116#define HV_set_dabr __BEAT_ADD_VENDOR_ID(0x118, 1)
117#define HV_get_dabr __BEAT_ADD_VENDOR_ID(0x119, 1)
118#define HV_start_hv_stats __BEAT_ADD_VENDOR_ID(0x21c, 1)
119#define HV_stop_hv_stats __BEAT_ADD_VENDOR_ID(0x21d, 1)
120#define HV_get_hv_stats __BEAT_ADD_VENDOR_ID(0x21e, 1)
121#define HV_get_hv_error_stats __BEAT_ADD_VENDOR_ID(0x221, 1)
122#define HV_get_stats __BEAT_ADD_VENDOR_ID(0x224, 1)
123#define HV_get_heap_stats __BEAT_ADD_VENDOR_ID(0x225, 1)
124#define HV_get_memory_stats __BEAT_ADD_VENDOR_ID(0x227, 1)
125#define HV_get_memory_detail __BEAT_ADD_VENDOR_ID(0x228, 1)
126#define HV_set_priority_of_irq_outlet __BEAT_ADD_VENDOR_ID(0x122, 1)
127#define HV_get_physical_spe_by_reservation_id __BEAT_ADD_VENDOR_ID(0x128, 1)
128#define HV_get_spe_context __BEAT_ADD_VENDOR_ID(0x129, 1)
129#define HV_set_spe_context __BEAT_ADD_VENDOR_ID(0x12a, 1)
130#define HV_downcount_of_interrupt __BEAT_ADD_VENDOR_ID(0x12e, 1)
131#define HV_peek_spe_context __BEAT_ADD_VENDOR_ID(0x12f, 1)
132#define HV_read_bpa_register __BEAT_ADD_VENDOR_ID(0x131, 1)
133#define HV_write_bpa_register __BEAT_ADD_VENDOR_ID(0x132, 1)
134#define HV_map_context_table_of_spe __BEAT_ADD_VENDOR_ID(0x137, 1)
135#define HV_get_slb_for_logical_spe __BEAT_ADD_VENDOR_ID(0x138, 1)
136#define HV_set_slb_for_logical_spe __BEAT_ADD_VENDOR_ID(0x139, 1)
137#define HV_init_pm __BEAT_ADD_VENDOR_ID(0x150, 1)
138#define HV_set_pm_signal __BEAT_ADD_VENDOR_ID(0x151, 1)
139#define HV_get_pm_signal __BEAT_ADD_VENDOR_ID(0x152, 1)
140#define HV_set_pm_config __BEAT_ADD_VENDOR_ID(0x153, 1)
141#define HV_get_pm_config __BEAT_ADD_VENDOR_ID(0x154, 1)
142#define HV_get_inner_trace_data __BEAT_ADD_VENDOR_ID(0x155, 1)
143#define HV_set_ext_trace_buffer __BEAT_ADD_VENDOR_ID(0x156, 1)
144#define HV_get_ext_trace_buffer __BEAT_ADD_VENDOR_ID(0x157, 1)
145#define HV_set_pm_interrupt __BEAT_ADD_VENDOR_ID(0x158, 1)
146#define HV_get_pm_interrupt __BEAT_ADD_VENDOR_ID(0x159, 1)
147#define HV_kick_pm __BEAT_ADD_VENDOR_ID(0x160, 1)
148#define HV_construct_pm_context __BEAT_ADD_VENDOR_ID(0x164, 1)
149#define HV_destruct_pm_context __BEAT_ADD_VENDOR_ID(0x165, 1)
150#define HV_be_slow __BEAT_ADD_VENDOR_ID(0x170, 1)
151#define HV_assign_ipspc_server_connection_status_notification_port \
152 __BEAT_ADD_VENDOR_ID(0x173, 1)
153#define HV_get_raid_of_physical_spe __BEAT_ADD_VENDOR_ID(0x174, 1)
154#define HV_set_physical_spe_to_rag __BEAT_ADD_VENDOR_ID(0x175, 1)
155#define HV_release_physical_spe_from_rag __BEAT_ADD_VENDOR_ID(0x176, 1)
156#define HV_rtc_read __BEAT_ADD_VENDOR_ID(0x190, 1)
157#define HV_rtc_write __BEAT_ADD_VENDOR_ID(0x191, 1)
158#define HV_eeprom_read __BEAT_ADD_VENDOR_ID(0x192, 1)
159#define HV_eeprom_write __BEAT_ADD_VENDOR_ID(0x193, 1)
160#define HV_insert_htab_entry3 __BEAT_ADD_VENDOR_ID(0x104, 1)
161#define HV_invalidate_htab_entry3 __BEAT_ADD_VENDOR_ID(0x105, 1)
162#define HV_update_htab_permission3 __BEAT_ADD_VENDOR_ID(0x106, 1)
163#define HV_clear_htab3 __BEAT_ADD_VENDOR_ID(0x107, 1)
164#endif
diff --git a/arch/powerpc/platforms/cell/beat_udbg.c b/arch/powerpc/platforms/cell/beat_udbg.c
deleted file mode 100644
index 350735bc8888..000000000000
--- a/arch/powerpc/platforms/cell/beat_udbg.c
+++ /dev/null
@@ -1,98 +0,0 @@
1/*
2 * udbg function for Beat
3 *
4 * (C) Copyright 2006 TOSHIBA CORPORATION
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <linux/kernel.h>
22#include <linux/console.h>
23
24#include <asm/machdep.h>
25#include <asm/prom.h>
26#include <asm/udbg.h>
27
28#include "beat.h"
29
30#define celleb_vtermno 0
31
32static void udbg_putc_beat(char c)
33{
34 unsigned long rc;
35
36 if (c == '\n')
37 udbg_putc_beat('\r');
38
39 rc = beat_put_term_char(celleb_vtermno, 1, (uint64_t)c << 56, 0);
40}
41
42/* Buffered chars getc */
43static u64 inbuflen;
44static u64 inbuf[2]; /* must be 2 u64s */
45
46static int udbg_getc_poll_beat(void)
47{
48 /* The interface is tricky because it may return up to 16 chars.
49 * We save them statically for future calls to udbg_getc().
50 */
51 char ch, *buf = (char *)inbuf;
52 int i;
53 long rc;
54 if (inbuflen == 0) {
55 /* get some more chars. */
56 inbuflen = 0;
57 rc = beat_get_term_char(celleb_vtermno, &inbuflen,
58 inbuf+0, inbuf+1);
59 if (rc != 0)
60 inbuflen = 0; /* otherwise inbuflen is garbage */
61 }
62 if (inbuflen <= 0 || inbuflen > 16) {
63 /* Catch error case as well as other oddities (corruption) */
64 inbuflen = 0;
65 return -1;
66 }
67 ch = buf[0];
68 for (i = 1; i < inbuflen; i++) /* shuffle them down. */
69 buf[i-1] = buf[i];
70 inbuflen--;
71 return ch;
72}
73
74static int udbg_getc_beat(void)
75{
76 int ch;
77 for (;;) {
78 ch = udbg_getc_poll_beat();
79 if (ch == -1) {
80 /* This shouldn't be needed...but... */
81 volatile unsigned long delay;
82 for (delay = 0; delay < 2000000; delay++)
83 ;
84 } else {
85 return ch;
86 }
87 }
88}
89
90/* call this from early_init() for a working debug console on
91 * vterm capable LPAR machines
92 */
93void __init udbg_init_debug_beat(void)
94{
95 udbg_putc = udbg_putc_beat;
96 udbg_getc = udbg_getc_beat;
97 udbg_getc_poll = udbg_getc_poll_beat;
98}
diff --git a/arch/powerpc/platforms/cell/beat_wrapper.h b/arch/powerpc/platforms/cell/beat_wrapper.h
deleted file mode 100644
index c1109969f242..000000000000
--- a/arch/powerpc/platforms/cell/beat_wrapper.h
+++ /dev/null
@@ -1,290 +0,0 @@
1/*
2 * Beat hypervisor call I/F
3 *
4 * (C) Copyright 2007 TOSHIBA CORPORATION
5 *
6 * This code is based on arch/powerpc/platforms/pseries/plpar_wrapper.h.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
21 */
22#ifndef BEAT_HCALL
23#include <linux/string.h>
24#include "beat_syscall.h"
25
26/* defined in hvCall.S */
27extern s64 beat_hcall_norets(u64 opcode, ...);
28extern s64 beat_hcall_norets8(u64 opcode, u64 arg1, u64 arg2, u64 arg3,
29 u64 arg4, u64 arg5, u64 arg6, u64 arg7, u64 arg8);
30extern s64 beat_hcall1(u64 opcode, u64 retbuf[1], ...);
31extern s64 beat_hcall2(u64 opcode, u64 retbuf[2], ...);
32extern s64 beat_hcall3(u64 opcode, u64 retbuf[3], ...);
33extern s64 beat_hcall4(u64 opcode, u64 retbuf[4], ...);
34extern s64 beat_hcall5(u64 opcode, u64 retbuf[5], ...);
35extern s64 beat_hcall6(u64 opcode, u64 retbuf[6], ...);
36
37static inline s64 beat_downcount_of_interrupt(u64 plug_id)
38{
39 return beat_hcall_norets(HV_downcount_of_interrupt, plug_id);
40}
41
42static inline s64 beat_set_interrupt_mask(u64 index,
43 u64 val0, u64 val1, u64 val2, u64 val3)
44{
45 return beat_hcall_norets(HV_set_interrupt_mask, index,
46 val0, val1, val2, val3);
47}
48
49static inline s64 beat_destruct_irq_plug(u64 plug_id)
50{
51 return beat_hcall_norets(HV_destruct_irq_plug, plug_id);
52}
53
54static inline s64 beat_construct_and_connect_irq_plug(u64 plug_id,
55 u64 outlet_id)
56{
57 return beat_hcall_norets(HV_construct_and_connect_irq_plug, plug_id,
58 outlet_id);
59}
60
61static inline s64 beat_detect_pending_interrupts(u64 index, u64 *retbuf)
62{
63 return beat_hcall4(HV_detect_pending_interrupts, retbuf, index);
64}
65
66static inline s64 beat_pause(u64 style)
67{
68 return beat_hcall_norets(HV_pause, style);
69}
70
71static inline s64 beat_read_htab_entries(u64 htab_id, u64 index, u64 *retbuf)
72{
73 return beat_hcall5(HV_read_htab_entries, retbuf, htab_id, index);
74}
75
76static inline s64 beat_insert_htab_entry(u64 htab_id, u64 group,
77 u64 bitmask, u64 hpte_v, u64 hpte_r, u64 *slot)
78{
79 u64 dummy[3];
80 s64 ret;
81
82 ret = beat_hcall3(HV_insert_htab_entry, dummy, htab_id, group,
83 bitmask, hpte_v, hpte_r);
84 *slot = dummy[0];
85 return ret;
86}
87
88static inline s64 beat_write_htab_entry(u64 htab_id, u64 slot,
89 u64 hpte_v, u64 hpte_r, u64 mask_v, u64 mask_r,
90 u64 *ret_v, u64 *ret_r)
91{
92 u64 dummy[2];
93 s64 ret;
94
95 ret = beat_hcall2(HV_write_htab_entry, dummy, htab_id, slot,
96 hpte_v, hpte_r, mask_v, mask_r);
97 *ret_v = dummy[0];
98 *ret_r = dummy[1];
99 return ret;
100}
101
102static inline s64 beat_insert_htab_entry3(u64 htab_id, u64 group,
103 u64 hpte_v, u64 hpte_r, u64 mask_v, u64 value_v, u64 *slot)
104{
105 u64 dummy[1];
106 s64 ret;
107
108 ret = beat_hcall1(HV_insert_htab_entry3, dummy, htab_id, group,
109 hpte_v, hpte_r, mask_v, value_v);
110 *slot = dummy[0];
111 return ret;
112}
113
114static inline s64 beat_invalidate_htab_entry3(u64 htab_id, u64 group,
115 u64 va, u64 pss)
116{
117 return beat_hcall_norets(HV_invalidate_htab_entry3,
118 htab_id, group, va, pss);
119}
120
121static inline s64 beat_update_htab_permission3(u64 htab_id, u64 group,
122 u64 va, u64 pss, u64 ptel_mask, u64 ptel_value)
123{
124 return beat_hcall_norets(HV_update_htab_permission3,
125 htab_id, group, va, pss, ptel_mask, ptel_value);
126}
127
128static inline s64 beat_clear_htab3(u64 htab_id)
129{
130 return beat_hcall_norets(HV_clear_htab3, htab_id);
131}
132
133static inline void beat_shutdown_logical_partition(u64 code)
134{
135 (void)beat_hcall_norets(HV_shutdown_logical_partition, code);
136}
137
138static inline s64 beat_rtc_write(u64 time_from_epoch)
139{
140 return beat_hcall_norets(HV_rtc_write, time_from_epoch);
141}
142
143static inline s64 beat_rtc_read(u64 *time_from_epoch)
144{
145 u64 dummy[1];
146 s64 ret;
147
148 ret = beat_hcall1(HV_rtc_read, dummy);
149 *time_from_epoch = dummy[0];
150 return ret;
151}
152
153#define BEAT_NVRW_CNT (sizeof(u64) * 6)
154
155static inline s64 beat_eeprom_write(u64 index, u64 length, u8 *buffer)
156{
157 u64 b[6];
158
159 if (length > BEAT_NVRW_CNT)
160 return -1;
161 memcpy(b, buffer, sizeof(b));
162 return beat_hcall_norets8(HV_eeprom_write, index, length,
163 b[0], b[1], b[2], b[3], b[4], b[5]);
164}
165
166static inline s64 beat_eeprom_read(u64 index, u64 length, u8 *buffer)
167{
168 u64 b[6];
169 s64 ret;
170
171 if (length > BEAT_NVRW_CNT)
172 return -1;
173 ret = beat_hcall6(HV_eeprom_read, b, index, length);
174 memcpy(buffer, b, length);
175 return ret;
176}
177
178static inline s64 beat_set_dabr(u64 value, u64 style)
179{
180 return beat_hcall_norets(HV_set_dabr, value, style);
181}
182
183static inline s64 beat_get_characters_from_console(u64 termno, u64 *len,
184 u8 *buffer)
185{
186 u64 dummy[3];
187 s64 ret;
188
189 ret = beat_hcall3(HV_get_characters_from_console, dummy, termno, len);
190 *len = dummy[0];
191 memcpy(buffer, dummy + 1, *len);
192 return ret;
193}
194
195static inline s64 beat_put_characters_to_console(u64 termno, u64 len,
196 u8 *buffer)
197{
198 u64 b[2];
199
200 memcpy(b, buffer, len);
201 return beat_hcall_norets(HV_put_characters_to_console, termno, len,
202 b[0], b[1]);
203}
204
205static inline s64 beat_get_spe_privileged_state_1_registers(
206 u64 id, u64 offsetof, u64 *value)
207{
208 u64 dummy[1];
209 s64 ret;
210
211 ret = beat_hcall1(HV_get_spe_privileged_state_1_registers, dummy, id,
212 offsetof);
213 *value = dummy[0];
214 return ret;
215}
216
217static inline s64 beat_set_irq_mask_for_spe(u64 id, u64 class, u64 mask)
218{
219 return beat_hcall_norets(HV_set_irq_mask_for_spe, id, class, mask);
220}
221
222static inline s64 beat_clear_interrupt_status_of_spe(u64 id, u64 class,
223 u64 mask)
224{
225 return beat_hcall_norets(HV_clear_interrupt_status_of_spe,
226 id, class, mask);
227}
228
229static inline s64 beat_set_spe_privileged_state_1_registers(
230 u64 id, u64 offsetof, u64 value)
231{
232 return beat_hcall_norets(HV_set_spe_privileged_state_1_registers,
233 id, offsetof, value);
234}
235
236static inline s64 beat_get_interrupt_status_of_spe(u64 id, u64 class, u64 *val)
237{
238 u64 dummy[1];
239 s64 ret;
240
241 ret = beat_hcall1(HV_get_interrupt_status_of_spe, dummy, id, class);
242 *val = dummy[0];
243 return ret;
244}
245
246static inline s64 beat_put_iopte(u64 ioas_id, u64 io_addr, u64 real_addr,
247 u64 ioid, u64 flags)
248{
249 return beat_hcall_norets(HV_put_iopte, ioas_id, io_addr, real_addr,
250 ioid, flags);
251}
252
253static inline s64 beat_construct_event_receive_port(u64 *port)
254{
255 u64 dummy[1];
256 s64 ret;
257
258 ret = beat_hcall1(HV_construct_event_receive_port, dummy);
259 *port = dummy[0];
260 return ret;
261}
262
263static inline s64 beat_destruct_event_receive_port(u64 port)
264{
265 s64 ret;
266
267 ret = beat_hcall_norets(HV_destruct_event_receive_port, port);
268 return ret;
269}
270
271static inline s64 beat_create_repository_node(u64 path[4], u64 data[2])
272{
273 s64 ret;
274
275 ret = beat_hcall_norets(HV_create_repository_node2,
276 path[0], path[1], path[2], path[3], data[0], data[1]);
277 return ret;
278}
279
280static inline s64 beat_get_repository_node_value(u64 lpid, u64 path[4],
281 u64 data[2])
282{
283 s64 ret;
284
285 ret = beat_hcall2(HV_get_repository_node_value2, data,
286 lpid, path[0], path[1], path[2], path[3]);
287 return ret;
288}
289
290#endif
diff --git a/arch/powerpc/platforms/cell/cell.h b/arch/powerpc/platforms/cell/cell.h
new file mode 100644
index 000000000000..ef143dfee068
--- /dev/null
+++ b/arch/powerpc/platforms/cell/cell.h
@@ -0,0 +1,24 @@
1/*
2 * Cell Platform common data structures
3 *
4 * Copyright 2015, Daniel Axtens, IBM Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2, or (at your option)
9 * any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#ifndef CELL_H
18#define CELL_H
19
20#include <asm/pci-bridge.h>
21
22extern struct pci_controller_ops cell_pci_controller_ops;
23
24#endif
diff --git a/arch/powerpc/platforms/cell/celleb_pci.c b/arch/powerpc/platforms/cell/celleb_pci.c
deleted file mode 100644
index 3ce70ded2d6a..000000000000
--- a/arch/powerpc/platforms/cell/celleb_pci.c
+++ /dev/null
@@ -1,500 +0,0 @@
1/*
2 * Support for PCI on Celleb platform.
3 *
4 * (C) Copyright 2006-2007 TOSHIBA CORPORATION
5 *
6 * This code is based on arch/powerpc/kernel/rtas_pci.c:
7 * Copyright (C) 2001 Dave Engebretsen, IBM Corporation
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
23 */
24
25#undef DEBUG
26
27#include <linux/kernel.h>
28#include <linux/threads.h>
29#include <linux/pci.h>
30#include <linux/string.h>
31#include <linux/init.h>
32#include <linux/memblock.h>
33#include <linux/pci_regs.h>
34#include <linux/of.h>
35#include <linux/of_device.h>
36#include <linux/slab.h>
37
38#include <asm/io.h>
39#include <asm/irq.h>
40#include <asm/prom.h>
41#include <asm/pci-bridge.h>
42#include <asm/ppc-pci.h>
43
44#include "celleb_pci.h"
45
46#define MAX_PCI_DEVICES 32
47#define MAX_PCI_FUNCTIONS 8
48#define MAX_PCI_BASE_ADDRS 3 /* use 64 bit address */
49
50/* definition for fake pci configuration area for GbE, .... ,and etc. */
51
52struct celleb_pci_resource {
53 struct resource r[MAX_PCI_BASE_ADDRS];
54};
55
56struct celleb_pci_private {
57 unsigned char *fake_config[MAX_PCI_DEVICES][MAX_PCI_FUNCTIONS];
58 struct celleb_pci_resource *res[MAX_PCI_DEVICES][MAX_PCI_FUNCTIONS];
59};
60
61static inline u8 celleb_fake_config_readb(void *addr)
62{
63 u8 *p = addr;
64 return *p;
65}
66
67static inline u16 celleb_fake_config_readw(void *addr)
68{
69 __le16 *p = addr;
70 return le16_to_cpu(*p);
71}
72
73static inline u32 celleb_fake_config_readl(void *addr)
74{
75 __le32 *p = addr;
76 return le32_to_cpu(*p);
77}
78
79static inline void celleb_fake_config_writeb(u32 val, void *addr)
80{
81 u8 *p = addr;
82 *p = val;
83}
84
85static inline void celleb_fake_config_writew(u32 val, void *addr)
86{
87 __le16 val16;
88 __le16 *p = addr;
89 val16 = cpu_to_le16(val);
90 *p = val16;
91}
92
93static inline void celleb_fake_config_writel(u32 val, void *addr)
94{
95 __le32 val32;
96 __le32 *p = addr;
97 val32 = cpu_to_le32(val);
98 *p = val32;
99}
100
101static unsigned char *get_fake_config_start(struct pci_controller *hose,
102 int devno, int fn)
103{
104 struct celleb_pci_private *private = hose->private_data;
105
106 if (private == NULL)
107 return NULL;
108
109 return private->fake_config[devno][fn];
110}
111
112static struct celleb_pci_resource *get_resource_start(
113 struct pci_controller *hose,
114 int devno, int fn)
115{
116 struct celleb_pci_private *private = hose->private_data;
117
118 if (private == NULL)
119 return NULL;
120
121 return private->res[devno][fn];
122}
123
124
125static void celleb_config_read_fake(unsigned char *config, int where,
126 int size, u32 *val)
127{
128 char *p = config + where;
129
130 switch (size) {
131 case 1:
132 *val = celleb_fake_config_readb(p);
133 break;
134 case 2:
135 *val = celleb_fake_config_readw(p);
136 break;
137 case 4:
138 *val = celleb_fake_config_readl(p);
139 break;
140 }
141}
142
143static void celleb_config_write_fake(unsigned char *config, int where,
144 int size, u32 val)
145{
146 char *p = config + where;
147
148 switch (size) {
149 case 1:
150 celleb_fake_config_writeb(val, p);
151 break;
152 case 2:
153 celleb_fake_config_writew(val, p);
154 break;
155 case 4:
156 celleb_fake_config_writel(val, p);
157 break;
158 }
159}
160
161static int celleb_fake_pci_read_config(struct pci_bus *bus,
162 unsigned int devfn, int where, int size, u32 *val)
163{
164 char *config;
165 struct pci_controller *hose = pci_bus_to_host(bus);
166 unsigned int devno = devfn >> 3;
167 unsigned int fn = devfn & 0x7;
168
169 /* allignment check */
170 BUG_ON(where % size);
171
172 pr_debug(" fake read: bus=0x%x, ", bus->number);
173 config = get_fake_config_start(hose, devno, fn);
174
175 pr_debug("devno=0x%x, where=0x%x, size=0x%x, ", devno, where, size);
176 if (!config) {
177 pr_debug("failed\n");
178 return PCIBIOS_DEVICE_NOT_FOUND;
179 }
180
181 celleb_config_read_fake(config, where, size, val);
182 pr_debug("val=0x%x\n", *val);
183
184 return PCIBIOS_SUCCESSFUL;
185}
186
187
188static int celleb_fake_pci_write_config(struct pci_bus *bus,
189 unsigned int devfn, int where, int size, u32 val)
190{
191 char *config;
192 struct pci_controller *hose = pci_bus_to_host(bus);
193 struct celleb_pci_resource *res;
194 unsigned int devno = devfn >> 3;
195 unsigned int fn = devfn & 0x7;
196
197 /* allignment check */
198 BUG_ON(where % size);
199
200 config = get_fake_config_start(hose, devno, fn);
201
202 if (!config)
203 return PCIBIOS_DEVICE_NOT_FOUND;
204
205 if (val == ~0) {
206 int i = (where - PCI_BASE_ADDRESS_0) >> 3;
207
208 switch (where) {
209 case PCI_BASE_ADDRESS_0:
210 case PCI_BASE_ADDRESS_2:
211 if (size != 4)
212 return PCIBIOS_DEVICE_NOT_FOUND;
213 res = get_resource_start(hose, devno, fn);
214 if (!res)
215 return PCIBIOS_DEVICE_NOT_FOUND;
216 celleb_config_write_fake(config, where, size,
217 (res->r[i].end - res->r[i].start));
218 return PCIBIOS_SUCCESSFUL;
219 case PCI_BASE_ADDRESS_1:
220 case PCI_BASE_ADDRESS_3:
221 case PCI_BASE_ADDRESS_4:
222 case PCI_BASE_ADDRESS_5:
223 break;
224 default:
225 break;
226 }
227 }
228
229 celleb_config_write_fake(config, where, size, val);
230 pr_debug(" fake write: where=%x, size=%d, val=%x\n",
231 where, size, val);
232
233 return PCIBIOS_SUCCESSFUL;
234}
235
236static struct pci_ops celleb_fake_pci_ops = {
237 .read = celleb_fake_pci_read_config,
238 .write = celleb_fake_pci_write_config,
239};
240
241static inline void celleb_setup_pci_base_addrs(struct pci_controller *hose,
242 unsigned int devno, unsigned int fn,
243 unsigned int num_base_addr)
244{
245 u32 val;
246 unsigned char *config;
247 struct celleb_pci_resource *res;
248
249 config = get_fake_config_start(hose, devno, fn);
250 res = get_resource_start(hose, devno, fn);
251
252 if (!config || !res)
253 return;
254
255 switch (num_base_addr) {
256 case 3:
257 val = (res->r[2].start & 0xfffffff0)
258 | PCI_BASE_ADDRESS_MEM_TYPE_64;
259 celleb_config_write_fake(config, PCI_BASE_ADDRESS_4, 4, val);
260 val = res->r[2].start >> 32;
261 celleb_config_write_fake(config, PCI_BASE_ADDRESS_5, 4, val);
262 /* FALLTHROUGH */
263 case 2:
264 val = (res->r[1].start & 0xfffffff0)
265 | PCI_BASE_ADDRESS_MEM_TYPE_64;
266 celleb_config_write_fake(config, PCI_BASE_ADDRESS_2, 4, val);
267 val = res->r[1].start >> 32;
268 celleb_config_write_fake(config, PCI_BASE_ADDRESS_3, 4, val);
269 /* FALLTHROUGH */
270 case 1:
271 val = (res->r[0].start & 0xfffffff0)
272 | PCI_BASE_ADDRESS_MEM_TYPE_64;
273 celleb_config_write_fake(config, PCI_BASE_ADDRESS_0, 4, val);
274 val = res->r[0].start >> 32;
275 celleb_config_write_fake(config, PCI_BASE_ADDRESS_1, 4, val);
276 break;
277 }
278
279 val = PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
280 celleb_config_write_fake(config, PCI_COMMAND, 2, val);
281}
282
283static int __init celleb_setup_fake_pci_device(struct device_node *node,
284 struct pci_controller *hose)
285{
286 unsigned int rlen;
287 int num_base_addr = 0;
288 u32 val;
289 const u32 *wi0, *wi1, *wi2, *wi3, *wi4;
290 unsigned int devno, fn;
291 struct celleb_pci_private *private = hose->private_data;
292 unsigned char **config = NULL;
293 struct celleb_pci_resource **res = NULL;
294 const char *name;
295 const unsigned long *li;
296 int size, result;
297
298 if (private == NULL) {
299 printk(KERN_ERR "PCI: "
300 "memory space for pci controller is not assigned\n");
301 goto error;
302 }
303
304 name = of_get_property(node, "model", &rlen);
305 if (!name) {
306 printk(KERN_ERR "PCI: model property not found.\n");
307 goto error;
308 }
309
310 wi4 = of_get_property(node, "reg", &rlen);
311 if (wi4 == NULL)
312 goto error;
313
314 devno = ((wi4[0] >> 8) & 0xff) >> 3;
315 fn = (wi4[0] >> 8) & 0x7;
316
317 pr_debug("PCI: celleb_setup_fake_pci() %s devno=%x fn=%x\n", name,
318 devno, fn);
319
320 size = 256;
321 config = &private->fake_config[devno][fn];
322 *config = zalloc_maybe_bootmem(size, GFP_KERNEL);
323 if (*config == NULL) {
324 printk(KERN_ERR "PCI: "
325 "not enough memory for fake configuration space\n");
326 goto error;
327 }
328 pr_debug("PCI: fake config area assigned 0x%016lx\n",
329 (unsigned long)*config);
330
331 size = sizeof(struct celleb_pci_resource);
332 res = &private->res[devno][fn];
333 *res = zalloc_maybe_bootmem(size, GFP_KERNEL);
334 if (*res == NULL) {
335 printk(KERN_ERR
336 "PCI: not enough memory for resource data space\n");
337 goto error;
338 }
339 pr_debug("PCI: res assigned 0x%016lx\n", (unsigned long)*res);
340
341 wi0 = of_get_property(node, "device-id", NULL);
342 wi1 = of_get_property(node, "vendor-id", NULL);
343 wi2 = of_get_property(node, "class-code", NULL);
344 wi3 = of_get_property(node, "revision-id", NULL);
345 if (!wi0 || !wi1 || !wi2 || !wi3) {
346 printk(KERN_ERR "PCI: Missing device tree properties.\n");
347 goto error;
348 }
349
350 celleb_config_write_fake(*config, PCI_DEVICE_ID, 2, wi0[0] & 0xffff);
351 celleb_config_write_fake(*config, PCI_VENDOR_ID, 2, wi1[0] & 0xffff);
352 pr_debug("class-code = 0x%08x\n", wi2[0]);
353
354 celleb_config_write_fake(*config, PCI_CLASS_PROG, 1, wi2[0] & 0xff);
355 celleb_config_write_fake(*config, PCI_CLASS_DEVICE, 2,
356 (wi2[0] >> 8) & 0xffff);
357 celleb_config_write_fake(*config, PCI_REVISION_ID, 1, wi3[0]);
358
359 while (num_base_addr < MAX_PCI_BASE_ADDRS) {
360 result = of_address_to_resource(node,
361 num_base_addr, &(*res)->r[num_base_addr]);
362 if (result)
363 break;
364 num_base_addr++;
365 }
366
367 celleb_setup_pci_base_addrs(hose, devno, fn, num_base_addr);
368
369 li = of_get_property(node, "interrupts", &rlen);
370 if (!li) {
371 printk(KERN_ERR "PCI: interrupts not found.\n");
372 goto error;
373 }
374 val = li[0];
375 celleb_config_write_fake(*config, PCI_INTERRUPT_PIN, 1, 1);
376 celleb_config_write_fake(*config, PCI_INTERRUPT_LINE, 1, val);
377
378#ifdef DEBUG
379 pr_debug("PCI: %s irq=%ld\n", name, li[0]);
380 for (i = 0; i < 6; i++) {
381 celleb_config_read_fake(*config,
382 PCI_BASE_ADDRESS_0 + 0x4 * i, 4,
383 &val);
384 pr_debug("PCI: %s fn=%d base_address_%d=0x%x\n",
385 name, fn, i, val);
386 }
387#endif
388
389 celleb_config_write_fake(*config, PCI_HEADER_TYPE, 1,
390 PCI_HEADER_TYPE_NORMAL);
391
392 return 0;
393
394error:
395 if (mem_init_done) {
396 if (config && *config)
397 kfree(*config);
398 if (res && *res)
399 kfree(*res);
400
401 } else {
402 if (config && *config) {
403 size = 256;
404 memblock_free(__pa(*config), size);
405 }
406 if (res && *res) {
407 size = sizeof(struct celleb_pci_resource);
408 memblock_free(__pa(*res), size);
409 }
410 }
411
412 return 1;
413}
414
415static int __init phb_set_bus_ranges(struct device_node *dev,
416 struct pci_controller *phb)
417{
418 const int *bus_range;
419 unsigned int len;
420
421 bus_range = of_get_property(dev, "bus-range", &len);
422 if (bus_range == NULL || len < 2 * sizeof(int))
423 return 1;
424
425 phb->first_busno = bus_range[0];
426 phb->last_busno = bus_range[1];
427
428 return 0;
429}
430
431static void __init celleb_alloc_private_mem(struct pci_controller *hose)
432{
433 hose->private_data =
434 zalloc_maybe_bootmem(sizeof(struct celleb_pci_private),
435 GFP_KERNEL);
436}
437
438static int __init celleb_setup_fake_pci(struct device_node *dev,
439 struct pci_controller *phb)
440{
441 struct device_node *node;
442
443 phb->ops = &celleb_fake_pci_ops;
444 celleb_alloc_private_mem(phb);
445
446 for (node = of_get_next_child(dev, NULL);
447 node != NULL; node = of_get_next_child(dev, node))
448 celleb_setup_fake_pci_device(node, phb);
449
450 return 0;
451}
452
453static struct celleb_phb_spec celleb_fake_pci_spec __initdata = {
454 .setup = celleb_setup_fake_pci,
455};
456
457static const struct of_device_id celleb_phb_match[] __initconst = {
458 {
459 .name = "pci-pseudo",
460 .data = &celleb_fake_pci_spec,
461 }, {
462 .name = "epci",
463 .data = &celleb_epci_spec,
464 }, {
465 .name = "pcie",
466 .data = &celleb_pciex_spec,
467 }, {
468 },
469};
470
471int __init celleb_setup_phb(struct pci_controller *phb)
472{
473 struct device_node *dev = phb->dn;
474 const struct of_device_id *match;
475 const struct celleb_phb_spec *phb_spec;
476 int rc;
477
478 match = of_match_node(celleb_phb_match, dev);
479 if (!match)
480 return 1;
481
482 phb_set_bus_ranges(dev, phb);
483 phb->buid = 1;
484
485 phb_spec = match->data;
486 rc = (*phb_spec->setup)(dev, phb);
487 if (rc)
488 return 1;
489
490 if (phb_spec->ops)
491 iowa_register_bus(phb, phb_spec->ops,
492 phb_spec->iowa_init,
493 phb_spec->iowa_data);
494 return 0;
495}
496
497int celleb_pci_probe_mode(struct pci_bus *bus)
498{
499 return PCI_PROBE_DEVTREE;
500}
diff --git a/arch/powerpc/platforms/cell/celleb_pci.h b/arch/powerpc/platforms/cell/celleb_pci.h
deleted file mode 100644
index a801fcc5f389..000000000000
--- a/arch/powerpc/platforms/cell/celleb_pci.h
+++ /dev/null
@@ -1,46 +0,0 @@
1/*
2 * pci prototypes for Celleb platform
3 *
4 * (C) Copyright 2006-2007 TOSHIBA CORPORATION
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#ifndef _CELLEB_PCI_H
22#define _CELLEB_PCI_H
23
24#include <linux/pci.h>
25
26#include <asm/pci-bridge.h>
27#include <asm/prom.h>
28#include <asm/ppc-pci.h>
29#include <asm/io-workarounds.h>
30
31struct iowa_bus;
32
33struct celleb_phb_spec {
34 int (*setup)(struct device_node *, struct pci_controller *);
35 struct ppc_pci_io *ops;
36 int (*iowa_init)(struct iowa_bus *, void *);
37 void *iowa_data;
38};
39
40extern int celleb_setup_phb(struct pci_controller *);
41extern int celleb_pci_probe_mode(struct pci_bus *);
42
43extern struct celleb_phb_spec celleb_epci_spec;
44extern struct celleb_phb_spec celleb_pciex_spec;
45
46#endif /* _CELLEB_PCI_H */
diff --git a/arch/powerpc/platforms/cell/celleb_scc.h b/arch/powerpc/platforms/cell/celleb_scc.h
deleted file mode 100644
index b596a711c348..000000000000
--- a/arch/powerpc/platforms/cell/celleb_scc.h
+++ /dev/null
@@ -1,232 +0,0 @@
1/*
2 * SCC (Super Companion Chip) definitions
3 *
4 * (C) Copyright 2004-2006 TOSHIBA CORPORATION
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#ifndef _CELLEB_SCC_H
22#define _CELLEB_SCC_H
23
24#define PCI_VENDOR_ID_TOSHIBA_2 0x102f
25#define PCI_DEVICE_ID_TOSHIBA_SCC_PCIEXC_BRIDGE 0x01b0
26#define PCI_DEVICE_ID_TOSHIBA_SCC_EPCI_BRIDGE 0x01b1
27#define PCI_DEVICE_ID_TOSHIBA_SCC_BRIDGE 0x01b2
28#define PCI_DEVICE_ID_TOSHIBA_SCC_GBE 0x01b3
29#define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4
30#define PCI_DEVICE_ID_TOSHIBA_SCC_USB2 0x01b5
31#define PCI_DEVICE_ID_TOSHIBA_SCC_USB 0x01b6
32#define PCI_DEVICE_ID_TOSHIBA_SCC_ENCDEC 0x01b7
33
34#define SCC_EPCI_REG 0x0000d000
35
36/* EPCI registers */
37#define SCC_EPCI_CNF10_REG 0x010
38#define SCC_EPCI_CNF14_REG 0x014
39#define SCC_EPCI_CNF18_REG 0x018
40#define SCC_EPCI_PVBAT 0x100
41#define SCC_EPCI_VPMBAT 0x104
42#define SCC_EPCI_VPIBAT 0x108
43#define SCC_EPCI_VCSR 0x110
44#define SCC_EPCI_VIENAB 0x114
45#define SCC_EPCI_VISTAT 0x118
46#define SCC_EPCI_VRDCOUNT 0x124
47#define SCC_EPCI_BAM0 0x12c
48#define SCC_EPCI_BAM1 0x134
49#define SCC_EPCI_BAM2 0x13c
50#define SCC_EPCI_IADR 0x164
51#define SCC_EPCI_CLKRST 0x800
52#define SCC_EPCI_INTSET 0x804
53#define SCC_EPCI_STATUS 0x808
54#define SCC_EPCI_ABTSET 0x80c
55#define SCC_EPCI_WATRP 0x810
56#define SCC_EPCI_DUMYRADR 0x814
57#define SCC_EPCI_SWRESP 0x818
58#define SCC_EPCI_CNTOPT 0x81c
59#define SCC_EPCI_ECMODE 0xf00
60#define SCC_EPCI_IOM_AC_NUM 5
61#define SCC_EPCI_IOM_ACTE(n) (0xf10 + (n) * 4)
62#define SCC_EPCI_IOT_AC_NUM 4
63#define SCC_EPCI_IOT_ACTE(n) (0xf30 + (n) * 4)
64#define SCC_EPCI_MAEA 0xf50
65#define SCC_EPCI_MAEC 0xf54
66#define SCC_EPCI_CKCTRL 0xff0
67
68/* bits for SCC_EPCI_VCSR */
69#define SCC_EPCI_VCSR_FRE 0x00020000
70#define SCC_EPCI_VCSR_FWE 0x00010000
71#define SCC_EPCI_VCSR_DR 0x00000400
72#define SCC_EPCI_VCSR_SR 0x00000008
73#define SCC_EPCI_VCSR_AT 0x00000004
74
75/* bits for SCC_EPCI_VIENAB/SCC_EPCI_VISTAT */
76#define SCC_EPCI_VISTAT_PMPE 0x00000008
77#define SCC_EPCI_VISTAT_PMFE 0x00000004
78#define SCC_EPCI_VISTAT_PRA 0x00000002
79#define SCC_EPCI_VISTAT_PRD 0x00000001
80#define SCC_EPCI_VISTAT_ALL 0x0000000f
81
82#define SCC_EPCI_VIENAB_PMPEE 0x00000008
83#define SCC_EPCI_VIENAB_PMFEE 0x00000004
84#define SCC_EPCI_VIENAB_PRA 0x00000002
85#define SCC_EPCI_VIENAB_PRD 0x00000001
86#define SCC_EPCI_VIENAB_ALL 0x0000000f
87
88/* bits for SCC_EPCI_CLKRST */
89#define SCC_EPCI_CLKRST_CKS_MASK 0x00030000
90#define SCC_EPCI_CLKRST_CKS_2 0x00000000
91#define SCC_EPCI_CLKRST_CKS_4 0x00010000
92#define SCC_EPCI_CLKRST_CKS_8 0x00020000
93#define SCC_EPCI_CLKRST_PCICRST 0x00000400
94#define SCC_EPCI_CLKRST_BC 0x00000200
95#define SCC_EPCI_CLKRST_PCIRST 0x00000100
96#define SCC_EPCI_CLKRST_PCKEN 0x00000001
97
98/* bits for SCC_EPCI_INTSET/SCC_EPCI_STATUS */
99#define SCC_EPCI_INT_2M 0x01000000
100#define SCC_EPCI_INT_RERR 0x00200000
101#define SCC_EPCI_INT_SERR 0x00100000
102#define SCC_EPCI_INT_PRTER 0x00080000
103#define SCC_EPCI_INT_SER 0x00040000
104#define SCC_EPCI_INT_PER 0x00020000
105#define SCC_EPCI_INT_PAI 0x00010000
106#define SCC_EPCI_INT_1M 0x00000100
107#define SCC_EPCI_INT_PME 0x00000010
108#define SCC_EPCI_INT_INTD 0x00000008
109#define SCC_EPCI_INT_INTC 0x00000004
110#define SCC_EPCI_INT_INTB 0x00000002
111#define SCC_EPCI_INT_INTA 0x00000001
112#define SCC_EPCI_INT_DEVINT 0x0000000f
113#define SCC_EPCI_INT_ALL 0x003f001f
114#define SCC_EPCI_INT_ALLERR 0x003f0000
115
116/* bits for SCC_EPCI_CKCTRL */
117#define SCC_EPCI_CKCTRL_CRST0 0x00010000
118#define SCC_EPCI_CKCTRL_CRST1 0x00020000
119#define SCC_EPCI_CKCTRL_OCLKEN 0x00000100
120#define SCC_EPCI_CKCTRL_LCLKEN 0x00000001
121
122#define SCC_EPCI_IDSEL_AD_TO_SLOT(ad) ((ad) - 10)
123#define SCC_EPCI_MAX_DEVNU SCC_EPCI_IDSEL_AD_TO_SLOT(32)
124
125/* bits for SCC_EPCI_CNTOPT */
126#define SCC_EPCI_CNTOPT_O2PMB 0x00000002
127
128/* SCC PCIEXC SMMIO registers */
129#define PEXCADRS 0x000
130#define PEXCWDATA 0x004
131#define PEXCRDATA 0x008
132#define PEXDADRS 0x010
133#define PEXDCMND 0x014
134#define PEXDWDATA 0x018
135#define PEXDRDATA 0x01c
136#define PEXREQID 0x020
137#define PEXTIDMAP 0x024
138#define PEXINTMASK 0x028
139#define PEXINTSTS 0x02c
140#define PEXAERRMASK 0x030
141#define PEXAERRSTS 0x034
142#define PEXPRERRMASK 0x040
143#define PEXPRERRSTS 0x044
144#define PEXPRERRID01 0x048
145#define PEXPRERRID23 0x04c
146#define PEXVDMASK 0x050
147#define PEXVDSTS 0x054
148#define PEXRCVCPLIDA 0x060
149#define PEXLENERRIDA 0x068
150#define PEXPHYPLLST 0x070
151#define PEXDMRDEN0 0x100
152#define PEXDMRDADR0 0x104
153#define PEXDMRDENX 0x110
154#define PEXDMRDADRX 0x114
155#define PEXECMODE 0xf00
156#define PEXMAEA(n) (0xf50 + (8 * n))
157#define PEXMAEC(n) (0xf54 + (8 * n))
158#define PEXCCRCTRL 0xff0
159
160/* SCC PCIEXC bits and shifts for PEXCADRS */
161#define PEXCADRS_BYTE_EN_SHIFT 20
162#define PEXCADRS_CMD_SHIFT 16
163#define PEXCADRS_CMD_READ (0xa << PEXCADRS_CMD_SHIFT)
164#define PEXCADRS_CMD_WRITE (0xb << PEXCADRS_CMD_SHIFT)
165
166/* SCC PCIEXC shifts for PEXDADRS */
167#define PEXDADRS_BUSNO_SHIFT 20
168#define PEXDADRS_DEVNO_SHIFT 15
169#define PEXDADRS_FUNCNO_SHIFT 12
170
171/* SCC PCIEXC bits and shifts for PEXDCMND */
172#define PEXDCMND_BYTE_EN_SHIFT 4
173#define PEXDCMND_IO_READ 0x2
174#define PEXDCMND_IO_WRITE 0x3
175#define PEXDCMND_CONFIG_READ 0xa
176#define PEXDCMND_CONFIG_WRITE 0xb
177
178/* SCC PCIEXC bits for PEXPHYPLLST */
179#define PEXPHYPLLST_PEXPHYAPLLST 0x00000001
180
181/* SCC PCIEXC bits for PEXECMODE */
182#define PEXECMODE_ALL_THROUGH 0x00000000
183#define PEXECMODE_ALL_8BIT 0x00550155
184#define PEXECMODE_ALL_16BIT 0x00aa02aa
185
186/* SCC PCIEXC bits for PEXCCRCTRL */
187#define PEXCCRCTRL_PEXIPCOREEN 0x00040000
188#define PEXCCRCTRL_PEXIPCONTEN 0x00020000
189#define PEXCCRCTRL_PEXPHYPLLEN 0x00010000
190#define PEXCCRCTRL_PCIEXCAOCKEN 0x00000100
191
192/* SCC PCIEXC port configuration registers */
193#define PEXTCERRCHK 0x21c
194#define PEXTAMAPB0 0x220
195#define PEXTAMAPL0 0x224
196#define PEXTAMAPB(n) (PEXTAMAPB0 + 8 * (n))
197#define PEXTAMAPL(n) (PEXTAMAPL0 + 8 * (n))
198#define PEXCHVC0P 0x500
199#define PEXCHVC0NP 0x504
200#define PEXCHVC0C 0x508
201#define PEXCDVC0P 0x50c
202#define PEXCDVC0NP 0x510
203#define PEXCDVC0C 0x514
204#define PEXCHVCXP 0x518
205#define PEXCHVCXNP 0x51c
206#define PEXCHVCXC 0x520
207#define PEXCDVCXP 0x524
208#define PEXCDVCXNP 0x528
209#define PEXCDVCXC 0x52c
210#define PEXCTTRG 0x530
211#define PEXTSCTRL 0x700
212#define PEXTSSTS 0x704
213#define PEXSKPCTRL 0x708
214
215/* UHC registers */
216#define SCC_UHC_CKRCTRL 0xff0
217#define SCC_UHC_ECMODE 0xf00
218
219/* bits for SCC_UHC_CKRCTRL */
220#define SCC_UHC_F48MCKLEN 0x00000001
221#define SCC_UHC_P_SUSPEND 0x00000002
222#define SCC_UHC_PHY_SUSPEND_SEL 0x00000004
223#define SCC_UHC_HCLKEN 0x00000100
224#define SCC_UHC_USBEN 0x00010000
225#define SCC_UHC_USBCEN 0x00020000
226#define SCC_UHC_PHYEN 0x00040000
227
228/* bits for SCC_UHC_ECMODE */
229#define SCC_UHC_ECMODE_BY_BYTE 0x00000555
230#define SCC_UHC_ECMODE_BY_WORD 0x00000aaa
231
232#endif /* _CELLEB_SCC_H */
diff --git a/arch/powerpc/platforms/cell/celleb_scc_epci.c b/arch/powerpc/platforms/cell/celleb_scc_epci.c
deleted file mode 100644
index 9438bbed402f..000000000000
--- a/arch/powerpc/platforms/cell/celleb_scc_epci.c
+++ /dev/null
@@ -1,428 +0,0 @@
1/*
2 * Support for SCC external PCI
3 *
4 * (C) Copyright 2004-2007 TOSHIBA CORPORATION
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#undef DEBUG
22
23#include <linux/kernel.h>
24#include <linux/threads.h>
25#include <linux/pci.h>
26#include <linux/init.h>
27#include <linux/pci_regs.h>
28
29#include <asm/io.h>
30#include <asm/irq.h>
31#include <asm/prom.h>
32#include <asm/pci-bridge.h>
33#include <asm/ppc-pci.h>
34
35#include "celleb_scc.h"
36#include "celleb_pci.h"
37
38#define MAX_PCI_DEVICES 32
39#define MAX_PCI_FUNCTIONS 8
40
41#define iob() __asm__ __volatile__("eieio; sync":::"memory")
42
43static inline PCI_IO_ADDR celleb_epci_get_epci_base(
44 struct pci_controller *hose)
45{
46 /*
47 * Note:
48 * Celleb epci uses cfg_addr as a base address for
49 * epci control registers.
50 */
51
52 return hose->cfg_addr;
53}
54
55static inline PCI_IO_ADDR celleb_epci_get_epci_cfg(
56 struct pci_controller *hose)
57{
58 /*
59 * Note:
60 * Celleb epci uses cfg_data as a base address for
61 * configuration area for epci devices.
62 */
63
64 return hose->cfg_data;
65}
66
67static inline void clear_and_disable_master_abort_interrupt(
68 struct pci_controller *hose)
69{
70 PCI_IO_ADDR epci_base;
71 PCI_IO_ADDR reg;
72 epci_base = celleb_epci_get_epci_base(hose);
73 reg = epci_base + PCI_COMMAND;
74 out_be32(reg, in_be32(reg) | (PCI_STATUS_REC_MASTER_ABORT << 16));
75}
76
77static int celleb_epci_check_abort(struct pci_controller *hose,
78 PCI_IO_ADDR addr)
79{
80 PCI_IO_ADDR reg;
81 PCI_IO_ADDR epci_base;
82 u32 val;
83
84 iob();
85 epci_base = celleb_epci_get_epci_base(hose);
86
87 reg = epci_base + PCI_COMMAND;
88 val = in_be32(reg);
89
90 if (val & (PCI_STATUS_REC_MASTER_ABORT << 16)) {
91 out_be32(reg,
92 (val & 0xffff) | (PCI_STATUS_REC_MASTER_ABORT << 16));
93
94 /* clear PCI Controller error, FRE, PMFE */
95 reg = epci_base + SCC_EPCI_STATUS;
96 out_be32(reg, SCC_EPCI_INT_PAI);
97
98 reg = epci_base + SCC_EPCI_VCSR;
99 val = in_be32(reg) & 0xffff;
100 val |= SCC_EPCI_VCSR_FRE;
101 out_be32(reg, val);
102
103 reg = epci_base + SCC_EPCI_VISTAT;
104 out_be32(reg, SCC_EPCI_VISTAT_PMFE);
105 return PCIBIOS_DEVICE_NOT_FOUND;
106 }
107
108 return PCIBIOS_SUCCESSFUL;
109}
110
111static PCI_IO_ADDR celleb_epci_make_config_addr(struct pci_bus *bus,
112 struct pci_controller *hose, unsigned int devfn, int where)
113{
114 PCI_IO_ADDR addr;
115
116 if (bus != hose->bus)
117 addr = celleb_epci_get_epci_cfg(hose) +
118 (((bus->number & 0xff) << 16)
119 | ((devfn & 0xff) << 8)
120 | (where & 0xff)
121 | 0x01000000);
122 else
123 addr = celleb_epci_get_epci_cfg(hose) +
124 (((devfn & 0xff) << 8) | (where & 0xff));
125
126 pr_debug("EPCI: config_addr = 0x%p\n", addr);
127
128 return addr;
129}
130
131static int celleb_epci_read_config(struct pci_bus *bus,
132 unsigned int devfn, int where, int size, u32 *val)
133{
134 PCI_IO_ADDR epci_base;
135 PCI_IO_ADDR addr;
136 struct pci_controller *hose = pci_bus_to_host(bus);
137
138 /* allignment check */
139 BUG_ON(where % size);
140
141 if (!celleb_epci_get_epci_cfg(hose))
142 return PCIBIOS_DEVICE_NOT_FOUND;
143
144 if (bus->number == hose->first_busno && devfn == 0) {
145 /* EPCI controller self */
146
147 epci_base = celleb_epci_get_epci_base(hose);
148 addr = epci_base + where;
149
150 switch (size) {
151 case 1:
152 *val = in_8(addr);
153 break;
154 case 2:
155 *val = in_be16(addr);
156 break;
157 case 4:
158 *val = in_be32(addr);
159 break;
160 default:
161 return PCIBIOS_DEVICE_NOT_FOUND;
162 }
163
164 } else {
165
166 clear_and_disable_master_abort_interrupt(hose);
167 addr = celleb_epci_make_config_addr(bus, hose, devfn, where);
168
169 switch (size) {
170 case 1:
171 *val = in_8(addr);
172 break;
173 case 2:
174 *val = in_le16(addr);
175 break;
176 case 4:
177 *val = in_le32(addr);
178 break;
179 default:
180 return PCIBIOS_DEVICE_NOT_FOUND;
181 }
182 }
183
184 pr_debug("EPCI: "
185 "addr=0x%p, devfn=0x%x, where=0x%x, size=0x%x, val=0x%x\n",
186 addr, devfn, where, size, *val);
187
188 return celleb_epci_check_abort(hose, NULL);
189}
190
191static int celleb_epci_write_config(struct pci_bus *bus,
192 unsigned int devfn, int where, int size, u32 val)
193{
194 PCI_IO_ADDR epci_base;
195 PCI_IO_ADDR addr;
196 struct pci_controller *hose = pci_bus_to_host(bus);
197
198 /* allignment check */
199 BUG_ON(where % size);
200
201 if (!celleb_epci_get_epci_cfg(hose))
202 return PCIBIOS_DEVICE_NOT_FOUND;
203
204 if (bus->number == hose->first_busno && devfn == 0) {
205 /* EPCI controller self */
206
207 epci_base = celleb_epci_get_epci_base(hose);
208 addr = epci_base + where;
209
210 switch (size) {
211 case 1:
212 out_8(addr, val);
213 break;
214 case 2:
215 out_be16(addr, val);
216 break;
217 case 4:
218 out_be32(addr, val);
219 break;
220 default:
221 return PCIBIOS_DEVICE_NOT_FOUND;
222 }
223
224 } else {
225
226 clear_and_disable_master_abort_interrupt(hose);
227 addr = celleb_epci_make_config_addr(bus, hose, devfn, where);
228
229 switch (size) {
230 case 1:
231 out_8(addr, val);
232 break;
233 case 2:
234 out_le16(addr, val);
235 break;
236 case 4:
237 out_le32(addr, val);
238 break;
239 default:
240 return PCIBIOS_DEVICE_NOT_FOUND;
241 }
242 }
243
244 return celleb_epci_check_abort(hose, addr);
245}
246
247struct pci_ops celleb_epci_ops = {
248 .read = celleb_epci_read_config,
249 .write = celleb_epci_write_config,
250};
251
252/* to be moved in FW */
253static int __init celleb_epci_init(struct pci_controller *hose)
254{
255 u32 val;
256 PCI_IO_ADDR reg;
257 PCI_IO_ADDR epci_base;
258 int hwres = 0;
259
260 epci_base = celleb_epci_get_epci_base(hose);
261
262 /* PCI core reset(Internal bus and PCI clock) */
263 reg = epci_base + SCC_EPCI_CKCTRL;
264 val = in_be32(reg);
265 if (val == 0x00030101)
266 hwres = 1;
267 else {
268 val &= ~(SCC_EPCI_CKCTRL_CRST0 | SCC_EPCI_CKCTRL_CRST1);
269 out_be32(reg, val);
270
271 /* set PCI core clock */
272 val = in_be32(reg);
273 val |= (SCC_EPCI_CKCTRL_OCLKEN | SCC_EPCI_CKCTRL_LCLKEN);
274 out_be32(reg, val);
275
276 /* release PCI core reset (internal bus) */
277 val = in_be32(reg);
278 val |= SCC_EPCI_CKCTRL_CRST0;
279 out_be32(reg, val);
280
281 /* set PCI clock select */
282 reg = epci_base + SCC_EPCI_CLKRST;
283 val = in_be32(reg);
284 val &= ~SCC_EPCI_CLKRST_CKS_MASK;
285 val |= SCC_EPCI_CLKRST_CKS_2;
286 out_be32(reg, val);
287
288 /* set arbiter */
289 reg = epci_base + SCC_EPCI_ABTSET;
290 out_be32(reg, 0x0f1f001f); /* temporary value */
291
292 /* buffer on */
293 reg = epci_base + SCC_EPCI_CLKRST;
294 val = in_be32(reg);
295 val |= SCC_EPCI_CLKRST_BC;
296 out_be32(reg, val);
297
298 /* PCI clock enable */
299 val = in_be32(reg);
300 val |= SCC_EPCI_CLKRST_PCKEN;
301 out_be32(reg, val);
302
303 /* release PCI core reset (all) */
304 reg = epci_base + SCC_EPCI_CKCTRL;
305 val = in_be32(reg);
306 val |= (SCC_EPCI_CKCTRL_CRST0 | SCC_EPCI_CKCTRL_CRST1);
307 out_be32(reg, val);
308
309 /* set base translation registers. (already set by Beat) */
310
311 /* set base address masks. (already set by Beat) */
312 }
313
314 /* release interrupt masks and clear all interrupts */
315 reg = epci_base + SCC_EPCI_INTSET;
316 out_be32(reg, 0x013f011f); /* all interrupts enable */
317 reg = epci_base + SCC_EPCI_VIENAB;
318 val = SCC_EPCI_VIENAB_PMPEE | SCC_EPCI_VIENAB_PMFEE;
319 out_be32(reg, val);
320 reg = epci_base + SCC_EPCI_STATUS;
321 out_be32(reg, 0xffffffff);
322 reg = epci_base + SCC_EPCI_VISTAT;
323 out_be32(reg, 0xffffffff);
324
325 /* disable PCI->IB address translation */
326 reg = epci_base + SCC_EPCI_VCSR;
327 val = in_be32(reg);
328 val &= ~(SCC_EPCI_VCSR_DR | SCC_EPCI_VCSR_AT);
329 out_be32(reg, val);
330
331 /* set base addresses. (no need to set?) */
332
333 /* memory space, bus master enable */
334 reg = epci_base + PCI_COMMAND;
335 val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
336 out_be32(reg, val);
337
338 /* endian mode setup */
339 reg = epci_base + SCC_EPCI_ECMODE;
340 val = 0x00550155;
341 out_be32(reg, val);
342
343 /* set control option */
344 reg = epci_base + SCC_EPCI_CNTOPT;
345 val = in_be32(reg);
346 val |= SCC_EPCI_CNTOPT_O2PMB;
347 out_be32(reg, val);
348
349 /* XXX: temporay: set registers for address conversion setup */
350 reg = epci_base + SCC_EPCI_CNF10_REG;
351 out_be32(reg, 0x80000008);
352 reg = epci_base + SCC_EPCI_CNF14_REG;
353 out_be32(reg, 0x40000008);
354
355 reg = epci_base + SCC_EPCI_BAM0;
356 out_be32(reg, 0x80000000);
357 reg = epci_base + SCC_EPCI_BAM1;
358 out_be32(reg, 0xe0000000);
359
360 reg = epci_base + SCC_EPCI_PVBAT;
361 out_be32(reg, 0x80000000);
362
363 if (!hwres) {
364 /* release external PCI reset */
365 reg = epci_base + SCC_EPCI_CLKRST;
366 val = in_be32(reg);
367 val |= SCC_EPCI_CLKRST_PCIRST;
368 out_be32(reg, val);
369 }
370
371 return 0;
372}
373
374static int __init celleb_setup_epci(struct device_node *node,
375 struct pci_controller *hose)
376{
377 struct resource r;
378
379 pr_debug("PCI: celleb_setup_epci()\n");
380
381 /*
382 * Note:
383 * Celleb epci uses cfg_addr and cfg_data member of
384 * pci_controller structure in irregular way.
385 *
386 * cfg_addr is used to map for control registers of
387 * celleb epci.
388 *
389 * cfg_data is used for configuration area of devices
390 * on Celleb epci buses.
391 */
392
393 if (of_address_to_resource(node, 0, &r))
394 goto error;
395 hose->cfg_addr = ioremap(r.start, resource_size(&r));
396 if (!hose->cfg_addr)
397 goto error;
398 pr_debug("EPCI: cfg_addr map 0x%016llx->0x%016lx + 0x%016llx\n",
399 r.start, (unsigned long)hose->cfg_addr, resource_size(&r));
400
401 if (of_address_to_resource(node, 2, &r))
402 goto error;
403 hose->cfg_data = ioremap(r.start, resource_size(&r));
404 if (!hose->cfg_data)
405 goto error;
406 pr_debug("EPCI: cfg_data map 0x%016llx->0x%016lx + 0x%016llx\n",
407 r.start, (unsigned long)hose->cfg_data, resource_size(&r));
408
409 hose->ops = &celleb_epci_ops;
410 celleb_epci_init(hose);
411
412 return 0;
413
414error:
415 if (hose->cfg_addr)
416 iounmap(hose->cfg_addr);
417
418 if (hose->cfg_data)
419 iounmap(hose->cfg_data);
420 return 1;
421}
422
423struct celleb_phb_spec celleb_epci_spec __initdata = {
424 .setup = celleb_setup_epci,
425 .ops = &spiderpci_ops,
426 .iowa_init = &spiderpci_iowa_init,
427 .iowa_data = (void *)0,
428};
diff --git a/arch/powerpc/platforms/cell/celleb_scc_pciex.c b/arch/powerpc/platforms/cell/celleb_scc_pciex.c
deleted file mode 100644
index 94170e4f2ce7..000000000000
--- a/arch/powerpc/platforms/cell/celleb_scc_pciex.c
+++ /dev/null
@@ -1,538 +0,0 @@
1/*
2 * Support for Celleb PCI-Express.
3 *
4 * (C) Copyright 2007-2008 TOSHIBA CORPORATION
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#undef DEBUG
22
23#include <linux/kernel.h>
24#include <linux/pci.h>
25#include <linux/string.h>
26#include <linux/slab.h>
27#include <linux/init.h>
28#include <linux/delay.h>
29#include <linux/interrupt.h>
30
31#include <asm/io.h>
32#include <asm/irq.h>
33#include <asm/iommu.h>
34#include <asm/byteorder.h>
35
36#include "celleb_scc.h"
37#include "celleb_pci.h"
38
39#define PEX_IN(base, off) in_be32((void __iomem *)(base) + (off))
40#define PEX_OUT(base, off, data) out_be32((void __iomem *)(base) + (off), (data))
41
42static void scc_pciex_io_flush(struct iowa_bus *bus)
43{
44 (void)PEX_IN(bus->phb->cfg_addr, PEXDMRDEN0);
45}
46
47/*
48 * Memory space access to device on PCIEX
49 */
50#define PCIEX_MMIO_READ(name, ret) \
51static ret scc_pciex_##name(const PCI_IO_ADDR addr) \
52{ \
53 ret val = __do_##name(addr); \
54 scc_pciex_io_flush(iowa_mem_find_bus(addr)); \
55 return val; \
56}
57
58#define PCIEX_MMIO_READ_STR(name) \
59static void scc_pciex_##name(const PCI_IO_ADDR addr, void *buf, \
60 unsigned long count) \
61{ \
62 __do_##name(addr, buf, count); \
63 scc_pciex_io_flush(iowa_mem_find_bus(addr)); \
64}
65
66PCIEX_MMIO_READ(readb, u8)
67PCIEX_MMIO_READ(readw, u16)
68PCIEX_MMIO_READ(readl, u32)
69PCIEX_MMIO_READ(readq, u64)
70PCIEX_MMIO_READ(readw_be, u16)
71PCIEX_MMIO_READ(readl_be, u32)
72PCIEX_MMIO_READ(readq_be, u64)
73PCIEX_MMIO_READ_STR(readsb)
74PCIEX_MMIO_READ_STR(readsw)
75PCIEX_MMIO_READ_STR(readsl)
76
77static void scc_pciex_memcpy_fromio(void *dest, const PCI_IO_ADDR src,
78 unsigned long n)
79{
80 __do_memcpy_fromio(dest, src, n);
81 scc_pciex_io_flush(iowa_mem_find_bus(src));
82}
83
84/*
85 * I/O port access to devices on PCIEX.
86 */
87
88static inline unsigned long get_bus_address(struct pci_controller *phb,
89 unsigned long port)
90{
91 return port - ((unsigned long)(phb->io_base_virt) - _IO_BASE);
92}
93
94static u32 scc_pciex_read_port(struct pci_controller *phb,
95 unsigned long port, int size)
96{
97 unsigned int byte_enable;
98 unsigned int cmd, shift;
99 unsigned long addr;
100 u32 data, ret;
101
102 BUG_ON(((port & 0x3ul) + size) > 4);
103
104 addr = get_bus_address(phb, port);
105 shift = addr & 0x3ul;
106 byte_enable = ((1 << size) - 1) << shift;
107 cmd = PEXDCMND_IO_READ | (byte_enable << PEXDCMND_BYTE_EN_SHIFT);
108 PEX_OUT(phb->cfg_addr, PEXDADRS, (addr & ~0x3ul));
109 PEX_OUT(phb->cfg_addr, PEXDCMND, cmd);
110 data = PEX_IN(phb->cfg_addr, PEXDRDATA);
111 ret = (data >> (shift * 8)) & (0xFFFFFFFF >> ((4 - size) * 8));
112
113 pr_debug("PCIEX:PIO READ:port=0x%lx, addr=0x%lx, size=%d, be=%x,"
114 " cmd=%x, data=%x, ret=%x\n", port, addr, size, byte_enable,
115 cmd, data, ret);
116
117 return ret;
118}
119
120static void scc_pciex_write_port(struct pci_controller *phb,
121 unsigned long port, int size, u32 val)
122{
123 unsigned int byte_enable;
124 unsigned int cmd, shift;
125 unsigned long addr;
126 u32 data;
127
128 BUG_ON(((port & 0x3ul) + size) > 4);
129
130 addr = get_bus_address(phb, port);
131 shift = addr & 0x3ul;
132 byte_enable = ((1 << size) - 1) << shift;
133 cmd = PEXDCMND_IO_WRITE | (byte_enable << PEXDCMND_BYTE_EN_SHIFT);
134 data = (val & (0xFFFFFFFF >> (4 - size) * 8)) << (shift * 8);
135 PEX_OUT(phb->cfg_addr, PEXDADRS, (addr & ~0x3ul));
136 PEX_OUT(phb->cfg_addr, PEXDCMND, cmd);
137 PEX_OUT(phb->cfg_addr, PEXDWDATA, data);
138
139 pr_debug("PCIEX:PIO WRITE:port=0x%lx, addr=%lx, size=%d, val=%x,"
140 " be=%x, cmd=%x, data=%x\n", port, addr, size, val,
141 byte_enable, cmd, data);
142}
143
144static u8 __scc_pciex_inb(struct pci_controller *phb, unsigned long port)
145{
146 return (u8)scc_pciex_read_port(phb, port, 1);
147}
148
149static u16 __scc_pciex_inw(struct pci_controller *phb, unsigned long port)
150{
151 u32 data;
152 if ((port & 0x3ul) < 3)
153 data = scc_pciex_read_port(phb, port, 2);
154 else {
155 u32 d1 = scc_pciex_read_port(phb, port, 1);
156 u32 d2 = scc_pciex_read_port(phb, port + 1, 1);
157 data = d1 | (d2 << 8);
158 }
159 return (u16)data;
160}
161
162static u32 __scc_pciex_inl(struct pci_controller *phb, unsigned long port)
163{
164 unsigned int mod = port & 0x3ul;
165 u32 data;
166 if (mod == 0)
167 data = scc_pciex_read_port(phb, port, 4);
168 else {
169 u32 d1 = scc_pciex_read_port(phb, port, 4 - mod);
170 u32 d2 = scc_pciex_read_port(phb, port + 1, mod);
171 data = d1 | (d2 << (mod * 8));
172 }
173 return data;
174}
175
176static void __scc_pciex_outb(struct pci_controller *phb,
177 u8 val, unsigned long port)
178{
179 scc_pciex_write_port(phb, port, 1, (u32)val);
180}
181
182static void __scc_pciex_outw(struct pci_controller *phb,
183 u16 val, unsigned long port)
184{
185 if ((port & 0x3ul) < 3)
186 scc_pciex_write_port(phb, port, 2, (u32)val);
187 else {
188 u32 d1 = val & 0x000000FF;
189 u32 d2 = (val & 0x0000FF00) >> 8;
190 scc_pciex_write_port(phb, port, 1, d1);
191 scc_pciex_write_port(phb, port + 1, 1, d2);
192 }
193}
194
195static void __scc_pciex_outl(struct pci_controller *phb,
196 u32 val, unsigned long port)
197{
198 unsigned int mod = port & 0x3ul;
199 if (mod == 0)
200 scc_pciex_write_port(phb, port, 4, val);
201 else {
202 u32 d1 = val & (0xFFFFFFFFul >> (mod * 8));
203 u32 d2 = val >> ((4 - mod) * 8);
204 scc_pciex_write_port(phb, port, 4 - mod, d1);
205 scc_pciex_write_port(phb, port + 1, mod, d2);
206 }
207}
208
209#define PCIEX_PIO_FUNC(size, name) \
210static u##size scc_pciex_in##name(unsigned long port) \
211{ \
212 struct iowa_bus *bus = iowa_pio_find_bus(port); \
213 u##size data = __scc_pciex_in##name(bus->phb, port); \
214 scc_pciex_io_flush(bus); \
215 return data; \
216} \
217static void scc_pciex_ins##name(unsigned long p, void *b, unsigned long c) \
218{ \
219 struct iowa_bus *bus = iowa_pio_find_bus(p); \
220 __le##size *dst = b; \
221 for (; c != 0; c--, dst++) \
222 *dst = cpu_to_le##size(__scc_pciex_in##name(bus->phb, p)); \
223 scc_pciex_io_flush(bus); \
224} \
225static void scc_pciex_out##name(u##size val, unsigned long port) \
226{ \
227 struct iowa_bus *bus = iowa_pio_find_bus(port); \
228 __scc_pciex_out##name(bus->phb, val, port); \
229} \
230static void scc_pciex_outs##name(unsigned long p, const void *b, \
231 unsigned long c) \
232{ \
233 struct iowa_bus *bus = iowa_pio_find_bus(p); \
234 const __le##size *src = b; \
235 for (; c != 0; c--, src++) \
236 __scc_pciex_out##name(bus->phb, le##size##_to_cpu(*src), p); \
237}
238#define __le8 u8
239#define cpu_to_le8(x) (x)
240#define le8_to_cpu(x) (x)
241PCIEX_PIO_FUNC(8, b)
242PCIEX_PIO_FUNC(16, w)
243PCIEX_PIO_FUNC(32, l)
244
245static struct ppc_pci_io scc_pciex_ops = {
246 .readb = scc_pciex_readb,
247 .readw = scc_pciex_readw,
248 .readl = scc_pciex_readl,
249 .readq = scc_pciex_readq,
250 .readw_be = scc_pciex_readw_be,
251 .readl_be = scc_pciex_readl_be,
252 .readq_be = scc_pciex_readq_be,
253 .readsb = scc_pciex_readsb,
254 .readsw = scc_pciex_readsw,
255 .readsl = scc_pciex_readsl,
256 .memcpy_fromio = scc_pciex_memcpy_fromio,
257 .inb = scc_pciex_inb,
258 .inw = scc_pciex_inw,
259 .inl = scc_pciex_inl,
260 .outb = scc_pciex_outb,
261 .outw = scc_pciex_outw,
262 .outl = scc_pciex_outl,
263 .insb = scc_pciex_insb,
264 .insw = scc_pciex_insw,
265 .insl = scc_pciex_insl,
266 .outsb = scc_pciex_outsb,
267 .outsw = scc_pciex_outsw,
268 .outsl = scc_pciex_outsl,
269};
270
271static int __init scc_pciex_iowa_init(struct iowa_bus *bus, void *data)
272{
273 dma_addr_t dummy_page_da;
274 void *dummy_page_va;
275
276 dummy_page_va = kmalloc(PAGE_SIZE, GFP_KERNEL);
277 if (!dummy_page_va) {
278 pr_err("PCIEX:Alloc dummy_page_va failed\n");
279 return -1;
280 }
281
282 dummy_page_da = dma_map_single(bus->phb->parent, dummy_page_va,
283 PAGE_SIZE, DMA_FROM_DEVICE);
284 if (dma_mapping_error(bus->phb->parent, dummy_page_da)) {
285 pr_err("PCIEX:Map dummy page failed.\n");
286 kfree(dummy_page_va);
287 return -1;
288 }
289
290 PEX_OUT(bus->phb->cfg_addr, PEXDMRDADR0, dummy_page_da);
291
292 return 0;
293}
294
295/*
296 * config space access
297 */
298#define MK_PEXDADRS(bus_no, dev_no, func_no, addr) \
299 ((uint32_t)(((addr) & ~0x3UL) | \
300 ((bus_no) << PEXDADRS_BUSNO_SHIFT) | \
301 ((dev_no) << PEXDADRS_DEVNO_SHIFT) | \
302 ((func_no) << PEXDADRS_FUNCNO_SHIFT)))
303
304#define MK_PEXDCMND_BYTE_EN(addr, size) \
305 ((((0x1 << (size))-1) << ((addr) & 0x3)) << PEXDCMND_BYTE_EN_SHIFT)
306#define MK_PEXDCMND(cmd, addr, size) ((cmd) | MK_PEXDCMND_BYTE_EN(addr, size))
307
308static uint32_t config_read_pciex_dev(unsigned int __iomem *base,
309 uint64_t bus_no, uint64_t dev_no, uint64_t func_no,
310 uint64_t off, uint64_t size)
311{
312 uint32_t ret;
313 uint32_t addr, cmd;
314
315 addr = MK_PEXDADRS(bus_no, dev_no, func_no, off);
316 cmd = MK_PEXDCMND(PEXDCMND_CONFIG_READ, off, size);
317 PEX_OUT(base, PEXDADRS, addr);
318 PEX_OUT(base, PEXDCMND, cmd);
319 ret = (PEX_IN(base, PEXDRDATA)
320 >> ((off & (4-size)) * 8)) & ((0x1 << (size * 8)) - 1);
321 return ret;
322}
323
324static void config_write_pciex_dev(unsigned int __iomem *base, uint64_t bus_no,
325 uint64_t dev_no, uint64_t func_no, uint64_t off, uint64_t size,
326 uint32_t data)
327{
328 uint32_t addr, cmd;
329
330 addr = MK_PEXDADRS(bus_no, dev_no, func_no, off);
331 cmd = MK_PEXDCMND(PEXDCMND_CONFIG_WRITE, off, size);
332 PEX_OUT(base, PEXDADRS, addr);
333 PEX_OUT(base, PEXDCMND, cmd);
334 PEX_OUT(base, PEXDWDATA,
335 (data & ((0x1 << (size * 8)) - 1)) << ((off & (4-size)) * 8));
336}
337
338#define MK_PEXCADRS_BYTE_EN(off, len) \
339 ((((0x1 << (len)) - 1) << ((off) & 0x3)) << PEXCADRS_BYTE_EN_SHIFT)
340#define MK_PEXCADRS(cmd, addr, size) \
341 ((cmd) | MK_PEXCADRS_BYTE_EN(addr, size) | ((addr) & ~0x3))
342static uint32_t config_read_pciex_rc(unsigned int __iomem *base,
343 uint32_t where, uint32_t size)
344{
345 PEX_OUT(base, PEXCADRS, MK_PEXCADRS(PEXCADRS_CMD_READ, where, size));
346 return (PEX_IN(base, PEXCRDATA)
347 >> ((where & (4 - size)) * 8)) & ((0x1 << (size * 8)) - 1);
348}
349
350static void config_write_pciex_rc(unsigned int __iomem *base, uint32_t where,
351 uint32_t size, uint32_t val)
352{
353 uint32_t data;
354
355 data = (val & ((0x1 << (size * 8)) - 1)) << ((where & (4 - size)) * 8);
356 PEX_OUT(base, PEXCADRS, MK_PEXCADRS(PEXCADRS_CMD_WRITE, where, size));
357 PEX_OUT(base, PEXCWDATA, data);
358}
359
360/* Interfaces */
361/* Note: Work-around
362 * On SCC PCIEXC, one device is seen on all 32 dev_no.
363 * As SCC PCIEXC can have only one device on the bus, we look only one dev_no.
364 * (dev_no = 1)
365 */
366static int scc_pciex_read_config(struct pci_bus *bus, unsigned int devfn,
367 int where, int size, unsigned int *val)
368{
369 struct pci_controller *phb = pci_bus_to_host(bus);
370
371 if (bus->number == phb->first_busno && PCI_SLOT(devfn) != 1) {
372 *val = ~0;
373 return PCIBIOS_DEVICE_NOT_FOUND;
374 }
375
376 if (bus->number == 0 && PCI_SLOT(devfn) == 0)
377 *val = config_read_pciex_rc(phb->cfg_addr, where, size);
378 else
379 *val = config_read_pciex_dev(phb->cfg_addr, bus->number,
380 PCI_SLOT(devfn), PCI_FUNC(devfn), where, size);
381
382 return PCIBIOS_SUCCESSFUL;
383}
384
385static int scc_pciex_write_config(struct pci_bus *bus, unsigned int devfn,
386 int where, int size, unsigned int val)
387{
388 struct pci_controller *phb = pci_bus_to_host(bus);
389
390 if (bus->number == phb->first_busno && PCI_SLOT(devfn) != 1)
391 return PCIBIOS_DEVICE_NOT_FOUND;
392
393 if (bus->number == 0 && PCI_SLOT(devfn) == 0)
394 config_write_pciex_rc(phb->cfg_addr, where, size, val);
395 else
396 config_write_pciex_dev(phb->cfg_addr, bus->number,
397 PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, val);
398 return PCIBIOS_SUCCESSFUL;
399}
400
401static struct pci_ops scc_pciex_pci_ops = {
402 .read = scc_pciex_read_config,
403 .write = scc_pciex_write_config,
404};
405
406static void pciex_clear_intr_all(unsigned int __iomem *base)
407{
408 PEX_OUT(base, PEXAERRSTS, 0xffffffff);
409 PEX_OUT(base, PEXPRERRSTS, 0xffffffff);
410 PEX_OUT(base, PEXINTSTS, 0xffffffff);
411}
412
413#if 0
414static void pciex_disable_intr_all(unsigned int *base)
415{
416 PEX_OUT(base, PEXINTMASK, 0x0);
417 PEX_OUT(base, PEXAERRMASK, 0x0);
418 PEX_OUT(base, PEXPRERRMASK, 0x0);
419 PEX_OUT(base, PEXVDMASK, 0x0);
420}
421#endif
422
423static void pciex_enable_intr_all(unsigned int __iomem *base)
424{
425 PEX_OUT(base, PEXINTMASK, 0x0000e7f1);
426 PEX_OUT(base, PEXAERRMASK, 0x03ff01ff);
427 PEX_OUT(base, PEXPRERRMASK, 0x0001010f);
428 PEX_OUT(base, PEXVDMASK, 0x00000001);
429}
430
431static void pciex_check_status(unsigned int __iomem *base)
432{
433 uint32_t err = 0;
434 uint32_t intsts, aerr, prerr, rcvcp, lenerr;
435 uint32_t maea, maec;
436
437 intsts = PEX_IN(base, PEXINTSTS);
438 aerr = PEX_IN(base, PEXAERRSTS);
439 prerr = PEX_IN(base, PEXPRERRSTS);
440 rcvcp = PEX_IN(base, PEXRCVCPLIDA);
441 lenerr = PEX_IN(base, PEXLENERRIDA);
442
443 if (intsts || aerr || prerr || rcvcp || lenerr)
444 err = 1;
445
446 pr_info("PCEXC interrupt!!\n");
447 pr_info("PEXINTSTS :0x%08x\n", intsts);
448 pr_info("PEXAERRSTS :0x%08x\n", aerr);
449 pr_info("PEXPRERRSTS :0x%08x\n", prerr);
450 pr_info("PEXRCVCPLIDA :0x%08x\n", rcvcp);
451 pr_info("PEXLENERRIDA :0x%08x\n", lenerr);
452
453 /* print detail of Protection Error */
454 if (intsts & 0x00004000) {
455 uint32_t i, n;
456 for (i = 0; i < 4; i++) {
457 n = 1 << i;
458 if (prerr & n) {
459 maea = PEX_IN(base, PEXMAEA(i));
460 maec = PEX_IN(base, PEXMAEC(i));
461 pr_info("PEXMAEC%d :0x%08x\n", i, maec);
462 pr_info("PEXMAEA%d :0x%08x\n", i, maea);
463 }
464 }
465 }
466
467 if (err)
468 pciex_clear_intr_all(base);
469}
470
471static irqreturn_t pciex_handle_internal_irq(int irq, void *dev_id)
472{
473 struct pci_controller *phb = dev_id;
474
475 pr_debug("PCIEX:pciex_handle_internal_irq(irq=%d)\n", irq);
476
477 BUG_ON(phb->cfg_addr == NULL);
478
479 pciex_check_status(phb->cfg_addr);
480
481 return IRQ_HANDLED;
482}
483
484static __init int celleb_setup_pciex(struct device_node *node,
485 struct pci_controller *phb)
486{
487 struct resource r;
488 int virq;
489
490 /* SMMIO registers; used inside this file */
491 if (of_address_to_resource(node, 0, &r)) {
492 pr_err("PCIEXC:Failed to get config resource.\n");
493 return 1;
494 }
495 phb->cfg_addr = ioremap(r.start, resource_size(&r));
496 if (!phb->cfg_addr) {
497 pr_err("PCIEXC:Failed to remap SMMIO region.\n");
498 return 1;
499 }
500
501 /* Not use cfg_data, cmd and data regs are near address reg */
502 phb->cfg_data = NULL;
503
504 /* set pci_ops */
505 phb->ops = &scc_pciex_pci_ops;
506
507 /* internal interrupt handler */
508 virq = irq_of_parse_and_map(node, 1);
509 if (!virq) {
510 pr_err("PCIEXC:Failed to map irq\n");
511 goto error;
512 }
513 if (request_irq(virq, pciex_handle_internal_irq,
514 0, "pciex", (void *)phb)) {
515 pr_err("PCIEXC:Failed to request irq\n");
516 goto error;
517 }
518
519 /* enable all interrupts */
520 pciex_clear_intr_all(phb->cfg_addr);
521 pciex_enable_intr_all(phb->cfg_addr);
522 /* MSI: TBD */
523
524 return 0;
525
526error:
527 phb->cfg_data = NULL;
528 if (phb->cfg_addr)
529 iounmap(phb->cfg_addr);
530 phb->cfg_addr = NULL;
531 return 1;
532}
533
534struct celleb_phb_spec celleb_pciex_spec __initdata = {
535 .setup = celleb_setup_pciex,
536 .ops = &scc_pciex_ops,
537 .iowa_init = &scc_pciex_iowa_init,
538};
diff --git a/arch/powerpc/platforms/cell/celleb_scc_sio.c b/arch/powerpc/platforms/cell/celleb_scc_sio.c
deleted file mode 100644
index c8eb57193826..000000000000
--- a/arch/powerpc/platforms/cell/celleb_scc_sio.c
+++ /dev/null
@@ -1,99 +0,0 @@
1/*
2 * setup serial port in SCC
3 *
4 * (C) Copyright 2006-2007 TOSHIBA CORPORATION
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <linux/tty.h>
22#include <linux/serial.h>
23#include <linux/serial_core.h>
24#include <linux/console.h>
25
26#include <asm/io.h>
27#include <asm/prom.h>
28
29/* sio irq0=0xb00010022 irq0=0xb00010023 irq2=0xb00010024
30 mmio=0xfff000-0x1000,0xff2000-0x1000 */
31static int txx9_serial_bitmap __initdata;
32
33static struct {
34 uint32_t offset;
35 uint32_t index;
36} txx9_scc_tab[3] __initdata = {
37 { 0x300, 0 }, /* 0xFFF300 */
38 { 0x400, 0 }, /* 0xFFF400 */
39 { 0x800, 1 } /* 0xFF2800 */
40};
41
42static int __init txx9_serial_init(void)
43{
44 extern int early_serial_txx9_setup(struct uart_port *port);
45 struct device_node *node;
46 int i;
47 struct uart_port req;
48 struct of_phandle_args irq;
49 struct resource res;
50
51 for_each_compatible_node(node, "serial", "toshiba,sio-scc") {
52 for (i = 0; i < ARRAY_SIZE(txx9_scc_tab); i++) {
53 if (!(txx9_serial_bitmap & (1<<i)))
54 continue;
55
56 if (of_irq_parse_one(node, i, &irq))
57 continue;
58 if (of_address_to_resource(node,
59 txx9_scc_tab[i].index, &res))
60 continue;
61
62 memset(&req, 0, sizeof(req));
63 req.line = i;
64 req.iotype = UPIO_MEM;
65 req.mapbase = res.start + txx9_scc_tab[i].offset;
66#ifdef CONFIG_SERIAL_TXX9_CONSOLE
67 req.membase = ioremap(req.mapbase, 0x24);
68#endif
69 req.irq = irq_create_of_mapping(&irq);
70 req.flags |= UPF_IOREMAP | UPF_BUGGY_UART
71 /*HAVE_CTS_LINE*/;
72 req.uartclk = 83300000;
73 early_serial_txx9_setup(&req);
74 }
75 }
76
77 return 0;
78}
79
80static int __init txx9_serial_config(char *ptr)
81{
82 int i;
83
84 for (;;) {
85 switch (get_option(&ptr, &i)) {
86 default:
87 return 0;
88 case 2:
89 txx9_serial_bitmap |= 1 << i;
90 break;
91 case 1:
92 txx9_serial_bitmap |= 1 << i;
93 return 0;
94 }
95 }
96}
97__setup("txx9_serial=", txx9_serial_config);
98
99console_initcall(txx9_serial_init);
diff --git a/arch/powerpc/platforms/cell/celleb_scc_uhc.c b/arch/powerpc/platforms/cell/celleb_scc_uhc.c
deleted file mode 100644
index d63b720bfe3a..000000000000
--- a/arch/powerpc/platforms/cell/celleb_scc_uhc.c
+++ /dev/null
@@ -1,95 +0,0 @@
1/*
2 * SCC (Super Companion Chip) UHC setup
3 *
4 * (C) Copyright 2006-2007 TOSHIBA CORPORATION
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <linux/kernel.h>
22#include <linux/pci.h>
23
24#include <asm/delay.h>
25#include <asm/io.h>
26#include <asm/machdep.h>
27
28#include "celleb_scc.h"
29
30#define UHC_RESET_WAIT_MAX 10000
31
32static inline int uhc_clkctrl_ready(u32 val)
33{
34 const u32 mask = SCC_UHC_USBCEN | SCC_UHC_USBCEN;
35 return((val & mask) == mask);
36}
37
38/*
39 * UHC(usb host controller) enable function.
40 * affect to both of OHCI and EHCI core module.
41 */
42static void enable_scc_uhc(struct pci_dev *dev)
43{
44 void __iomem *uhc_base;
45 u32 __iomem *uhc_clkctrl;
46 u32 __iomem *uhc_ecmode;
47 u32 val = 0;
48 int i;
49
50 if (!machine_is(celleb_beat) &&
51 !machine_is(celleb_native))
52 return;
53
54 uhc_base = ioremap(pci_resource_start(dev, 0),
55 pci_resource_len(dev, 0));
56 if (!uhc_base) {
57 printk(KERN_ERR "failed to map UHC register base.\n");
58 return;
59 }
60 uhc_clkctrl = uhc_base + SCC_UHC_CKRCTRL;
61 uhc_ecmode = uhc_base + SCC_UHC_ECMODE;
62
63 /* setup for normal mode */
64 val |= SCC_UHC_F48MCKLEN;
65 out_be32(uhc_clkctrl, val);
66 val |= SCC_UHC_PHY_SUSPEND_SEL;
67 out_be32(uhc_clkctrl, val);
68 udelay(10);
69 val |= SCC_UHC_PHYEN;
70 out_be32(uhc_clkctrl, val);
71 udelay(50);
72
73 /* disable reset */
74 val |= SCC_UHC_HCLKEN;
75 out_be32(uhc_clkctrl, val);
76 val |= (SCC_UHC_USBCEN | SCC_UHC_USBEN);
77 out_be32(uhc_clkctrl, val);
78 i = 0;
79 while (!uhc_clkctrl_ready(in_be32(uhc_clkctrl))) {
80 udelay(10);
81 if (i++ > UHC_RESET_WAIT_MAX) {
82 printk(KERN_ERR "Failed to disable UHC reset %x\n",
83 in_be32(uhc_clkctrl));
84 break;
85 }
86 }
87
88 /* Endian Conversion Mode for Master ALL area */
89 out_be32(uhc_ecmode, SCC_UHC_ECMODE_BY_BYTE);
90
91 iounmap(uhc_base);
92}
93
94DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
95 PCI_DEVICE_ID_TOSHIBA_SCC_USB, enable_scc_uhc);
diff --git a/arch/powerpc/platforms/cell/celleb_setup.c b/arch/powerpc/platforms/cell/celleb_setup.c
deleted file mode 100644
index 90be8ec51686..000000000000
--- a/arch/powerpc/platforms/cell/celleb_setup.c
+++ /dev/null
@@ -1,243 +0,0 @@
1/*
2 * Celleb setup code
3 *
4 * (C) Copyright 2006-2007 TOSHIBA CORPORATION
5 *
6 * This code is based on arch/powerpc/platforms/cell/setup.c:
7 * Copyright (C) 1995 Linus Torvalds
8 * Adapted from 'alpha' version by Gary Thomas
9 * Modified by Cort Dougan (cort@cs.nmt.edu)
10 * Modified by PPC64 Team, IBM Corp
11 * Modified by Cell Team, IBM Deutschland Entwicklung GmbH
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
26 */
27
28#undef DEBUG
29
30#include <linux/cpu.h>
31#include <linux/sched.h>
32#include <linux/kernel.h>
33#include <linux/export.h>
34#include <linux/mm.h>
35#include <linux/stddef.h>
36#include <linux/unistd.h>
37#include <linux/reboot.h>
38#include <linux/init.h>
39#include <linux/delay.h>
40#include <linux/irq.h>
41#include <linux/seq_file.h>
42#include <linux/root_dev.h>
43#include <linux/console.h>
44#include <linux/of_platform.h>
45
46#include <asm/mmu.h>
47#include <asm/processor.h>
48#include <asm/io.h>
49#include <asm/prom.h>
50#include <asm/machdep.h>
51#include <asm/cputable.h>
52#include <asm/irq.h>
53#include <asm/time.h>
54#include <asm/spu_priv1.h>
55#include <asm/firmware.h>
56#include <asm/rtas.h>
57#include <asm/cell-regs.h>
58
59#include "beat_interrupt.h"
60#include "beat_wrapper.h"
61#include "beat.h"
62#include "celleb_pci.h"
63#include "interrupt.h"
64#include "pervasive.h"
65#include "ras.h"
66
67static char celleb_machine_type[128] = "Celleb";
68
69static void celleb_show_cpuinfo(struct seq_file *m)
70{
71 struct device_node *root;
72 const char *model = "";
73
74 root = of_find_node_by_path("/");
75 if (root)
76 model = of_get_property(root, "model", NULL);
77 /* using "CHRP" is to trick anaconda into installing FCx into Celleb */
78 seq_printf(m, "machine\t\t: %s %s\n", celleb_machine_type, model);
79 of_node_put(root);
80}
81
82static int __init celleb_machine_type_hack(char *ptr)
83{
84 strlcpy(celleb_machine_type, ptr, sizeof(celleb_machine_type));
85 return 0;
86}
87
88__setup("celleb_machine_type_hack=", celleb_machine_type_hack);
89
90static void celleb_progress(char *s, unsigned short hex)
91{
92 printk("*** %04x : %s\n", hex, s ? s : "");
93}
94
95static void __init celleb_setup_arch_common(void)
96{
97 /* init to some ~sane value until calibrate_delay() runs */
98 loops_per_jiffy = 50000000;
99
100#ifdef CONFIG_DUMMY_CONSOLE
101 conswitchp = &dummy_con;
102#endif
103}
104
105static const struct of_device_id celleb_bus_ids[] __initconst = {
106 { .type = "scc", },
107 { .type = "ioif", }, /* old style */
108 {},
109};
110
111static int __init celleb_publish_devices(void)
112{
113 /* Publish OF platform devices for southbridge IOs */
114 of_platform_bus_probe(NULL, celleb_bus_ids, NULL);
115
116 return 0;
117}
118machine_device_initcall(celleb_beat, celleb_publish_devices);
119machine_device_initcall(celleb_native, celleb_publish_devices);
120
121
122/*
123 * functions for Celleb-Beat
124 */
125static void __init celleb_setup_arch_beat(void)
126{
127#ifdef CONFIG_SPU_BASE
128 spu_priv1_ops = &spu_priv1_beat_ops;
129 spu_management_ops = &spu_management_of_ops;
130#endif
131
132 celleb_setup_arch_common();
133}
134
135static int __init celleb_probe_beat(void)
136{
137 unsigned long root = of_get_flat_dt_root();
138
139 if (!of_flat_dt_is_compatible(root, "Beat"))
140 return 0;
141
142 powerpc_firmware_features |= FW_FEATURE_CELLEB_ALWAYS
143 | FW_FEATURE_BEAT | FW_FEATURE_LPAR;
144 hpte_init_beat_v3();
145 pm_power_off = beat_power_off;
146
147 return 1;
148}
149
150
151/*
152 * functions for Celleb-native
153 */
154static void __init celleb_init_IRQ_native(void)
155{
156 iic_init_IRQ();
157 spider_init_IRQ();
158}
159
160static void __init celleb_setup_arch_native(void)
161{
162#ifdef CONFIG_SPU_BASE
163 spu_priv1_ops = &spu_priv1_mmio_ops;
164 spu_management_ops = &spu_management_of_ops;
165#endif
166
167 cbe_regs_init();
168
169#ifdef CONFIG_CBE_RAS
170 cbe_ras_init();
171#endif
172
173#ifdef CONFIG_SMP
174 smp_init_cell();
175#endif
176
177 cbe_pervasive_init();
178
179 /* XXX: nvram initialization should be added */
180
181 celleb_setup_arch_common();
182}
183
184static int __init celleb_probe_native(void)
185{
186 unsigned long root = of_get_flat_dt_root();
187
188 if (of_flat_dt_is_compatible(root, "Beat") ||
189 !of_flat_dt_is_compatible(root, "TOSHIBA,Celleb"))
190 return 0;
191
192 powerpc_firmware_features |= FW_FEATURE_CELLEB_ALWAYS;
193 hpte_init_native();
194 pm_power_off = rtas_power_off;
195
196 return 1;
197}
198
199
200/*
201 * machine definitions
202 */
203define_machine(celleb_beat) {
204 .name = "Cell Reference Set (Beat)",
205 .probe = celleb_probe_beat,
206 .setup_arch = celleb_setup_arch_beat,
207 .show_cpuinfo = celleb_show_cpuinfo,
208 .restart = beat_restart,
209 .halt = beat_halt,
210 .get_rtc_time = beat_get_rtc_time,
211 .set_rtc_time = beat_set_rtc_time,
212 .calibrate_decr = generic_calibrate_decr,
213 .progress = celleb_progress,
214 .power_save = beat_power_save,
215 .nvram_size = beat_nvram_get_size,
216 .nvram_read = beat_nvram_read,
217 .nvram_write = beat_nvram_write,
218 .set_dabr = beat_set_xdabr,
219 .init_IRQ = beatic_init_IRQ,
220 .get_irq = beatic_get_irq,
221 .pci_probe_mode = celleb_pci_probe_mode,
222 .pci_setup_phb = celleb_setup_phb,
223#ifdef CONFIG_KEXEC
224 .kexec_cpu_down = beat_kexec_cpu_down,
225#endif
226};
227
228define_machine(celleb_native) {
229 .name = "Cell Reference Set (native)",
230 .probe = celleb_probe_native,
231 .setup_arch = celleb_setup_arch_native,
232 .show_cpuinfo = celleb_show_cpuinfo,
233 .restart = rtas_restart,
234 .halt = rtas_halt,
235 .get_boot_time = rtas_get_boot_time,
236 .get_rtc_time = rtas_get_rtc_time,
237 .set_rtc_time = rtas_set_rtc_time,
238 .calibrate_decr = generic_calibrate_decr,
239 .progress = celleb_progress,
240 .pci_probe_mode = celleb_pci_probe_mode,
241 .pci_setup_phb = celleb_setup_phb,
242 .init_IRQ = celleb_init_IRQ_native,
243};
diff --git a/arch/powerpc/platforms/cell/interrupt.c b/arch/powerpc/platforms/cell/interrupt.c
index 4c11421847be..3af8324c122e 100644
--- a/arch/powerpc/platforms/cell/interrupt.c
+++ b/arch/powerpc/platforms/cell/interrupt.c
@@ -163,7 +163,7 @@ static unsigned int iic_get_irq(void)
163 163
164void iic_setup_cpu(void) 164void iic_setup_cpu(void)
165{ 165{
166 out_be64(this_cpu_ptr(&cpu_iic.regs->prio), 0xff); 166 out_be64(&this_cpu_ptr(&cpu_iic)->regs->prio, 0xff);
167} 167}
168 168
169u8 iic_get_target_id(int cpu) 169u8 iic_get_target_id(int cpu)
diff --git a/arch/powerpc/platforms/cell/iommu.c b/arch/powerpc/platforms/cell/iommu.c
index c7c8720aa39f..21b502398bf3 100644
--- a/arch/powerpc/platforms/cell/iommu.c
+++ b/arch/powerpc/platforms/cell/iommu.c
@@ -39,6 +39,7 @@
39#include <asm/firmware.h> 39#include <asm/firmware.h>
40#include <asm/cell-regs.h> 40#include <asm/cell-regs.h>
41 41
42#include "cell.h"
42#include "interrupt.h" 43#include "interrupt.h"
43 44
44/* Define CELL_IOMMU_REAL_UNMAP to actually unmap non-used pages 45/* Define CELL_IOMMU_REAL_UNMAP to actually unmap non-used pages
@@ -197,7 +198,7 @@ static int tce_build_cell(struct iommu_table *tbl, long index, long npages,
197 198
198 io_pte = (unsigned long *)tbl->it_base + (index - tbl->it_offset); 199 io_pte = (unsigned long *)tbl->it_base + (index - tbl->it_offset);
199 200
200 for (i = 0; i < npages; i++, uaddr += tbl->it_page_shift) 201 for (i = 0; i < npages; i++, uaddr += (1 << tbl->it_page_shift))
201 io_pte[i] = base_pte | (__pa(uaddr) & CBE_IOPTE_RPN_Mask); 202 io_pte[i] = base_pte | (__pa(uaddr) & CBE_IOPTE_RPN_Mask);
202 203
203 mb(); 204 mb();
@@ -857,7 +858,7 @@ static int __init cell_iommu_init_disabled(void)
857 cell_dma_direct_offset += base; 858 cell_dma_direct_offset += base;
858 859
859 if (cell_dma_direct_offset != 0) 860 if (cell_dma_direct_offset != 0)
860 ppc_md.pci_dma_dev_setup = cell_pci_dma_dev_setup; 861 cell_pci_controller_ops.dma_dev_setup = cell_pci_dma_dev_setup;
861 862
862 printk("iommu: disabled, direct DMA offset is 0x%lx\n", 863 printk("iommu: disabled, direct DMA offset is 0x%lx\n",
863 cell_dma_direct_offset); 864 cell_dma_direct_offset);
@@ -1197,8 +1198,8 @@ static int __init cell_iommu_init(void)
1197 if (cell_iommu_init_disabled() == 0) 1198 if (cell_iommu_init_disabled() == 0)
1198 goto bail; 1199 goto bail;
1199 1200
1200 /* Setup various ppc_md. callbacks */ 1201 /* Setup various callbacks */
1201 ppc_md.pci_dma_dev_setup = cell_pci_dma_dev_setup; 1202 cell_pci_controller_ops.dma_dev_setup = cell_pci_dma_dev_setup;
1202 ppc_md.dma_get_required_mask = cell_dma_get_required_mask; 1203 ppc_md.dma_get_required_mask = cell_dma_get_required_mask;
1203 ppc_md.tce_build = tce_build_cell; 1204 ppc_md.tce_build = tce_build_cell;
1204 ppc_md.tce_free = tce_free_cell; 1205 ppc_md.tce_free = tce_free_cell;
@@ -1234,5 +1235,3 @@ static int __init cell_iommu_init(void)
1234 return 0; 1235 return 0;
1235} 1236}
1236machine_arch_initcall(cell, cell_iommu_init); 1237machine_arch_initcall(cell, cell_iommu_init);
1237machine_arch_initcall(celleb_native, cell_iommu_init);
1238
diff --git a/arch/powerpc/platforms/cell/setup.c b/arch/powerpc/platforms/cell/setup.c
index d62aa982d530..36cff28d0293 100644
--- a/arch/powerpc/platforms/cell/setup.c
+++ b/arch/powerpc/platforms/cell/setup.c
@@ -54,6 +54,7 @@
54#include <asm/cell-regs.h> 54#include <asm/cell-regs.h>
55#include <asm/io-workarounds.h> 55#include <asm/io-workarounds.h>
56 56
57#include "cell.h"
57#include "interrupt.h" 58#include "interrupt.h"
58#include "pervasive.h" 59#include "pervasive.h"
59#include "ras.h" 60#include "ras.h"
@@ -126,6 +127,8 @@ static int cell_setup_phb(struct pci_controller *phb)
126 if (rc) 127 if (rc)
127 return rc; 128 return rc;
128 129
130 phb->controller_ops = cell_pci_controller_ops;
131
129 np = phb->dn; 132 np = phb->dn;
130 model = of_get_property(np, "model", NULL); 133 model = of_get_property(np, "model", NULL);
131 if (model == NULL || strcmp(np->name, "pci")) 134 if (model == NULL || strcmp(np->name, "pci"))
@@ -279,3 +282,5 @@ define_machine(cell) {
279 .init_IRQ = cell_init_irq, 282 .init_IRQ = cell_init_irq,
280 .pci_setup_phb = cell_setup_phb, 283 .pci_setup_phb = cell_setup_phb,
281}; 284};
285
286struct pci_controller_ops cell_pci_controller_ops;
diff --git a/arch/powerpc/platforms/cell/smp.c b/arch/powerpc/platforms/cell/smp.c
index b64e7ead752f..895560f4be69 100644
--- a/arch/powerpc/platforms/cell/smp.c
+++ b/arch/powerpc/platforms/cell/smp.c
@@ -102,13 +102,6 @@ static inline int smp_startup_cpu(unsigned int lcpu)
102 return 1; 102 return 1;
103} 103}
104 104
105static int __init smp_iic_probe(void)
106{
107 iic_request_IPIs();
108
109 return num_possible_cpus();
110}
111
112static void smp_cell_setup_cpu(int cpu) 105static void smp_cell_setup_cpu(int cpu)
113{ 106{
114 if (cpu != boot_cpuid) 107 if (cpu != boot_cpuid)
@@ -139,7 +132,7 @@ static int smp_cell_kick_cpu(int nr)
139 132
140static struct smp_ops_t bpa_iic_smp_ops = { 133static struct smp_ops_t bpa_iic_smp_ops = {
141 .message_pass = iic_message_pass, 134 .message_pass = iic_message_pass,
142 .probe = smp_iic_probe, 135 .probe = iic_request_IPIs,
143 .kick_cpu = smp_cell_kick_cpu, 136 .kick_cpu = smp_cell_kick_cpu,
144 .setup_cpu = smp_cell_setup_cpu, 137 .setup_cpu = smp_cell_setup_cpu,
145 .cpu_bootable = smp_generic_cpu_bootable, 138 .cpu_bootable = smp_generic_cpu_bootable,
diff --git a/arch/powerpc/platforms/cell/spu_callbacks.c b/arch/powerpc/platforms/cell/spu_callbacks.c
index b0ec78e8ad68..a494028b2cdf 100644
--- a/arch/powerpc/platforms/cell/spu_callbacks.c
+++ b/arch/powerpc/platforms/cell/spu_callbacks.c
@@ -39,6 +39,7 @@ static void *spu_syscall_table[] = {
39#define PPC_SYS(func) sys_ni_syscall, 39#define PPC_SYS(func) sys_ni_syscall,
40#define OLDSYS(func) sys_ni_syscall, 40#define OLDSYS(func) sys_ni_syscall,
41#define SYS32ONLY(func) sys_ni_syscall, 41#define SYS32ONLY(func) sys_ni_syscall,
42#define PPC64ONLY(func) sys_ni_syscall,
42#define SYSX(f, f3264, f32) sys_ni_syscall, 43#define SYSX(f, f3264, f32) sys_ni_syscall,
43 44
44#define SYSCALL_SPU(func) sys_##func, 45#define SYSCALL_SPU(func) sys_##func,
diff --git a/arch/powerpc/platforms/chrp/setup.c b/arch/powerpc/platforms/chrp/setup.c
index 860a59eb8ea2..15ebc4e8a151 100644
--- a/arch/powerpc/platforms/chrp/setup.c
+++ b/arch/powerpc/platforms/chrp/setup.c
@@ -253,7 +253,7 @@ static void briq_restart(char *cmd)
253 * But unfortunately, the firmware does not connect /chosen/{stdin,stdout} 253 * But unfortunately, the firmware does not connect /chosen/{stdin,stdout}
254 * the the built-in serial node. Instead, a /failsafe node is created. 254 * the the built-in serial node. Instead, a /failsafe node is created.
255 */ 255 */
256static void chrp_init_early(void) 256static __init void chrp_init_early(void)
257{ 257{
258 struct device_node *node; 258 struct device_node *node;
259 const char *property; 259 const char *property;
diff --git a/arch/powerpc/platforms/maple/maple.h b/arch/powerpc/platforms/maple/maple.h
index c6911ddc479f..eecfa182b06e 100644
--- a/arch/powerpc/platforms/maple/maple.h
+++ b/arch/powerpc/platforms/maple/maple.h
@@ -10,3 +10,5 @@ extern void maple_calibrate_decr(void);
10extern void maple_pci_init(void); 10extern void maple_pci_init(void);
11extern void maple_pci_irq_fixup(struct pci_dev *dev); 11extern void maple_pci_irq_fixup(struct pci_dev *dev);
12extern int maple_pci_get_legacy_ide_irq(struct pci_dev *dev, int channel); 12extern int maple_pci_get_legacy_ide_irq(struct pci_dev *dev, int channel);
13
14extern struct pci_controller_ops maple_pci_controller_ops;
diff --git a/arch/powerpc/platforms/maple/pci.c b/arch/powerpc/platforms/maple/pci.c
index d3a13067ec42..a923230e575b 100644
--- a/arch/powerpc/platforms/maple/pci.c
+++ b/arch/powerpc/platforms/maple/pci.c
@@ -510,6 +510,7 @@ static int __init maple_add_bridge(struct device_node *dev)
510 return -ENOMEM; 510 return -ENOMEM;
511 hose->first_busno = bus_range ? bus_range[0] : 0; 511 hose->first_busno = bus_range ? bus_range[0] : 0;
512 hose->last_busno = bus_range ? bus_range[1] : 0xff; 512 hose->last_busno = bus_range ? bus_range[1] : 0xff;
513 hose->controller_ops = maple_pci_controller_ops;
513 514
514 disp_name = NULL; 515 disp_name = NULL;
515 if (of_device_is_compatible(dev, "u3-agp")) { 516 if (of_device_is_compatible(dev, "u3-agp")) {
@@ -660,3 +661,6 @@ static void quirk_ipr_msi(struct pci_dev *dev)
660} 661}
661DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN, 662DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN,
662 quirk_ipr_msi); 663 quirk_ipr_msi);
664
665struct pci_controller_ops maple_pci_controller_ops = {
666};
diff --git a/arch/powerpc/platforms/maple/setup.c b/arch/powerpc/platforms/maple/setup.c
index 56b85cd61aaf..a837188544c8 100644
--- a/arch/powerpc/platforms/maple/setup.c
+++ b/arch/powerpc/platforms/maple/setup.c
@@ -203,7 +203,7 @@ static void __init maple_init_early(void)
203{ 203{
204 DBG(" -> maple_init_early\n"); 204 DBG(" -> maple_init_early\n");
205 205
206 iommu_init_early_dart(); 206 iommu_init_early_dart(&maple_pci_controller_ops);
207 207
208 DBG(" <- maple_init_early\n"); 208 DBG(" <- maple_init_early\n");
209} 209}
diff --git a/arch/powerpc/platforms/pasemi/iommu.c b/arch/powerpc/platforms/pasemi/iommu.c
index 2e576f2ae442..b8f567b2ea19 100644
--- a/arch/powerpc/platforms/pasemi/iommu.c
+++ b/arch/powerpc/platforms/pasemi/iommu.c
@@ -27,6 +27,8 @@
27#include <asm/machdep.h> 27#include <asm/machdep.h>
28#include <asm/firmware.h> 28#include <asm/firmware.h>
29 29
30#include "pasemi.h"
31
30#define IOBMAP_PAGE_SHIFT 12 32#define IOBMAP_PAGE_SHIFT 12
31#define IOBMAP_PAGE_SIZE (1 << IOBMAP_PAGE_SHIFT) 33#define IOBMAP_PAGE_SIZE (1 << IOBMAP_PAGE_SHIFT)
32#define IOBMAP_PAGE_MASK (IOBMAP_PAGE_SIZE - 1) 34#define IOBMAP_PAGE_MASK (IOBMAP_PAGE_SIZE - 1)
@@ -248,8 +250,8 @@ void __init iommu_init_early_pasemi(void)
248 250
249 iob_init(NULL); 251 iob_init(NULL);
250 252
251 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_pasemi; 253 pasemi_pci_controller_ops.dma_dev_setup = pci_dma_dev_setup_pasemi;
252 ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pasemi; 254 pasemi_pci_controller_ops.dma_bus_setup = pci_dma_bus_setup_pasemi;
253 ppc_md.tce_build = iobmap_build; 255 ppc_md.tce_build = iobmap_build;
254 ppc_md.tce_free = iobmap_free; 256 ppc_md.tce_free = iobmap_free;
255 set_pci_dma_ops(&dma_iommu_ops); 257 set_pci_dma_ops(&dma_iommu_ops);
diff --git a/arch/powerpc/platforms/pasemi/pasemi.h b/arch/powerpc/platforms/pasemi/pasemi.h
index ea65bf0eb897..11f230a48227 100644
--- a/arch/powerpc/platforms/pasemi/pasemi.h
+++ b/arch/powerpc/platforms/pasemi/pasemi.h
@@ -30,5 +30,6 @@ static inline void restore_astate(int cpu)
30} 30}
31#endif 31#endif
32 32
33extern struct pci_controller_ops pasemi_pci_controller_ops;
33 34
34#endif /* _PASEMI_PASEMI_H */ 35#endif /* _PASEMI_PASEMI_H */
diff --git a/arch/powerpc/platforms/pasemi/pci.c b/arch/powerpc/platforms/pasemi/pci.c
index aa862713258c..f3a68a0fef23 100644
--- a/arch/powerpc/platforms/pasemi/pci.c
+++ b/arch/powerpc/platforms/pasemi/pci.c
@@ -31,6 +31,8 @@
31 31
32#include <asm/ppc-pci.h> 32#include <asm/ppc-pci.h>
33 33
34#include "pasemi.h"
35
34#define PA_PXP_CFA(bus, devfn, off) (((bus) << 20) | ((devfn) << 12) | (off)) 36#define PA_PXP_CFA(bus, devfn, off) (((bus) << 20) | ((devfn) << 12) | (off))
35 37
36static inline int pa_pxp_offset_valid(u8 bus, u8 devfn, int offset) 38static inline int pa_pxp_offset_valid(u8 bus, u8 devfn, int offset)
@@ -199,6 +201,7 @@ static int __init pas_add_bridge(struct device_node *dev)
199 201
200 hose->first_busno = 0; 202 hose->first_busno = 0;
201 hose->last_busno = 0xff; 203 hose->last_busno = 0xff;
204 hose->controller_ops = pasemi_pci_controller_ops;
202 205
203 setup_pa_pxp(hose); 206 setup_pa_pxp(hose);
204 207
@@ -239,3 +242,5 @@ void __iomem *pasemi_pci_getcfgaddr(struct pci_dev *dev, int offset)
239 242
240 return (void __iomem *)pa_pxp_cfg_addr(hose, dev->bus->number, dev->devfn, offset); 243 return (void __iomem *)pa_pxp_cfg_addr(hose, dev->bus->number, dev->devfn, offset);
241} 244}
245
246struct pci_controller_ops pasemi_pci_controller_ops;
diff --git a/arch/powerpc/platforms/powermac/bootx_init.c b/arch/powerpc/platforms/powermac/bootx_init.c
index 3e91ef538114..76f5013c35e5 100644
--- a/arch/powerpc/platforms/powermac/bootx_init.c
+++ b/arch/powerpc/platforms/powermac/bootx_init.c
@@ -246,7 +246,7 @@ static void __init bootx_scan_dt_build_strings(unsigned long base,
246 DBG(" detected display ! adding properties names !\n"); 246 DBG(" detected display ! adding properties names !\n");
247 bootx_dt_add_string("linux,boot-display", mem_end); 247 bootx_dt_add_string("linux,boot-display", mem_end);
248 bootx_dt_add_string("linux,opened", mem_end); 248 bootx_dt_add_string("linux,opened", mem_end);
249 strncpy(bootx_disp_path, namep, 255); 249 strlcpy(bootx_disp_path, namep, sizeof(bootx_disp_path));
250 } 250 }
251 251
252 /* get and store all property names */ 252 /* get and store all property names */
diff --git a/arch/powerpc/platforms/powermac/pci.c b/arch/powerpc/platforms/powermac/pci.c
index f4071a67ad00..59ab16fa600f 100644
--- a/arch/powerpc/platforms/powermac/pci.c
+++ b/arch/powerpc/platforms/powermac/pci.c
@@ -27,6 +27,8 @@
27#include <asm/grackle.h> 27#include <asm/grackle.h>
28#include <asm/ppc-pci.h> 28#include <asm/ppc-pci.h>
29 29
30#include "pmac.h"
31
30#undef DEBUG 32#undef DEBUG
31 33
32#ifdef DEBUG 34#ifdef DEBUG
@@ -798,6 +800,7 @@ static int __init pmac_add_bridge(struct device_node *dev)
798 return -ENOMEM; 800 return -ENOMEM;
799 hose->first_busno = bus_range ? bus_range[0] : 0; 801 hose->first_busno = bus_range ? bus_range[0] : 0;
800 hose->last_busno = bus_range ? bus_range[1] : 0xff; 802 hose->last_busno = bus_range ? bus_range[1] : 0xff;
803 hose->controller_ops = pmac_pci_controller_ops;
801 804
802 disp_name = NULL; 805 disp_name = NULL;
803 806
@@ -942,7 +945,7 @@ void __init pmac_pci_init(void)
942} 945}
943 946
944#ifdef CONFIG_PPC32 947#ifdef CONFIG_PPC32
945int pmac_pci_enable_device_hook(struct pci_dev *dev) 948static bool pmac_pci_enable_device_hook(struct pci_dev *dev)
946{ 949{
947 struct device_node* node; 950 struct device_node* node;
948 int updatecfg = 0; 951 int updatecfg = 0;
@@ -958,11 +961,11 @@ int pmac_pci_enable_device_hook(struct pci_dev *dev)
958 && !node) { 961 && !node) {
959 printk(KERN_INFO "Apple USB OHCI %s disabled by firmware\n", 962 printk(KERN_INFO "Apple USB OHCI %s disabled by firmware\n",
960 pci_name(dev)); 963 pci_name(dev));
961 return -EINVAL; 964 return false;
962 } 965 }
963 966
964 if (!node) 967 if (!node)
965 return 0; 968 return true;
966 969
967 uninorth_child = node->parent && 970 uninorth_child = node->parent &&
968 of_device_is_compatible(node->parent, "uni-north"); 971 of_device_is_compatible(node->parent, "uni-north");
@@ -1003,7 +1006,7 @@ int pmac_pci_enable_device_hook(struct pci_dev *dev)
1003 L1_CACHE_BYTES >> 2); 1006 L1_CACHE_BYTES >> 2);
1004 } 1007 }
1005 1008
1006 return 0; 1009 return true;
1007} 1010}
1008 1011
1009void pmac_pci_fixup_ohci(struct pci_dev *dev) 1012void pmac_pci_fixup_ohci(struct pci_dev *dev)
@@ -1223,3 +1226,30 @@ static void fixup_u4_pcie(struct pci_dev* dev)
1223 pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0); 1226 pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0);
1224} 1227}
1225DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_U4_PCIE, fixup_u4_pcie); 1228DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_U4_PCIE, fixup_u4_pcie);
1229
1230#ifdef CONFIG_PPC64
1231static int pmac_pci_probe_mode(struct pci_bus *bus)
1232{
1233 struct device_node *node = pci_bus_to_OF_node(bus);
1234
1235 /* We need to use normal PCI probing for the AGP bus,
1236 * since the device for the AGP bridge isn't in the tree.
1237 * Same for the PCIe host on U4 and the HT host bridge.
1238 */
1239 if (bus->self == NULL && (of_device_is_compatible(node, "u3-agp") ||
1240 of_device_is_compatible(node, "u4-pcie") ||
1241 of_device_is_compatible(node, "u3-ht")))
1242 return PCI_PROBE_NORMAL;
1243 return PCI_PROBE_DEVTREE;
1244}
1245#endif /* CONFIG_PPC64 */
1246
1247struct pci_controller_ops pmac_pci_controller_ops = {
1248#ifdef CONFIG_PPC64
1249 .probe_mode = pmac_pci_probe_mode,
1250#endif
1251#ifdef CONFIG_PPC32
1252 .enable_device_hook = pmac_pci_enable_device_hook,
1253#endif
1254};
1255
diff --git a/arch/powerpc/platforms/powermac/pic.c b/arch/powerpc/platforms/powermac/pic.c
index 4c24bf60d39d..59cfc9d63c2d 100644
--- a/arch/powerpc/platforms/powermac/pic.c
+++ b/arch/powerpc/platforms/powermac/pic.c
@@ -321,6 +321,9 @@ static void __init pmac_pic_probe_oldstyle(void)
321 max_irqs = max_real_irqs = 64; 321 max_irqs = max_real_irqs = 64;
322 322
323 /* We might have a second cascaded heathrow */ 323 /* We might have a second cascaded heathrow */
324
325 /* Compensate for of_node_put() in of_find_node_by_name() */
326 of_node_get(master);
324 slave = of_find_node_by_name(master, "mac-io"); 327 slave = of_find_node_by_name(master, "mac-io");
325 328
326 /* Check ordering of master & slave */ 329 /* Check ordering of master & slave */
diff --git a/arch/powerpc/platforms/powermac/pmac.h b/arch/powerpc/platforms/powermac/pmac.h
index 8327cce2bdb0..e7f8163d6769 100644
--- a/arch/powerpc/platforms/powermac/pmac.h
+++ b/arch/powerpc/platforms/powermac/pmac.h
@@ -25,7 +25,6 @@ extern void pmac_pci_init(void);
25extern void pmac_nvram_update(void); 25extern void pmac_nvram_update(void);
26extern unsigned char pmac_nvram_read_byte(int addr); 26extern unsigned char pmac_nvram_read_byte(int addr);
27extern void pmac_nvram_write_byte(int addr, unsigned char val); 27extern void pmac_nvram_write_byte(int addr, unsigned char val);
28extern int pmac_pci_enable_device_hook(struct pci_dev *dev);
29extern void pmac_pcibios_after_init(void); 28extern void pmac_pcibios_after_init(void);
30extern int of_show_percpuinfo(struct seq_file *m, int i); 29extern int of_show_percpuinfo(struct seq_file *m, int i);
31 30
@@ -39,4 +38,6 @@ extern void low_cpu_die(void) __attribute__((noreturn));
39extern int pmac_nvram_init(void); 38extern int pmac_nvram_init(void);
40extern void pmac_pic_init(void); 39extern void pmac_pic_init(void);
41 40
41extern struct pci_controller_ops pmac_pci_controller_ops;
42
42#endif /* __PMAC_H__ */ 43#endif /* __PMAC_H__ */
diff --git a/arch/powerpc/platforms/powermac/setup.c b/arch/powerpc/platforms/powermac/setup.c
index 713d36d45d1d..8dd78f4e1af4 100644
--- a/arch/powerpc/platforms/powermac/setup.c
+++ b/arch/powerpc/platforms/powermac/setup.c
@@ -473,7 +473,7 @@ static void __init pmac_init_early(void)
473 udbg_adb_init(!!strstr(boot_command_line, "btextdbg")); 473 udbg_adb_init(!!strstr(boot_command_line, "btextdbg"));
474 474
475#ifdef CONFIG_PPC64 475#ifdef CONFIG_PPC64
476 iommu_init_early_dart(); 476 iommu_init_early_dart(&pmac_pci_controller_ops);
477#endif 477#endif
478 478
479 /* SMP Init has to be done early as we need to patch up 479 /* SMP Init has to be done early as we need to patch up
@@ -637,24 +637,6 @@ static int __init pmac_probe(void)
637 return 1; 637 return 1;
638} 638}
639 639
640#ifdef CONFIG_PPC64
641/* Move that to pci.c */
642static int pmac_pci_probe_mode(struct pci_bus *bus)
643{
644 struct device_node *node = pci_bus_to_OF_node(bus);
645
646 /* We need to use normal PCI probing for the AGP bus,
647 * since the device for the AGP bridge isn't in the tree.
648 * Same for the PCIe host on U4 and the HT host bridge.
649 */
650 if (bus->self == NULL && (of_device_is_compatible(node, "u3-agp") ||
651 of_device_is_compatible(node, "u4-pcie") ||
652 of_device_is_compatible(node, "u3-ht")))
653 return PCI_PROBE_NORMAL;
654 return PCI_PROBE_DEVTREE;
655}
656#endif /* CONFIG_PPC64 */
657
658define_machine(powermac) { 640define_machine(powermac) {
659 .name = "PowerMac", 641 .name = "PowerMac",
660 .probe = pmac_probe, 642 .probe = pmac_probe,
@@ -674,12 +656,10 @@ define_machine(powermac) {
674 .feature_call = pmac_do_feature_call, 656 .feature_call = pmac_do_feature_call,
675 .progress = udbg_progress, 657 .progress = udbg_progress,
676#ifdef CONFIG_PPC64 658#ifdef CONFIG_PPC64
677 .pci_probe_mode = pmac_pci_probe_mode,
678 .power_save = power4_idle, 659 .power_save = power4_idle,
679 .enable_pmcs = power4_enable_pmcs, 660 .enable_pmcs = power4_enable_pmcs,
680#endif /* CONFIG_PPC64 */ 661#endif /* CONFIG_PPC64 */
681#ifdef CONFIG_PPC32 662#ifdef CONFIG_PPC32
682 .pcibios_enable_device_hook = pmac_pci_enable_device_hook,
683 .pcibios_after_init = pmac_pcibios_after_init, 663 .pcibios_after_init = pmac_pcibios_after_init,
684 .phys_mem_access_prot = pci_phys_mem_access_prot, 664 .phys_mem_access_prot = pci_phys_mem_access_prot,
685#endif 665#endif
diff --git a/arch/powerpc/platforms/powermac/smp.c b/arch/powerpc/platforms/powermac/smp.c
index af094ae03dbb..28a147ca32ba 100644
--- a/arch/powerpc/platforms/powermac/smp.c
+++ b/arch/powerpc/platforms/powermac/smp.c
@@ -268,14 +268,14 @@ static void __init psurge_quad_init(void)
268 mdelay(33); 268 mdelay(33);
269} 269}
270 270
271static int __init smp_psurge_probe(void) 271static void __init smp_psurge_probe(void)
272{ 272{
273 int i, ncpus; 273 int i, ncpus;
274 struct device_node *dn; 274 struct device_node *dn;
275 275
276 /* We don't do SMP on the PPC601 -- paulus */ 276 /* We don't do SMP on the PPC601 -- paulus */
277 if (PVR_VER(mfspr(SPRN_PVR)) == 1) 277 if (PVR_VER(mfspr(SPRN_PVR)) == 1)
278 return 1; 278 return;
279 279
280 /* 280 /*
281 * The powersurge cpu board can be used in the generation 281 * The powersurge cpu board can be used in the generation
@@ -289,7 +289,7 @@ static int __init smp_psurge_probe(void)
289 */ 289 */
290 dn = of_find_node_by_name(NULL, "hammerhead"); 290 dn = of_find_node_by_name(NULL, "hammerhead");
291 if (dn == NULL) 291 if (dn == NULL)
292 return 1; 292 return;
293 of_node_put(dn); 293 of_node_put(dn);
294 294
295 hhead_base = ioremap(HAMMERHEAD_BASE, 0x800); 295 hhead_base = ioremap(HAMMERHEAD_BASE, 0x800);
@@ -310,13 +310,13 @@ static int __init smp_psurge_probe(void)
310 /* not a dual-cpu card */ 310 /* not a dual-cpu card */
311 iounmap(hhead_base); 311 iounmap(hhead_base);
312 psurge_type = PSURGE_NONE; 312 psurge_type = PSURGE_NONE;
313 return 1; 313 return;
314 } 314 }
315 ncpus = 2; 315 ncpus = 2;
316 } 316 }
317 317
318 if (psurge_secondary_ipi_init()) 318 if (psurge_secondary_ipi_init())
319 return 1; 319 return;
320 320
321 psurge_start = ioremap(PSURGE_START, 4); 321 psurge_start = ioremap(PSURGE_START, 4);
322 psurge_pri_intr = ioremap(PSURGE_PRI_INTR, 4); 322 psurge_pri_intr = ioremap(PSURGE_PRI_INTR, 4);
@@ -332,8 +332,6 @@ static int __init smp_psurge_probe(void)
332 set_cpu_present(i, true); 332 set_cpu_present(i, true);
333 333
334 if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352); 334 if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352);
335
336 return ncpus;
337} 335}
338 336
339static int __init smp_psurge_kick_cpu(int nr) 337static int __init smp_psurge_kick_cpu(int nr)
@@ -766,7 +764,7 @@ static void __init smp_core99_setup(int ncpus)
766 powersave_nap = 0; 764 powersave_nap = 0;
767} 765}
768 766
769static int __init smp_core99_probe(void) 767static void __init smp_core99_probe(void)
770{ 768{
771 struct device_node *cpus; 769 struct device_node *cpus;
772 int ncpus = 0; 770 int ncpus = 0;
@@ -781,7 +779,7 @@ static int __init smp_core99_probe(void)
781 779
782 /* Nothing more to do if less than 2 of them */ 780 /* Nothing more to do if less than 2 of them */
783 if (ncpus <= 1) 781 if (ncpus <= 1)
784 return 1; 782 return;
785 783
786 /* We need to perform some early initialisations before we can start 784 /* We need to perform some early initialisations before we can start
787 * setting up SMP as we are running before initcalls 785 * setting up SMP as we are running before initcalls
@@ -797,8 +795,6 @@ static int __init smp_core99_probe(void)
797 795
798 /* Collect l2cr and l3cr values from CPU 0 */ 796 /* Collect l2cr and l3cr values from CPU 0 */
799 core99_init_caches(0); 797 core99_init_caches(0);
800
801 return ncpus;
802} 798}
803 799
804static int smp_core99_kick_cpu(int nr) 800static int smp_core99_kick_cpu(int nr)
diff --git a/arch/powerpc/platforms/powernv/Kconfig b/arch/powerpc/platforms/powernv/Kconfig
index 45a8ed0585cd..4b044d8cb49a 100644
--- a/arch/powerpc/platforms/powernv/Kconfig
+++ b/arch/powerpc/platforms/powernv/Kconfig
@@ -19,10 +19,3 @@ config PPC_POWERNV
19 select CPU_FREQ_GOV_CONSERVATIVE 19 select CPU_FREQ_GOV_CONSERVATIVE
20 select PPC_DOORBELL 20 select PPC_DOORBELL
21 default y 21 default y
22
23config PPC_POWERNV_RTAS
24 depends on PPC_POWERNV
25 bool "Support for RTAS based PowerNV platforms such as BML"
26 default y
27 select PPC_ICS_RTAS
28 select PPC_RTAS
diff --git a/arch/powerpc/platforms/powernv/Makefile b/arch/powerpc/platforms/powernv/Makefile
index 6f3c5d33c3af..33e44f37212f 100644
--- a/arch/powerpc/platforms/powernv/Makefile
+++ b/arch/powerpc/platforms/powernv/Makefile
@@ -5,7 +5,7 @@ obj-y += opal-msglog.o opal-hmi.o opal-power.o
5 5
6obj-$(CONFIG_SMP) += smp.o subcore.o subcore-asm.o 6obj-$(CONFIG_SMP) += smp.o subcore.o subcore-asm.o
7obj-$(CONFIG_PCI) += pci.o pci-p5ioc2.o pci-ioda.o 7obj-$(CONFIG_PCI) += pci.o pci-p5ioc2.o pci-ioda.o
8obj-$(CONFIG_EEH) += eeh-ioda.o eeh-powernv.o 8obj-$(CONFIG_EEH) += eeh-powernv.o
9obj-$(CONFIG_PPC_SCOM) += opal-xscom.o 9obj-$(CONFIG_PPC_SCOM) += opal-xscom.o
10obj-$(CONFIG_MEMORY_FAILURE) += opal-memory-errors.o 10obj-$(CONFIG_MEMORY_FAILURE) += opal-memory-errors.o
11obj-$(CONFIG_TRACEPOINTS) += opal-tracepoints.o 11obj-$(CONFIG_TRACEPOINTS) += opal-tracepoints.o
diff --git a/arch/powerpc/platforms/powernv/eeh-ioda.c b/arch/powerpc/platforms/powernv/eeh-ioda.c
deleted file mode 100644
index 2809c9895288..000000000000
--- a/arch/powerpc/platforms/powernv/eeh-ioda.c
+++ /dev/null
@@ -1,1149 +0,0 @@
1/*
2 * The file intends to implement the functions needed by EEH, which is
3 * built on IODA compliant chip. Actually, lots of functions related
4 * to EEH would be built based on the OPAL APIs.
5 *
6 * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/debugfs.h>
15#include <linux/delay.h>
16#include <linux/io.h>
17#include <linux/irq.h>
18#include <linux/kernel.h>
19#include <linux/msi.h>
20#include <linux/notifier.h>
21#include <linux/pci.h>
22#include <linux/string.h>
23
24#include <asm/eeh.h>
25#include <asm/eeh_event.h>
26#include <asm/io.h>
27#include <asm/iommu.h>
28#include <asm/msi_bitmap.h>
29#include <asm/opal.h>
30#include <asm/pci-bridge.h>
31#include <asm/ppc-pci.h>
32#include <asm/tce.h>
33
34#include "powernv.h"
35#include "pci.h"
36
37static int ioda_eeh_nb_init = 0;
38
39static int ioda_eeh_event(struct notifier_block *nb,
40 unsigned long events, void *change)
41{
42 uint64_t changed_evts = (uint64_t)change;
43
44 /*
45 * We simply send special EEH event if EEH has
46 * been enabled, or clear pending events in
47 * case that we enable EEH soon
48 */
49 if (!(changed_evts & OPAL_EVENT_PCI_ERROR) ||
50 !(events & OPAL_EVENT_PCI_ERROR))
51 return 0;
52
53 if (eeh_enabled())
54 eeh_send_failure_event(NULL);
55 else
56 opal_notifier_update_evt(OPAL_EVENT_PCI_ERROR, 0x0ul);
57
58 return 0;
59}
60
61static struct notifier_block ioda_eeh_nb = {
62 .notifier_call = ioda_eeh_event,
63 .next = NULL,
64 .priority = 0
65};
66
67#ifdef CONFIG_DEBUG_FS
68static ssize_t ioda_eeh_ei_write(struct file *filp,
69 const char __user *user_buf,
70 size_t count, loff_t *ppos)
71{
72 struct pci_controller *hose = filp->private_data;
73 struct pnv_phb *phb = hose->private_data;
74 struct eeh_dev *edev;
75 struct eeh_pe *pe;
76 int pe_no, type, func;
77 unsigned long addr, mask;
78 char buf[50];
79 int ret;
80
81 if (!phb->eeh_ops || !phb->eeh_ops->err_inject)
82 return -ENXIO;
83
84 ret = simple_write_to_buffer(buf, sizeof(buf), ppos, user_buf, count);
85 if (!ret)
86 return -EFAULT;
87
88 /* Retrieve parameters */
89 ret = sscanf(buf, "%x:%x:%x:%lx:%lx",
90 &pe_no, &type, &func, &addr, &mask);
91 if (ret != 5)
92 return -EINVAL;
93
94 /* Retrieve PE */
95 edev = kzalloc(sizeof(*edev), GFP_KERNEL);
96 if (!edev)
97 return -ENOMEM;
98 edev->phb = hose;
99 edev->pe_config_addr = pe_no;
100 pe = eeh_pe_get(edev);
101 kfree(edev);
102 if (!pe)
103 return -ENODEV;
104
105 /* Do error injection */
106 ret = phb->eeh_ops->err_inject(pe, type, func, addr, mask);
107 return ret < 0 ? ret : count;
108}
109
110static const struct file_operations ioda_eeh_ei_fops = {
111 .open = simple_open,
112 .llseek = no_llseek,
113 .write = ioda_eeh_ei_write,
114};
115
116static int ioda_eeh_dbgfs_set(void *data, int offset, u64 val)
117{
118 struct pci_controller *hose = data;
119 struct pnv_phb *phb = hose->private_data;
120
121 out_be64(phb->regs + offset, val);
122 return 0;
123}
124
125static int ioda_eeh_dbgfs_get(void *data, int offset, u64 *val)
126{
127 struct pci_controller *hose = data;
128 struct pnv_phb *phb = hose->private_data;
129
130 *val = in_be64(phb->regs + offset);
131 return 0;
132}
133
134static int ioda_eeh_outb_dbgfs_set(void *data, u64 val)
135{
136 return ioda_eeh_dbgfs_set(data, 0xD10, val);
137}
138
139static int ioda_eeh_outb_dbgfs_get(void *data, u64 *val)
140{
141 return ioda_eeh_dbgfs_get(data, 0xD10, val);
142}
143
144static int ioda_eeh_inbA_dbgfs_set(void *data, u64 val)
145{
146 return ioda_eeh_dbgfs_set(data, 0xD90, val);
147}
148
149static int ioda_eeh_inbA_dbgfs_get(void *data, u64 *val)
150{
151 return ioda_eeh_dbgfs_get(data, 0xD90, val);
152}
153
154static int ioda_eeh_inbB_dbgfs_set(void *data, u64 val)
155{
156 return ioda_eeh_dbgfs_set(data, 0xE10, val);
157}
158
159static int ioda_eeh_inbB_dbgfs_get(void *data, u64 *val)
160{
161 return ioda_eeh_dbgfs_get(data, 0xE10, val);
162}
163
164DEFINE_SIMPLE_ATTRIBUTE(ioda_eeh_outb_dbgfs_ops, ioda_eeh_outb_dbgfs_get,
165 ioda_eeh_outb_dbgfs_set, "0x%llx\n");
166DEFINE_SIMPLE_ATTRIBUTE(ioda_eeh_inbA_dbgfs_ops, ioda_eeh_inbA_dbgfs_get,
167 ioda_eeh_inbA_dbgfs_set, "0x%llx\n");
168DEFINE_SIMPLE_ATTRIBUTE(ioda_eeh_inbB_dbgfs_ops, ioda_eeh_inbB_dbgfs_get,
169 ioda_eeh_inbB_dbgfs_set, "0x%llx\n");
170#endif /* CONFIG_DEBUG_FS */
171
172
173/**
174 * ioda_eeh_post_init - Chip dependent post initialization
175 * @hose: PCI controller
176 *
177 * The function will be called after eeh PEs and devices
178 * have been built. That means the EEH is ready to supply
179 * service with I/O cache.
180 */
181static int ioda_eeh_post_init(struct pci_controller *hose)
182{
183 struct pnv_phb *phb = hose->private_data;
184 int ret;
185
186 /* Register OPAL event notifier */
187 if (!ioda_eeh_nb_init) {
188 ret = opal_notifier_register(&ioda_eeh_nb);
189 if (ret) {
190 pr_err("%s: Can't register OPAL event notifier (%d)\n",
191 __func__, ret);
192 return ret;
193 }
194
195 ioda_eeh_nb_init = 1;
196 }
197
198#ifdef CONFIG_DEBUG_FS
199 if (!phb->has_dbgfs && phb->dbgfs) {
200 phb->has_dbgfs = 1;
201
202 debugfs_create_file("err_injct", 0200,
203 phb->dbgfs, hose,
204 &ioda_eeh_ei_fops);
205
206 debugfs_create_file("err_injct_outbound", 0600,
207 phb->dbgfs, hose,
208 &ioda_eeh_outb_dbgfs_ops);
209 debugfs_create_file("err_injct_inboundA", 0600,
210 phb->dbgfs, hose,
211 &ioda_eeh_inbA_dbgfs_ops);
212 debugfs_create_file("err_injct_inboundB", 0600,
213 phb->dbgfs, hose,
214 &ioda_eeh_inbB_dbgfs_ops);
215 }
216#endif
217
218 /* If EEH is enabled, we're going to rely on that.
219 * Otherwise, we restore to conventional mechanism
220 * to clear frozen PE during PCI config access.
221 */
222 if (eeh_enabled())
223 phb->flags |= PNV_PHB_FLAG_EEH;
224 else
225 phb->flags &= ~PNV_PHB_FLAG_EEH;
226
227 return 0;
228}
229
230/**
231 * ioda_eeh_set_option - Set EEH operation or I/O setting
232 * @pe: EEH PE
233 * @option: options
234 *
235 * Enable or disable EEH option for the indicated PE. The
236 * function also can be used to enable I/O or DMA for the
237 * PE.
238 */
239static int ioda_eeh_set_option(struct eeh_pe *pe, int option)
240{
241 struct pci_controller *hose = pe->phb;
242 struct pnv_phb *phb = hose->private_data;
243 bool freeze_pe = false;
244 int enable, ret = 0;
245 s64 rc;
246
247 /* Check on PE number */
248 if (pe->addr < 0 || pe->addr >= phb->ioda.total_pe) {
249 pr_err("%s: PE address %x out of range [0, %x] "
250 "on PHB#%x\n",
251 __func__, pe->addr, phb->ioda.total_pe,
252 hose->global_number);
253 return -EINVAL;
254 }
255
256 switch (option) {
257 case EEH_OPT_DISABLE:
258 return -EPERM;
259 case EEH_OPT_ENABLE:
260 return 0;
261 case EEH_OPT_THAW_MMIO:
262 enable = OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO;
263 break;
264 case EEH_OPT_THAW_DMA:
265 enable = OPAL_EEH_ACTION_CLEAR_FREEZE_DMA;
266 break;
267 case EEH_OPT_FREEZE_PE:
268 freeze_pe = true;
269 enable = OPAL_EEH_ACTION_SET_FREEZE_ALL;
270 break;
271 default:
272 pr_warn("%s: Invalid option %d\n",
273 __func__, option);
274 return -EINVAL;
275 }
276
277 /* If PHB supports compound PE, to handle it */
278 if (freeze_pe) {
279 if (phb->freeze_pe) {
280 phb->freeze_pe(phb, pe->addr);
281 } else {
282 rc = opal_pci_eeh_freeze_set(phb->opal_id,
283 pe->addr,
284 enable);
285 if (rc != OPAL_SUCCESS) {
286 pr_warn("%s: Failure %lld freezing "
287 "PHB#%x-PE#%x\n",
288 __func__, rc,
289 phb->hose->global_number, pe->addr);
290 ret = -EIO;
291 }
292 }
293 } else {
294 if (phb->unfreeze_pe) {
295 ret = phb->unfreeze_pe(phb, pe->addr, enable);
296 } else {
297 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
298 pe->addr,
299 enable);
300 if (rc != OPAL_SUCCESS) {
301 pr_warn("%s: Failure %lld enable %d "
302 "for PHB#%x-PE#%x\n",
303 __func__, rc, option,
304 phb->hose->global_number, pe->addr);
305 ret = -EIO;
306 }
307 }
308 }
309
310 return ret;
311}
312
313static void ioda_eeh_phb_diag(struct eeh_pe *pe)
314{
315 struct pnv_phb *phb = pe->phb->private_data;
316 long rc;
317
318 rc = opal_pci_get_phb_diag_data2(phb->opal_id, pe->data,
319 PNV_PCI_DIAG_BUF_SIZE);
320 if (rc != OPAL_SUCCESS)
321 pr_warn("%s: Failed to get diag-data for PHB#%x (%ld)\n",
322 __func__, pe->phb->global_number, rc);
323}
324
325static int ioda_eeh_get_phb_state(struct eeh_pe *pe)
326{
327 struct pnv_phb *phb = pe->phb->private_data;
328 u8 fstate;
329 __be16 pcierr;
330 s64 rc;
331 int result = 0;
332
333 rc = opal_pci_eeh_freeze_status(phb->opal_id,
334 pe->addr,
335 &fstate,
336 &pcierr,
337 NULL);
338 if (rc != OPAL_SUCCESS) {
339 pr_warn("%s: Failure %lld getting PHB#%x state\n",
340 __func__, rc, phb->hose->global_number);
341 return EEH_STATE_NOT_SUPPORT;
342 }
343
344 /*
345 * Check PHB state. If the PHB is frozen for the
346 * first time, to dump the PHB diag-data.
347 */
348 if (be16_to_cpu(pcierr) != OPAL_EEH_PHB_ERROR) {
349 result = (EEH_STATE_MMIO_ACTIVE |
350 EEH_STATE_DMA_ACTIVE |
351 EEH_STATE_MMIO_ENABLED |
352 EEH_STATE_DMA_ENABLED);
353 } else if (!(pe->state & EEH_PE_ISOLATED)) {
354 eeh_pe_state_mark(pe, EEH_PE_ISOLATED);
355 ioda_eeh_phb_diag(pe);
356
357 if (eeh_has_flag(EEH_EARLY_DUMP_LOG))
358 pnv_pci_dump_phb_diag_data(pe->phb, pe->data);
359 }
360
361 return result;
362}
363
364static int ioda_eeh_get_pe_state(struct eeh_pe *pe)
365{
366 struct pnv_phb *phb = pe->phb->private_data;
367 u8 fstate;
368 __be16 pcierr;
369 s64 rc;
370 int result;
371
372 /*
373 * We don't clobber hardware frozen state until PE
374 * reset is completed. In order to keep EEH core
375 * moving forward, we have to return operational
376 * state during PE reset.
377 */
378 if (pe->state & EEH_PE_RESET) {
379 result = (EEH_STATE_MMIO_ACTIVE |
380 EEH_STATE_DMA_ACTIVE |
381 EEH_STATE_MMIO_ENABLED |
382 EEH_STATE_DMA_ENABLED);
383 return result;
384 }
385
386 /*
387 * Fetch PE state from hardware. If the PHB
388 * supports compound PE, let it handle that.
389 */
390 if (phb->get_pe_state) {
391 fstate = phb->get_pe_state(phb, pe->addr);
392 } else {
393 rc = opal_pci_eeh_freeze_status(phb->opal_id,
394 pe->addr,
395 &fstate,
396 &pcierr,
397 NULL);
398 if (rc != OPAL_SUCCESS) {
399 pr_warn("%s: Failure %lld getting PHB#%x-PE%x state\n",
400 __func__, rc, phb->hose->global_number, pe->addr);
401 return EEH_STATE_NOT_SUPPORT;
402 }
403 }
404
405 /* Figure out state */
406 switch (fstate) {
407 case OPAL_EEH_STOPPED_NOT_FROZEN:
408 result = (EEH_STATE_MMIO_ACTIVE |
409 EEH_STATE_DMA_ACTIVE |
410 EEH_STATE_MMIO_ENABLED |
411 EEH_STATE_DMA_ENABLED);
412 break;
413 case OPAL_EEH_STOPPED_MMIO_FREEZE:
414 result = (EEH_STATE_DMA_ACTIVE |
415 EEH_STATE_DMA_ENABLED);
416 break;
417 case OPAL_EEH_STOPPED_DMA_FREEZE:
418 result = (EEH_STATE_MMIO_ACTIVE |
419 EEH_STATE_MMIO_ENABLED);
420 break;
421 case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE:
422 result = 0;
423 break;
424 case OPAL_EEH_STOPPED_RESET:
425 result = EEH_STATE_RESET_ACTIVE;
426 break;
427 case OPAL_EEH_STOPPED_TEMP_UNAVAIL:
428 result = EEH_STATE_UNAVAILABLE;
429 break;
430 case OPAL_EEH_STOPPED_PERM_UNAVAIL:
431 result = EEH_STATE_NOT_SUPPORT;
432 break;
433 default:
434 result = EEH_STATE_NOT_SUPPORT;
435 pr_warn("%s: Invalid PHB#%x-PE#%x state %x\n",
436 __func__, phb->hose->global_number,
437 pe->addr, fstate);
438 }
439
440 /*
441 * If PHB supports compound PE, to freeze all
442 * slave PEs for consistency.
443 *
444 * If the PE is switching to frozen state for the
445 * first time, to dump the PHB diag-data.
446 */
447 if (!(result & EEH_STATE_NOT_SUPPORT) &&
448 !(result & EEH_STATE_UNAVAILABLE) &&
449 !(result & EEH_STATE_MMIO_ACTIVE) &&
450 !(result & EEH_STATE_DMA_ACTIVE) &&
451 !(pe->state & EEH_PE_ISOLATED)) {
452 if (phb->freeze_pe)
453 phb->freeze_pe(phb, pe->addr);
454
455 eeh_pe_state_mark(pe, EEH_PE_ISOLATED);
456 ioda_eeh_phb_diag(pe);
457
458 if (eeh_has_flag(EEH_EARLY_DUMP_LOG))
459 pnv_pci_dump_phb_diag_data(pe->phb, pe->data);
460 }
461
462 return result;
463}
464
465/**
466 * ioda_eeh_get_state - Retrieve the state of PE
467 * @pe: EEH PE
468 *
469 * The PE's state should be retrieved from the PEEV, PEST
470 * IODA tables. Since the OPAL has exported the function
471 * to do it, it'd better to use that.
472 */
473static int ioda_eeh_get_state(struct eeh_pe *pe)
474{
475 struct pnv_phb *phb = pe->phb->private_data;
476
477 /* Sanity check on PE number. PHB PE should have 0 */
478 if (pe->addr < 0 ||
479 pe->addr >= phb->ioda.total_pe) {
480 pr_warn("%s: PHB#%x-PE#%x out of range [0, %x]\n",
481 __func__, phb->hose->global_number,
482 pe->addr, phb->ioda.total_pe);
483 return EEH_STATE_NOT_SUPPORT;
484 }
485
486 if (pe->type & EEH_PE_PHB)
487 return ioda_eeh_get_phb_state(pe);
488
489 return ioda_eeh_get_pe_state(pe);
490}
491
492static s64 ioda_eeh_phb_poll(struct pnv_phb *phb)
493{
494 s64 rc = OPAL_HARDWARE;
495
496 while (1) {
497 rc = opal_pci_poll(phb->opal_id);
498 if (rc <= 0)
499 break;
500
501 if (system_state < SYSTEM_RUNNING)
502 udelay(1000 * rc);
503 else
504 msleep(rc);
505 }
506
507 return rc;
508}
509
510int ioda_eeh_phb_reset(struct pci_controller *hose, int option)
511{
512 struct pnv_phb *phb = hose->private_data;
513 s64 rc = OPAL_HARDWARE;
514
515 pr_debug("%s: Reset PHB#%x, option=%d\n",
516 __func__, hose->global_number, option);
517
518 /* Issue PHB complete reset request */
519 if (option == EEH_RESET_FUNDAMENTAL ||
520 option == EEH_RESET_HOT)
521 rc = opal_pci_reset(phb->opal_id,
522 OPAL_RESET_PHB_COMPLETE,
523 OPAL_ASSERT_RESET);
524 else if (option == EEH_RESET_DEACTIVATE)
525 rc = opal_pci_reset(phb->opal_id,
526 OPAL_RESET_PHB_COMPLETE,
527 OPAL_DEASSERT_RESET);
528 if (rc < 0)
529 goto out;
530
531 /*
532 * Poll state of the PHB until the request is done
533 * successfully. The PHB reset is usually PHB complete
534 * reset followed by hot reset on root bus. So we also
535 * need the PCI bus settlement delay.
536 */
537 rc = ioda_eeh_phb_poll(phb);
538 if (option == EEH_RESET_DEACTIVATE) {
539 if (system_state < SYSTEM_RUNNING)
540 udelay(1000 * EEH_PE_RST_SETTLE_TIME);
541 else
542 msleep(EEH_PE_RST_SETTLE_TIME);
543 }
544out:
545 if (rc != OPAL_SUCCESS)
546 return -EIO;
547
548 return 0;
549}
550
551static int ioda_eeh_root_reset(struct pci_controller *hose, int option)
552{
553 struct pnv_phb *phb = hose->private_data;
554 s64 rc = OPAL_SUCCESS;
555
556 pr_debug("%s: Reset PHB#%x, option=%d\n",
557 __func__, hose->global_number, option);
558
559 /*
560 * During the reset deassert time, we needn't care
561 * the reset scope because the firmware does nothing
562 * for fundamental or hot reset during deassert phase.
563 */
564 if (option == EEH_RESET_FUNDAMENTAL)
565 rc = opal_pci_reset(phb->opal_id,
566 OPAL_RESET_PCI_FUNDAMENTAL,
567 OPAL_ASSERT_RESET);
568 else if (option == EEH_RESET_HOT)
569 rc = opal_pci_reset(phb->opal_id,
570 OPAL_RESET_PCI_HOT,
571 OPAL_ASSERT_RESET);
572 else if (option == EEH_RESET_DEACTIVATE)
573 rc = opal_pci_reset(phb->opal_id,
574 OPAL_RESET_PCI_HOT,
575 OPAL_DEASSERT_RESET);
576 if (rc < 0)
577 goto out;
578
579 /* Poll state of the PHB until the request is done */
580 rc = ioda_eeh_phb_poll(phb);
581 if (option == EEH_RESET_DEACTIVATE)
582 msleep(EEH_PE_RST_SETTLE_TIME);
583out:
584 if (rc != OPAL_SUCCESS)
585 return -EIO;
586
587 return 0;
588}
589
590static int ioda_eeh_bridge_reset(struct pci_dev *dev, int option)
591
592{
593 struct device_node *dn = pci_device_to_OF_node(dev);
594 struct eeh_dev *edev = of_node_to_eeh_dev(dn);
595 int aer = edev ? edev->aer_cap : 0;
596 u32 ctrl;
597
598 pr_debug("%s: Reset PCI bus %04x:%02x with option %d\n",
599 __func__, pci_domain_nr(dev->bus),
600 dev->bus->number, option);
601
602 switch (option) {
603 case EEH_RESET_FUNDAMENTAL:
604 case EEH_RESET_HOT:
605 /* Don't report linkDown event */
606 if (aer) {
607 eeh_ops->read_config(dn, aer + PCI_ERR_UNCOR_MASK,
608 4, &ctrl);
609 ctrl |= PCI_ERR_UNC_SURPDN;
610 eeh_ops->write_config(dn, aer + PCI_ERR_UNCOR_MASK,
611 4, ctrl);
612 }
613
614 eeh_ops->read_config(dn, PCI_BRIDGE_CONTROL, 2, &ctrl);
615 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
616 eeh_ops->write_config(dn, PCI_BRIDGE_CONTROL, 2, ctrl);
617 msleep(EEH_PE_RST_HOLD_TIME);
618
619 break;
620 case EEH_RESET_DEACTIVATE:
621 eeh_ops->read_config(dn, PCI_BRIDGE_CONTROL, 2, &ctrl);
622 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
623 eeh_ops->write_config(dn, PCI_BRIDGE_CONTROL, 2, ctrl);
624 msleep(EEH_PE_RST_SETTLE_TIME);
625
626 /* Continue reporting linkDown event */
627 if (aer) {
628 eeh_ops->read_config(dn, aer + PCI_ERR_UNCOR_MASK,
629 4, &ctrl);
630 ctrl &= ~PCI_ERR_UNC_SURPDN;
631 eeh_ops->write_config(dn, aer + PCI_ERR_UNCOR_MASK,
632 4, ctrl);
633 }
634
635 break;
636 }
637
638 return 0;
639}
640
641void pnv_pci_reset_secondary_bus(struct pci_dev *dev)
642{
643 struct pci_controller *hose;
644
645 if (pci_is_root_bus(dev->bus)) {
646 hose = pci_bus_to_host(dev->bus);
647 ioda_eeh_root_reset(hose, EEH_RESET_HOT);
648 ioda_eeh_root_reset(hose, EEH_RESET_DEACTIVATE);
649 } else {
650 ioda_eeh_bridge_reset(dev, EEH_RESET_HOT);
651 ioda_eeh_bridge_reset(dev, EEH_RESET_DEACTIVATE);
652 }
653}
654
655/**
656 * ioda_eeh_reset - Reset the indicated PE
657 * @pe: EEH PE
658 * @option: reset option
659 *
660 * Do reset on the indicated PE. For PCI bus sensitive PE,
661 * we need to reset the parent p2p bridge. The PHB has to
662 * be reinitialized if the p2p bridge is root bridge. For
663 * PCI device sensitive PE, we will try to reset the device
664 * through FLR. For now, we don't have OPAL APIs to do HARD
665 * reset yet, so all reset would be SOFT (HOT) reset.
666 */
667static int ioda_eeh_reset(struct eeh_pe *pe, int option)
668{
669 struct pci_controller *hose = pe->phb;
670 struct pci_bus *bus;
671 int ret;
672
673 /*
674 * For PHB reset, we always have complete reset. For those PEs whose
675 * primary bus derived from root complex (root bus) or root port
676 * (usually bus#1), we apply hot or fundamental reset on the root port.
677 * For other PEs, we always have hot reset on the PE primary bus.
678 *
679 * Here, we have different design to pHyp, which always clear the
680 * frozen state during PE reset. However, the good idea here from
681 * benh is to keep frozen state before we get PE reset done completely
682 * (until BAR restore). With the frozen state, HW drops illegal IO
683 * or MMIO access, which can incur recrusive frozen PE during PE
684 * reset. The side effect is that EEH core has to clear the frozen
685 * state explicitly after BAR restore.
686 */
687 if (pe->type & EEH_PE_PHB) {
688 ret = ioda_eeh_phb_reset(hose, option);
689 } else {
690 struct pnv_phb *phb;
691 s64 rc;
692
693 /*
694 * The frozen PE might be caused by PAPR error injection
695 * registers, which are expected to be cleared after hitting
696 * frozen PE as stated in the hardware spec. Unfortunately,
697 * that's not true on P7IOC. So we have to clear it manually
698 * to avoid recursive EEH errors during recovery.
699 */
700 phb = hose->private_data;
701 if (phb->model == PNV_PHB_MODEL_P7IOC &&
702 (option == EEH_RESET_HOT ||
703 option == EEH_RESET_FUNDAMENTAL)) {
704 rc = opal_pci_reset(phb->opal_id,
705 OPAL_RESET_PHB_ERROR,
706 OPAL_ASSERT_RESET);
707 if (rc != OPAL_SUCCESS) {
708 pr_warn("%s: Failure %lld clearing "
709 "error injection registers\n",
710 __func__, rc);
711 return -EIO;
712 }
713 }
714
715 bus = eeh_pe_bus_get(pe);
716 if (pci_is_root_bus(bus) ||
717 pci_is_root_bus(bus->parent))
718 ret = ioda_eeh_root_reset(hose, option);
719 else
720 ret = ioda_eeh_bridge_reset(bus->self, option);
721 }
722
723 return ret;
724}
725
726/**
727 * ioda_eeh_get_log - Retrieve error log
728 * @pe: frozen PE
729 * @severity: permanent or temporary error
730 * @drv_log: device driver log
731 * @len: length of device driver log
732 *
733 * Retrieve error log, which contains log from device driver
734 * and firmware.
735 */
736static int ioda_eeh_get_log(struct eeh_pe *pe, int severity,
737 char *drv_log, unsigned long len)
738{
739 if (!eeh_has_flag(EEH_EARLY_DUMP_LOG))
740 pnv_pci_dump_phb_diag_data(pe->phb, pe->data);
741
742 return 0;
743}
744
745/**
746 * ioda_eeh_configure_bridge - Configure the PCI bridges for the indicated PE
747 * @pe: EEH PE
748 *
749 * For particular PE, it might have included PCI bridges. In order
750 * to make the PE work properly, those PCI bridges should be configured
751 * correctly. However, we need do nothing on P7IOC since the reset
752 * function will do everything that should be covered by the function.
753 */
754static int ioda_eeh_configure_bridge(struct eeh_pe *pe)
755{
756 return 0;
757}
758
759static int ioda_eeh_err_inject(struct eeh_pe *pe, int type, int func,
760 unsigned long addr, unsigned long mask)
761{
762 struct pci_controller *hose = pe->phb;
763 struct pnv_phb *phb = hose->private_data;
764 s64 ret;
765
766 /* Sanity check on error type */
767 if (type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR &&
768 type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64) {
769 pr_warn("%s: Invalid error type %d\n",
770 __func__, type);
771 return -ERANGE;
772 }
773
774 if (func < OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR ||
775 func > OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET) {
776 pr_warn("%s: Invalid error function %d\n",
777 __func__, func);
778 return -ERANGE;
779 }
780
781 /* Firmware supports error injection ? */
782 if (!opal_check_token(OPAL_PCI_ERR_INJECT)) {
783 pr_warn("%s: Firmware doesn't support error injection\n",
784 __func__);
785 return -ENXIO;
786 }
787
788 /* Do error injection */
789 ret = opal_pci_err_inject(phb->opal_id, pe->addr,
790 type, func, addr, mask);
791 if (ret != OPAL_SUCCESS) {
792 pr_warn("%s: Failure %lld injecting error "
793 "%d-%d to PHB#%x-PE#%x\n",
794 __func__, ret, type, func,
795 hose->global_number, pe->addr);
796 return -EIO;
797 }
798
799 return 0;
800}
801
802static void ioda_eeh_hub_diag_common(struct OpalIoP7IOCErrorData *data)
803{
804 /* GEM */
805 if (data->gemXfir || data->gemRfir ||
806 data->gemRirqfir || data->gemMask || data->gemRwof)
807 pr_info(" GEM: %016llx %016llx %016llx %016llx %016llx\n",
808 be64_to_cpu(data->gemXfir),
809 be64_to_cpu(data->gemRfir),
810 be64_to_cpu(data->gemRirqfir),
811 be64_to_cpu(data->gemMask),
812 be64_to_cpu(data->gemRwof));
813
814 /* LEM */
815 if (data->lemFir || data->lemErrMask ||
816 data->lemAction0 || data->lemAction1 || data->lemWof)
817 pr_info(" LEM: %016llx %016llx %016llx %016llx %016llx\n",
818 be64_to_cpu(data->lemFir),
819 be64_to_cpu(data->lemErrMask),
820 be64_to_cpu(data->lemAction0),
821 be64_to_cpu(data->lemAction1),
822 be64_to_cpu(data->lemWof));
823}
824
825static void ioda_eeh_hub_diag(struct pci_controller *hose)
826{
827 struct pnv_phb *phb = hose->private_data;
828 struct OpalIoP7IOCErrorData *data = &phb->diag.hub_diag;
829 long rc;
830
831 rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data));
832 if (rc != OPAL_SUCCESS) {
833 pr_warn("%s: Failed to get HUB#%llx diag-data (%ld)\n",
834 __func__, phb->hub_id, rc);
835 return;
836 }
837
838 switch (data->type) {
839 case OPAL_P7IOC_DIAG_TYPE_RGC:
840 pr_info("P7IOC diag-data for RGC\n\n");
841 ioda_eeh_hub_diag_common(data);
842 if (data->rgc.rgcStatus || data->rgc.rgcLdcp)
843 pr_info(" RGC: %016llx %016llx\n",
844 be64_to_cpu(data->rgc.rgcStatus),
845 be64_to_cpu(data->rgc.rgcLdcp));
846 break;
847 case OPAL_P7IOC_DIAG_TYPE_BI:
848 pr_info("P7IOC diag-data for BI %s\n\n",
849 data->bi.biDownbound ? "Downbound" : "Upbound");
850 ioda_eeh_hub_diag_common(data);
851 if (data->bi.biLdcp0 || data->bi.biLdcp1 ||
852 data->bi.biLdcp2 || data->bi.biFenceStatus)
853 pr_info(" BI: %016llx %016llx %016llx %016llx\n",
854 be64_to_cpu(data->bi.biLdcp0),
855 be64_to_cpu(data->bi.biLdcp1),
856 be64_to_cpu(data->bi.biLdcp2),
857 be64_to_cpu(data->bi.biFenceStatus));
858 break;
859 case OPAL_P7IOC_DIAG_TYPE_CI:
860 pr_info("P7IOC diag-data for CI Port %d\n\n",
861 data->ci.ciPort);
862 ioda_eeh_hub_diag_common(data);
863 if (data->ci.ciPortStatus || data->ci.ciPortLdcp)
864 pr_info(" CI: %016llx %016llx\n",
865 be64_to_cpu(data->ci.ciPortStatus),
866 be64_to_cpu(data->ci.ciPortLdcp));
867 break;
868 case OPAL_P7IOC_DIAG_TYPE_MISC:
869 pr_info("P7IOC diag-data for MISC\n\n");
870 ioda_eeh_hub_diag_common(data);
871 break;
872 case OPAL_P7IOC_DIAG_TYPE_I2C:
873 pr_info("P7IOC diag-data for I2C\n\n");
874 ioda_eeh_hub_diag_common(data);
875 break;
876 default:
877 pr_warn("%s: Invalid type of HUB#%llx diag-data (%d)\n",
878 __func__, phb->hub_id, data->type);
879 }
880}
881
882static int ioda_eeh_get_pe(struct pci_controller *hose,
883 u16 pe_no, struct eeh_pe **pe)
884{
885 struct pnv_phb *phb = hose->private_data;
886 struct pnv_ioda_pe *pnv_pe;
887 struct eeh_pe *dev_pe;
888 struct eeh_dev edev;
889
890 /*
891 * If PHB supports compound PE, to fetch
892 * the master PE because slave PE is invisible
893 * to EEH core.
894 */
895 pnv_pe = &phb->ioda.pe_array[pe_no];
896 if (pnv_pe->flags & PNV_IODA_PE_SLAVE) {
897 pnv_pe = pnv_pe->master;
898 WARN_ON(!pnv_pe ||
899 !(pnv_pe->flags & PNV_IODA_PE_MASTER));
900 pe_no = pnv_pe->pe_number;
901 }
902
903 /* Find the PE according to PE# */
904 memset(&edev, 0, sizeof(struct eeh_dev));
905 edev.phb = hose;
906 edev.pe_config_addr = pe_no;
907 dev_pe = eeh_pe_get(&edev);
908 if (!dev_pe)
909 return -EEXIST;
910
911 /* Freeze the (compound) PE */
912 *pe = dev_pe;
913 if (!(dev_pe->state & EEH_PE_ISOLATED))
914 phb->freeze_pe(phb, pe_no);
915
916 /*
917 * At this point, we're sure the (compound) PE should
918 * have been frozen. However, we still need poke until
919 * hitting the frozen PE on top level.
920 */
921 dev_pe = dev_pe->parent;
922 while (dev_pe && !(dev_pe->type & EEH_PE_PHB)) {
923 int ret;
924 int active_flags = (EEH_STATE_MMIO_ACTIVE |
925 EEH_STATE_DMA_ACTIVE);
926
927 ret = eeh_ops->get_state(dev_pe, NULL);
928 if (ret <= 0 || (ret & active_flags) == active_flags) {
929 dev_pe = dev_pe->parent;
930 continue;
931 }
932
933 /* Frozen parent PE */
934 *pe = dev_pe;
935 if (!(dev_pe->state & EEH_PE_ISOLATED))
936 phb->freeze_pe(phb, dev_pe->addr);
937
938 /* Next one */
939 dev_pe = dev_pe->parent;
940 }
941
942 return 0;
943}
944
945/**
946 * ioda_eeh_next_error - Retrieve next error for EEH core to handle
947 * @pe: The affected PE
948 *
949 * The function is expected to be called by EEH core while it gets
950 * special EEH event (without binding PE). The function calls to
951 * OPAL APIs for next error to handle. The informational error is
952 * handled internally by platform. However, the dead IOC, dead PHB,
953 * fenced PHB and frozen PE should be handled by EEH core eventually.
954 */
955static int ioda_eeh_next_error(struct eeh_pe **pe)
956{
957 struct pci_controller *hose;
958 struct pnv_phb *phb;
959 struct eeh_pe *phb_pe, *parent_pe;
960 __be64 frozen_pe_no;
961 __be16 err_type, severity;
962 int active_flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE);
963 long rc;
964 int state, ret = EEH_NEXT_ERR_NONE;
965
966 /*
967 * While running here, it's safe to purge the event queue.
968 * And we should keep the cached OPAL notifier event sychronized
969 * between the kernel and firmware.
970 */
971 eeh_remove_event(NULL, false);
972 opal_notifier_update_evt(OPAL_EVENT_PCI_ERROR, 0x0ul);
973
974 list_for_each_entry(hose, &hose_list, list_node) {
975 /*
976 * If the subordinate PCI buses of the PHB has been
977 * removed or is exactly under error recovery, we
978 * needn't take care of it any more.
979 */
980 phb = hose->private_data;
981 phb_pe = eeh_phb_pe_get(hose);
982 if (!phb_pe || (phb_pe->state & EEH_PE_ISOLATED))
983 continue;
984
985 rc = opal_pci_next_error(phb->opal_id,
986 &frozen_pe_no, &err_type, &severity);
987
988 /* If OPAL API returns error, we needn't proceed */
989 if (rc != OPAL_SUCCESS) {
990 pr_devel("%s: Invalid return value on "
991 "PHB#%x (0x%lx) from opal_pci_next_error",
992 __func__, hose->global_number, rc);
993 continue;
994 }
995
996 /* If the PHB doesn't have error, stop processing */
997 if (be16_to_cpu(err_type) == OPAL_EEH_NO_ERROR ||
998 be16_to_cpu(severity) == OPAL_EEH_SEV_NO_ERROR) {
999 pr_devel("%s: No error found on PHB#%x\n",
1000 __func__, hose->global_number);
1001 continue;
1002 }
1003
1004 /*
1005 * Processing the error. We're expecting the error with
1006 * highest priority reported upon multiple errors on the
1007 * specific PHB.
1008 */
1009 pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n",
1010 __func__, be16_to_cpu(err_type), be16_to_cpu(severity),
1011 be64_to_cpu(frozen_pe_no), hose->global_number);
1012 switch (be16_to_cpu(err_type)) {
1013 case OPAL_EEH_IOC_ERROR:
1014 if (be16_to_cpu(severity) == OPAL_EEH_SEV_IOC_DEAD) {
1015 pr_err("EEH: dead IOC detected\n");
1016 ret = EEH_NEXT_ERR_DEAD_IOC;
1017 } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) {
1018 pr_info("EEH: IOC informative error "
1019 "detected\n");
1020 ioda_eeh_hub_diag(hose);
1021 ret = EEH_NEXT_ERR_NONE;
1022 }
1023
1024 break;
1025 case OPAL_EEH_PHB_ERROR:
1026 if (be16_to_cpu(severity) == OPAL_EEH_SEV_PHB_DEAD) {
1027 *pe = phb_pe;
1028 pr_err("EEH: dead PHB#%x detected, "
1029 "location: %s\n",
1030 hose->global_number,
1031 eeh_pe_loc_get(phb_pe));
1032 ret = EEH_NEXT_ERR_DEAD_PHB;
1033 } else if (be16_to_cpu(severity) ==
1034 OPAL_EEH_SEV_PHB_FENCED) {
1035 *pe = phb_pe;
1036 pr_err("EEH: Fenced PHB#%x detected, "
1037 "location: %s\n",
1038 hose->global_number,
1039 eeh_pe_loc_get(phb_pe));
1040 ret = EEH_NEXT_ERR_FENCED_PHB;
1041 } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) {
1042 pr_info("EEH: PHB#%x informative error "
1043 "detected, location: %s\n",
1044 hose->global_number,
1045 eeh_pe_loc_get(phb_pe));
1046 ioda_eeh_phb_diag(phb_pe);
1047 pnv_pci_dump_phb_diag_data(hose, phb_pe->data);
1048 ret = EEH_NEXT_ERR_NONE;
1049 }
1050
1051 break;
1052 case OPAL_EEH_PE_ERROR:
1053 /*
1054 * If we can't find the corresponding PE, we
1055 * just try to unfreeze.
1056 */
1057 if (ioda_eeh_get_pe(hose,
1058 be64_to_cpu(frozen_pe_no), pe)) {
1059 /* Try best to clear it */
1060 pr_info("EEH: Clear non-existing PHB#%x-PE#%llx\n",
1061 hose->global_number, frozen_pe_no);
1062 pr_info("EEH: PHB location: %s\n",
1063 eeh_pe_loc_get(phb_pe));
1064 opal_pci_eeh_freeze_clear(phb->opal_id, frozen_pe_no,
1065 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
1066 ret = EEH_NEXT_ERR_NONE;
1067 } else if ((*pe)->state & EEH_PE_ISOLATED ||
1068 eeh_pe_passed(*pe)) {
1069 ret = EEH_NEXT_ERR_NONE;
1070 } else {
1071 pr_err("EEH: Frozen PE#%x on PHB#%x detected\n",
1072 (*pe)->addr, (*pe)->phb->global_number);
1073 pr_err("EEH: PE location: %s, PHB location: %s\n",
1074 eeh_pe_loc_get(*pe), eeh_pe_loc_get(phb_pe));
1075 ret = EEH_NEXT_ERR_FROZEN_PE;
1076 }
1077
1078 break;
1079 default:
1080 pr_warn("%s: Unexpected error type %d\n",
1081 __func__, be16_to_cpu(err_type));
1082 }
1083
1084 /*
1085 * EEH core will try recover from fenced PHB or
1086 * frozen PE. In the time for frozen PE, EEH core
1087 * enable IO path for that before collecting logs,
1088 * but it ruins the site. So we have to dump the
1089 * log in advance here.
1090 */
1091 if ((ret == EEH_NEXT_ERR_FROZEN_PE ||
1092 ret == EEH_NEXT_ERR_FENCED_PHB) &&
1093 !((*pe)->state & EEH_PE_ISOLATED)) {
1094 eeh_pe_state_mark(*pe, EEH_PE_ISOLATED);
1095 ioda_eeh_phb_diag(*pe);
1096
1097 if (eeh_has_flag(EEH_EARLY_DUMP_LOG))
1098 pnv_pci_dump_phb_diag_data((*pe)->phb,
1099 (*pe)->data);
1100 }
1101
1102 /*
1103 * We probably have the frozen parent PE out there and
1104 * we need have to handle frozen parent PE firstly.
1105 */
1106 if (ret == EEH_NEXT_ERR_FROZEN_PE) {
1107 parent_pe = (*pe)->parent;
1108 while (parent_pe) {
1109 /* Hit the ceiling ? */
1110 if (parent_pe->type & EEH_PE_PHB)
1111 break;
1112
1113 /* Frozen parent PE ? */
1114 state = ioda_eeh_get_state(parent_pe);
1115 if (state > 0 &&
1116 (state & active_flags) != active_flags)
1117 *pe = parent_pe;
1118
1119 /* Next parent level */
1120 parent_pe = parent_pe->parent;
1121 }
1122
1123 /* We possibly migrate to another PE */
1124 eeh_pe_state_mark(*pe, EEH_PE_ISOLATED);
1125 }
1126
1127 /*
1128 * If we have no errors on the specific PHB or only
1129 * informative error there, we continue poking it.
1130 * Otherwise, we need actions to be taken by upper
1131 * layer.
1132 */
1133 if (ret > EEH_NEXT_ERR_INF)
1134 break;
1135 }
1136
1137 return ret;
1138}
1139
1140struct pnv_eeh_ops ioda_eeh_ops = {
1141 .post_init = ioda_eeh_post_init,
1142 .set_option = ioda_eeh_set_option,
1143 .get_state = ioda_eeh_get_state,
1144 .reset = ioda_eeh_reset,
1145 .get_log = ioda_eeh_get_log,
1146 .configure_bridge = ioda_eeh_configure_bridge,
1147 .err_inject = ioda_eeh_err_inject,
1148 .next_error = ioda_eeh_next_error
1149};
diff --git a/arch/powerpc/platforms/powernv/eeh-powernv.c b/arch/powerpc/platforms/powernv/eeh-powernv.c
index e261869adc86..ce738ab3d5a9 100644
--- a/arch/powerpc/platforms/powernv/eeh-powernv.c
+++ b/arch/powerpc/platforms/powernv/eeh-powernv.c
@@ -12,6 +12,7 @@
12 */ 12 */
13 13
14#include <linux/atomic.h> 14#include <linux/atomic.h>
15#include <linux/debugfs.h>
15#include <linux/delay.h> 16#include <linux/delay.h>
16#include <linux/export.h> 17#include <linux/export.h>
17#include <linux/init.h> 18#include <linux/init.h>
@@ -38,12 +39,14 @@
38#include "powernv.h" 39#include "powernv.h"
39#include "pci.h" 40#include "pci.h"
40 41
42static bool pnv_eeh_nb_init = false;
43
41/** 44/**
42 * powernv_eeh_init - EEH platform dependent initialization 45 * pnv_eeh_init - EEH platform dependent initialization
43 * 46 *
44 * EEH platform dependent initialization on powernv 47 * EEH platform dependent initialization on powernv
45 */ 48 */
46static int powernv_eeh_init(void) 49static int pnv_eeh_init(void)
47{ 50{
48 struct pci_controller *hose; 51 struct pci_controller *hose;
49 struct pnv_phb *phb; 52 struct pnv_phb *phb;
@@ -85,37 +88,280 @@ static int powernv_eeh_init(void)
85 return 0; 88 return 0;
86} 89}
87 90
91static int pnv_eeh_event(struct notifier_block *nb,
92 unsigned long events, void *change)
93{
94 uint64_t changed_evts = (uint64_t)change;
95
96 /*
97 * We simply send special EEH event if EEH has
98 * been enabled, or clear pending events in
99 * case that we enable EEH soon
100 */
101 if (!(changed_evts & OPAL_EVENT_PCI_ERROR) ||
102 !(events & OPAL_EVENT_PCI_ERROR))
103 return 0;
104
105 if (eeh_enabled())
106 eeh_send_failure_event(NULL);
107 else
108 opal_notifier_update_evt(OPAL_EVENT_PCI_ERROR, 0x0ul);
109
110 return 0;
111}
112
113static struct notifier_block pnv_eeh_nb = {
114 .notifier_call = pnv_eeh_event,
115 .next = NULL,
116 .priority = 0
117};
118
119#ifdef CONFIG_DEBUG_FS
120static ssize_t pnv_eeh_ei_write(struct file *filp,
121 const char __user *user_buf,
122 size_t count, loff_t *ppos)
123{
124 struct pci_controller *hose = filp->private_data;
125 struct eeh_dev *edev;
126 struct eeh_pe *pe;
127 int pe_no, type, func;
128 unsigned long addr, mask;
129 char buf[50];
130 int ret;
131
132 if (!eeh_ops || !eeh_ops->err_inject)
133 return -ENXIO;
134
135 /* Copy over argument buffer */
136 ret = simple_write_to_buffer(buf, sizeof(buf), ppos, user_buf, count);
137 if (!ret)
138 return -EFAULT;
139
140 /* Retrieve parameters */
141 ret = sscanf(buf, "%x:%x:%x:%lx:%lx",
142 &pe_no, &type, &func, &addr, &mask);
143 if (ret != 5)
144 return -EINVAL;
145
146 /* Retrieve PE */
147 edev = kzalloc(sizeof(*edev), GFP_KERNEL);
148 if (!edev)
149 return -ENOMEM;
150 edev->phb = hose;
151 edev->pe_config_addr = pe_no;
152 pe = eeh_pe_get(edev);
153 kfree(edev);
154 if (!pe)
155 return -ENODEV;
156
157 /* Do error injection */
158 ret = eeh_ops->err_inject(pe, type, func, addr, mask);
159 return ret < 0 ? ret : count;
160}
161
162static const struct file_operations pnv_eeh_ei_fops = {
163 .open = simple_open,
164 .llseek = no_llseek,
165 .write = pnv_eeh_ei_write,
166};
167
168static int pnv_eeh_dbgfs_set(void *data, int offset, u64 val)
169{
170 struct pci_controller *hose = data;
171 struct pnv_phb *phb = hose->private_data;
172
173 out_be64(phb->regs + offset, val);
174 return 0;
175}
176
177static int pnv_eeh_dbgfs_get(void *data, int offset, u64 *val)
178{
179 struct pci_controller *hose = data;
180 struct pnv_phb *phb = hose->private_data;
181
182 *val = in_be64(phb->regs + offset);
183 return 0;
184}
185
186static int pnv_eeh_outb_dbgfs_set(void *data, u64 val)
187{
188 return pnv_eeh_dbgfs_set(data, 0xD10, val);
189}
190
191static int pnv_eeh_outb_dbgfs_get(void *data, u64 *val)
192{
193 return pnv_eeh_dbgfs_get(data, 0xD10, val);
194}
195
196static int pnv_eeh_inbA_dbgfs_set(void *data, u64 val)
197{
198 return pnv_eeh_dbgfs_set(data, 0xD90, val);
199}
200
201static int pnv_eeh_inbA_dbgfs_get(void *data, u64 *val)
202{
203 return pnv_eeh_dbgfs_get(data, 0xD90, val);
204}
205
206static int pnv_eeh_inbB_dbgfs_set(void *data, u64 val)
207{
208 return pnv_eeh_dbgfs_set(data, 0xE10, val);
209}
210
211static int pnv_eeh_inbB_dbgfs_get(void *data, u64 *val)
212{
213 return pnv_eeh_dbgfs_get(data, 0xE10, val);
214}
215
216DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_outb_dbgfs_ops, pnv_eeh_outb_dbgfs_get,
217 pnv_eeh_outb_dbgfs_set, "0x%llx\n");
218DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_inbA_dbgfs_ops, pnv_eeh_inbA_dbgfs_get,
219 pnv_eeh_inbA_dbgfs_set, "0x%llx\n");
220DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_inbB_dbgfs_ops, pnv_eeh_inbB_dbgfs_get,
221 pnv_eeh_inbB_dbgfs_set, "0x%llx\n");
222#endif /* CONFIG_DEBUG_FS */
223
88/** 224/**
89 * powernv_eeh_post_init - EEH platform dependent post initialization 225 * pnv_eeh_post_init - EEH platform dependent post initialization
90 * 226 *
91 * EEH platform dependent post initialization on powernv. When 227 * EEH platform dependent post initialization on powernv. When
92 * the function is called, the EEH PEs and devices should have 228 * the function is called, the EEH PEs and devices should have
93 * been built. If the I/O cache staff has been built, EEH is 229 * been built. If the I/O cache staff has been built, EEH is
94 * ready to supply service. 230 * ready to supply service.
95 */ 231 */
96static int powernv_eeh_post_init(void) 232static int pnv_eeh_post_init(void)
97{ 233{
98 struct pci_controller *hose; 234 struct pci_controller *hose;
99 struct pnv_phb *phb; 235 struct pnv_phb *phb;
100 int ret = 0; 236 int ret = 0;
101 237
238 /* Register OPAL event notifier */
239 if (!pnv_eeh_nb_init) {
240 ret = opal_notifier_register(&pnv_eeh_nb);
241 if (ret) {
242 pr_warn("%s: Can't register OPAL event notifier (%d)\n",
243 __func__, ret);
244 return ret;
245 }
246
247 pnv_eeh_nb_init = true;
248 }
249
102 list_for_each_entry(hose, &hose_list, list_node) { 250 list_for_each_entry(hose, &hose_list, list_node) {
103 phb = hose->private_data; 251 phb = hose->private_data;
104 252
105 if (phb->eeh_ops && phb->eeh_ops->post_init) { 253 /*
106 ret = phb->eeh_ops->post_init(hose); 254 * If EEH is enabled, we're going to rely on that.
107 if (ret) 255 * Otherwise, we restore to conventional mechanism
108 break; 256 * to clear frozen PE during PCI config access.
109 } 257 */
258 if (eeh_enabled())
259 phb->flags |= PNV_PHB_FLAG_EEH;
260 else
261 phb->flags &= ~PNV_PHB_FLAG_EEH;
262
263 /* Create debugfs entries */
264#ifdef CONFIG_DEBUG_FS
265 if (phb->has_dbgfs || !phb->dbgfs)
266 continue;
267
268 phb->has_dbgfs = 1;
269 debugfs_create_file("err_injct", 0200,
270 phb->dbgfs, hose,
271 &pnv_eeh_ei_fops);
272
273 debugfs_create_file("err_injct_outbound", 0600,
274 phb->dbgfs, hose,
275 &pnv_eeh_outb_dbgfs_ops);
276 debugfs_create_file("err_injct_inboundA", 0600,
277 phb->dbgfs, hose,
278 &pnv_eeh_inbA_dbgfs_ops);
279 debugfs_create_file("err_injct_inboundB", 0600,
280 phb->dbgfs, hose,
281 &pnv_eeh_inbB_dbgfs_ops);
282#endif /* CONFIG_DEBUG_FS */
110 } 283 }
111 284
285
112 return ret; 286 return ret;
113} 287}
114 288
289static int pnv_eeh_cap_start(struct pci_dn *pdn)
290{
291 u32 status;
292
293 if (!pdn)
294 return 0;
295
296 pnv_pci_cfg_read(pdn, PCI_STATUS, 2, &status);
297 if (!(status & PCI_STATUS_CAP_LIST))
298 return 0;
299
300 return PCI_CAPABILITY_LIST;
301}
302
303static int pnv_eeh_find_cap(struct pci_dn *pdn, int cap)
304{
305 int pos = pnv_eeh_cap_start(pdn);
306 int cnt = 48; /* Maximal number of capabilities */
307 u32 id;
308
309 if (!pos)
310 return 0;
311
312 while (cnt--) {
313 pnv_pci_cfg_read(pdn, pos, 1, &pos);
314 if (pos < 0x40)
315 break;
316
317 pos &= ~3;
318 pnv_pci_cfg_read(pdn, pos + PCI_CAP_LIST_ID, 1, &id);
319 if (id == 0xff)
320 break;
321
322 /* Found */
323 if (id == cap)
324 return pos;
325
326 /* Next one */
327 pos += PCI_CAP_LIST_NEXT;
328 }
329
330 return 0;
331}
332
333static int pnv_eeh_find_ecap(struct pci_dn *pdn, int cap)
334{
335 struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
336 u32 header;
337 int pos = 256, ttl = (4096 - 256) / 8;
338
339 if (!edev || !edev->pcie_cap)
340 return 0;
341 if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL)
342 return 0;
343 else if (!header)
344 return 0;
345
346 while (ttl-- > 0) {
347 if (PCI_EXT_CAP_ID(header) == cap && pos)
348 return pos;
349
350 pos = PCI_EXT_CAP_NEXT(header);
351 if (pos < 256)
352 break;
353
354 if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL)
355 break;
356 }
357
358 return 0;
359}
360
115/** 361/**
116 * powernv_eeh_dev_probe - Do probe on PCI device 362 * pnv_eeh_probe - Do probe on PCI device
117 * @dev: PCI device 363 * @pdn: PCI device node
118 * @flag: unused 364 * @data: unused
119 * 365 *
120 * When EEH module is installed during system boot, all PCI devices 366 * When EEH module is installed during system boot, all PCI devices
121 * are checked one by one to see if it supports EEH. The function 367 * are checked one by one to see if it supports EEH. The function
@@ -129,12 +375,12 @@ static int powernv_eeh_post_init(void)
129 * was possiblly triggered by EEH core, the binding between EEH device 375 * was possiblly triggered by EEH core, the binding between EEH device
130 * and the PCI device isn't built yet. 376 * and the PCI device isn't built yet.
131 */ 377 */
132static int powernv_eeh_dev_probe(struct pci_dev *dev, void *flag) 378static void *pnv_eeh_probe(struct pci_dn *pdn, void *data)
133{ 379{
134 struct pci_controller *hose = pci_bus_to_host(dev->bus); 380 struct pci_controller *hose = pdn->phb;
135 struct pnv_phb *phb = hose->private_data; 381 struct pnv_phb *phb = hose->private_data;
136 struct device_node *dn = pci_device_to_OF_node(dev); 382 struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
137 struct eeh_dev *edev = of_node_to_eeh_dev(dn); 383 uint32_t pcie_flags;
138 int ret; 384 int ret;
139 385
140 /* 386 /*
@@ -143,40 +389,42 @@ static int powernv_eeh_dev_probe(struct pci_dev *dev, void *flag)
143 * the root bridge. So it's not reasonable to continue 389 * the root bridge. So it's not reasonable to continue
144 * the probing. 390 * the probing.
145 */ 391 */
146 if (!dn || !edev || edev->pe) 392 if (!edev || edev->pe)
147 return 0; 393 return NULL;
148 394
149 /* Skip for PCI-ISA bridge */ 395 /* Skip for PCI-ISA bridge */
150 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_ISA) 396 if ((pdn->class_code >> 8) == PCI_CLASS_BRIDGE_ISA)
151 return 0; 397 return NULL;
152 398
153 /* Initialize eeh device */ 399 /* Initialize eeh device */
154 edev->class_code = dev->class; 400 edev->class_code = pdn->class_code;
155 edev->mode &= 0xFFFFFF00; 401 edev->mode &= 0xFFFFFF00;
156 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) 402 edev->pcix_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_PCIX);
403 edev->pcie_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_EXP);
404 edev->aer_cap = pnv_eeh_find_ecap(pdn, PCI_EXT_CAP_ID_ERR);
405 if ((edev->class_code >> 8) == PCI_CLASS_BRIDGE_PCI) {
157 edev->mode |= EEH_DEV_BRIDGE; 406 edev->mode |= EEH_DEV_BRIDGE;
158 edev->pcix_cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); 407 if (edev->pcie_cap) {
159 if (pci_is_pcie(dev)) { 408 pnv_pci_cfg_read(pdn, edev->pcie_cap + PCI_EXP_FLAGS,
160 edev->pcie_cap = pci_pcie_cap(dev); 409 2, &pcie_flags);
161 410 pcie_flags = (pcie_flags & PCI_EXP_FLAGS_TYPE) >> 4;
162 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) 411 if (pcie_flags == PCI_EXP_TYPE_ROOT_PORT)
163 edev->mode |= EEH_DEV_ROOT_PORT; 412 edev->mode |= EEH_DEV_ROOT_PORT;
164 else if (pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) 413 else if (pcie_flags == PCI_EXP_TYPE_DOWNSTREAM)
165 edev->mode |= EEH_DEV_DS_PORT; 414 edev->mode |= EEH_DEV_DS_PORT;
166 415 }
167 edev->aer_cap = pci_find_ext_capability(dev,
168 PCI_EXT_CAP_ID_ERR);
169 } 416 }
170 417
171 edev->config_addr = ((dev->bus->number << 8) | dev->devfn); 418 edev->config_addr = (pdn->busno << 8) | (pdn->devfn);
172 edev->pe_config_addr = phb->bdfn_to_pe(phb, dev->bus, dev->devfn & 0xff); 419 edev->pe_config_addr = phb->ioda.pe_rmap[edev->config_addr];
173 420
174 /* Create PE */ 421 /* Create PE */
175 ret = eeh_add_to_parent_pe(edev); 422 ret = eeh_add_to_parent_pe(edev);
176 if (ret) { 423 if (ret) {
177 pr_warn("%s: Can't add PCI dev %s to parent PE (%d)\n", 424 pr_warn("%s: Can't add PCI dev %04x:%02x:%02x.%01x to parent PE (%d)\n",
178 __func__, pci_name(dev), ret); 425 __func__, hose->global_number, pdn->busno,
179 return ret; 426 PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn), ret);
427 return NULL;
180 } 428 }
181 429
182 /* 430 /*
@@ -195,8 +443,10 @@ static int powernv_eeh_dev_probe(struct pci_dev *dev, void *flag)
195 * Broadcom Austin 4-ports NICs (14e4:1657) 443 * Broadcom Austin 4-ports NICs (14e4:1657)
196 * Broadcom Shiner 2-ports 10G NICs (14e4:168e) 444 * Broadcom Shiner 2-ports 10G NICs (14e4:168e)
197 */ 445 */
198 if ((dev->vendor == PCI_VENDOR_ID_BROADCOM && dev->device == 0x1657) || 446 if ((pdn->vendor_id == PCI_VENDOR_ID_BROADCOM &&
199 (dev->vendor == PCI_VENDOR_ID_BROADCOM && dev->device == 0x168e)) 447 pdn->device_id == 0x1657) ||
448 (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM &&
449 pdn->device_id == 0x168e))
200 edev->pe->state |= EEH_PE_CFG_RESTRICTED; 450 edev->pe->state |= EEH_PE_CFG_RESTRICTED;
201 451
202 /* 452 /*
@@ -206,7 +456,8 @@ static int powernv_eeh_dev_probe(struct pci_dev *dev, void *flag)
206 * to PE reset. 456 * to PE reset.
207 */ 457 */
208 if (!edev->pe->bus) 458 if (!edev->pe->bus)
209 edev->pe->bus = dev->bus; 459 edev->pe->bus = pci_find_bus(hose->global_number,
460 pdn->busno);
210 461
211 /* 462 /*
212 * Enable EEH explicitly so that we will do EEH check 463 * Enable EEH explicitly so that we will do EEH check
@@ -217,11 +468,11 @@ static int powernv_eeh_dev_probe(struct pci_dev *dev, void *flag)
217 /* Save memory bars */ 468 /* Save memory bars */
218 eeh_save_bars(edev); 469 eeh_save_bars(edev);
219 470
220 return 0; 471 return NULL;
221} 472}
222 473
223/** 474/**
224 * powernv_eeh_set_option - Initialize EEH or MMIO/DMA reenable 475 * pnv_eeh_set_option - Initialize EEH or MMIO/DMA reenable
225 * @pe: EEH PE 476 * @pe: EEH PE
226 * @option: operation to be issued 477 * @option: operation to be issued
227 * 478 *
@@ -229,36 +480,236 @@ static int powernv_eeh_dev_probe(struct pci_dev *dev, void *flag)
229 * Currently, following options are support according to PAPR: 480 * Currently, following options are support according to PAPR:
230 * Enable EEH, Disable EEH, Enable MMIO and Enable DMA 481 * Enable EEH, Disable EEH, Enable MMIO and Enable DMA
231 */ 482 */
232static int powernv_eeh_set_option(struct eeh_pe *pe, int option) 483static int pnv_eeh_set_option(struct eeh_pe *pe, int option)
233{ 484{
234 struct pci_controller *hose = pe->phb; 485 struct pci_controller *hose = pe->phb;
235 struct pnv_phb *phb = hose->private_data; 486 struct pnv_phb *phb = hose->private_data;
236 int ret = -EEXIST; 487 bool freeze_pe = false;
488 int opt, ret = 0;
489 s64 rc;
490
491 /* Sanity check on option */
492 switch (option) {
493 case EEH_OPT_DISABLE:
494 return -EPERM;
495 case EEH_OPT_ENABLE:
496 return 0;
497 case EEH_OPT_THAW_MMIO:
498 opt = OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO;
499 break;
500 case EEH_OPT_THAW_DMA:
501 opt = OPAL_EEH_ACTION_CLEAR_FREEZE_DMA;
502 break;
503 case EEH_OPT_FREEZE_PE:
504 freeze_pe = true;
505 opt = OPAL_EEH_ACTION_SET_FREEZE_ALL;
506 break;
507 default:
508 pr_warn("%s: Invalid option %d\n", __func__, option);
509 return -EINVAL;
510 }
237 511
238 /* 512 /* If PHB supports compound PE, to handle it */
239 * What we need do is pass it down for hardware 513 if (freeze_pe) {
240 * implementation to handle it. 514 if (phb->freeze_pe) {
241 */ 515 phb->freeze_pe(phb, pe->addr);
242 if (phb->eeh_ops && phb->eeh_ops->set_option) 516 } else {
243 ret = phb->eeh_ops->set_option(pe, option); 517 rc = opal_pci_eeh_freeze_set(phb->opal_id,
518 pe->addr, opt);
519 if (rc != OPAL_SUCCESS) {
520 pr_warn("%s: Failure %lld freezing "
521 "PHB#%x-PE#%x\n",
522 __func__, rc,
523 phb->hose->global_number, pe->addr);
524 ret = -EIO;
525 }
526 }
527 } else {
528 if (phb->unfreeze_pe) {
529 ret = phb->unfreeze_pe(phb, pe->addr, opt);
530 } else {
531 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
532 pe->addr, opt);
533 if (rc != OPAL_SUCCESS) {
534 pr_warn("%s: Failure %lld enable %d "
535 "for PHB#%x-PE#%x\n",
536 __func__, rc, option,
537 phb->hose->global_number, pe->addr);
538 ret = -EIO;
539 }
540 }
541 }
244 542
245 return ret; 543 return ret;
246} 544}
247 545
248/** 546/**
249 * powernv_eeh_get_pe_addr - Retrieve PE address 547 * pnv_eeh_get_pe_addr - Retrieve PE address
250 * @pe: EEH PE 548 * @pe: EEH PE
251 * 549 *
252 * Retrieve the PE address according to the given tranditional 550 * Retrieve the PE address according to the given tranditional
253 * PCI BDF (Bus/Device/Function) address. 551 * PCI BDF (Bus/Device/Function) address.
254 */ 552 */
255static int powernv_eeh_get_pe_addr(struct eeh_pe *pe) 553static int pnv_eeh_get_pe_addr(struct eeh_pe *pe)
256{ 554{
257 return pe->addr; 555 return pe->addr;
258} 556}
259 557
558static void pnv_eeh_get_phb_diag(struct eeh_pe *pe)
559{
560 struct pnv_phb *phb = pe->phb->private_data;
561 s64 rc;
562
563 rc = opal_pci_get_phb_diag_data2(phb->opal_id, pe->data,
564 PNV_PCI_DIAG_BUF_SIZE);
565 if (rc != OPAL_SUCCESS)
566 pr_warn("%s: Failure %lld getting PHB#%x diag-data\n",
567 __func__, rc, pe->phb->global_number);
568}
569
570static int pnv_eeh_get_phb_state(struct eeh_pe *pe)
571{
572 struct pnv_phb *phb = pe->phb->private_data;
573 u8 fstate;
574 __be16 pcierr;
575 s64 rc;
576 int result = 0;
577
578 rc = opal_pci_eeh_freeze_status(phb->opal_id,
579 pe->addr,
580 &fstate,
581 &pcierr,
582 NULL);
583 if (rc != OPAL_SUCCESS) {
584 pr_warn("%s: Failure %lld getting PHB#%x state\n",
585 __func__, rc, phb->hose->global_number);
586 return EEH_STATE_NOT_SUPPORT;
587 }
588
589 /*
590 * Check PHB state. If the PHB is frozen for the
591 * first time, to dump the PHB diag-data.
592 */
593 if (be16_to_cpu(pcierr) != OPAL_EEH_PHB_ERROR) {
594 result = (EEH_STATE_MMIO_ACTIVE |
595 EEH_STATE_DMA_ACTIVE |
596 EEH_STATE_MMIO_ENABLED |
597 EEH_STATE_DMA_ENABLED);
598 } else if (!(pe->state & EEH_PE_ISOLATED)) {
599 eeh_pe_state_mark(pe, EEH_PE_ISOLATED);
600 pnv_eeh_get_phb_diag(pe);
601
602 if (eeh_has_flag(EEH_EARLY_DUMP_LOG))
603 pnv_pci_dump_phb_diag_data(pe->phb, pe->data);
604 }
605
606 return result;
607}
608
609static int pnv_eeh_get_pe_state(struct eeh_pe *pe)
610{
611 struct pnv_phb *phb = pe->phb->private_data;
612 u8 fstate;
613 __be16 pcierr;
614 s64 rc;
615 int result;
616
617 /*
618 * We don't clobber hardware frozen state until PE
619 * reset is completed. In order to keep EEH core
620 * moving forward, we have to return operational
621 * state during PE reset.
622 */
623 if (pe->state & EEH_PE_RESET) {
624 result = (EEH_STATE_MMIO_ACTIVE |
625 EEH_STATE_DMA_ACTIVE |
626 EEH_STATE_MMIO_ENABLED |
627 EEH_STATE_DMA_ENABLED);
628 return result;
629 }
630
631 /*
632 * Fetch PE state from hardware. If the PHB
633 * supports compound PE, let it handle that.
634 */
635 if (phb->get_pe_state) {
636 fstate = phb->get_pe_state(phb, pe->addr);
637 } else {
638 rc = opal_pci_eeh_freeze_status(phb->opal_id,
639 pe->addr,
640 &fstate,
641 &pcierr,
642 NULL);
643 if (rc != OPAL_SUCCESS) {
644 pr_warn("%s: Failure %lld getting PHB#%x-PE%x state\n",
645 __func__, rc, phb->hose->global_number,
646 pe->addr);
647 return EEH_STATE_NOT_SUPPORT;
648 }
649 }
650
651 /* Figure out state */
652 switch (fstate) {
653 case OPAL_EEH_STOPPED_NOT_FROZEN:
654 result = (EEH_STATE_MMIO_ACTIVE |
655 EEH_STATE_DMA_ACTIVE |
656 EEH_STATE_MMIO_ENABLED |
657 EEH_STATE_DMA_ENABLED);
658 break;
659 case OPAL_EEH_STOPPED_MMIO_FREEZE:
660 result = (EEH_STATE_DMA_ACTIVE |
661 EEH_STATE_DMA_ENABLED);
662 break;
663 case OPAL_EEH_STOPPED_DMA_FREEZE:
664 result = (EEH_STATE_MMIO_ACTIVE |
665 EEH_STATE_MMIO_ENABLED);
666 break;
667 case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE:
668 result = 0;
669 break;
670 case OPAL_EEH_STOPPED_RESET:
671 result = EEH_STATE_RESET_ACTIVE;
672 break;
673 case OPAL_EEH_STOPPED_TEMP_UNAVAIL:
674 result = EEH_STATE_UNAVAILABLE;
675 break;
676 case OPAL_EEH_STOPPED_PERM_UNAVAIL:
677 result = EEH_STATE_NOT_SUPPORT;
678 break;
679 default:
680 result = EEH_STATE_NOT_SUPPORT;
681 pr_warn("%s: Invalid PHB#%x-PE#%x state %x\n",
682 __func__, phb->hose->global_number,
683 pe->addr, fstate);
684 }
685
686 /*
687 * If PHB supports compound PE, to freeze all
688 * slave PEs for consistency.
689 *
690 * If the PE is switching to frozen state for the
691 * first time, to dump the PHB diag-data.
692 */
693 if (!(result & EEH_STATE_NOT_SUPPORT) &&
694 !(result & EEH_STATE_UNAVAILABLE) &&
695 !(result & EEH_STATE_MMIO_ACTIVE) &&
696 !(result & EEH_STATE_DMA_ACTIVE) &&
697 !(pe->state & EEH_PE_ISOLATED)) {
698 if (phb->freeze_pe)
699 phb->freeze_pe(phb, pe->addr);
700
701 eeh_pe_state_mark(pe, EEH_PE_ISOLATED);
702 pnv_eeh_get_phb_diag(pe);
703
704 if (eeh_has_flag(EEH_EARLY_DUMP_LOG))
705 pnv_pci_dump_phb_diag_data(pe->phb, pe->data);
706 }
707
708 return result;
709}
710
260/** 711/**
261 * powernv_eeh_get_state - Retrieve PE state 712 * pnv_eeh_get_state - Retrieve PE state
262 * @pe: EEH PE 713 * @pe: EEH PE
263 * @delay: delay while PE state is temporarily unavailable 714 * @delay: delay while PE state is temporarily unavailable
264 * 715 *
@@ -267,64 +718,279 @@ static int powernv_eeh_get_pe_addr(struct eeh_pe *pe)
267 * we prefer passing down to hardware implementation to handle 718 * we prefer passing down to hardware implementation to handle
268 * it. 719 * it.
269 */ 720 */
270static int powernv_eeh_get_state(struct eeh_pe *pe, int *delay) 721static int pnv_eeh_get_state(struct eeh_pe *pe, int *delay)
722{
723 int ret;
724
725 if (pe->type & EEH_PE_PHB)
726 ret = pnv_eeh_get_phb_state(pe);
727 else
728 ret = pnv_eeh_get_pe_state(pe);
729
730 if (!delay)
731 return ret;
732
733 /*
734 * If the PE state is temporarily unavailable,
735 * to inform the EEH core delay for default
736 * period (1 second)
737 */
738 *delay = 0;
739 if (ret & EEH_STATE_UNAVAILABLE)
740 *delay = 1000;
741
742 return ret;
743}
744
745static s64 pnv_eeh_phb_poll(struct pnv_phb *phb)
746{
747 s64 rc = OPAL_HARDWARE;
748
749 while (1) {
750 rc = opal_pci_poll(phb->opal_id);
751 if (rc <= 0)
752 break;
753
754 if (system_state < SYSTEM_RUNNING)
755 udelay(1000 * rc);
756 else
757 msleep(rc);
758 }
759
760 return rc;
761}
762
763int pnv_eeh_phb_reset(struct pci_controller *hose, int option)
271{ 764{
272 struct pci_controller *hose = pe->phb;
273 struct pnv_phb *phb = hose->private_data; 765 struct pnv_phb *phb = hose->private_data;
274 int ret = EEH_STATE_NOT_SUPPORT; 766 s64 rc = OPAL_HARDWARE;
767
768 pr_debug("%s: Reset PHB#%x, option=%d\n",
769 __func__, hose->global_number, option);
770
771 /* Issue PHB complete reset request */
772 if (option == EEH_RESET_FUNDAMENTAL ||
773 option == EEH_RESET_HOT)
774 rc = opal_pci_reset(phb->opal_id,
775 OPAL_RESET_PHB_COMPLETE,
776 OPAL_ASSERT_RESET);
777 else if (option == EEH_RESET_DEACTIVATE)
778 rc = opal_pci_reset(phb->opal_id,
779 OPAL_RESET_PHB_COMPLETE,
780 OPAL_DEASSERT_RESET);
781 if (rc < 0)
782 goto out;
275 783
276 if (phb->eeh_ops && phb->eeh_ops->get_state) { 784 /*
277 ret = phb->eeh_ops->get_state(pe); 785 * Poll state of the PHB until the request is done
786 * successfully. The PHB reset is usually PHB complete
787 * reset followed by hot reset on root bus. So we also
788 * need the PCI bus settlement delay.
789 */
790 rc = pnv_eeh_phb_poll(phb);
791 if (option == EEH_RESET_DEACTIVATE) {
792 if (system_state < SYSTEM_RUNNING)
793 udelay(1000 * EEH_PE_RST_SETTLE_TIME);
794 else
795 msleep(EEH_PE_RST_SETTLE_TIME);
796 }
797out:
798 if (rc != OPAL_SUCCESS)
799 return -EIO;
278 800
279 /* 801 return 0;
280 * If the PE state is temporarily unavailable, 802}
281 * to inform the EEH core delay for default 803
282 * period (1 second) 804static int pnv_eeh_root_reset(struct pci_controller *hose, int option)
283 */ 805{
284 if (delay) { 806 struct pnv_phb *phb = hose->private_data;
285 *delay = 0; 807 s64 rc = OPAL_HARDWARE;
286 if (ret & EEH_STATE_UNAVAILABLE) 808
287 *delay = 1000; 809 pr_debug("%s: Reset PHB#%x, option=%d\n",
810 __func__, hose->global_number, option);
811
812 /*
813 * During the reset deassert time, we needn't care
814 * the reset scope because the firmware does nothing
815 * for fundamental or hot reset during deassert phase.
816 */
817 if (option == EEH_RESET_FUNDAMENTAL)
818 rc = opal_pci_reset(phb->opal_id,
819 OPAL_RESET_PCI_FUNDAMENTAL,
820 OPAL_ASSERT_RESET);
821 else if (option == EEH_RESET_HOT)
822 rc = opal_pci_reset(phb->opal_id,
823 OPAL_RESET_PCI_HOT,
824 OPAL_ASSERT_RESET);
825 else if (option == EEH_RESET_DEACTIVATE)
826 rc = opal_pci_reset(phb->opal_id,
827 OPAL_RESET_PCI_HOT,
828 OPAL_DEASSERT_RESET);
829 if (rc < 0)
830 goto out;
831
832 /* Poll state of the PHB until the request is done */
833 rc = pnv_eeh_phb_poll(phb);
834 if (option == EEH_RESET_DEACTIVATE)
835 msleep(EEH_PE_RST_SETTLE_TIME);
836out:
837 if (rc != OPAL_SUCCESS)
838 return -EIO;
839
840 return 0;
841}
842
843static int pnv_eeh_bridge_reset(struct pci_dev *dev, int option)
844{
845 struct pci_dn *pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn);
846 struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
847 int aer = edev ? edev->aer_cap : 0;
848 u32 ctrl;
849
850 pr_debug("%s: Reset PCI bus %04x:%02x with option %d\n",
851 __func__, pci_domain_nr(dev->bus),
852 dev->bus->number, option);
853
854 switch (option) {
855 case EEH_RESET_FUNDAMENTAL:
856 case EEH_RESET_HOT:
857 /* Don't report linkDown event */
858 if (aer) {
859 eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK,
860 4, &ctrl);
861 ctrl |= PCI_ERR_UNC_SURPDN;
862 eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK,
863 4, ctrl);
288 } 864 }
865
866 eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl);
867 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
868 eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl);
869
870 msleep(EEH_PE_RST_HOLD_TIME);
871 break;
872 case EEH_RESET_DEACTIVATE:
873 eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl);
874 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
875 eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl);
876
877 msleep(EEH_PE_RST_SETTLE_TIME);
878
879 /* Continue reporting linkDown event */
880 if (aer) {
881 eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK,
882 4, &ctrl);
883 ctrl &= ~PCI_ERR_UNC_SURPDN;
884 eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK,
885 4, ctrl);
886 }
887
888 break;
289 } 889 }
290 890
291 return ret; 891 return 0;
892}
893
894void pnv_pci_reset_secondary_bus(struct pci_dev *dev)
895{
896 struct pci_controller *hose;
897
898 if (pci_is_root_bus(dev->bus)) {
899 hose = pci_bus_to_host(dev->bus);
900 pnv_eeh_root_reset(hose, EEH_RESET_HOT);
901 pnv_eeh_root_reset(hose, EEH_RESET_DEACTIVATE);
902 } else {
903 pnv_eeh_bridge_reset(dev, EEH_RESET_HOT);
904 pnv_eeh_bridge_reset(dev, EEH_RESET_DEACTIVATE);
905 }
292} 906}
293 907
294/** 908/**
295 * powernv_eeh_reset - Reset the specified PE 909 * pnv_eeh_reset - Reset the specified PE
296 * @pe: EEH PE 910 * @pe: EEH PE
297 * @option: reset option 911 * @option: reset option
298 * 912 *
299 * Reset the specified PE 913 * Do reset on the indicated PE. For PCI bus sensitive PE,
914 * we need to reset the parent p2p bridge. The PHB has to
915 * be reinitialized if the p2p bridge is root bridge. For
916 * PCI device sensitive PE, we will try to reset the device
917 * through FLR. For now, we don't have OPAL APIs to do HARD
918 * reset yet, so all reset would be SOFT (HOT) reset.
300 */ 919 */
301static int powernv_eeh_reset(struct eeh_pe *pe, int option) 920static int pnv_eeh_reset(struct eeh_pe *pe, int option)
302{ 921{
303 struct pci_controller *hose = pe->phb; 922 struct pci_controller *hose = pe->phb;
304 struct pnv_phb *phb = hose->private_data; 923 struct pci_bus *bus;
305 int ret = -EEXIST; 924 int ret;
925
926 /*
927 * For PHB reset, we always have complete reset. For those PEs whose
928 * primary bus derived from root complex (root bus) or root port
929 * (usually bus#1), we apply hot or fundamental reset on the root port.
930 * For other PEs, we always have hot reset on the PE primary bus.
931 *
932 * Here, we have different design to pHyp, which always clear the
933 * frozen state during PE reset. However, the good idea here from
934 * benh is to keep frozen state before we get PE reset done completely
935 * (until BAR restore). With the frozen state, HW drops illegal IO
936 * or MMIO access, which can incur recrusive frozen PE during PE
937 * reset. The side effect is that EEH core has to clear the frozen
938 * state explicitly after BAR restore.
939 */
940 if (pe->type & EEH_PE_PHB) {
941 ret = pnv_eeh_phb_reset(hose, option);
942 } else {
943 struct pnv_phb *phb;
944 s64 rc;
306 945
307 if (phb->eeh_ops && phb->eeh_ops->reset) 946 /*
308 ret = phb->eeh_ops->reset(pe, option); 947 * The frozen PE might be caused by PAPR error injection
948 * registers, which are expected to be cleared after hitting
949 * frozen PE as stated in the hardware spec. Unfortunately,
950 * that's not true on P7IOC. So we have to clear it manually
951 * to avoid recursive EEH errors during recovery.
952 */
953 phb = hose->private_data;
954 if (phb->model == PNV_PHB_MODEL_P7IOC &&
955 (option == EEH_RESET_HOT ||
956 option == EEH_RESET_FUNDAMENTAL)) {
957 rc = opal_pci_reset(phb->opal_id,
958 OPAL_RESET_PHB_ERROR,
959 OPAL_ASSERT_RESET);
960 if (rc != OPAL_SUCCESS) {
961 pr_warn("%s: Failure %lld clearing "
962 "error injection registers\n",
963 __func__, rc);
964 return -EIO;
965 }
966 }
967
968 bus = eeh_pe_bus_get(pe);
969 if (pci_is_root_bus(bus) ||
970 pci_is_root_bus(bus->parent))
971 ret = pnv_eeh_root_reset(hose, option);
972 else
973 ret = pnv_eeh_bridge_reset(bus->self, option);
974 }
309 975
310 return ret; 976 return ret;
311} 977}
312 978
313/** 979/**
314 * powernv_eeh_wait_state - Wait for PE state 980 * pnv_eeh_wait_state - Wait for PE state
315 * @pe: EEH PE 981 * @pe: EEH PE
316 * @max_wait: maximal period in microsecond 982 * @max_wait: maximal period in microsecond
317 * 983 *
318 * Wait for the state of associated PE. It might take some time 984 * Wait for the state of associated PE. It might take some time
319 * to retrieve the PE's state. 985 * to retrieve the PE's state.
320 */ 986 */
321static int powernv_eeh_wait_state(struct eeh_pe *pe, int max_wait) 987static int pnv_eeh_wait_state(struct eeh_pe *pe, int max_wait)
322{ 988{
323 int ret; 989 int ret;
324 int mwait; 990 int mwait;
325 991
326 while (1) { 992 while (1) {
327 ret = powernv_eeh_get_state(pe, &mwait); 993 ret = pnv_eeh_get_state(pe, &mwait);
328 994
329 /* 995 /*
330 * If the PE's state is temporarily unavailable, 996 * If the PE's state is temporarily unavailable,
@@ -348,7 +1014,7 @@ static int powernv_eeh_wait_state(struct eeh_pe *pe, int max_wait)
348} 1014}
349 1015
350/** 1016/**
351 * powernv_eeh_get_log - Retrieve error log 1017 * pnv_eeh_get_log - Retrieve error log
352 * @pe: EEH PE 1018 * @pe: EEH PE
353 * @severity: temporary or permanent error log 1019 * @severity: temporary or permanent error log
354 * @drv_log: driver log to be combined with retrieved error log 1020 * @drv_log: driver log to be combined with retrieved error log
@@ -356,41 +1022,30 @@ static int powernv_eeh_wait_state(struct eeh_pe *pe, int max_wait)
356 * 1022 *
357 * Retrieve the temporary or permanent error from the PE. 1023 * Retrieve the temporary or permanent error from the PE.
358 */ 1024 */
359static int powernv_eeh_get_log(struct eeh_pe *pe, int severity, 1025static int pnv_eeh_get_log(struct eeh_pe *pe, int severity,
360 char *drv_log, unsigned long len) 1026 char *drv_log, unsigned long len)
361{ 1027{
362 struct pci_controller *hose = pe->phb; 1028 if (!eeh_has_flag(EEH_EARLY_DUMP_LOG))
363 struct pnv_phb *phb = hose->private_data; 1029 pnv_pci_dump_phb_diag_data(pe->phb, pe->data);
364 int ret = -EEXIST;
365 1030
366 if (phb->eeh_ops && phb->eeh_ops->get_log) 1031 return 0;
367 ret = phb->eeh_ops->get_log(pe, severity, drv_log, len);
368
369 return ret;
370} 1032}
371 1033
372/** 1034/**
373 * powernv_eeh_configure_bridge - Configure PCI bridges in the indicated PE 1035 * pnv_eeh_configure_bridge - Configure PCI bridges in the indicated PE
374 * @pe: EEH PE 1036 * @pe: EEH PE
375 * 1037 *
376 * The function will be called to reconfigure the bridges included 1038 * The function will be called to reconfigure the bridges included
377 * in the specified PE so that the mulfunctional PE would be recovered 1039 * in the specified PE so that the mulfunctional PE would be recovered
378 * again. 1040 * again.
379 */ 1041 */
380static int powernv_eeh_configure_bridge(struct eeh_pe *pe) 1042static int pnv_eeh_configure_bridge(struct eeh_pe *pe)
381{ 1043{
382 struct pci_controller *hose = pe->phb; 1044 return 0;
383 struct pnv_phb *phb = hose->private_data;
384 int ret = 0;
385
386 if (phb->eeh_ops && phb->eeh_ops->configure_bridge)
387 ret = phb->eeh_ops->configure_bridge(pe);
388
389 return ret;
390} 1045}
391 1046
392/** 1047/**
393 * powernv_pe_err_inject - Inject specified error to the indicated PE 1048 * pnv_pe_err_inject - Inject specified error to the indicated PE
394 * @pe: the indicated PE 1049 * @pe: the indicated PE
395 * @type: error type 1050 * @type: error type
396 * @func: specific error type 1051 * @func: specific error type
@@ -401,22 +1056,52 @@ static int powernv_eeh_configure_bridge(struct eeh_pe *pe)
401 * determined by @type and @func, to the indicated PE for 1056 * determined by @type and @func, to the indicated PE for
402 * testing purpose. 1057 * testing purpose.
403 */ 1058 */
404static int powernv_eeh_err_inject(struct eeh_pe *pe, int type, int func, 1059static int pnv_eeh_err_inject(struct eeh_pe *pe, int type, int func,
405 unsigned long addr, unsigned long mask) 1060 unsigned long addr, unsigned long mask)
406{ 1061{
407 struct pci_controller *hose = pe->phb; 1062 struct pci_controller *hose = pe->phb;
408 struct pnv_phb *phb = hose->private_data; 1063 struct pnv_phb *phb = hose->private_data;
409 int ret = -EEXIST; 1064 s64 rc;
1065
1066 /* Sanity check on error type */
1067 if (type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR &&
1068 type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64) {
1069 pr_warn("%s: Invalid error type %d\n",
1070 __func__, type);
1071 return -ERANGE;
1072 }
410 1073
411 if (phb->eeh_ops && phb->eeh_ops->err_inject) 1074 if (func < OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR ||
412 ret = phb->eeh_ops->err_inject(pe, type, func, addr, mask); 1075 func > OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET) {
1076 pr_warn("%s: Invalid error function %d\n",
1077 __func__, func);
1078 return -ERANGE;
1079 }
413 1080
414 return ret; 1081 /* Firmware supports error injection ? */
1082 if (!opal_check_token(OPAL_PCI_ERR_INJECT)) {
1083 pr_warn("%s: Firmware doesn't support error injection\n",
1084 __func__);
1085 return -ENXIO;
1086 }
1087
1088 /* Do error injection */
1089 rc = opal_pci_err_inject(phb->opal_id, pe->addr,
1090 type, func, addr, mask);
1091 if (rc != OPAL_SUCCESS) {
1092 pr_warn("%s: Failure %lld injecting error "
1093 "%d-%d to PHB#%x-PE#%x\n",
1094 __func__, rc, type, func,
1095 hose->global_number, pe->addr);
1096 return -EIO;
1097 }
1098
1099 return 0;
415} 1100}
416 1101
417static inline bool powernv_eeh_cfg_blocked(struct device_node *dn) 1102static inline bool pnv_eeh_cfg_blocked(struct pci_dn *pdn)
418{ 1103{
419 struct eeh_dev *edev = of_node_to_eeh_dev(dn); 1104 struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
420 1105
421 if (!edev || !edev->pe) 1106 if (!edev || !edev->pe)
422 return false; 1107 return false;
@@ -427,51 +1112,377 @@ static inline bool powernv_eeh_cfg_blocked(struct device_node *dn)
427 return false; 1112 return false;
428} 1113}
429 1114
430static int powernv_eeh_read_config(struct device_node *dn, 1115static int pnv_eeh_read_config(struct pci_dn *pdn,
431 int where, int size, u32 *val) 1116 int where, int size, u32 *val)
432{ 1117{
433 if (powernv_eeh_cfg_blocked(dn)) { 1118 if (!pdn)
1119 return PCIBIOS_DEVICE_NOT_FOUND;
1120
1121 if (pnv_eeh_cfg_blocked(pdn)) {
434 *val = 0xFFFFFFFF; 1122 *val = 0xFFFFFFFF;
435 return PCIBIOS_SET_FAILED; 1123 return PCIBIOS_SET_FAILED;
436 } 1124 }
437 1125
438 return pnv_pci_cfg_read(dn, where, size, val); 1126 return pnv_pci_cfg_read(pdn, where, size, val);
439} 1127}
440 1128
441static int powernv_eeh_write_config(struct device_node *dn, 1129static int pnv_eeh_write_config(struct pci_dn *pdn,
442 int where, int size, u32 val) 1130 int where, int size, u32 val)
443{ 1131{
444 if (powernv_eeh_cfg_blocked(dn)) 1132 if (!pdn)
1133 return PCIBIOS_DEVICE_NOT_FOUND;
1134
1135 if (pnv_eeh_cfg_blocked(pdn))
445 return PCIBIOS_SET_FAILED; 1136 return PCIBIOS_SET_FAILED;
446 1137
447 return pnv_pci_cfg_write(dn, where, size, val); 1138 return pnv_pci_cfg_write(pdn, where, size, val);
1139}
1140
1141static void pnv_eeh_dump_hub_diag_common(struct OpalIoP7IOCErrorData *data)
1142{
1143 /* GEM */
1144 if (data->gemXfir || data->gemRfir ||
1145 data->gemRirqfir || data->gemMask || data->gemRwof)
1146 pr_info(" GEM: %016llx %016llx %016llx %016llx %016llx\n",
1147 be64_to_cpu(data->gemXfir),
1148 be64_to_cpu(data->gemRfir),
1149 be64_to_cpu(data->gemRirqfir),
1150 be64_to_cpu(data->gemMask),
1151 be64_to_cpu(data->gemRwof));
1152
1153 /* LEM */
1154 if (data->lemFir || data->lemErrMask ||
1155 data->lemAction0 || data->lemAction1 || data->lemWof)
1156 pr_info(" LEM: %016llx %016llx %016llx %016llx %016llx\n",
1157 be64_to_cpu(data->lemFir),
1158 be64_to_cpu(data->lemErrMask),
1159 be64_to_cpu(data->lemAction0),
1160 be64_to_cpu(data->lemAction1),
1161 be64_to_cpu(data->lemWof));
1162}
1163
1164static void pnv_eeh_get_and_dump_hub_diag(struct pci_controller *hose)
1165{
1166 struct pnv_phb *phb = hose->private_data;
1167 struct OpalIoP7IOCErrorData *data = &phb->diag.hub_diag;
1168 long rc;
1169
1170 rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data));
1171 if (rc != OPAL_SUCCESS) {
1172 pr_warn("%s: Failed to get HUB#%llx diag-data (%ld)\n",
1173 __func__, phb->hub_id, rc);
1174 return;
1175 }
1176
1177 switch (data->type) {
1178 case OPAL_P7IOC_DIAG_TYPE_RGC:
1179 pr_info("P7IOC diag-data for RGC\n\n");
1180 pnv_eeh_dump_hub_diag_common(data);
1181 if (data->rgc.rgcStatus || data->rgc.rgcLdcp)
1182 pr_info(" RGC: %016llx %016llx\n",
1183 be64_to_cpu(data->rgc.rgcStatus),
1184 be64_to_cpu(data->rgc.rgcLdcp));
1185 break;
1186 case OPAL_P7IOC_DIAG_TYPE_BI:
1187 pr_info("P7IOC diag-data for BI %s\n\n",
1188 data->bi.biDownbound ? "Downbound" : "Upbound");
1189 pnv_eeh_dump_hub_diag_common(data);
1190 if (data->bi.biLdcp0 || data->bi.biLdcp1 ||
1191 data->bi.biLdcp2 || data->bi.biFenceStatus)
1192 pr_info(" BI: %016llx %016llx %016llx %016llx\n",
1193 be64_to_cpu(data->bi.biLdcp0),
1194 be64_to_cpu(data->bi.biLdcp1),
1195 be64_to_cpu(data->bi.biLdcp2),
1196 be64_to_cpu(data->bi.biFenceStatus));
1197 break;
1198 case OPAL_P7IOC_DIAG_TYPE_CI:
1199 pr_info("P7IOC diag-data for CI Port %d\n\n",
1200 data->ci.ciPort);
1201 pnv_eeh_dump_hub_diag_common(data);
1202 if (data->ci.ciPortStatus || data->ci.ciPortLdcp)
1203 pr_info(" CI: %016llx %016llx\n",
1204 be64_to_cpu(data->ci.ciPortStatus),
1205 be64_to_cpu(data->ci.ciPortLdcp));
1206 break;
1207 case OPAL_P7IOC_DIAG_TYPE_MISC:
1208 pr_info("P7IOC diag-data for MISC\n\n");
1209 pnv_eeh_dump_hub_diag_common(data);
1210 break;
1211 case OPAL_P7IOC_DIAG_TYPE_I2C:
1212 pr_info("P7IOC diag-data for I2C\n\n");
1213 pnv_eeh_dump_hub_diag_common(data);
1214 break;
1215 default:
1216 pr_warn("%s: Invalid type of HUB#%llx diag-data (%d)\n",
1217 __func__, phb->hub_id, data->type);
1218 }
1219}
1220
1221static int pnv_eeh_get_pe(struct pci_controller *hose,
1222 u16 pe_no, struct eeh_pe **pe)
1223{
1224 struct pnv_phb *phb = hose->private_data;
1225 struct pnv_ioda_pe *pnv_pe;
1226 struct eeh_pe *dev_pe;
1227 struct eeh_dev edev;
1228
1229 /*
1230 * If PHB supports compound PE, to fetch
1231 * the master PE because slave PE is invisible
1232 * to EEH core.
1233 */
1234 pnv_pe = &phb->ioda.pe_array[pe_no];
1235 if (pnv_pe->flags & PNV_IODA_PE_SLAVE) {
1236 pnv_pe = pnv_pe->master;
1237 WARN_ON(!pnv_pe ||
1238 !(pnv_pe->flags & PNV_IODA_PE_MASTER));
1239 pe_no = pnv_pe->pe_number;
1240 }
1241
1242 /* Find the PE according to PE# */
1243 memset(&edev, 0, sizeof(struct eeh_dev));
1244 edev.phb = hose;
1245 edev.pe_config_addr = pe_no;
1246 dev_pe = eeh_pe_get(&edev);
1247 if (!dev_pe)
1248 return -EEXIST;
1249
1250 /* Freeze the (compound) PE */
1251 *pe = dev_pe;
1252 if (!(dev_pe->state & EEH_PE_ISOLATED))
1253 phb->freeze_pe(phb, pe_no);
1254
1255 /*
1256 * At this point, we're sure the (compound) PE should
1257 * have been frozen. However, we still need poke until
1258 * hitting the frozen PE on top level.
1259 */
1260 dev_pe = dev_pe->parent;
1261 while (dev_pe && !(dev_pe->type & EEH_PE_PHB)) {
1262 int ret;
1263 int active_flags = (EEH_STATE_MMIO_ACTIVE |
1264 EEH_STATE_DMA_ACTIVE);
1265
1266 ret = eeh_ops->get_state(dev_pe, NULL);
1267 if (ret <= 0 || (ret & active_flags) == active_flags) {
1268 dev_pe = dev_pe->parent;
1269 continue;
1270 }
1271
1272 /* Frozen parent PE */
1273 *pe = dev_pe;
1274 if (!(dev_pe->state & EEH_PE_ISOLATED))
1275 phb->freeze_pe(phb, dev_pe->addr);
1276
1277 /* Next one */
1278 dev_pe = dev_pe->parent;
1279 }
1280
1281 return 0;
448} 1282}
449 1283
450/** 1284/**
451 * powernv_eeh_next_error - Retrieve next EEH error to handle 1285 * pnv_eeh_next_error - Retrieve next EEH error to handle
452 * @pe: Affected PE 1286 * @pe: Affected PE
453 * 1287 *
454 * Using OPAL API, to retrieve next EEH error for EEH core to handle 1288 * The function is expected to be called by EEH core while it gets
1289 * special EEH event (without binding PE). The function calls to
1290 * OPAL APIs for next error to handle. The informational error is
1291 * handled internally by platform. However, the dead IOC, dead PHB,
1292 * fenced PHB and frozen PE should be handled by EEH core eventually.
455 */ 1293 */
456static int powernv_eeh_next_error(struct eeh_pe **pe) 1294static int pnv_eeh_next_error(struct eeh_pe **pe)
457{ 1295{
458 struct pci_controller *hose; 1296 struct pci_controller *hose;
459 struct pnv_phb *phb = NULL; 1297 struct pnv_phb *phb;
1298 struct eeh_pe *phb_pe, *parent_pe;
1299 __be64 frozen_pe_no;
1300 __be16 err_type, severity;
1301 int active_flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE);
1302 long rc;
1303 int state, ret = EEH_NEXT_ERR_NONE;
1304
1305 /*
1306 * While running here, it's safe to purge the event queue.
1307 * And we should keep the cached OPAL notifier event sychronized
1308 * between the kernel and firmware.
1309 */
1310 eeh_remove_event(NULL, false);
1311 opal_notifier_update_evt(OPAL_EVENT_PCI_ERROR, 0x0ul);
460 1312
461 list_for_each_entry(hose, &hose_list, list_node) { 1313 list_for_each_entry(hose, &hose_list, list_node) {
1314 /*
1315 * If the subordinate PCI buses of the PHB has been
1316 * removed or is exactly under error recovery, we
1317 * needn't take care of it any more.
1318 */
462 phb = hose->private_data; 1319 phb = hose->private_data;
463 break; 1320 phb_pe = eeh_phb_pe_get(hose);
464 } 1321 if (!phb_pe || (phb_pe->state & EEH_PE_ISOLATED))
1322 continue;
1323
1324 rc = opal_pci_next_error(phb->opal_id,
1325 &frozen_pe_no, &err_type, &severity);
1326 if (rc != OPAL_SUCCESS) {
1327 pr_devel("%s: Invalid return value on "
1328 "PHB#%x (0x%lx) from opal_pci_next_error",
1329 __func__, hose->global_number, rc);
1330 continue;
1331 }
1332
1333 /* If the PHB doesn't have error, stop processing */
1334 if (be16_to_cpu(err_type) == OPAL_EEH_NO_ERROR ||
1335 be16_to_cpu(severity) == OPAL_EEH_SEV_NO_ERROR) {
1336 pr_devel("%s: No error found on PHB#%x\n",
1337 __func__, hose->global_number);
1338 continue;
1339 }
1340
1341 /*
1342 * Processing the error. We're expecting the error with
1343 * highest priority reported upon multiple errors on the
1344 * specific PHB.
1345 */
1346 pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n",
1347 __func__, be16_to_cpu(err_type),
1348 be16_to_cpu(severity), be64_to_cpu(frozen_pe_no),
1349 hose->global_number);
1350 switch (be16_to_cpu(err_type)) {
1351 case OPAL_EEH_IOC_ERROR:
1352 if (be16_to_cpu(severity) == OPAL_EEH_SEV_IOC_DEAD) {
1353 pr_err("EEH: dead IOC detected\n");
1354 ret = EEH_NEXT_ERR_DEAD_IOC;
1355 } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) {
1356 pr_info("EEH: IOC informative error "
1357 "detected\n");
1358 pnv_eeh_get_and_dump_hub_diag(hose);
1359 ret = EEH_NEXT_ERR_NONE;
1360 }
1361
1362 break;
1363 case OPAL_EEH_PHB_ERROR:
1364 if (be16_to_cpu(severity) == OPAL_EEH_SEV_PHB_DEAD) {
1365 *pe = phb_pe;
1366 pr_err("EEH: dead PHB#%x detected, "
1367 "location: %s\n",
1368 hose->global_number,
1369 eeh_pe_loc_get(phb_pe));
1370 ret = EEH_NEXT_ERR_DEAD_PHB;
1371 } else if (be16_to_cpu(severity) ==
1372 OPAL_EEH_SEV_PHB_FENCED) {
1373 *pe = phb_pe;
1374 pr_err("EEH: Fenced PHB#%x detected, "
1375 "location: %s\n",
1376 hose->global_number,
1377 eeh_pe_loc_get(phb_pe));
1378 ret = EEH_NEXT_ERR_FENCED_PHB;
1379 } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) {
1380 pr_info("EEH: PHB#%x informative error "
1381 "detected, location: %s\n",
1382 hose->global_number,
1383 eeh_pe_loc_get(phb_pe));
1384 pnv_eeh_get_phb_diag(phb_pe);
1385 pnv_pci_dump_phb_diag_data(hose, phb_pe->data);
1386 ret = EEH_NEXT_ERR_NONE;
1387 }
1388
1389 break;
1390 case OPAL_EEH_PE_ERROR:
1391 /*
1392 * If we can't find the corresponding PE, we
1393 * just try to unfreeze.
1394 */
1395 if (pnv_eeh_get_pe(hose,
1396 be64_to_cpu(frozen_pe_no), pe)) {
1397 /* Try best to clear it */
1398 pr_info("EEH: Clear non-existing PHB#%x-PE#%llx\n",
1399 hose->global_number, frozen_pe_no);
1400 pr_info("EEH: PHB location: %s\n",
1401 eeh_pe_loc_get(phb_pe));
1402 opal_pci_eeh_freeze_clear(phb->opal_id,
1403 frozen_pe_no,
1404 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
1405 ret = EEH_NEXT_ERR_NONE;
1406 } else if ((*pe)->state & EEH_PE_ISOLATED ||
1407 eeh_pe_passed(*pe)) {
1408 ret = EEH_NEXT_ERR_NONE;
1409 } else {
1410 pr_err("EEH: Frozen PE#%x "
1411 "on PHB#%x detected\n",
1412 (*pe)->addr,
1413 (*pe)->phb->global_number);
1414 pr_err("EEH: PE location: %s, "
1415 "PHB location: %s\n",
1416 eeh_pe_loc_get(*pe),
1417 eeh_pe_loc_get(phb_pe));
1418 ret = EEH_NEXT_ERR_FROZEN_PE;
1419 }
1420
1421 break;
1422 default:
1423 pr_warn("%s: Unexpected error type %d\n",
1424 __func__, be16_to_cpu(err_type));
1425 }
465 1426
466 if (phb && phb->eeh_ops->next_error) 1427 /*
467 return phb->eeh_ops->next_error(pe); 1428 * EEH core will try recover from fenced PHB or
1429 * frozen PE. In the time for frozen PE, EEH core
1430 * enable IO path for that before collecting logs,
1431 * but it ruins the site. So we have to dump the
1432 * log in advance here.
1433 */
1434 if ((ret == EEH_NEXT_ERR_FROZEN_PE ||
1435 ret == EEH_NEXT_ERR_FENCED_PHB) &&
1436 !((*pe)->state & EEH_PE_ISOLATED)) {
1437 eeh_pe_state_mark(*pe, EEH_PE_ISOLATED);
1438 pnv_eeh_get_phb_diag(*pe);
1439
1440 if (eeh_has_flag(EEH_EARLY_DUMP_LOG))
1441 pnv_pci_dump_phb_diag_data((*pe)->phb,
1442 (*pe)->data);
1443 }
468 1444
469 return -EEXIST; 1445 /*
1446 * We probably have the frozen parent PE out there and
1447 * we need have to handle frozen parent PE firstly.
1448 */
1449 if (ret == EEH_NEXT_ERR_FROZEN_PE) {
1450 parent_pe = (*pe)->parent;
1451 while (parent_pe) {
1452 /* Hit the ceiling ? */
1453 if (parent_pe->type & EEH_PE_PHB)
1454 break;
1455
1456 /* Frozen parent PE ? */
1457 state = eeh_ops->get_state(parent_pe, NULL);
1458 if (state > 0 &&
1459 (state & active_flags) != active_flags)
1460 *pe = parent_pe;
1461
1462 /* Next parent level */
1463 parent_pe = parent_pe->parent;
1464 }
1465
1466 /* We possibly migrate to another PE */
1467 eeh_pe_state_mark(*pe, EEH_PE_ISOLATED);
1468 }
1469
1470 /*
1471 * If we have no errors on the specific PHB or only
1472 * informative error there, we continue poking it.
1473 * Otherwise, we need actions to be taken by upper
1474 * layer.
1475 */
1476 if (ret > EEH_NEXT_ERR_INF)
1477 break;
1478 }
1479
1480 return ret;
470} 1481}
471 1482
472static int powernv_eeh_restore_config(struct device_node *dn) 1483static int pnv_eeh_restore_config(struct pci_dn *pdn)
473{ 1484{
474 struct eeh_dev *edev = of_node_to_eeh_dev(dn); 1485 struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
475 struct pnv_phb *phb; 1486 struct pnv_phb *phb;
476 s64 ret; 1487 s64 ret;
477 1488
@@ -490,24 +1501,23 @@ static int powernv_eeh_restore_config(struct device_node *dn)
490 return 0; 1501 return 0;
491} 1502}
492 1503
493static struct eeh_ops powernv_eeh_ops = { 1504static struct eeh_ops pnv_eeh_ops = {
494 .name = "powernv", 1505 .name = "powernv",
495 .init = powernv_eeh_init, 1506 .init = pnv_eeh_init,
496 .post_init = powernv_eeh_post_init, 1507 .post_init = pnv_eeh_post_init,
497 .of_probe = NULL, 1508 .probe = pnv_eeh_probe,
498 .dev_probe = powernv_eeh_dev_probe, 1509 .set_option = pnv_eeh_set_option,
499 .set_option = powernv_eeh_set_option, 1510 .get_pe_addr = pnv_eeh_get_pe_addr,
500 .get_pe_addr = powernv_eeh_get_pe_addr, 1511 .get_state = pnv_eeh_get_state,
501 .get_state = powernv_eeh_get_state, 1512 .reset = pnv_eeh_reset,
502 .reset = powernv_eeh_reset, 1513 .wait_state = pnv_eeh_wait_state,
503 .wait_state = powernv_eeh_wait_state, 1514 .get_log = pnv_eeh_get_log,
504 .get_log = powernv_eeh_get_log, 1515 .configure_bridge = pnv_eeh_configure_bridge,
505 .configure_bridge = powernv_eeh_configure_bridge, 1516 .err_inject = pnv_eeh_err_inject,
506 .err_inject = powernv_eeh_err_inject, 1517 .read_config = pnv_eeh_read_config,
507 .read_config = powernv_eeh_read_config, 1518 .write_config = pnv_eeh_write_config,
508 .write_config = powernv_eeh_write_config, 1519 .next_error = pnv_eeh_next_error,
509 .next_error = powernv_eeh_next_error, 1520 .restore_config = pnv_eeh_restore_config
510 .restore_config = powernv_eeh_restore_config
511}; 1521};
512 1522
513/** 1523/**
@@ -521,7 +1531,7 @@ static int __init eeh_powernv_init(void)
521 int ret = -EINVAL; 1531 int ret = -EINVAL;
522 1532
523 eeh_set_pe_aux_size(PNV_PCI_DIAG_BUF_SIZE); 1533 eeh_set_pe_aux_size(PNV_PCI_DIAG_BUF_SIZE);
524 ret = eeh_ops_register(&powernv_eeh_ops); 1534 ret = eeh_ops_register(&pnv_eeh_ops);
525 if (!ret) 1535 if (!ret)
526 pr_info("EEH: PowerNV platform initialized\n"); 1536 pr_info("EEH: PowerNV platform initialized\n");
527 else 1537 else
diff --git a/arch/powerpc/platforms/powernv/opal-dump.c b/arch/powerpc/platforms/powernv/opal-dump.c
index 23260f7dfa7a..5aa9c1ce4de3 100644
--- a/arch/powerpc/platforms/powernv/opal-dump.c
+++ b/arch/powerpc/platforms/powernv/opal-dump.c
@@ -452,5 +452,6 @@ void __init opal_platform_dump_init(void)
452 return; 452 return;
453 } 453 }
454 454
455 opal_dump_resend_notification(); 455 if (opal_check_token(OPAL_DUMP_RESEND))
456 opal_dump_resend_notification();
456} 457}
diff --git a/arch/powerpc/platforms/powernv/opal-elog.c b/arch/powerpc/platforms/powernv/opal-elog.c
index 518fe95dbf24..38ce757e5e2a 100644
--- a/arch/powerpc/platforms/powernv/opal-elog.c
+++ b/arch/powerpc/platforms/powernv/opal-elog.c
@@ -313,7 +313,8 @@ int __init opal_elog_init(void)
313 } 313 }
314 314
315 /* We are now ready to pull error logs from opal. */ 315 /* We are now ready to pull error logs from opal. */
316 opal_resend_pending_logs(); 316 if (opal_check_token(OPAL_ELOG_RESEND))
317 opal_resend_pending_logs();
317 318
318 return 0; 319 return 0;
319} 320}
diff --git a/arch/powerpc/platforms/powernv/opal-flash.c b/arch/powerpc/platforms/powernv/opal-flash.c
index 5c21d9c07f45..4ec6219287fc 100644
--- a/arch/powerpc/platforms/powernv/opal-flash.c
+++ b/arch/powerpc/platforms/powernv/opal-flash.c
@@ -120,7 +120,11 @@ static struct image_header_t image_header;
120static struct image_data_t image_data; 120static struct image_data_t image_data;
121static struct validate_flash_t validate_flash_data; 121static struct validate_flash_t validate_flash_data;
122static struct manage_flash_t manage_flash_data; 122static struct manage_flash_t manage_flash_data;
123static struct update_flash_t update_flash_data; 123
124/* Initialize update_flash_data status to No Operation */
125static struct update_flash_t update_flash_data = {
126 .status = FLASH_NO_OP,
127};
124 128
125static DEFINE_MUTEX(image_data_mutex); 129static DEFINE_MUTEX(image_data_mutex);
126 130
@@ -542,7 +546,7 @@ static struct attribute_group image_op_attr_group = {
542 .attrs = image_op_attrs, 546 .attrs = image_op_attrs,
543}; 547};
544 548
545void __init opal_flash_init(void) 549void __init opal_flash_update_init(void)
546{ 550{
547 int ret; 551 int ret;
548 552
diff --git a/arch/powerpc/platforms/powernv/opal-nvram.c b/arch/powerpc/platforms/powernv/opal-nvram.c
index f9896fd5d04a..9db4398ded5d 100644
--- a/arch/powerpc/platforms/powernv/opal-nvram.c
+++ b/arch/powerpc/platforms/powernv/opal-nvram.c
@@ -16,6 +16,7 @@
16#include <linux/of.h> 16#include <linux/of.h>
17 17
18#include <asm/opal.h> 18#include <asm/opal.h>
19#include <asm/nvram.h>
19#include <asm/machdep.h> 20#include <asm/machdep.h>
20 21
21static unsigned int nvram_size; 22static unsigned int nvram_size;
@@ -62,6 +63,15 @@ static ssize_t opal_nvram_write(char *buf, size_t count, loff_t *index)
62 return count; 63 return count;
63} 64}
64 65
66static int __init opal_nvram_init_log_partitions(void)
67{
68 /* Scan nvram for partitions */
69 nvram_scan_partitions();
70 nvram_init_oops_partition(0);
71 return 0;
72}
73machine_arch_initcall(powernv, opal_nvram_init_log_partitions);
74
65void __init opal_nvram_init(void) 75void __init opal_nvram_init(void)
66{ 76{
67 struct device_node *np; 77 struct device_node *np;
diff --git a/arch/powerpc/platforms/powernv/opal-sensor.c b/arch/powerpc/platforms/powernv/opal-sensor.c
index 4ab67ef7abc9..655250499d18 100644
--- a/arch/powerpc/platforms/powernv/opal-sensor.c
+++ b/arch/powerpc/platforms/powernv/opal-sensor.c
@@ -46,18 +46,28 @@ int opal_get_sensor_data(u32 sensor_hndl, u32 *sensor_data)
46 46
47 mutex_lock(&opal_sensor_mutex); 47 mutex_lock(&opal_sensor_mutex);
48 ret = opal_sensor_read(sensor_hndl, token, &data); 48 ret = opal_sensor_read(sensor_hndl, token, &data);
49 if (ret != OPAL_ASYNC_COMPLETION) 49 switch (ret) {
50 goto out_token; 50 case OPAL_ASYNC_COMPLETION:
51 ret = opal_async_wait_response(token, &msg);
52 if (ret) {
53 pr_err("%s: Failed to wait for the async response, %d\n",
54 __func__, ret);
55 goto out_token;
56 }
51 57
52 ret = opal_async_wait_response(token, &msg); 58 ret = opal_error_code(be64_to_cpu(msg.params[1]));
53 if (ret) { 59 *sensor_data = be32_to_cpu(data);
54 pr_err("%s: Failed to wait for the async response, %d\n", 60 break;
55 __func__, ret); 61
56 goto out_token; 62 case OPAL_SUCCESS:
57 } 63 ret = 0;
64 *sensor_data = be32_to_cpu(data);
65 break;
58 66
59 *sensor_data = be32_to_cpu(data); 67 default:
60 ret = be64_to_cpu(msg.params[1]); 68 ret = opal_error_code(ret);
69 break;
70 }
61 71
62out_token: 72out_token:
63 mutex_unlock(&opal_sensor_mutex); 73 mutex_unlock(&opal_sensor_mutex);
diff --git a/arch/powerpc/platforms/powernv/opal-wrappers.S b/arch/powerpc/platforms/powernv/opal-wrappers.S
index fcbe899fe299..a7ade94cdf87 100644
--- a/arch/powerpc/platforms/powernv/opal-wrappers.S
+++ b/arch/powerpc/platforms/powernv/opal-wrappers.S
@@ -286,9 +286,12 @@ OPAL_CALL(opal_handle_hmi, OPAL_HANDLE_HMI);
286OPAL_CALL(opal_slw_set_reg, OPAL_SLW_SET_REG); 286OPAL_CALL(opal_slw_set_reg, OPAL_SLW_SET_REG);
287OPAL_CALL(opal_register_dump_region, OPAL_REGISTER_DUMP_REGION); 287OPAL_CALL(opal_register_dump_region, OPAL_REGISTER_DUMP_REGION);
288OPAL_CALL(opal_unregister_dump_region, OPAL_UNREGISTER_DUMP_REGION); 288OPAL_CALL(opal_unregister_dump_region, OPAL_UNREGISTER_DUMP_REGION);
289OPAL_CALL(opal_pci_set_phb_cxl_mode, OPAL_PCI_SET_PHB_CXL_MODE); 289OPAL_CALL(opal_pci_set_phb_cxl_mode, OPAL_PCI_SET_PHB_CAPI_MODE);
290OPAL_CALL(opal_tpo_write, OPAL_WRITE_TPO); 290OPAL_CALL(opal_tpo_write, OPAL_WRITE_TPO);
291OPAL_CALL(opal_tpo_read, OPAL_READ_TPO); 291OPAL_CALL(opal_tpo_read, OPAL_READ_TPO);
292OPAL_CALL(opal_ipmi_send, OPAL_IPMI_SEND); 292OPAL_CALL(opal_ipmi_send, OPAL_IPMI_SEND);
293OPAL_CALL(opal_ipmi_recv, OPAL_IPMI_RECV); 293OPAL_CALL(opal_ipmi_recv, OPAL_IPMI_RECV);
294OPAL_CALL(opal_i2c_request, OPAL_I2C_REQUEST); 294OPAL_CALL(opal_i2c_request, OPAL_I2C_REQUEST);
295OPAL_CALL(opal_flash_read, OPAL_FLASH_READ);
296OPAL_CALL(opal_flash_write, OPAL_FLASH_WRITE);
297OPAL_CALL(opal_flash_erase, OPAL_FLASH_ERASE);
diff --git a/arch/powerpc/platforms/powernv/opal.c b/arch/powerpc/platforms/powernv/opal.c
index 18fd4e71c9c1..2241565b0739 100644
--- a/arch/powerpc/platforms/powernv/opal.c
+++ b/arch/powerpc/platforms/powernv/opal.c
@@ -23,6 +23,8 @@
23#include <linux/kobject.h> 23#include <linux/kobject.h>
24#include <linux/delay.h> 24#include <linux/delay.h>
25#include <linux/memblock.h> 25#include <linux/memblock.h>
26#include <linux/kthread.h>
27#include <linux/freezer.h>
26 28
27#include <asm/machdep.h> 29#include <asm/machdep.h>
28#include <asm/opal.h> 30#include <asm/opal.h>
@@ -58,6 +60,7 @@ static struct atomic_notifier_head opal_msg_notifier_head[OPAL_MSG_TYPE_MAX];
58static DEFINE_SPINLOCK(opal_notifier_lock); 60static DEFINE_SPINLOCK(opal_notifier_lock);
59static uint64_t last_notified_mask = 0x0ul; 61static uint64_t last_notified_mask = 0x0ul;
60static atomic_t opal_notifier_hold = ATOMIC_INIT(0); 62static atomic_t opal_notifier_hold = ATOMIC_INIT(0);
63static uint32_t opal_heartbeat;
61 64
62static void opal_reinit_cores(void) 65static void opal_reinit_cores(void)
63{ 66{
@@ -302,23 +305,26 @@ void opal_notifier_disable(void)
302 * Opal message notifier based on message type. Allow subscribers to get 305 * Opal message notifier based on message type. Allow subscribers to get
303 * notified for specific messgae type. 306 * notified for specific messgae type.
304 */ 307 */
305int opal_message_notifier_register(enum OpalMessageType msg_type, 308int opal_message_notifier_register(enum opal_msg_type msg_type,
306 struct notifier_block *nb) 309 struct notifier_block *nb)
307{ 310{
308 if (!nb) { 311 if (!nb || msg_type >= OPAL_MSG_TYPE_MAX) {
309 pr_warning("%s: Invalid argument (%p)\n", 312 pr_warning("%s: Invalid arguments, msg_type:%d\n",
310 __func__, nb);
311 return -EINVAL;
312 }
313 if (msg_type > OPAL_MSG_TYPE_MAX) {
314 pr_warning("%s: Invalid message type argument (%d)\n",
315 __func__, msg_type); 313 __func__, msg_type);
316 return -EINVAL; 314 return -EINVAL;
317 } 315 }
316
318 return atomic_notifier_chain_register( 317 return atomic_notifier_chain_register(
319 &opal_msg_notifier_head[msg_type], nb); 318 &opal_msg_notifier_head[msg_type], nb);
320} 319}
321 320
321int opal_message_notifier_unregister(enum opal_msg_type msg_type,
322 struct notifier_block *nb)
323{
324 return atomic_notifier_chain_unregister(
325 &opal_msg_notifier_head[msg_type], nb);
326}
327
322static void opal_message_do_notify(uint32_t msg_type, void *msg) 328static void opal_message_do_notify(uint32_t msg_type, void *msg)
323{ 329{
324 /* notify subscribers */ 330 /* notify subscribers */
@@ -351,7 +357,7 @@ static void opal_handle_message(void)
351 type = be32_to_cpu(msg.msg_type); 357 type = be32_to_cpu(msg.msg_type);
352 358
353 /* Sanity check */ 359 /* Sanity check */
354 if (type > OPAL_MSG_TYPE_MAX) { 360 if (type >= OPAL_MSG_TYPE_MAX) {
355 pr_warning("%s: Unknown message type: %u\n", __func__, type); 361 pr_warning("%s: Unknown message type: %u\n", __func__, type);
356 return; 362 return;
357 } 363 }
@@ -665,6 +671,9 @@ static void __init opal_dump_region_init(void)
665 uint64_t size; 671 uint64_t size;
666 int rc; 672 int rc;
667 673
674 if (!opal_check_token(OPAL_REGISTER_DUMP_REGION))
675 return;
676
668 /* Register kernel log buffer */ 677 /* Register kernel log buffer */
669 addr = log_buf_addr_get(); 678 addr = log_buf_addr_get();
670 if (addr == NULL) 679 if (addr == NULL)
@@ -684,6 +693,15 @@ static void __init opal_dump_region_init(void)
684 "rc = %d\n", rc); 693 "rc = %d\n", rc);
685} 694}
686 695
696static void opal_flash_init(struct device_node *opal_node)
697{
698 struct device_node *np;
699
700 for_each_child_of_node(opal_node, np)
701 if (of_device_is_compatible(np, "ibm,opal-flash"))
702 of_platform_device_create(np, NULL, NULL);
703}
704
687static void opal_ipmi_init(struct device_node *opal_node) 705static void opal_ipmi_init(struct device_node *opal_node)
688{ 706{
689 struct device_node *np; 707 struct device_node *np;
@@ -741,6 +759,29 @@ static void __init opal_irq_init(struct device_node *dn)
741 } 759 }
742} 760}
743 761
762static int kopald(void *unused)
763{
764 set_freezable();
765 do {
766 try_to_freeze();
767 opal_poll_events(NULL);
768 msleep_interruptible(opal_heartbeat);
769 } while (!kthread_should_stop());
770
771 return 0;
772}
773
774static void opal_init_heartbeat(void)
775{
776 /* Old firwmware, we assume the HVC heartbeat is sufficient */
777 if (of_property_read_u32(opal_node, "ibm,heartbeat-ms",
778 &opal_heartbeat) != 0)
779 opal_heartbeat = 0;
780
781 if (opal_heartbeat)
782 kthread_run(kopald, NULL, "kopald");
783}
784
744static int __init opal_init(void) 785static int __init opal_init(void)
745{ 786{
746 struct device_node *np, *consoles; 787 struct device_node *np, *consoles;
@@ -769,6 +810,9 @@ static int __init opal_init(void)
769 /* Create i2c platform devices */ 810 /* Create i2c platform devices */
770 opal_i2c_create_devs(); 811 opal_i2c_create_devs();
771 812
813 /* Setup a heatbeat thread if requested by OPAL */
814 opal_init_heartbeat();
815
772 /* Find all OPAL interrupts and request them */ 816 /* Find all OPAL interrupts and request them */
773 opal_irq_init(opal_node); 817 opal_irq_init(opal_node);
774 818
@@ -782,7 +826,7 @@ static int __init opal_init(void)
782 /* Setup error log interface */ 826 /* Setup error log interface */
783 rc = opal_elog_init(); 827 rc = opal_elog_init();
784 /* Setup code update interface */ 828 /* Setup code update interface */
785 opal_flash_init(); 829 opal_flash_update_init();
786 /* Setup platform dump extract interface */ 830 /* Setup platform dump extract interface */
787 opal_platform_dump_init(); 831 opal_platform_dump_init();
788 /* Setup system parameters interface */ 832 /* Setup system parameters interface */
@@ -791,8 +835,11 @@ static int __init opal_init(void)
791 opal_msglog_init(); 835 opal_msglog_init();
792 } 836 }
793 837
838 /* Initialize OPAL IPMI backend */
794 opal_ipmi_init(opal_node); 839 opal_ipmi_init(opal_node);
795 840
841 opal_flash_init(opal_node);
842
796 return 0; 843 return 0;
797} 844}
798machine_subsys_initcall(powernv, opal_init); 845machine_subsys_initcall(powernv, opal_init);
@@ -823,13 +870,17 @@ void opal_shutdown(void)
823 } 870 }
824 871
825 /* Unregister memory dump region */ 872 /* Unregister memory dump region */
826 opal_unregister_dump_region(OPAL_DUMP_REGION_LOG_BUF); 873 if (opal_check_token(OPAL_UNREGISTER_DUMP_REGION))
874 opal_unregister_dump_region(OPAL_DUMP_REGION_LOG_BUF);
827} 875}
828 876
829/* Export this so that test modules can use it */ 877/* Export this so that test modules can use it */
830EXPORT_SYMBOL_GPL(opal_invalid_call); 878EXPORT_SYMBOL_GPL(opal_invalid_call);
831EXPORT_SYMBOL_GPL(opal_ipmi_send); 879EXPORT_SYMBOL_GPL(opal_ipmi_send);
832EXPORT_SYMBOL_GPL(opal_ipmi_recv); 880EXPORT_SYMBOL_GPL(opal_ipmi_recv);
881EXPORT_SYMBOL_GPL(opal_flash_read);
882EXPORT_SYMBOL_GPL(opal_flash_write);
883EXPORT_SYMBOL_GPL(opal_flash_erase);
833 884
834/* Convert a region of vmalloc memory to an opal sg list */ 885/* Convert a region of vmalloc memory to an opal sg list */
835struct opal_sg_list *opal_vmalloc_to_sg_list(void *vmalloc_addr, 886struct opal_sg_list *opal_vmalloc_to_sg_list(void *vmalloc_addr,
@@ -894,6 +945,25 @@ void opal_free_sg_list(struct opal_sg_list *sg)
894 } 945 }
895} 946}
896 947
948int opal_error_code(int rc)
949{
950 switch (rc) {
951 case OPAL_SUCCESS: return 0;
952
953 case OPAL_PARAMETER: return -EINVAL;
954 case OPAL_ASYNC_COMPLETION: return -EINPROGRESS;
955 case OPAL_BUSY_EVENT: return -EBUSY;
956 case OPAL_NO_MEM: return -ENOMEM;
957
958 case OPAL_UNSUPPORTED: return -EIO;
959 case OPAL_HARDWARE: return -EIO;
960 case OPAL_INTERNAL_ERROR: return -EIO;
961 default:
962 pr_err("%s: unexpected OPAL error %d\n", __func__, rc);
963 return -EIO;
964 }
965}
966
897EXPORT_SYMBOL_GPL(opal_poll_events); 967EXPORT_SYMBOL_GPL(opal_poll_events);
898EXPORT_SYMBOL_GPL(opal_rtc_read); 968EXPORT_SYMBOL_GPL(opal_rtc_read);
899EXPORT_SYMBOL_GPL(opal_rtc_write); 969EXPORT_SYMBOL_GPL(opal_rtc_write);
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
index 6c9ff2b95119..920c252d1f49 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -44,6 +44,9 @@
44#include "powernv.h" 44#include "powernv.h"
45#include "pci.h" 45#include "pci.h"
46 46
47/* 256M DMA window, 4K TCE pages, 8 bytes TCE */
48#define TCE32_TABLE_SIZE ((0x10000000 / 0x1000) * 8)
49
47static void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, 50static void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
48 const char *fmt, ...) 51 const char *fmt, ...)
49{ 52{
@@ -56,11 +59,18 @@ static void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
56 vaf.fmt = fmt; 59 vaf.fmt = fmt;
57 vaf.va = &args; 60 vaf.va = &args;
58 61
59 if (pe->pdev) 62 if (pe->flags & PNV_IODA_PE_DEV)
60 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); 63 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
61 else 64 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
62 sprintf(pfix, "%04x:%02x ", 65 sprintf(pfix, "%04x:%02x ",
63 pci_domain_nr(pe->pbus), pe->pbus->number); 66 pci_domain_nr(pe->pbus), pe->pbus->number);
67#ifdef CONFIG_PCI_IOV
68 else if (pe->flags & PNV_IODA_PE_VF)
69 sprintf(pfix, "%04x:%02x:%2x.%d",
70 pci_domain_nr(pe->parent_dev->bus),
71 (pe->rid & 0xff00) >> 8,
72 PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
73#endif /* CONFIG_PCI_IOV*/
64 74
65 printk("%spci %s: [PE# %.3d] %pV", 75 printk("%spci %s: [PE# %.3d] %pV",
66 level, pfix, pe->pe_number, &vaf); 76 level, pfix, pe->pe_number, &vaf);
@@ -591,7 +601,7 @@ static int pnv_ioda_set_peltv(struct pnv_phb *phb,
591 bool is_add) 601 bool is_add)
592{ 602{
593 struct pnv_ioda_pe *slave; 603 struct pnv_ioda_pe *slave;
594 struct pci_dev *pdev; 604 struct pci_dev *pdev = NULL;
595 int ret; 605 int ret;
596 606
597 /* 607 /*
@@ -630,8 +640,12 @@ static int pnv_ioda_set_peltv(struct pnv_phb *phb,
630 640
631 if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) 641 if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
632 pdev = pe->pbus->self; 642 pdev = pe->pbus->self;
633 else 643 else if (pe->flags & PNV_IODA_PE_DEV)
634 pdev = pe->pdev->bus->self; 644 pdev = pe->pdev->bus->self;
645#ifdef CONFIG_PCI_IOV
646 else if (pe->flags & PNV_IODA_PE_VF)
647 pdev = pe->parent_dev->bus->self;
648#endif /* CONFIG_PCI_IOV */
635 while (pdev) { 649 while (pdev) {
636 struct pci_dn *pdn = pci_get_pdn(pdev); 650 struct pci_dn *pdn = pci_get_pdn(pdev);
637 struct pnv_ioda_pe *parent; 651 struct pnv_ioda_pe *parent;
@@ -649,6 +663,87 @@ static int pnv_ioda_set_peltv(struct pnv_phb *phb,
649 return 0; 663 return 0;
650} 664}
651 665
666#ifdef CONFIG_PCI_IOV
667static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
668{
669 struct pci_dev *parent;
670 uint8_t bcomp, dcomp, fcomp;
671 int64_t rc;
672 long rid_end, rid;
673
674 /* Currently, we just deconfigure VF PE. Bus PE will always there.*/
675 if (pe->pbus) {
676 int count;
677
678 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
679 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
680 parent = pe->pbus->self;
681 if (pe->flags & PNV_IODA_PE_BUS_ALL)
682 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
683 else
684 count = 1;
685
686 switch(count) {
687 case 1: bcomp = OpalPciBusAll; break;
688 case 2: bcomp = OpalPciBus7Bits; break;
689 case 4: bcomp = OpalPciBus6Bits; break;
690 case 8: bcomp = OpalPciBus5Bits; break;
691 case 16: bcomp = OpalPciBus4Bits; break;
692 case 32: bcomp = OpalPciBus3Bits; break;
693 default:
694 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
695 count);
696 /* Do an exact match only */
697 bcomp = OpalPciBusAll;
698 }
699 rid_end = pe->rid + (count << 8);
700 } else {
701 if (pe->flags & PNV_IODA_PE_VF)
702 parent = pe->parent_dev;
703 else
704 parent = pe->pdev->bus->self;
705 bcomp = OpalPciBusAll;
706 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
707 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
708 rid_end = pe->rid + 1;
709 }
710
711 /* Clear the reverse map */
712 for (rid = pe->rid; rid < rid_end; rid++)
713 phb->ioda.pe_rmap[rid] = 0;
714
715 /* Release from all parents PELT-V */
716 while (parent) {
717 struct pci_dn *pdn = pci_get_pdn(parent);
718 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
719 rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
720 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
721 /* XXX What to do in case of error ? */
722 }
723 parent = parent->bus->self;
724 }
725
726 opal_pci_eeh_freeze_set(phb->opal_id, pe->pe_number,
727 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
728
729 /* Disassociate PE in PELT */
730 rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
731 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
732 if (rc)
733 pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc);
734 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
735 bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
736 if (rc)
737 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
738
739 pe->pbus = NULL;
740 pe->pdev = NULL;
741 pe->parent_dev = NULL;
742
743 return 0;
744}
745#endif /* CONFIG_PCI_IOV */
746
652static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) 747static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
653{ 748{
654 struct pci_dev *parent; 749 struct pci_dev *parent;
@@ -675,15 +770,19 @@ static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
675 case 16: bcomp = OpalPciBus4Bits; break; 770 case 16: bcomp = OpalPciBus4Bits; break;
676 case 32: bcomp = OpalPciBus3Bits; break; 771 case 32: bcomp = OpalPciBus3Bits; break;
677 default: 772 default:
678 pr_err("%s: Number of subordinate busses %d" 773 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
679 " unsupported\n", 774 count);
680 pci_name(pe->pbus->self), count);
681 /* Do an exact match only */ 775 /* Do an exact match only */
682 bcomp = OpalPciBusAll; 776 bcomp = OpalPciBusAll;
683 } 777 }
684 rid_end = pe->rid + (count << 8); 778 rid_end = pe->rid + (count << 8);
685 } else { 779 } else {
686 parent = pe->pdev->bus->self; 780#ifdef CONFIG_PCI_IOV
781 if (pe->flags & PNV_IODA_PE_VF)
782 parent = pe->parent_dev;
783 else
784#endif /* CONFIG_PCI_IOV */
785 parent = pe->pdev->bus->self;
687 bcomp = OpalPciBusAll; 786 bcomp = OpalPciBusAll;
688 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; 787 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
689 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; 788 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
@@ -774,6 +873,78 @@ static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev)
774 return 10; 873 return 10;
775} 874}
776 875
876#ifdef CONFIG_PCI_IOV
877static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
878{
879 struct pci_dn *pdn = pci_get_pdn(dev);
880 int i;
881 struct resource *res, res2;
882 resource_size_t size;
883 u16 num_vfs;
884
885 if (!dev->is_physfn)
886 return -EINVAL;
887
888 /*
889 * "offset" is in VFs. The M64 windows are sized so that when they
890 * are segmented, each segment is the same size as the IOV BAR.
891 * Each segment is in a separate PE, and the high order bits of the
892 * address are the PE number. Therefore, each VF's BAR is in a
893 * separate PE, and changing the IOV BAR start address changes the
894 * range of PEs the VFs are in.
895 */
896 num_vfs = pdn->num_vfs;
897 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
898 res = &dev->resource[i + PCI_IOV_RESOURCES];
899 if (!res->flags || !res->parent)
900 continue;
901
902 if (!pnv_pci_is_mem_pref_64(res->flags))
903 continue;
904
905 /*
906 * The actual IOV BAR range is determined by the start address
907 * and the actual size for num_vfs VFs BAR. This check is to
908 * make sure that after shifting, the range will not overlap
909 * with another device.
910 */
911 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
912 res2.flags = res->flags;
913 res2.start = res->start + (size * offset);
914 res2.end = res2.start + (size * num_vfs) - 1;
915
916 if (res2.end > res->end) {
917 dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
918 i, &res2, res, num_vfs, offset);
919 return -EBUSY;
920 }
921 }
922
923 /*
924 * After doing so, there would be a "hole" in the /proc/iomem when
925 * offset is a positive value. It looks like the device return some
926 * mmio back to the system, which actually no one could use it.
927 */
928 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
929 res = &dev->resource[i + PCI_IOV_RESOURCES];
930 if (!res->flags || !res->parent)
931 continue;
932
933 if (!pnv_pci_is_mem_pref_64(res->flags))
934 continue;
935
936 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
937 res2 = *res;
938 res->start += size * offset;
939
940 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (enabling %d VFs shifted by %d)\n",
941 i, &res2, res, num_vfs, offset);
942 pci_update_resource(dev, i + PCI_IOV_RESOURCES);
943 }
944 return 0;
945}
946#endif /* CONFIG_PCI_IOV */
947
777#if 0 948#if 0
778static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) 949static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
779{ 950{
@@ -857,7 +1028,6 @@ static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
857 pci_name(dev)); 1028 pci_name(dev));
858 continue; 1029 continue;
859 } 1030 }
860 pdn->pcidev = dev;
861 pdn->pe_number = pe->pe_number; 1031 pdn->pe_number = pe->pe_number;
862 pe->dma_weight += pnv_ioda_dma_weight(dev); 1032 pe->dma_weight += pnv_ioda_dma_weight(dev);
863 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) 1033 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
@@ -916,6 +1086,10 @@ static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, int all)
916 return; 1086 return;
917 } 1087 }
918 1088
1089 pe->tce32_table = kzalloc_node(sizeof(struct iommu_table),
1090 GFP_KERNEL, hose->node);
1091 pe->tce32_table->data = pe;
1092
919 /* Associate it with all child devices */ 1093 /* Associate it with all child devices */
920 pnv_ioda_setup_same_PE(bus, pe); 1094 pnv_ioda_setup_same_PE(bus, pe);
921 1095
@@ -974,6 +1148,441 @@ static void pnv_pci_ioda_setup_PEs(void)
974 } 1148 }
975} 1149}
976 1150
1151#ifdef CONFIG_PCI_IOV
1152static int pnv_pci_vf_release_m64(struct pci_dev *pdev)
1153{
1154 struct pci_bus *bus;
1155 struct pci_controller *hose;
1156 struct pnv_phb *phb;
1157 struct pci_dn *pdn;
1158 int i, j;
1159
1160 bus = pdev->bus;
1161 hose = pci_bus_to_host(bus);
1162 phb = hose->private_data;
1163 pdn = pci_get_pdn(pdev);
1164
1165 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
1166 for (j = 0; j < M64_PER_IOV; j++) {
1167 if (pdn->m64_wins[i][j] == IODA_INVALID_M64)
1168 continue;
1169 opal_pci_phb_mmio_enable(phb->opal_id,
1170 OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 0);
1171 clear_bit(pdn->m64_wins[i][j], &phb->ioda.m64_bar_alloc);
1172 pdn->m64_wins[i][j] = IODA_INVALID_M64;
1173 }
1174
1175 return 0;
1176}
1177
1178static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
1179{
1180 struct pci_bus *bus;
1181 struct pci_controller *hose;
1182 struct pnv_phb *phb;
1183 struct pci_dn *pdn;
1184 unsigned int win;
1185 struct resource *res;
1186 int i, j;
1187 int64_t rc;
1188 int total_vfs;
1189 resource_size_t size, start;
1190 int pe_num;
1191 int vf_groups;
1192 int vf_per_group;
1193
1194 bus = pdev->bus;
1195 hose = pci_bus_to_host(bus);
1196 phb = hose->private_data;
1197 pdn = pci_get_pdn(pdev);
1198 total_vfs = pci_sriov_get_totalvfs(pdev);
1199
1200 /* Initialize the m64_wins to IODA_INVALID_M64 */
1201 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
1202 for (j = 0; j < M64_PER_IOV; j++)
1203 pdn->m64_wins[i][j] = IODA_INVALID_M64;
1204
1205 if (pdn->m64_per_iov == M64_PER_IOV) {
1206 vf_groups = (num_vfs <= M64_PER_IOV) ? num_vfs: M64_PER_IOV;
1207 vf_per_group = (num_vfs <= M64_PER_IOV)? 1:
1208 roundup_pow_of_two(num_vfs) / pdn->m64_per_iov;
1209 } else {
1210 vf_groups = 1;
1211 vf_per_group = 1;
1212 }
1213
1214 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1215 res = &pdev->resource[i + PCI_IOV_RESOURCES];
1216 if (!res->flags || !res->parent)
1217 continue;
1218
1219 if (!pnv_pci_is_mem_pref_64(res->flags))
1220 continue;
1221
1222 for (j = 0; j < vf_groups; j++) {
1223 do {
1224 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc,
1225 phb->ioda.m64_bar_idx + 1, 0);
1226
1227 if (win >= phb->ioda.m64_bar_idx + 1)
1228 goto m64_failed;
1229 } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));
1230
1231 pdn->m64_wins[i][j] = win;
1232
1233 if (pdn->m64_per_iov == M64_PER_IOV) {
1234 size = pci_iov_resource_size(pdev,
1235 PCI_IOV_RESOURCES + i);
1236 size = size * vf_per_group;
1237 start = res->start + size * j;
1238 } else {
1239 size = resource_size(res);
1240 start = res->start;
1241 }
1242
1243 /* Map the M64 here */
1244 if (pdn->m64_per_iov == M64_PER_IOV) {
1245 pe_num = pdn->offset + j;
1246 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
1247 pe_num, OPAL_M64_WINDOW_TYPE,
1248 pdn->m64_wins[i][j], 0);
1249 }
1250
1251 rc = opal_pci_set_phb_mem_window(phb->opal_id,
1252 OPAL_M64_WINDOW_TYPE,
1253 pdn->m64_wins[i][j],
1254 start,
1255 0, /* unused */
1256 size);
1257
1258
1259 if (rc != OPAL_SUCCESS) {
1260 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n",
1261 win, rc);
1262 goto m64_failed;
1263 }
1264
1265 if (pdn->m64_per_iov == M64_PER_IOV)
1266 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1267 OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 2);
1268 else
1269 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1270 OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 1);
1271
1272 if (rc != OPAL_SUCCESS) {
1273 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n",
1274 win, rc);
1275 goto m64_failed;
1276 }
1277 }
1278 }
1279 return 0;
1280
1281m64_failed:
1282 pnv_pci_vf_release_m64(pdev);
1283 return -EBUSY;
1284}
1285
1286static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe)
1287{
1288 struct pci_bus *bus;
1289 struct pci_controller *hose;
1290 struct pnv_phb *phb;
1291 struct iommu_table *tbl;
1292 unsigned long addr;
1293 int64_t rc;
1294
1295 bus = dev->bus;
1296 hose = pci_bus_to_host(bus);
1297 phb = hose->private_data;
1298 tbl = pe->tce32_table;
1299 addr = tbl->it_base;
1300
1301 opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
1302 pe->pe_number << 1, 1, __pa(addr),
1303 0, 0x1000);
1304
1305 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
1306 pe->pe_number,
1307 (pe->pe_number << 1) + 1,
1308 pe->tce_bypass_base,
1309 0);
1310 if (rc)
1311 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
1312
1313 iommu_free_table(tbl, of_node_full_name(dev->dev.of_node));
1314 free_pages(addr, get_order(TCE32_TABLE_SIZE));
1315 pe->tce32_table = NULL;
1316}
1317
1318static void pnv_ioda_release_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1319{
1320 struct pci_bus *bus;
1321 struct pci_controller *hose;
1322 struct pnv_phb *phb;
1323 struct pnv_ioda_pe *pe, *pe_n;
1324 struct pci_dn *pdn;
1325 u16 vf_index;
1326 int64_t rc;
1327
1328 bus = pdev->bus;
1329 hose = pci_bus_to_host(bus);
1330 phb = hose->private_data;
1331 pdn = pci_get_pdn(pdev);
1332
1333 if (!pdev->is_physfn)
1334 return;
1335
1336 if (pdn->m64_per_iov == M64_PER_IOV && num_vfs > M64_PER_IOV) {
1337 int vf_group;
1338 int vf_per_group;
1339 int vf_index1;
1340
1341 vf_per_group = roundup_pow_of_two(num_vfs) / pdn->m64_per_iov;
1342
1343 for (vf_group = 0; vf_group < M64_PER_IOV; vf_group++)
1344 for (vf_index = vf_group * vf_per_group;
1345 vf_index < (vf_group + 1) * vf_per_group &&
1346 vf_index < num_vfs;
1347 vf_index++)
1348 for (vf_index1 = vf_group * vf_per_group;
1349 vf_index1 < (vf_group + 1) * vf_per_group &&
1350 vf_index1 < num_vfs;
1351 vf_index1++){
1352
1353 rc = opal_pci_set_peltv(phb->opal_id,
1354 pdn->offset + vf_index,
1355 pdn->offset + vf_index1,
1356 OPAL_REMOVE_PE_FROM_DOMAIN);
1357
1358 if (rc)
1359 dev_warn(&pdev->dev, "%s: Failed to unlink same group PE#%d(%lld)\n",
1360 __func__,
1361 pdn->offset + vf_index1, rc);
1362 }
1363 }
1364
1365 list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
1366 if (pe->parent_dev != pdev)
1367 continue;
1368
1369 pnv_pci_ioda2_release_dma_pe(pdev, pe);
1370
1371 /* Remove from list */
1372 mutex_lock(&phb->ioda.pe_list_mutex);
1373 list_del(&pe->list);
1374 mutex_unlock(&phb->ioda.pe_list_mutex);
1375
1376 pnv_ioda_deconfigure_pe(phb, pe);
1377
1378 pnv_ioda_free_pe(phb, pe->pe_number);
1379 }
1380}
1381
1382void pnv_pci_sriov_disable(struct pci_dev *pdev)
1383{
1384 struct pci_bus *bus;
1385 struct pci_controller *hose;
1386 struct pnv_phb *phb;
1387 struct pci_dn *pdn;
1388 struct pci_sriov *iov;
1389 u16 num_vfs;
1390
1391 bus = pdev->bus;
1392 hose = pci_bus_to_host(bus);
1393 phb = hose->private_data;
1394 pdn = pci_get_pdn(pdev);
1395 iov = pdev->sriov;
1396 num_vfs = pdn->num_vfs;
1397
1398 /* Release VF PEs */
1399 pnv_ioda_release_vf_PE(pdev, num_vfs);
1400
1401 if (phb->type == PNV_PHB_IODA2) {
1402 if (pdn->m64_per_iov == 1)
1403 pnv_pci_vf_resource_shift(pdev, -pdn->offset);
1404
1405 /* Release M64 windows */
1406 pnv_pci_vf_release_m64(pdev);
1407
1408 /* Release PE numbers */
1409 bitmap_clear(phb->ioda.pe_alloc, pdn->offset, num_vfs);
1410 pdn->offset = 0;
1411 }
1412}
1413
1414static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1415 struct pnv_ioda_pe *pe);
1416static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1417{
1418 struct pci_bus *bus;
1419 struct pci_controller *hose;
1420 struct pnv_phb *phb;
1421 struct pnv_ioda_pe *pe;
1422 int pe_num;
1423 u16 vf_index;
1424 struct pci_dn *pdn;
1425 int64_t rc;
1426
1427 bus = pdev->bus;
1428 hose = pci_bus_to_host(bus);
1429 phb = hose->private_data;
1430 pdn = pci_get_pdn(pdev);
1431
1432 if (!pdev->is_physfn)
1433 return;
1434
1435 /* Reserve PE for each VF */
1436 for (vf_index = 0; vf_index < num_vfs; vf_index++) {
1437 pe_num = pdn->offset + vf_index;
1438
1439 pe = &phb->ioda.pe_array[pe_num];
1440 pe->pe_number = pe_num;
1441 pe->phb = phb;
1442 pe->flags = PNV_IODA_PE_VF;
1443 pe->pbus = NULL;
1444 pe->parent_dev = pdev;
1445 pe->tce32_seg = -1;
1446 pe->mve_number = -1;
1447 pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) |
1448 pci_iov_virtfn_devfn(pdev, vf_index);
1449
1450 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%d\n",
1451 hose->global_number, pdev->bus->number,
1452 PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)),
1453 PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num);
1454
1455 if (pnv_ioda_configure_pe(phb, pe)) {
1456 /* XXX What do we do here ? */
1457 if (pe_num)
1458 pnv_ioda_free_pe(phb, pe_num);
1459 pe->pdev = NULL;
1460 continue;
1461 }
1462
1463 pe->tce32_table = kzalloc_node(sizeof(struct iommu_table),
1464 GFP_KERNEL, hose->node);
1465 pe->tce32_table->data = pe;
1466
1467 /* Put PE to the list */
1468 mutex_lock(&phb->ioda.pe_list_mutex);
1469 list_add_tail(&pe->list, &phb->ioda.pe_list);
1470 mutex_unlock(&phb->ioda.pe_list_mutex);
1471
1472 pnv_pci_ioda2_setup_dma_pe(phb, pe);
1473 }
1474
1475 if (pdn->m64_per_iov == M64_PER_IOV && num_vfs > M64_PER_IOV) {
1476 int vf_group;
1477 int vf_per_group;
1478 int vf_index1;
1479
1480 vf_per_group = roundup_pow_of_two(num_vfs) / pdn->m64_per_iov;
1481
1482 for (vf_group = 0; vf_group < M64_PER_IOV; vf_group++) {
1483 for (vf_index = vf_group * vf_per_group;
1484 vf_index < (vf_group + 1) * vf_per_group &&
1485 vf_index < num_vfs;
1486 vf_index++) {
1487 for (vf_index1 = vf_group * vf_per_group;
1488 vf_index1 < (vf_group + 1) * vf_per_group &&
1489 vf_index1 < num_vfs;
1490 vf_index1++) {
1491
1492 rc = opal_pci_set_peltv(phb->opal_id,
1493 pdn->offset + vf_index,
1494 pdn->offset + vf_index1,
1495 OPAL_ADD_PE_TO_DOMAIN);
1496
1497 if (rc)
1498 dev_warn(&pdev->dev, "%s: Failed to link same group PE#%d(%lld)\n",
1499 __func__,
1500 pdn->offset + vf_index1, rc);
1501 }
1502 }
1503 }
1504 }
1505}
1506
1507int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1508{
1509 struct pci_bus *bus;
1510 struct pci_controller *hose;
1511 struct pnv_phb *phb;
1512 struct pci_dn *pdn;
1513 int ret;
1514
1515 bus = pdev->bus;
1516 hose = pci_bus_to_host(bus);
1517 phb = hose->private_data;
1518 pdn = pci_get_pdn(pdev);
1519
1520 if (phb->type == PNV_PHB_IODA2) {
1521 /* Calculate available PE for required VFs */
1522 mutex_lock(&phb->ioda.pe_alloc_mutex);
1523 pdn->offset = bitmap_find_next_zero_area(
1524 phb->ioda.pe_alloc, phb->ioda.total_pe,
1525 0, num_vfs, 0);
1526 if (pdn->offset >= phb->ioda.total_pe) {
1527 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1528 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs);
1529 pdn->offset = 0;
1530 return -EBUSY;
1531 }
1532 bitmap_set(phb->ioda.pe_alloc, pdn->offset, num_vfs);
1533 pdn->num_vfs = num_vfs;
1534 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1535
1536 /* Assign M64 window accordingly */
1537 ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
1538 if (ret) {
1539 dev_info(&pdev->dev, "Not enough M64 window resources\n");
1540 goto m64_failed;
1541 }
1542
1543 /*
1544 * When using one M64 BAR to map one IOV BAR, we need to shift
1545 * the IOV BAR according to the PE# allocated to the VFs.
1546 * Otherwise, the PE# for the VF will conflict with others.
1547 */
1548 if (pdn->m64_per_iov == 1) {
1549 ret = pnv_pci_vf_resource_shift(pdev, pdn->offset);
1550 if (ret)
1551 goto m64_failed;
1552 }
1553 }
1554
1555 /* Setup VF PEs */
1556 pnv_ioda_setup_vf_PE(pdev, num_vfs);
1557
1558 return 0;
1559
1560m64_failed:
1561 bitmap_clear(phb->ioda.pe_alloc, pdn->offset, num_vfs);
1562 pdn->offset = 0;
1563
1564 return ret;
1565}
1566
1567int pcibios_sriov_disable(struct pci_dev *pdev)
1568{
1569 pnv_pci_sriov_disable(pdev);
1570
1571 /* Release PCI data */
1572 remove_dev_pci_data(pdev);
1573 return 0;
1574}
1575
1576int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1577{
1578 /* Allocate PCI data */
1579 add_dev_pci_data(pdev);
1580
1581 pnv_pci_sriov_enable(pdev, num_vfs);
1582 return 0;
1583}
1584#endif /* CONFIG_PCI_IOV */
1585
977static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) 1586static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
978{ 1587{
979 struct pci_dn *pdn = pci_get_pdn(pdev); 1588 struct pci_dn *pdn = pci_get_pdn(pdev);
@@ -989,7 +1598,7 @@ static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev
989 1598
990 pe = &phb->ioda.pe_array[pdn->pe_number]; 1599 pe = &phb->ioda.pe_array[pdn->pe_number];
991 WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); 1600 WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
992 set_iommu_table_base_and_group(&pdev->dev, &pe->tce32_table); 1601 set_iommu_table_base_and_group(&pdev->dev, pe->tce32_table);
993} 1602}
994 1603
995static int pnv_pci_ioda_dma_set_mask(struct pnv_phb *phb, 1604static int pnv_pci_ioda_dma_set_mask(struct pnv_phb *phb,
@@ -1016,7 +1625,7 @@ static int pnv_pci_ioda_dma_set_mask(struct pnv_phb *phb,
1016 } else { 1625 } else {
1017 dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); 1626 dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n");
1018 set_dma_ops(&pdev->dev, &dma_iommu_ops); 1627 set_dma_ops(&pdev->dev, &dma_iommu_ops);
1019 set_iommu_table_base(&pdev->dev, &pe->tce32_table); 1628 set_iommu_table_base(&pdev->dev, pe->tce32_table);
1020 } 1629 }
1021 *pdev->dev.dma_mask = dma_mask; 1630 *pdev->dev.dma_mask = dma_mask;
1022 return 0; 1631 return 0;
@@ -1053,9 +1662,9 @@ static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe,
1053 list_for_each_entry(dev, &bus->devices, bus_list) { 1662 list_for_each_entry(dev, &bus->devices, bus_list) {
1054 if (add_to_iommu_group) 1663 if (add_to_iommu_group)
1055 set_iommu_table_base_and_group(&dev->dev, 1664 set_iommu_table_base_and_group(&dev->dev,
1056 &pe->tce32_table); 1665 pe->tce32_table);
1057 else 1666 else
1058 set_iommu_table_base(&dev->dev, &pe->tce32_table); 1667 set_iommu_table_base(&dev->dev, pe->tce32_table);
1059 1668
1060 if (dev->subordinate) 1669 if (dev->subordinate)
1061 pnv_ioda_setup_bus_dma(pe, dev->subordinate, 1670 pnv_ioda_setup_bus_dma(pe, dev->subordinate,
@@ -1145,8 +1754,7 @@ static void pnv_pci_ioda2_tce_invalidate(struct pnv_ioda_pe *pe,
1145void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl, 1754void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl,
1146 __be64 *startp, __be64 *endp, bool rm) 1755 __be64 *startp, __be64 *endp, bool rm)
1147{ 1756{
1148 struct pnv_ioda_pe *pe = container_of(tbl, struct pnv_ioda_pe, 1757 struct pnv_ioda_pe *pe = tbl->data;
1149 tce32_table);
1150 struct pnv_phb *phb = pe->phb; 1758 struct pnv_phb *phb = pe->phb;
1151 1759
1152 if (phb->type == PNV_PHB_IODA1) 1760 if (phb->type == PNV_PHB_IODA1)
@@ -1167,9 +1775,6 @@ static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb,
1167 int64_t rc; 1775 int64_t rc;
1168 void *addr; 1776 void *addr;
1169 1777
1170 /* 256M DMA window, 4K TCE pages, 8 bytes TCE */
1171#define TCE32_TABLE_SIZE ((0x10000000 / 0x1000) * 8)
1172
1173 /* XXX FIXME: Handle 64-bit only DMA devices */ 1778 /* XXX FIXME: Handle 64-bit only DMA devices */
1174 /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ 1779 /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
1175 /* XXX FIXME: Allocate multi-level tables on PHB3 */ 1780 /* XXX FIXME: Allocate multi-level tables on PHB3 */
@@ -1212,7 +1817,7 @@ static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb,
1212 } 1817 }
1213 1818
1214 /* Setup linux iommu table */ 1819 /* Setup linux iommu table */
1215 tbl = &pe->tce32_table; 1820 tbl = pe->tce32_table;
1216 pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs, 1821 pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs,
1217 base << 28, IOMMU_PAGE_SHIFT_4K); 1822 base << 28, IOMMU_PAGE_SHIFT_4K);
1218 1823
@@ -1232,12 +1837,19 @@ static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb,
1232 TCE_PCI_SWINV_PAIR); 1837 TCE_PCI_SWINV_PAIR);
1233 } 1838 }
1234 iommu_init_table(tbl, phb->hose->node); 1839 iommu_init_table(tbl, phb->hose->node);
1235 iommu_register_group(tbl, phb->hose->global_number, pe->pe_number);
1236 1840
1237 if (pe->pdev) 1841 if (pe->flags & PNV_IODA_PE_DEV) {
1842 iommu_register_group(tbl, phb->hose->global_number,
1843 pe->pe_number);
1238 set_iommu_table_base_and_group(&pe->pdev->dev, tbl); 1844 set_iommu_table_base_and_group(&pe->pdev->dev, tbl);
1239 else 1845 } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) {
1846 iommu_register_group(tbl, phb->hose->global_number,
1847 pe->pe_number);
1240 pnv_ioda_setup_bus_dma(pe, pe->pbus, true); 1848 pnv_ioda_setup_bus_dma(pe, pe->pbus, true);
1849 } else if (pe->flags & PNV_IODA_PE_VF) {
1850 iommu_register_group(tbl, phb->hose->global_number,
1851 pe->pe_number);
1852 }
1241 1853
1242 return; 1854 return;
1243 fail: 1855 fail:
@@ -1250,8 +1862,7 @@ static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb,
1250 1862
1251static void pnv_pci_ioda2_set_bypass(struct iommu_table *tbl, bool enable) 1863static void pnv_pci_ioda2_set_bypass(struct iommu_table *tbl, bool enable)
1252{ 1864{
1253 struct pnv_ioda_pe *pe = container_of(tbl, struct pnv_ioda_pe, 1865 struct pnv_ioda_pe *pe = tbl->data;
1254 tce32_table);
1255 uint16_t window_id = (pe->pe_number << 1 ) + 1; 1866 uint16_t window_id = (pe->pe_number << 1 ) + 1;
1256 int64_t rc; 1867 int64_t rc;
1257 1868
@@ -1296,10 +1907,10 @@ static void pnv_pci_ioda2_setup_bypass_pe(struct pnv_phb *phb,
1296 pe->tce_bypass_base = 1ull << 59; 1907 pe->tce_bypass_base = 1ull << 59;
1297 1908
1298 /* Install set_bypass callback for VFIO */ 1909 /* Install set_bypass callback for VFIO */
1299 pe->tce32_table.set_bypass = pnv_pci_ioda2_set_bypass; 1910 pe->tce32_table->set_bypass = pnv_pci_ioda2_set_bypass;
1300 1911
1301 /* Enable bypass by default */ 1912 /* Enable bypass by default */
1302 pnv_pci_ioda2_set_bypass(&pe->tce32_table, true); 1913 pnv_pci_ioda2_set_bypass(pe->tce32_table, true);
1303} 1914}
1304 1915
1305static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, 1916static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
@@ -1347,7 +1958,7 @@ static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1347 } 1958 }
1348 1959
1349 /* Setup linux iommu table */ 1960 /* Setup linux iommu table */
1350 tbl = &pe->tce32_table; 1961 tbl = pe->tce32_table;
1351 pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, 0, 1962 pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, 0,
1352 IOMMU_PAGE_SHIFT_4K); 1963 IOMMU_PAGE_SHIFT_4K);
1353 1964
@@ -1365,12 +1976,19 @@ static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1365 tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); 1976 tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE);
1366 } 1977 }
1367 iommu_init_table(tbl, phb->hose->node); 1978 iommu_init_table(tbl, phb->hose->node);
1368 iommu_register_group(tbl, phb->hose->global_number, pe->pe_number);
1369 1979
1370 if (pe->pdev) 1980 if (pe->flags & PNV_IODA_PE_DEV) {
1981 iommu_register_group(tbl, phb->hose->global_number,
1982 pe->pe_number);
1371 set_iommu_table_base_and_group(&pe->pdev->dev, tbl); 1983 set_iommu_table_base_and_group(&pe->pdev->dev, tbl);
1372 else 1984 } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) {
1985 iommu_register_group(tbl, phb->hose->global_number,
1986 pe->pe_number);
1373 pnv_ioda_setup_bus_dma(pe, pe->pbus, true); 1987 pnv_ioda_setup_bus_dma(pe, pe->pbus, true);
1988 } else if (pe->flags & PNV_IODA_PE_VF) {
1989 iommu_register_group(tbl, phb->hose->global_number,
1990 pe->pe_number);
1991 }
1374 1992
1375 /* Also create a bypass window */ 1993 /* Also create a bypass window */
1376 if (!pnv_iommu_bypass_disabled) 1994 if (!pnv_iommu_bypass_disabled)
@@ -1731,6 +2349,73 @@ static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
1731static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } 2349static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { }
1732#endif /* CONFIG_PCI_MSI */ 2350#endif /* CONFIG_PCI_MSI */
1733 2351
2352#ifdef CONFIG_PCI_IOV
2353static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
2354{
2355 struct pci_controller *hose;
2356 struct pnv_phb *phb;
2357 struct resource *res;
2358 int i;
2359 resource_size_t size;
2360 struct pci_dn *pdn;
2361 int mul, total_vfs;
2362
2363 if (!pdev->is_physfn || pdev->is_added)
2364 return;
2365
2366 hose = pci_bus_to_host(pdev->bus);
2367 phb = hose->private_data;
2368
2369 pdn = pci_get_pdn(pdev);
2370 pdn->vfs_expanded = 0;
2371
2372 total_vfs = pci_sriov_get_totalvfs(pdev);
2373 pdn->m64_per_iov = 1;
2374 mul = phb->ioda.total_pe;
2375
2376 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2377 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2378 if (!res->flags || res->parent)
2379 continue;
2380 if (!pnv_pci_is_mem_pref_64(res->flags)) {
2381 dev_warn(&pdev->dev, " non M64 VF BAR%d: %pR\n",
2382 i, res);
2383 continue;
2384 }
2385
2386 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
2387
2388 /* bigger than 64M */
2389 if (size > (1 << 26)) {
2390 dev_info(&pdev->dev, "PowerNV: VF BAR%d: %pR IOV size is bigger than 64M, roundup power2\n",
2391 i, res);
2392 pdn->m64_per_iov = M64_PER_IOV;
2393 mul = roundup_pow_of_two(total_vfs);
2394 break;
2395 }
2396 }
2397
2398 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2399 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2400 if (!res->flags || res->parent)
2401 continue;
2402 if (!pnv_pci_is_mem_pref_64(res->flags)) {
2403 dev_warn(&pdev->dev, "Skipping expanding VF BAR%d: %pR\n",
2404 i, res);
2405 continue;
2406 }
2407
2408 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res);
2409 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
2410 res->end = res->start + size * mul - 1;
2411 dev_dbg(&pdev->dev, " %pR\n", res);
2412 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
2413 i, res, mul);
2414 }
2415 pdn->vfs_expanded = mul;
2416}
2417#endif /* CONFIG_PCI_IOV */
2418
1734/* 2419/*
1735 * This function is supposed to be called on basis of PE from top 2420 * This function is supposed to be called on basis of PE from top
1736 * to bottom style. So the the I/O or MMIO segment assigned to 2421 * to bottom style. So the the I/O or MMIO segment assigned to
@@ -1777,7 +2462,8 @@ static void pnv_ioda_setup_pe_seg(struct pci_controller *hose,
1777 region.start += phb->ioda.io_segsize; 2462 region.start += phb->ioda.io_segsize;
1778 index++; 2463 index++;
1779 } 2464 }
1780 } else if (res->flags & IORESOURCE_MEM) { 2465 } else if ((res->flags & IORESOURCE_MEM) &&
2466 !pnv_pci_is_mem_pref_64(res->flags)) {
1781 region.start = res->start - 2467 region.start = res->start -
1782 hose->mem_offset[0] - 2468 hose->mem_offset[0] -
1783 phb->ioda.m32_pci_base; 2469 phb->ioda.m32_pci_base;
@@ -1907,10 +2593,29 @@ static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
1907 return phb->ioda.io_segsize; 2593 return phb->ioda.io_segsize;
1908} 2594}
1909 2595
2596#ifdef CONFIG_PCI_IOV
2597static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
2598 int resno)
2599{
2600 struct pci_dn *pdn = pci_get_pdn(pdev);
2601 resource_size_t align, iov_align;
2602
2603 iov_align = resource_size(&pdev->resource[resno]);
2604 if (iov_align)
2605 return iov_align;
2606
2607 align = pci_iov_resource_size(pdev, resno);
2608 if (pdn->vfs_expanded)
2609 return pdn->vfs_expanded * align;
2610
2611 return align;
2612}
2613#endif /* CONFIG_PCI_IOV */
2614
1910/* Prevent enabling devices for which we couldn't properly 2615/* Prevent enabling devices for which we couldn't properly
1911 * assign a PE 2616 * assign a PE
1912 */ 2617 */
1913static int pnv_pci_enable_device_hook(struct pci_dev *dev) 2618static bool pnv_pci_enable_device_hook(struct pci_dev *dev)
1914{ 2619{
1915 struct pci_controller *hose = pci_bus_to_host(dev->bus); 2620 struct pci_controller *hose = pci_bus_to_host(dev->bus);
1916 struct pnv_phb *phb = hose->private_data; 2621 struct pnv_phb *phb = hose->private_data;
@@ -1922,13 +2627,13 @@ static int pnv_pci_enable_device_hook(struct pci_dev *dev)
1922 * PEs isn't ready. 2627 * PEs isn't ready.
1923 */ 2628 */
1924 if (!phb->initialized) 2629 if (!phb->initialized)
1925 return 0; 2630 return true;
1926 2631
1927 pdn = pci_get_pdn(dev); 2632 pdn = pci_get_pdn(dev);
1928 if (!pdn || pdn->pe_number == IODA_INVALID_PE) 2633 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1929 return -EINVAL; 2634 return false;
1930 2635
1931 return 0; 2636 return true;
1932} 2637}
1933 2638
1934static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus, 2639static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus,
@@ -1988,9 +2693,11 @@ static void __init pnv_pci_init_ioda_phb(struct device_node *np,
1988 hose->last_busno = 0xff; 2693 hose->last_busno = 0xff;
1989 } 2694 }
1990 hose->private_data = phb; 2695 hose->private_data = phb;
2696 hose->controller_ops = pnv_pci_controller_ops;
1991 phb->hub_id = hub_id; 2697 phb->hub_id = hub_id;
1992 phb->opal_id = phb_id; 2698 phb->opal_id = phb_id;
1993 phb->type = ioda_type; 2699 phb->type = ioda_type;
2700 mutex_init(&phb->ioda.pe_alloc_mutex);
1994 2701
1995 /* Detect specific models for error handling */ 2702 /* Detect specific models for error handling */
1996 if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) 2703 if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
@@ -2050,6 +2757,7 @@ static void __init pnv_pci_init_ioda_phb(struct device_node *np,
2050 2757
2051 INIT_LIST_HEAD(&phb->ioda.pe_dma_list); 2758 INIT_LIST_HEAD(&phb->ioda.pe_dma_list);
2052 INIT_LIST_HEAD(&phb->ioda.pe_list); 2759 INIT_LIST_HEAD(&phb->ioda.pe_list);
2760 mutex_init(&phb->ioda.pe_list_mutex);
2053 2761
2054 /* Calculate how many 32-bit TCE segments we have */ 2762 /* Calculate how many 32-bit TCE segments we have */
2055 phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28; 2763 phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28;
@@ -2078,9 +2786,6 @@ static void __init pnv_pci_init_ioda_phb(struct device_node *np,
2078 phb->get_pe_state = pnv_ioda_get_pe_state; 2786 phb->get_pe_state = pnv_ioda_get_pe_state;
2079 phb->freeze_pe = pnv_ioda_freeze_pe; 2787 phb->freeze_pe = pnv_ioda_freeze_pe;
2080 phb->unfreeze_pe = pnv_ioda_unfreeze_pe; 2788 phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
2081#ifdef CONFIG_EEH
2082 phb->eeh_ops = &ioda_eeh_ops;
2083#endif
2084 2789
2085 /* Setup RID -> PE mapping function */ 2790 /* Setup RID -> PE mapping function */
2086 phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe; 2791 phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe;
@@ -2104,9 +2809,15 @@ static void __init pnv_pci_init_ioda_phb(struct device_node *np,
2104 * the child P2P bridges) can form individual PE. 2809 * the child P2P bridges) can form individual PE.
2105 */ 2810 */
2106 ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; 2811 ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
2107 ppc_md.pcibios_enable_device_hook = pnv_pci_enable_device_hook; 2812 pnv_pci_controller_ops.enable_device_hook = pnv_pci_enable_device_hook;
2108 ppc_md.pcibios_window_alignment = pnv_pci_window_alignment; 2813 pnv_pci_controller_ops.window_alignment = pnv_pci_window_alignment;
2109 ppc_md.pcibios_reset_secondary_bus = pnv_pci_reset_secondary_bus; 2814 pnv_pci_controller_ops.reset_secondary_bus = pnv_pci_reset_secondary_bus;
2815
2816#ifdef CONFIG_PCI_IOV
2817 ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources;
2818 ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
2819#endif
2820
2110 pci_add_flags(PCI_REASSIGN_ALL_RSRC); 2821 pci_add_flags(PCI_REASSIGN_ALL_RSRC);
2111 2822
2112 /* Reset IODA tables to a clean state */ 2823 /* Reset IODA tables to a clean state */
@@ -2121,8 +2832,8 @@ static void __init pnv_pci_init_ioda_phb(struct device_node *np,
2121 */ 2832 */
2122 if (is_kdump_kernel()) { 2833 if (is_kdump_kernel()) {
2123 pr_info(" Issue PHB reset ...\n"); 2834 pr_info(" Issue PHB reset ...\n");
2124 ioda_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); 2835 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
2125 ioda_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); 2836 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
2126 } 2837 }
2127 2838
2128 /* Remove M64 resource if we can't configure it successfully */ 2839 /* Remove M64 resource if we can't configure it successfully */
diff --git a/arch/powerpc/platforms/powernv/pci-p5ioc2.c b/arch/powerpc/platforms/powernv/pci-p5ioc2.c
index 6ef6d4d8e7e2..4729ca793813 100644
--- a/arch/powerpc/platforms/powernv/pci-p5ioc2.c
+++ b/arch/powerpc/platforms/powernv/pci-p5ioc2.c
@@ -133,6 +133,7 @@ static void __init pnv_pci_init_p5ioc2_phb(struct device_node *np, u64 hub_id,
133 phb->hose->first_busno = 0; 133 phb->hose->first_busno = 0;
134 phb->hose->last_busno = 0xff; 134 phb->hose->last_busno = 0xff;
135 phb->hose->private_data = phb; 135 phb->hose->private_data = phb;
136 phb->hose->controller_ops = pnv_pci_controller_ops;
136 phb->hub_id = hub_id; 137 phb->hub_id = hub_id;
137 phb->opal_id = phb_id; 138 phb->opal_id = phb_id;
138 phb->type = PNV_PHB_P5IOC2; 139 phb->type = PNV_PHB_P5IOC2;
diff --git a/arch/powerpc/platforms/powernv/pci.c b/arch/powerpc/platforms/powernv/pci.c
index 54323d6b5166..bca2aeb6e4b6 100644
--- a/arch/powerpc/platforms/powernv/pci.c
+++ b/arch/powerpc/platforms/powernv/pci.c
@@ -366,9 +366,9 @@ static void pnv_pci_handle_eeh_config(struct pnv_phb *phb, u32 pe_no)
366 spin_unlock_irqrestore(&phb->lock, flags); 366 spin_unlock_irqrestore(&phb->lock, flags);
367} 367}
368 368
369static void pnv_pci_config_check_eeh(struct pnv_phb *phb, 369static void pnv_pci_config_check_eeh(struct pci_dn *pdn)
370 struct device_node *dn)
371{ 370{
371 struct pnv_phb *phb = pdn->phb->private_data;
372 u8 fstate; 372 u8 fstate;
373 __be16 pcierr; 373 __be16 pcierr;
374 int pe_no; 374 int pe_no;
@@ -379,7 +379,7 @@ static void pnv_pci_config_check_eeh(struct pnv_phb *phb,
379 * setup that yet. So all ER errors should be mapped to 379 * setup that yet. So all ER errors should be mapped to
380 * reserved PE. 380 * reserved PE.
381 */ 381 */
382 pe_no = PCI_DN(dn)->pe_number; 382 pe_no = pdn->pe_number;
383 if (pe_no == IODA_INVALID_PE) { 383 if (pe_no == IODA_INVALID_PE) {
384 if (phb->type == PNV_PHB_P5IOC2) 384 if (phb->type == PNV_PHB_P5IOC2)
385 pe_no = 0; 385 pe_no = 0;
@@ -407,8 +407,7 @@ static void pnv_pci_config_check_eeh(struct pnv_phb *phb,
407 } 407 }
408 408
409 cfg_dbg(" -> EEH check, bdfn=%04x PE#%d fstate=%x\n", 409 cfg_dbg(" -> EEH check, bdfn=%04x PE#%d fstate=%x\n",
410 (PCI_DN(dn)->busno << 8) | (PCI_DN(dn)->devfn), 410 (pdn->busno << 8) | (pdn->devfn), pe_no, fstate);
411 pe_no, fstate);
412 411
413 /* Clear the frozen state if applicable */ 412 /* Clear the frozen state if applicable */
414 if (fstate == OPAL_EEH_STOPPED_MMIO_FREEZE || 413 if (fstate == OPAL_EEH_STOPPED_MMIO_FREEZE ||
@@ -425,10 +424,9 @@ static void pnv_pci_config_check_eeh(struct pnv_phb *phb,
425 } 424 }
426} 425}
427 426
428int pnv_pci_cfg_read(struct device_node *dn, 427int pnv_pci_cfg_read(struct pci_dn *pdn,
429 int where, int size, u32 *val) 428 int where, int size, u32 *val)
430{ 429{
431 struct pci_dn *pdn = PCI_DN(dn);
432 struct pnv_phb *phb = pdn->phb->private_data; 430 struct pnv_phb *phb = pdn->phb->private_data;
433 u32 bdfn = (pdn->busno << 8) | pdn->devfn; 431 u32 bdfn = (pdn->busno << 8) | pdn->devfn;
434 s64 rc; 432 s64 rc;
@@ -462,10 +460,9 @@ int pnv_pci_cfg_read(struct device_node *dn,
462 return PCIBIOS_SUCCESSFUL; 460 return PCIBIOS_SUCCESSFUL;
463} 461}
464 462
465int pnv_pci_cfg_write(struct device_node *dn, 463int pnv_pci_cfg_write(struct pci_dn *pdn,
466 int where, int size, u32 val) 464 int where, int size, u32 val)
467{ 465{
468 struct pci_dn *pdn = PCI_DN(dn);
469 struct pnv_phb *phb = pdn->phb->private_data; 466 struct pnv_phb *phb = pdn->phb->private_data;
470 u32 bdfn = (pdn->busno << 8) | pdn->devfn; 467 u32 bdfn = (pdn->busno << 8) | pdn->devfn;
471 468
@@ -489,18 +486,17 @@ int pnv_pci_cfg_write(struct device_node *dn,
489} 486}
490 487
491#if CONFIG_EEH 488#if CONFIG_EEH
492static bool pnv_pci_cfg_check(struct pci_controller *hose, 489static bool pnv_pci_cfg_check(struct pci_dn *pdn)
493 struct device_node *dn)
494{ 490{
495 struct eeh_dev *edev = NULL; 491 struct eeh_dev *edev = NULL;
496 struct pnv_phb *phb = hose->private_data; 492 struct pnv_phb *phb = pdn->phb->private_data;
497 493
498 /* EEH not enabled ? */ 494 /* EEH not enabled ? */
499 if (!(phb->flags & PNV_PHB_FLAG_EEH)) 495 if (!(phb->flags & PNV_PHB_FLAG_EEH))
500 return true; 496 return true;
501 497
502 /* PE reset or device removed ? */ 498 /* PE reset or device removed ? */
503 edev = of_node_to_eeh_dev(dn); 499 edev = pdn->edev;
504 if (edev) { 500 if (edev) {
505 if (edev->pe && 501 if (edev->pe &&
506 (edev->pe->state & EEH_PE_CFG_BLOCKED)) 502 (edev->pe->state & EEH_PE_CFG_BLOCKED))
@@ -513,8 +509,7 @@ static bool pnv_pci_cfg_check(struct pci_controller *hose,
513 return true; 509 return true;
514} 510}
515#else 511#else
516static inline pnv_pci_cfg_check(struct pci_controller *hose, 512static inline pnv_pci_cfg_check(struct pci_dn *pdn)
517 struct device_node *dn)
518{ 513{
519 return true; 514 return true;
520} 515}
@@ -524,32 +519,26 @@ static int pnv_pci_read_config(struct pci_bus *bus,
524 unsigned int devfn, 519 unsigned int devfn,
525 int where, int size, u32 *val) 520 int where, int size, u32 *val)
526{ 521{
527 struct device_node *dn, *busdn = pci_bus_to_OF_node(bus);
528 struct pci_dn *pdn; 522 struct pci_dn *pdn;
529 struct pnv_phb *phb; 523 struct pnv_phb *phb;
530 bool found = false;
531 int ret; 524 int ret;
532 525
533 *val = 0xFFFFFFFF; 526 *val = 0xFFFFFFFF;
534 for (dn = busdn->child; dn; dn = dn->sibling) { 527 pdn = pci_get_pdn_by_devfn(bus, devfn);
535 pdn = PCI_DN(dn); 528 if (!pdn)
536 if (pdn && pdn->devfn == devfn) { 529 return PCIBIOS_DEVICE_NOT_FOUND;
537 phb = pdn->phb->private_data;
538 found = true;
539 break;
540 }
541 }
542 530
543 if (!found || !pnv_pci_cfg_check(pdn->phb, dn)) 531 if (!pnv_pci_cfg_check(pdn))
544 return PCIBIOS_DEVICE_NOT_FOUND; 532 return PCIBIOS_DEVICE_NOT_FOUND;
545 533
546 ret = pnv_pci_cfg_read(dn, where, size, val); 534 ret = pnv_pci_cfg_read(pdn, where, size, val);
547 if (phb->flags & PNV_PHB_FLAG_EEH) { 535 phb = pdn->phb->private_data;
536 if (phb->flags & PNV_PHB_FLAG_EEH && pdn->edev) {
548 if (*val == EEH_IO_ERROR_VALUE(size) && 537 if (*val == EEH_IO_ERROR_VALUE(size) &&
549 eeh_dev_check_failure(of_node_to_eeh_dev(dn))) 538 eeh_dev_check_failure(pdn->edev))
550 return PCIBIOS_DEVICE_NOT_FOUND; 539 return PCIBIOS_DEVICE_NOT_FOUND;
551 } else { 540 } else {
552 pnv_pci_config_check_eeh(phb, dn); 541 pnv_pci_config_check_eeh(pdn);
553 } 542 }
554 543
555 return ret; 544 return ret;
@@ -559,27 +548,21 @@ static int pnv_pci_write_config(struct pci_bus *bus,
559 unsigned int devfn, 548 unsigned int devfn,
560 int where, int size, u32 val) 549 int where, int size, u32 val)
561{ 550{
562 struct device_node *dn, *busdn = pci_bus_to_OF_node(bus);
563 struct pci_dn *pdn; 551 struct pci_dn *pdn;
564 struct pnv_phb *phb; 552 struct pnv_phb *phb;
565 bool found = false;
566 int ret; 553 int ret;
567 554
568 for (dn = busdn->child; dn; dn = dn->sibling) { 555 pdn = pci_get_pdn_by_devfn(bus, devfn);
569 pdn = PCI_DN(dn); 556 if (!pdn)
570 if (pdn && pdn->devfn == devfn) { 557 return PCIBIOS_DEVICE_NOT_FOUND;
571 phb = pdn->phb->private_data;
572 found = true;
573 break;
574 }
575 }
576 558
577 if (!found || !pnv_pci_cfg_check(pdn->phb, dn)) 559 if (!pnv_pci_cfg_check(pdn))
578 return PCIBIOS_DEVICE_NOT_FOUND; 560 return PCIBIOS_DEVICE_NOT_FOUND;
579 561
580 ret = pnv_pci_cfg_write(dn, where, size, val); 562 ret = pnv_pci_cfg_write(pdn, where, size, val);
563 phb = pdn->phb->private_data;
581 if (!(phb->flags & PNV_PHB_FLAG_EEH)) 564 if (!(phb->flags & PNV_PHB_FLAG_EEH))
582 pnv_pci_config_check_eeh(phb, dn); 565 pnv_pci_config_check_eeh(pdn);
583 566
584 return ret; 567 return ret;
585} 568}
@@ -679,66 +662,31 @@ void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
679 tbl->it_type = TCE_PCI; 662 tbl->it_type = TCE_PCI;
680} 663}
681 664
682static struct iommu_table *pnv_pci_setup_bml_iommu(struct pci_controller *hose)
683{
684 struct iommu_table *tbl;
685 const __be64 *basep, *swinvp;
686 const __be32 *sizep;
687
688 basep = of_get_property(hose->dn, "linux,tce-base", NULL);
689 sizep = of_get_property(hose->dn, "linux,tce-size", NULL);
690 if (basep == NULL || sizep == NULL) {
691 pr_err("PCI: %s has missing tce entries !\n",
692 hose->dn->full_name);
693 return NULL;
694 }
695 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, hose->node);
696 if (WARN_ON(!tbl))
697 return NULL;
698 pnv_pci_setup_iommu_table(tbl, __va(be64_to_cpup(basep)),
699 be32_to_cpup(sizep), 0, IOMMU_PAGE_SHIFT_4K);
700 iommu_init_table(tbl, hose->node);
701 iommu_register_group(tbl, pci_domain_nr(hose->bus), 0);
702
703 /* Deal with SW invalidated TCEs when needed (BML way) */
704 swinvp = of_get_property(hose->dn, "linux,tce-sw-invalidate-info",
705 NULL);
706 if (swinvp) {
707 tbl->it_busno = be64_to_cpu(swinvp[1]);
708 tbl->it_index = (unsigned long)ioremap(be64_to_cpup(swinvp), 8);
709 tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE;
710 }
711 return tbl;
712}
713
714static void pnv_pci_dma_fallback_setup(struct pci_controller *hose,
715 struct pci_dev *pdev)
716{
717 struct device_node *np = pci_bus_to_OF_node(hose->bus);
718 struct pci_dn *pdn;
719
720 if (np == NULL)
721 return;
722 pdn = PCI_DN(np);
723 if (!pdn->iommu_table)
724 pdn->iommu_table = pnv_pci_setup_bml_iommu(hose);
725 if (!pdn->iommu_table)
726 return;
727 set_iommu_table_base_and_group(&pdev->dev, pdn->iommu_table);
728}
729
730static void pnv_pci_dma_dev_setup(struct pci_dev *pdev) 665static void pnv_pci_dma_dev_setup(struct pci_dev *pdev)
731{ 666{
732 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 667 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
733 struct pnv_phb *phb = hose->private_data; 668 struct pnv_phb *phb = hose->private_data;
669#ifdef CONFIG_PCI_IOV
670 struct pnv_ioda_pe *pe;
671 struct pci_dn *pdn;
672
673 /* Fix the VF pdn PE number */
674 if (pdev->is_virtfn) {
675 pdn = pci_get_pdn(pdev);
676 WARN_ON(pdn->pe_number != IODA_INVALID_PE);
677 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
678 if (pe->rid == ((pdev->bus->number << 8) |
679 (pdev->devfn & 0xff))) {
680 pdn->pe_number = pe->pe_number;
681 pe->pdev = pdev;
682 break;
683 }
684 }
685 }
686#endif /* CONFIG_PCI_IOV */
734 687
735 /* If we have no phb structure, try to setup a fallback based on
736 * the device-tree (RTAS PCI for example)
737 */
738 if (phb && phb->dma_dev_setup) 688 if (phb && phb->dma_dev_setup)
739 phb->dma_dev_setup(phb, pdev); 689 phb->dma_dev_setup(phb, pdev);
740 else
741 pnv_pci_dma_fallback_setup(hose, pdev);
742} 690}
743 691
744int pnv_pci_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) 692int pnv_pci_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
@@ -784,44 +732,36 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IBM, 0x3b9, pnv_p7ioc_rc_quirk);
784void __init pnv_pci_init(void) 732void __init pnv_pci_init(void)
785{ 733{
786 struct device_node *np; 734 struct device_node *np;
735 bool found_ioda = false;
787 736
788 pci_add_flags(PCI_CAN_SKIP_ISA_ALIGN); 737 pci_add_flags(PCI_CAN_SKIP_ISA_ALIGN);
789 738
790 /* OPAL absent, try POPAL first then RTAS detection of PHBs */ 739 /* If we don't have OPAL, eg. in sim, just skip PCI probe */
791 if (!firmware_has_feature(FW_FEATURE_OPAL)) { 740 if (!firmware_has_feature(FW_FEATURE_OPAL))
792#ifdef CONFIG_PPC_POWERNV_RTAS 741 return;
793 init_pci_config_tokens();
794 find_and_init_phbs();
795#endif /* CONFIG_PPC_POWERNV_RTAS */
796 }
797 /* OPAL is here, do our normal stuff */
798 else {
799 int found_ioda = 0;
800 742
801 /* Look for IODA IO-Hubs. We don't support mixing IODA 743 /* Look for IODA IO-Hubs. We don't support mixing IODA
802 * and p5ioc2 due to the need to change some global 744 * and p5ioc2 due to the need to change some global
803 * probing flags 745 * probing flags
804 */ 746 */
805 for_each_compatible_node(np, NULL, "ibm,ioda-hub") { 747 for_each_compatible_node(np, NULL, "ibm,ioda-hub") {
806 pnv_pci_init_ioda_hub(np); 748 pnv_pci_init_ioda_hub(np);
807 found_ioda = 1; 749 found_ioda = true;
808 } 750 }
809 751
810 /* Look for p5ioc2 IO-Hubs */ 752 /* Look for p5ioc2 IO-Hubs */
811 if (!found_ioda) 753 if (!found_ioda)
812 for_each_compatible_node(np, NULL, "ibm,p5ioc2") 754 for_each_compatible_node(np, NULL, "ibm,p5ioc2")
813 pnv_pci_init_p5ioc2_hub(np); 755 pnv_pci_init_p5ioc2_hub(np);
814 756
815 /* Look for ioda2 built-in PHB3's */ 757 /* Look for ioda2 built-in PHB3's */
816 for_each_compatible_node(np, NULL, "ibm,ioda2-phb") 758 for_each_compatible_node(np, NULL, "ibm,ioda2-phb")
817 pnv_pci_init_ioda2_phb(np); 759 pnv_pci_init_ioda2_phb(np);
818 }
819 760
820 /* Setup the linkage between OF nodes and PHBs */ 761 /* Setup the linkage between OF nodes and PHBs */
821 pci_devs_phb_init(); 762 pci_devs_phb_init();
822 763
823 /* Configure IOMMU DMA hooks */ 764 /* Configure IOMMU DMA hooks */
824 ppc_md.pci_dma_dev_setup = pnv_pci_dma_dev_setup;
825 ppc_md.tce_build = pnv_tce_build_vm; 765 ppc_md.tce_build = pnv_tce_build_vm;
826 ppc_md.tce_free = pnv_tce_free_vm; 766 ppc_md.tce_free = pnv_tce_free_vm;
827 ppc_md.tce_build_rm = pnv_tce_build_rm; 767 ppc_md.tce_build_rm = pnv_tce_build_rm;
@@ -837,3 +777,7 @@ void __init pnv_pci_init(void)
837} 777}
838 778
839machine_subsys_initcall_sync(powernv, tce_iommu_bus_notifier_init); 779machine_subsys_initcall_sync(powernv, tce_iommu_bus_notifier_init);
780
781struct pci_controller_ops pnv_pci_controller_ops = {
782 .dma_dev_setup = pnv_pci_dma_dev_setup,
783};
diff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h
index 6c02ff8dd69f..070ee888fc95 100644
--- a/arch/powerpc/platforms/powernv/pci.h
+++ b/arch/powerpc/platforms/powernv/pci.h
@@ -23,6 +23,7 @@ enum pnv_phb_model {
23#define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */ 23#define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */
24#define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */ 24#define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */
25#define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */ 25#define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */
26#define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */
26 27
27/* Data associated with a PE, including IOMMU tracking etc.. */ 28/* Data associated with a PE, including IOMMU tracking etc.. */
28struct pnv_phb; 29struct pnv_phb;
@@ -34,6 +35,9 @@ struct pnv_ioda_pe {
34 * entire bus (& children). In the former case, pdev 35 * entire bus (& children). In the former case, pdev
35 * is populated, in the later case, pbus is. 36 * is populated, in the later case, pbus is.
36 */ 37 */
38#ifdef CONFIG_PCI_IOV
39 struct pci_dev *parent_dev;
40#endif
37 struct pci_dev *pdev; 41 struct pci_dev *pdev;
38 struct pci_bus *pbus; 42 struct pci_bus *pbus;
39 43
@@ -53,7 +57,7 @@ struct pnv_ioda_pe {
53 /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */ 57 /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
54 int tce32_seg; 58 int tce32_seg;
55 int tce32_segcount; 59 int tce32_segcount;
56 struct iommu_table tce32_table; 60 struct iommu_table *tce32_table;
57 phys_addr_t tce_inval_reg_phys; 61 phys_addr_t tce_inval_reg_phys;
58 62
59 /* 64-bit TCE bypass region */ 63 /* 64-bit TCE bypass region */
@@ -75,22 +79,6 @@ struct pnv_ioda_pe {
75 struct list_head list; 79 struct list_head list;
76}; 80};
77 81
78/* IOC dependent EEH operations */
79#ifdef CONFIG_EEH
80struct pnv_eeh_ops {
81 int (*post_init)(struct pci_controller *hose);
82 int (*set_option)(struct eeh_pe *pe, int option);
83 int (*get_state)(struct eeh_pe *pe);
84 int (*reset)(struct eeh_pe *pe, int option);
85 int (*get_log)(struct eeh_pe *pe, int severity,
86 char *drv_log, unsigned long len);
87 int (*configure_bridge)(struct eeh_pe *pe);
88 int (*err_inject)(struct eeh_pe *pe, int type, int func,
89 unsigned long addr, unsigned long mask);
90 int (*next_error)(struct eeh_pe **pe);
91};
92#endif /* CONFIG_EEH */
93
94#define PNV_PHB_FLAG_EEH (1 << 0) 82#define PNV_PHB_FLAG_EEH (1 << 0)
95 83
96struct pnv_phb { 84struct pnv_phb {
@@ -104,10 +92,6 @@ struct pnv_phb {
104 int initialized; 92 int initialized;
105 spinlock_t lock; 93 spinlock_t lock;
106 94
107#ifdef CONFIG_EEH
108 struct pnv_eeh_ops *eeh_ops;
109#endif
110
111#ifdef CONFIG_DEBUG_FS 95#ifdef CONFIG_DEBUG_FS
112 int has_dbgfs; 96 int has_dbgfs;
113 struct dentry *dbgfs; 97 struct dentry *dbgfs;
@@ -165,6 +149,8 @@ struct pnv_phb {
165 149
166 /* PE allocation bitmap */ 150 /* PE allocation bitmap */
167 unsigned long *pe_alloc; 151 unsigned long *pe_alloc;
152 /* PE allocation mutex */
153 struct mutex pe_alloc_mutex;
168 154
169 /* M32 & IO segment maps */ 155 /* M32 & IO segment maps */
170 unsigned int *m32_segmap; 156 unsigned int *m32_segmap;
@@ -179,6 +165,7 @@ struct pnv_phb {
179 * on the sequence of creation 165 * on the sequence of creation
180 */ 166 */
181 struct list_head pe_list; 167 struct list_head pe_list;
168 struct mutex pe_list_mutex;
182 169
183 /* Reverse map of PEs, will have to extend if 170 /* Reverse map of PEs, will have to extend if
184 * we are to support more than 256 PEs, indexed 171 * we are to support more than 256 PEs, indexed
@@ -213,15 +200,12 @@ struct pnv_phb {
213}; 200};
214 201
215extern struct pci_ops pnv_pci_ops; 202extern struct pci_ops pnv_pci_ops;
216#ifdef CONFIG_EEH
217extern struct pnv_eeh_ops ioda_eeh_ops;
218#endif
219 203
220void pnv_pci_dump_phb_diag_data(struct pci_controller *hose, 204void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
221 unsigned char *log_buff); 205 unsigned char *log_buff);
222int pnv_pci_cfg_read(struct device_node *dn, 206int pnv_pci_cfg_read(struct pci_dn *pdn,
223 int where, int size, u32 *val); 207 int where, int size, u32 *val);
224int pnv_pci_cfg_write(struct device_node *dn, 208int pnv_pci_cfg_write(struct pci_dn *pdn,
225 int where, int size, u32 val); 209 int where, int size, u32 val);
226extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl, 210extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
227 void *tce_mem, u64 tce_size, 211 void *tce_mem, u64 tce_size,
@@ -232,6 +216,6 @@ extern void pnv_pci_init_ioda2_phb(struct device_node *np);
232extern void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl, 216extern void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl,
233 __be64 *startp, __be64 *endp, bool rm); 217 __be64 *startp, __be64 *endp, bool rm);
234extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev); 218extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);
235extern int ioda_eeh_phb_reset(struct pci_controller *hose, int option); 219extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option);
236 220
237#endif /* __POWERNV_PCI_H */ 221#endif /* __POWERNV_PCI_H */
diff --git a/arch/powerpc/platforms/powernv/powernv.h b/arch/powerpc/platforms/powernv/powernv.h
index 604c48e7879a..826d2c9bea56 100644
--- a/arch/powerpc/platforms/powernv/powernv.h
+++ b/arch/powerpc/platforms/powernv/powernv.h
@@ -29,6 +29,8 @@ static inline u64 pnv_pci_dma_get_required_mask(struct pci_dev *pdev)
29} 29}
30#endif 30#endif
31 31
32extern struct pci_controller_ops pnv_pci_controller_ops;
33
32extern u32 pnv_get_supported_cpuidle_states(void); 34extern u32 pnv_get_supported_cpuidle_states(void);
33 35
34extern void pnv_lpc_init(void); 36extern void pnv_lpc_init(void);
diff --git a/arch/powerpc/platforms/powernv/setup.c b/arch/powerpc/platforms/powernv/setup.c
index d2de7d5d7574..16fdcb23f4c3 100644
--- a/arch/powerpc/platforms/powernv/setup.c
+++ b/arch/powerpc/platforms/powernv/setup.c
@@ -32,7 +32,6 @@
32#include <asm/machdep.h> 32#include <asm/machdep.h>
33#include <asm/firmware.h> 33#include <asm/firmware.h>
34#include <asm/xics.h> 34#include <asm/xics.h>
35#include <asm/rtas.h>
36#include <asm/opal.h> 35#include <asm/opal.h>
37#include <asm/kexec.h> 36#include <asm/kexec.h>
38#include <asm/smp.h> 37#include <asm/smp.h>
@@ -278,20 +277,6 @@ static void __init pnv_setup_machdep_opal(void)
278 ppc_md.handle_hmi_exception = opal_handle_hmi_exception; 277 ppc_md.handle_hmi_exception = opal_handle_hmi_exception;
279} 278}
280 279
281#ifdef CONFIG_PPC_POWERNV_RTAS
282static void __init pnv_setup_machdep_rtas(void)
283{
284 if (rtas_token("get-time-of-day") != RTAS_UNKNOWN_SERVICE) {
285 ppc_md.get_boot_time = rtas_get_boot_time;
286 ppc_md.get_rtc_time = rtas_get_rtc_time;
287 ppc_md.set_rtc_time = rtas_set_rtc_time;
288 }
289 ppc_md.restart = rtas_restart;
290 pm_power_off = rtas_power_off;
291 ppc_md.halt = rtas_halt;
292}
293#endif /* CONFIG_PPC_POWERNV_RTAS */
294
295static u32 supported_cpuidle_states; 280static u32 supported_cpuidle_states;
296 281
297int pnv_save_sprs_for_winkle(void) 282int pnv_save_sprs_for_winkle(void)
@@ -409,37 +394,39 @@ static int __init pnv_init_idle_states(void)
409{ 394{
410 struct device_node *power_mgt; 395 struct device_node *power_mgt;
411 int dt_idle_states; 396 int dt_idle_states;
412 const __be32 *idle_state_flags; 397 u32 *flags;
413 u32 len_flags, flags;
414 int i; 398 int i;
415 399
416 supported_cpuidle_states = 0; 400 supported_cpuidle_states = 0;
417 401
418 if (cpuidle_disable != IDLE_NO_OVERRIDE) 402 if (cpuidle_disable != IDLE_NO_OVERRIDE)
419 return 0; 403 goto out;
420 404
421 if (!firmware_has_feature(FW_FEATURE_OPALv3)) 405 if (!firmware_has_feature(FW_FEATURE_OPALv3))
422 return 0; 406 goto out;
423 407
424 power_mgt = of_find_node_by_path("/ibm,opal/power-mgt"); 408 power_mgt = of_find_node_by_path("/ibm,opal/power-mgt");
425 if (!power_mgt) { 409 if (!power_mgt) {
426 pr_warn("opal: PowerMgmt Node not found\n"); 410 pr_warn("opal: PowerMgmt Node not found\n");
427 return 0; 411 goto out;
412 }
413 dt_idle_states = of_property_count_u32_elems(power_mgt,
414 "ibm,cpu-idle-state-flags");
415 if (dt_idle_states < 0) {
416 pr_warn("cpuidle-powernv: no idle states found in the DT\n");
417 goto out;
428 } 418 }
429 419
430 idle_state_flags = of_get_property(power_mgt, 420 flags = kzalloc(sizeof(*flags) * dt_idle_states, GFP_KERNEL);
431 "ibm,cpu-idle-state-flags", &len_flags); 421 if (of_property_read_u32_array(power_mgt,
432 if (!idle_state_flags) { 422 "ibm,cpu-idle-state-flags", flags, dt_idle_states)) {
433 pr_warn("DT-PowerMgmt: missing ibm,cpu-idle-state-flags\n"); 423 pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-flags in DT\n");
434 return 0; 424 goto out_free;
435 } 425 }
436 426
437 dt_idle_states = len_flags / sizeof(u32); 427 for (i = 0; i < dt_idle_states; i++)
428 supported_cpuidle_states |= flags[i];
438 429
439 for (i = 0; i < dt_idle_states; i++) {
440 flags = be32_to_cpu(idle_state_flags[i]);
441 supported_cpuidle_states |= flags;
442 }
443 if (!(supported_cpuidle_states & OPAL_PM_SLEEP_ENABLED_ER1)) { 430 if (!(supported_cpuidle_states & OPAL_PM_SLEEP_ENABLED_ER1)) {
444 patch_instruction( 431 patch_instruction(
445 (unsigned int *)pnv_fastsleep_workaround_at_entry, 432 (unsigned int *)pnv_fastsleep_workaround_at_entry,
@@ -449,6 +436,9 @@ static int __init pnv_init_idle_states(void)
449 PPC_INST_NOP); 436 PPC_INST_NOP);
450 } 437 }
451 pnv_alloc_idle_core_states(); 438 pnv_alloc_idle_core_states();
439out_free:
440 kfree(flags);
441out:
452 return 0; 442 return 0;
453} 443}
454 444
@@ -465,10 +455,6 @@ static int __init pnv_probe(void)
465 455
466 if (firmware_has_feature(FW_FEATURE_OPAL)) 456 if (firmware_has_feature(FW_FEATURE_OPAL))
467 pnv_setup_machdep_opal(); 457 pnv_setup_machdep_opal();
468#ifdef CONFIG_PPC_POWERNV_RTAS
469 else if (rtas.base)
470 pnv_setup_machdep_rtas();
471#endif /* CONFIG_PPC_POWERNV_RTAS */
472 458
473 pr_debug("PowerNV detected !\n"); 459 pr_debug("PowerNV detected !\n");
474 460
diff --git a/arch/powerpc/platforms/powernv/smp.c b/arch/powerpc/platforms/powernv/smp.c
index 38a45088f633..8f70ba681a78 100644
--- a/arch/powerpc/platforms/powernv/smp.c
+++ b/arch/powerpc/platforms/powernv/smp.c
@@ -25,7 +25,6 @@
25#include <asm/machdep.h> 25#include <asm/machdep.h>
26#include <asm/cputable.h> 26#include <asm/cputable.h>
27#include <asm/firmware.h> 27#include <asm/firmware.h>
28#include <asm/rtas.h>
29#include <asm/vdso_datapage.h> 28#include <asm/vdso_datapage.h>
30#include <asm/cputhreads.h> 29#include <asm/cputhreads.h>
31#include <asm/xics.h> 30#include <asm/xics.h>
@@ -251,18 +250,6 @@ void __init pnv_smp_init(void)
251{ 250{
252 smp_ops = &pnv_smp_ops; 251 smp_ops = &pnv_smp_ops;
253 252
254 /* XXX We don't yet have a proper entry point from HAL, for
255 * now we rely on kexec-style entry from BML
256 */
257
258#ifdef CONFIG_PPC_RTAS
259 /* Non-lpar has additional take/give timebase */
260 if (rtas_token("freeze-time-base") != RTAS_UNKNOWN_SERVICE) {
261 smp_ops->give_timebase = rtas_give_timebase;
262 smp_ops->take_timebase = rtas_take_timebase;
263 }
264#endif /* CONFIG_PPC_RTAS */
265
266#ifdef CONFIG_HOTPLUG_CPU 253#ifdef CONFIG_HOTPLUG_CPU
267 ppc_md.cpu_die = pnv_smp_cpu_kill_self; 254 ppc_md.cpu_die = pnv_smp_cpu_kill_self;
268#endif 255#endif
diff --git a/arch/powerpc/platforms/ps3/smp.c b/arch/powerpc/platforms/ps3/smp.c
index b358bec6c8cb..3c7707af3384 100644
--- a/arch/powerpc/platforms/ps3/smp.c
+++ b/arch/powerpc/platforms/ps3/smp.c
@@ -57,7 +57,7 @@ static void ps3_smp_message_pass(int cpu, int msg)
57 " (%d)\n", __func__, __LINE__, cpu, msg, result); 57 " (%d)\n", __func__, __LINE__, cpu, msg, result);
58} 58}
59 59
60static int __init ps3_smp_probe(void) 60static void __init ps3_smp_probe(void)
61{ 61{
62 int cpu; 62 int cpu;
63 63
@@ -100,8 +100,6 @@ static int __init ps3_smp_probe(void)
100 100
101 DBG(" <- %s:%d: (%d)\n", __func__, __LINE__, cpu); 101 DBG(" <- %s:%d: (%d)\n", __func__, __LINE__, cpu);
102 } 102 }
103
104 return 2;
105} 103}
106 104
107void ps3_smp_cleanup_cpu(int cpu) 105void ps3_smp_cleanup_cpu(int cpu)
diff --git a/arch/powerpc/platforms/pseries/Kconfig b/arch/powerpc/platforms/pseries/Kconfig
index a758a9c3bbba..54c87d5d349d 100644
--- a/arch/powerpc/platforms/pseries/Kconfig
+++ b/arch/powerpc/platforms/pseries/Kconfig
@@ -16,7 +16,6 @@ config PPC_PSERIES
16 select PPC_UDBG_16550 16 select PPC_UDBG_16550
17 select PPC_NATIVE 17 select PPC_NATIVE
18 select PPC_PCI_CHOICE if EXPERT 18 select PPC_PCI_CHOICE if EXPERT
19 select ZLIB_DEFLATE
20 select PPC_DOORBELL 19 select PPC_DOORBELL
21 select HAVE_CONTEXT_TRACKING 20 select HAVE_CONTEXT_TRACKING
22 select HOTPLUG_CPU if SMP 21 select HOTPLUG_CPU if SMP
diff --git a/arch/powerpc/platforms/pseries/dlpar.c b/arch/powerpc/platforms/pseries/dlpar.c
index c22bb1b4beb8..b4b11096ea8b 100644
--- a/arch/powerpc/platforms/pseries/dlpar.c
+++ b/arch/powerpc/platforms/pseries/dlpar.c
@@ -10,6 +10,8 @@
10 * 2 as published by the Free Software Foundation. 10 * 2 as published by the Free Software Foundation.
11 */ 11 */
12 12
13#define pr_fmt(fmt) "dlpar: " fmt
14
13#include <linux/kernel.h> 15#include <linux/kernel.h>
14#include <linux/notifier.h> 16#include <linux/notifier.h>
15#include <linux/spinlock.h> 17#include <linux/spinlock.h>
@@ -535,13 +537,125 @@ static ssize_t dlpar_cpu_release(const char *buf, size_t count)
535 return count; 537 return count;
536} 538}
537 539
540#endif /* CONFIG_ARCH_CPU_PROBE_RELEASE */
541
542static int handle_dlpar_errorlog(struct pseries_hp_errorlog *hp_elog)
543{
544 int rc;
545
546 /* pseries error logs are in BE format, convert to cpu type */
547 switch (hp_elog->id_type) {
548 case PSERIES_HP_ELOG_ID_DRC_COUNT:
549 hp_elog->_drc_u.drc_count =
550 be32_to_cpu(hp_elog->_drc_u.drc_count);
551 break;
552 case PSERIES_HP_ELOG_ID_DRC_INDEX:
553 hp_elog->_drc_u.drc_index =
554 be32_to_cpu(hp_elog->_drc_u.drc_index);
555 }
556
557 switch (hp_elog->resource) {
558 case PSERIES_HP_ELOG_RESOURCE_MEM:
559 rc = dlpar_memory(hp_elog);
560 break;
561 default:
562 pr_warn_ratelimited("Invalid resource (%d) specified\n",
563 hp_elog->resource);
564 rc = -EINVAL;
565 }
566
567 return rc;
568}
569
570static ssize_t dlpar_store(struct class *class, struct class_attribute *attr,
571 const char *buf, size_t count)
572{
573 struct pseries_hp_errorlog *hp_elog;
574 const char *arg;
575 int rc;
576
577 hp_elog = kzalloc(sizeof(*hp_elog), GFP_KERNEL);
578 if (!hp_elog) {
579 rc = -ENOMEM;
580 goto dlpar_store_out;
581 }
582
583 /* Parse out the request from the user, this will be in the form
584 * <resource> <action> <id_type> <id>
585 */
586 arg = buf;
587 if (!strncmp(arg, "memory", 6)) {
588 hp_elog->resource = PSERIES_HP_ELOG_RESOURCE_MEM;
589 arg += strlen("memory ");
590 } else {
591 pr_err("Invalid resource specified: \"%s\"\n", buf);
592 rc = -EINVAL;
593 goto dlpar_store_out;
594 }
595
596 if (!strncmp(arg, "add", 3)) {
597 hp_elog->action = PSERIES_HP_ELOG_ACTION_ADD;
598 arg += strlen("add ");
599 } else if (!strncmp(arg, "remove", 6)) {
600 hp_elog->action = PSERIES_HP_ELOG_ACTION_REMOVE;
601 arg += strlen("remove ");
602 } else {
603 pr_err("Invalid action specified: \"%s\"\n", buf);
604 rc = -EINVAL;
605 goto dlpar_store_out;
606 }
607
608 if (!strncmp(arg, "index", 5)) {
609 u32 index;
610
611 hp_elog->id_type = PSERIES_HP_ELOG_ID_DRC_INDEX;
612 arg += strlen("index ");
613 if (kstrtou32(arg, 0, &index)) {
614 rc = -EINVAL;
615 pr_err("Invalid drc_index specified: \"%s\"\n", buf);
616 goto dlpar_store_out;
617 }
618
619 hp_elog->_drc_u.drc_index = cpu_to_be32(index);
620 } else if (!strncmp(arg, "count", 5)) {
621 u32 count;
622
623 hp_elog->id_type = PSERIES_HP_ELOG_ID_DRC_COUNT;
624 arg += strlen("count ");
625 if (kstrtou32(arg, 0, &count)) {
626 rc = -EINVAL;
627 pr_err("Invalid count specified: \"%s\"\n", buf);
628 goto dlpar_store_out;
629 }
630
631 hp_elog->_drc_u.drc_count = cpu_to_be32(count);
632 } else {
633 pr_err("Invalid id_type specified: \"%s\"\n", buf);
634 rc = -EINVAL;
635 goto dlpar_store_out;
636 }
637
638 rc = handle_dlpar_errorlog(hp_elog);
639
640dlpar_store_out:
641 kfree(hp_elog);
642 return rc ? rc : count;
643}
644
645static CLASS_ATTR(dlpar, S_IWUSR, NULL, dlpar_store);
646
538static int __init pseries_dlpar_init(void) 647static int __init pseries_dlpar_init(void)
539{ 648{
649 int rc;
650
651#ifdef CONFIG_ARCH_CPU_PROBE_RELEASE
540 ppc_md.cpu_probe = dlpar_cpu_probe; 652 ppc_md.cpu_probe = dlpar_cpu_probe;
541 ppc_md.cpu_release = dlpar_cpu_release; 653 ppc_md.cpu_release = dlpar_cpu_release;
654#endif /* CONFIG_ARCH_CPU_PROBE_RELEASE */
542 655
543 return 0; 656 rc = sysfs_create_file(kernel_kobj, &class_attr_dlpar.attr);
657
658 return rc;
544} 659}
545machine_device_initcall(pseries, pseries_dlpar_init); 660machine_device_initcall(pseries, pseries_dlpar_init);
546 661
547#endif /* CONFIG_ARCH_CPU_PROBE_RELEASE */
diff --git a/arch/powerpc/platforms/pseries/eeh_pseries.c b/arch/powerpc/platforms/pseries/eeh_pseries.c
index a6c7e19f5eb3..2039397cc75d 100644
--- a/arch/powerpc/platforms/pseries/eeh_pseries.c
+++ b/arch/powerpc/platforms/pseries/eeh_pseries.c
@@ -118,9 +118,8 @@ static int pseries_eeh_init(void)
118 return 0; 118 return 0;
119} 119}
120 120
121static int pseries_eeh_cap_start(struct device_node *dn) 121static int pseries_eeh_cap_start(struct pci_dn *pdn)
122{ 122{
123 struct pci_dn *pdn = PCI_DN(dn);
124 u32 status; 123 u32 status;
125 124
126 if (!pdn) 125 if (!pdn)
@@ -134,10 +133,9 @@ static int pseries_eeh_cap_start(struct device_node *dn)
134} 133}
135 134
136 135
137static int pseries_eeh_find_cap(struct device_node *dn, int cap) 136static int pseries_eeh_find_cap(struct pci_dn *pdn, int cap)
138{ 137{
139 struct pci_dn *pdn = PCI_DN(dn); 138 int pos = pseries_eeh_cap_start(pdn);
140 int pos = pseries_eeh_cap_start(dn);
141 int cnt = 48; /* Maximal number of capabilities */ 139 int cnt = 48; /* Maximal number of capabilities */
142 u32 id; 140 u32 id;
143 141
@@ -160,10 +158,9 @@ static int pseries_eeh_find_cap(struct device_node *dn, int cap)
160 return 0; 158 return 0;
161} 159}
162 160
163static int pseries_eeh_find_ecap(struct device_node *dn, int cap) 161static int pseries_eeh_find_ecap(struct pci_dn *pdn, int cap)
164{ 162{
165 struct pci_dn *pdn = PCI_DN(dn); 163 struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
166 struct eeh_dev *edev = of_node_to_eeh_dev(dn);
167 u32 header; 164 u32 header;
168 int pos = 256; 165 int pos = 256;
169 int ttl = (4096 - 256) / 8; 166 int ttl = (4096 - 256) / 8;
@@ -191,53 +188,44 @@ static int pseries_eeh_find_ecap(struct device_node *dn, int cap)
191} 188}
192 189
193/** 190/**
194 * pseries_eeh_of_probe - EEH probe on the given device 191 * pseries_eeh_probe - EEH probe on the given device
195 * @dn: OF node 192 * @pdn: PCI device node
196 * @flag: Unused 193 * @data: Unused
197 * 194 *
198 * When EEH module is installed during system boot, all PCI devices 195 * When EEH module is installed during system boot, all PCI devices
199 * are checked one by one to see if it supports EEH. The function 196 * are checked one by one to see if it supports EEH. The function
200 * is introduced for the purpose. 197 * is introduced for the purpose.
201 */ 198 */
202static void *pseries_eeh_of_probe(struct device_node *dn, void *flag) 199static void *pseries_eeh_probe(struct pci_dn *pdn, void *data)
203{ 200{
204 struct eeh_dev *edev; 201 struct eeh_dev *edev;
205 struct eeh_pe pe; 202 struct eeh_pe pe;
206 struct pci_dn *pdn = PCI_DN(dn);
207 const __be32 *classp, *vendorp, *devicep;
208 u32 class_code;
209 const __be32 *regs;
210 u32 pcie_flags; 203 u32 pcie_flags;
211 int enable = 0; 204 int enable = 0;
212 int ret; 205 int ret;
213 206
214 /* Retrieve OF node and eeh device */ 207 /* Retrieve OF node and eeh device */
215 edev = of_node_to_eeh_dev(dn); 208 edev = pdn_to_eeh_dev(pdn);
216 if (edev->pe || !of_device_is_available(dn)) 209 if (!edev || edev->pe)
217 return NULL; 210 return NULL;
218 211
219 /* Retrieve class/vendor/device IDs */ 212 /* Check class/vendor/device IDs */
220 classp = of_get_property(dn, "class-code", NULL); 213 if (!pdn->vendor_id || !pdn->device_id || !pdn->class_code)
221 vendorp = of_get_property(dn, "vendor-id", NULL);
222 devicep = of_get_property(dn, "device-id", NULL);
223
224 /* Skip for bad OF node or PCI-ISA bridge */
225 if (!classp || !vendorp || !devicep)
226 return NULL;
227 if (dn->type && !strcmp(dn->type, "isa"))
228 return NULL; 214 return NULL;
229 215
230 class_code = of_read_number(classp, 1); 216 /* Skip for PCI-ISA bridge */
217 if ((pdn->class_code >> 8) == PCI_CLASS_BRIDGE_ISA)
218 return NULL;
231 219
232 /* 220 /*
233 * Update class code and mode of eeh device. We need 221 * Update class code and mode of eeh device. We need
234 * correctly reflects that current device is root port 222 * correctly reflects that current device is root port
235 * or PCIe switch downstream port. 223 * or PCIe switch downstream port.
236 */ 224 */
237 edev->class_code = class_code; 225 edev->class_code = pdn->class_code;
238 edev->pcix_cap = pseries_eeh_find_cap(dn, PCI_CAP_ID_PCIX); 226 edev->pcix_cap = pseries_eeh_find_cap(pdn, PCI_CAP_ID_PCIX);
239 edev->pcie_cap = pseries_eeh_find_cap(dn, PCI_CAP_ID_EXP); 227 edev->pcie_cap = pseries_eeh_find_cap(pdn, PCI_CAP_ID_EXP);
240 edev->aer_cap = pseries_eeh_find_ecap(dn, PCI_EXT_CAP_ID_ERR); 228 edev->aer_cap = pseries_eeh_find_ecap(pdn, PCI_EXT_CAP_ID_ERR);
241 edev->mode &= 0xFFFFFF00; 229 edev->mode &= 0xFFFFFF00;
242 if ((edev->class_code >> 8) == PCI_CLASS_BRIDGE_PCI) { 230 if ((edev->class_code >> 8) == PCI_CLASS_BRIDGE_PCI) {
243 edev->mode |= EEH_DEV_BRIDGE; 231 edev->mode |= EEH_DEV_BRIDGE;
@@ -252,24 +240,16 @@ static void *pseries_eeh_of_probe(struct device_node *dn, void *flag)
252 } 240 }
253 } 241 }
254 242
255 /* Retrieve the device address */
256 regs = of_get_property(dn, "reg", NULL);
257 if (!regs) {
258 pr_warn("%s: OF node property %s::reg not found\n",
259 __func__, dn->full_name);
260 return NULL;
261 }
262
263 /* Initialize the fake PE */ 243 /* Initialize the fake PE */
264 memset(&pe, 0, sizeof(struct eeh_pe)); 244 memset(&pe, 0, sizeof(struct eeh_pe));
265 pe.phb = edev->phb; 245 pe.phb = edev->phb;
266 pe.config_addr = of_read_number(regs, 1); 246 pe.config_addr = (pdn->busno << 16) | (pdn->devfn << 8);
267 247
268 /* Enable EEH on the device */ 248 /* Enable EEH on the device */
269 ret = eeh_ops->set_option(&pe, EEH_OPT_ENABLE); 249 ret = eeh_ops->set_option(&pe, EEH_OPT_ENABLE);
270 if (!ret) { 250 if (!ret) {
271 edev->config_addr = of_read_number(regs, 1);
272 /* Retrieve PE address */ 251 /* Retrieve PE address */
252 edev->config_addr = (pdn->busno << 16) | (pdn->devfn << 8);
273 edev->pe_config_addr = eeh_ops->get_pe_addr(&pe); 253 edev->pe_config_addr = eeh_ops->get_pe_addr(&pe);
274 pe.addr = edev->pe_config_addr; 254 pe.addr = edev->pe_config_addr;
275 255
@@ -285,16 +265,17 @@ static void *pseries_eeh_of_probe(struct device_node *dn, void *flag)
285 eeh_add_flag(EEH_ENABLED); 265 eeh_add_flag(EEH_ENABLED);
286 eeh_add_to_parent_pe(edev); 266 eeh_add_to_parent_pe(edev);
287 267
288 pr_debug("%s: EEH enabled on %s PHB#%d-PE#%x, config addr#%x\n", 268 pr_debug("%s: EEH enabled on %02x:%02x.%01x PHB#%d-PE#%x\n",
289 __func__, dn->full_name, pe.phb->global_number, 269 __func__, pdn->busno, PCI_SLOT(pdn->devfn),
290 pe.addr, pe.config_addr); 270 PCI_FUNC(pdn->devfn), pe.phb->global_number,
291 } else if (dn->parent && of_node_to_eeh_dev(dn->parent) && 271 pe.addr);
292 (of_node_to_eeh_dev(dn->parent))->pe) { 272 } else if (pdn->parent && pdn_to_eeh_dev(pdn->parent) &&
273 (pdn_to_eeh_dev(pdn->parent))->pe) {
293 /* This device doesn't support EEH, but it may have an 274 /* This device doesn't support EEH, but it may have an
294 * EEH parent, in which case we mark it as supported. 275 * EEH parent, in which case we mark it as supported.
295 */ 276 */
296 edev->config_addr = of_node_to_eeh_dev(dn->parent)->config_addr; 277 edev->config_addr = pdn_to_eeh_dev(pdn->parent)->config_addr;
297 edev->pe_config_addr = of_node_to_eeh_dev(dn->parent)->pe_config_addr; 278 edev->pe_config_addr = pdn_to_eeh_dev(pdn->parent)->pe_config_addr;
298 eeh_add_to_parent_pe(edev); 279 eeh_add_to_parent_pe(edev);
299 } 280 }
300 } 281 }
@@ -670,45 +651,36 @@ static int pseries_eeh_configure_bridge(struct eeh_pe *pe)
670 651
671/** 652/**
672 * pseries_eeh_read_config - Read PCI config space 653 * pseries_eeh_read_config - Read PCI config space
673 * @dn: device node 654 * @pdn: PCI device node
674 * @where: PCI address 655 * @where: PCI address
675 * @size: size to read 656 * @size: size to read
676 * @val: return value 657 * @val: return value
677 * 658 *
678 * Read config space from the speicifed device 659 * Read config space from the speicifed device
679 */ 660 */
680static int pseries_eeh_read_config(struct device_node *dn, int where, int size, u32 *val) 661static int pseries_eeh_read_config(struct pci_dn *pdn, int where, int size, u32 *val)
681{ 662{
682 struct pci_dn *pdn;
683
684 pdn = PCI_DN(dn);
685
686 return rtas_read_config(pdn, where, size, val); 663 return rtas_read_config(pdn, where, size, val);
687} 664}
688 665
689/** 666/**
690 * pseries_eeh_write_config - Write PCI config space 667 * pseries_eeh_write_config - Write PCI config space
691 * @dn: device node 668 * @pdn: PCI device node
692 * @where: PCI address 669 * @where: PCI address
693 * @size: size to write 670 * @size: size to write
694 * @val: value to be written 671 * @val: value to be written
695 * 672 *
696 * Write config space to the specified device 673 * Write config space to the specified device
697 */ 674 */
698static int pseries_eeh_write_config(struct device_node *dn, int where, int size, u32 val) 675static int pseries_eeh_write_config(struct pci_dn *pdn, int where, int size, u32 val)
699{ 676{
700 struct pci_dn *pdn;
701
702 pdn = PCI_DN(dn);
703
704 return rtas_write_config(pdn, where, size, val); 677 return rtas_write_config(pdn, where, size, val);
705} 678}
706 679
707static struct eeh_ops pseries_eeh_ops = { 680static struct eeh_ops pseries_eeh_ops = {
708 .name = "pseries", 681 .name = "pseries",
709 .init = pseries_eeh_init, 682 .init = pseries_eeh_init,
710 .of_probe = pseries_eeh_of_probe, 683 .probe = pseries_eeh_probe,
711 .dev_probe = NULL,
712 .set_option = pseries_eeh_set_option, 684 .set_option = pseries_eeh_set_option,
713 .get_pe_addr = pseries_eeh_get_pe_addr, 685 .get_pe_addr = pseries_eeh_get_pe_addr,
714 .get_state = pseries_eeh_get_state, 686 .get_state = pseries_eeh_get_state,
diff --git a/arch/powerpc/platforms/pseries/hotplug-memory.c b/arch/powerpc/platforms/pseries/hotplug-memory.c
index fa41f0da5b6f..0ced387e1463 100644
--- a/arch/powerpc/platforms/pseries/hotplug-memory.c
+++ b/arch/powerpc/platforms/pseries/hotplug-memory.c
@@ -9,11 +9,14 @@
9 * 2 of the License, or (at your option) any later version. 9 * 2 of the License, or (at your option) any later version.
10 */ 10 */
11 11
12#define pr_fmt(fmt) "pseries-hotplug-mem: " fmt
13
12#include <linux/of.h> 14#include <linux/of.h>
13#include <linux/of_address.h> 15#include <linux/of_address.h>
14#include <linux/memblock.h> 16#include <linux/memblock.h>
15#include <linux/memory.h> 17#include <linux/memory.h>
16#include <linux/memory_hotplug.h> 18#include <linux/memory_hotplug.h>
19#include <linux/slab.h>
17 20
18#include <asm/firmware.h> 21#include <asm/firmware.h>
19#include <asm/machdep.h> 22#include <asm/machdep.h>
@@ -21,6 +24,8 @@
21#include <asm/sparsemem.h> 24#include <asm/sparsemem.h>
22#include "pseries.h" 25#include "pseries.h"
23 26
27static bool rtas_hp_event;
28
24unsigned long pseries_memory_block_size(void) 29unsigned long pseries_memory_block_size(void)
25{ 30{
26 struct device_node *np; 31 struct device_node *np;
@@ -64,6 +69,67 @@ unsigned long pseries_memory_block_size(void)
64 return memblock_size; 69 return memblock_size;
65} 70}
66 71
72static void dlpar_free_drconf_property(struct property *prop)
73{
74 kfree(prop->name);
75 kfree(prop->value);
76 kfree(prop);
77}
78
79static struct property *dlpar_clone_drconf_property(struct device_node *dn)
80{
81 struct property *prop, *new_prop;
82 struct of_drconf_cell *lmbs;
83 u32 num_lmbs, *p;
84 int i;
85
86 prop = of_find_property(dn, "ibm,dynamic-memory", NULL);
87 if (!prop)
88 return NULL;
89
90 new_prop = kzalloc(sizeof(*new_prop), GFP_KERNEL);
91 if (!new_prop)
92 return NULL;
93
94 new_prop->name = kstrdup(prop->name, GFP_KERNEL);
95 new_prop->value = kmalloc(prop->length, GFP_KERNEL);
96 if (!new_prop->name || !new_prop->value) {
97 dlpar_free_drconf_property(new_prop);
98 return NULL;
99 }
100
101 memcpy(new_prop->value, prop->value, prop->length);
102 new_prop->length = prop->length;
103
104 /* Convert the property to cpu endian-ness */
105 p = new_prop->value;
106 *p = be32_to_cpu(*p);
107
108 num_lmbs = *p++;
109 lmbs = (struct of_drconf_cell *)p;
110
111 for (i = 0; i < num_lmbs; i++) {
112 lmbs[i].base_addr = be64_to_cpu(lmbs[i].base_addr);
113 lmbs[i].drc_index = be32_to_cpu(lmbs[i].drc_index);
114 lmbs[i].flags = be32_to_cpu(lmbs[i].flags);
115 }
116
117 return new_prop;
118}
119
120static struct memory_block *lmb_to_memblock(struct of_drconf_cell *lmb)
121{
122 unsigned long section_nr;
123 struct mem_section *mem_sect;
124 struct memory_block *mem_block;
125
126 section_nr = pfn_to_section_nr(PFN_DOWN(lmb->base_addr));
127 mem_sect = __nr_to_section(section_nr);
128
129 mem_block = find_memory_block(mem_sect);
130 return mem_block;
131}
132
67#ifdef CONFIG_MEMORY_HOTREMOVE 133#ifdef CONFIG_MEMORY_HOTREMOVE
68static int pseries_remove_memblock(unsigned long base, unsigned int memblock_size) 134static int pseries_remove_memblock(unsigned long base, unsigned int memblock_size)
69{ 135{
@@ -122,6 +188,173 @@ static int pseries_remove_mem_node(struct device_node *np)
122 pseries_remove_memblock(base, lmb_size); 188 pseries_remove_memblock(base, lmb_size);
123 return 0; 189 return 0;
124} 190}
191
192static bool lmb_is_removable(struct of_drconf_cell *lmb)
193{
194 int i, scns_per_block;
195 int rc = 1;
196 unsigned long pfn, block_sz;
197 u64 phys_addr;
198
199 if (!(lmb->flags & DRCONF_MEM_ASSIGNED))
200 return false;
201
202 block_sz = memory_block_size_bytes();
203 scns_per_block = block_sz / MIN_MEMORY_BLOCK_SIZE;
204 phys_addr = lmb->base_addr;
205
206 for (i = 0; i < scns_per_block; i++) {
207 pfn = PFN_DOWN(phys_addr);
208 if (!pfn_present(pfn))
209 continue;
210
211 rc &= is_mem_section_removable(pfn, PAGES_PER_SECTION);
212 phys_addr += MIN_MEMORY_BLOCK_SIZE;
213 }
214
215 return rc ? true : false;
216}
217
218static int dlpar_add_lmb(struct of_drconf_cell *);
219
220static int dlpar_remove_lmb(struct of_drconf_cell *lmb)
221{
222 struct memory_block *mem_block;
223 unsigned long block_sz;
224 int nid, rc;
225
226 if (!lmb_is_removable(lmb))
227 return -EINVAL;
228
229 mem_block = lmb_to_memblock(lmb);
230 if (!mem_block)
231 return -EINVAL;
232
233 rc = device_offline(&mem_block->dev);
234 put_device(&mem_block->dev);
235 if (rc)
236 return rc;
237
238 block_sz = pseries_memory_block_size();
239 nid = memory_add_physaddr_to_nid(lmb->base_addr);
240
241 remove_memory(nid, lmb->base_addr, block_sz);
242
243 /* Update memory regions for memory remove */
244 memblock_remove(lmb->base_addr, block_sz);
245
246 dlpar_release_drc(lmb->drc_index);
247
248 lmb->flags &= ~DRCONF_MEM_ASSIGNED;
249 return 0;
250}
251
252static int dlpar_memory_remove_by_count(u32 lmbs_to_remove,
253 struct property *prop)
254{
255 struct of_drconf_cell *lmbs;
256 int lmbs_removed = 0;
257 int lmbs_available = 0;
258 u32 num_lmbs, *p;
259 int i, rc;
260
261 pr_info("Attempting to hot-remove %d LMB(s)\n", lmbs_to_remove);
262
263 if (lmbs_to_remove == 0)
264 return -EINVAL;
265
266 p = prop->value;
267 num_lmbs = *p++;
268 lmbs = (struct of_drconf_cell *)p;
269
270 /* Validate that there are enough LMBs to satisfy the request */
271 for (i = 0; i < num_lmbs; i++) {
272 if (lmbs[i].flags & DRCONF_MEM_ASSIGNED)
273 lmbs_available++;
274 }
275
276 if (lmbs_available < lmbs_to_remove)
277 return -EINVAL;
278
279 for (i = 0; i < num_lmbs && lmbs_removed < lmbs_to_remove; i++) {
280 rc = dlpar_remove_lmb(&lmbs[i]);
281 if (rc)
282 continue;
283
284 lmbs_removed++;
285
286 /* Mark this lmb so we can add it later if all of the
287 * requested LMBs cannot be removed.
288 */
289 lmbs[i].reserved = 1;
290 }
291
292 if (lmbs_removed != lmbs_to_remove) {
293 pr_err("Memory hot-remove failed, adding LMB's back\n");
294
295 for (i = 0; i < num_lmbs; i++) {
296 if (!lmbs[i].reserved)
297 continue;
298
299 rc = dlpar_add_lmb(&lmbs[i]);
300 if (rc)
301 pr_err("Failed to add LMB back, drc index %x\n",
302 lmbs[i].drc_index);
303
304 lmbs[i].reserved = 0;
305 }
306
307 rc = -EINVAL;
308 } else {
309 for (i = 0; i < num_lmbs; i++) {
310 if (!lmbs[i].reserved)
311 continue;
312
313 pr_info("Memory at %llx was hot-removed\n",
314 lmbs[i].base_addr);
315
316 lmbs[i].reserved = 0;
317 }
318 rc = 0;
319 }
320
321 return rc;
322}
323
324static int dlpar_memory_remove_by_index(u32 drc_index, struct property *prop)
325{
326 struct of_drconf_cell *lmbs;
327 u32 num_lmbs, *p;
328 int lmb_found;
329 int i, rc;
330
331 pr_info("Attempting to hot-remove LMB, drc index %x\n", drc_index);
332
333 p = prop->value;
334 num_lmbs = *p++;
335 lmbs = (struct of_drconf_cell *)p;
336
337 lmb_found = 0;
338 for (i = 0; i < num_lmbs; i++) {
339 if (lmbs[i].drc_index == drc_index) {
340 lmb_found = 1;
341 rc = dlpar_remove_lmb(&lmbs[i]);
342 break;
343 }
344 }
345
346 if (!lmb_found)
347 rc = -EINVAL;
348
349 if (rc)
350 pr_info("Failed to hot-remove memory at %llx\n",
351 lmbs[i].base_addr);
352 else
353 pr_info("Memory at %llx was hot-removed\n", lmbs[i].base_addr);
354
355 return rc;
356}
357
125#else 358#else
126static inline int pseries_remove_memblock(unsigned long base, 359static inline int pseries_remove_memblock(unsigned long base,
127 unsigned int memblock_size) 360 unsigned int memblock_size)
@@ -132,8 +365,261 @@ static inline int pseries_remove_mem_node(struct device_node *np)
132{ 365{
133 return 0; 366 return 0;
134} 367}
368static inline int dlpar_memory_remove(struct pseries_hp_errorlog *hp_elog)
369{
370 return -EOPNOTSUPP;
371}
372static int dlpar_remove_lmb(struct of_drconf_cell *lmb)
373{
374 return -EOPNOTSUPP;
375}
376static int dlpar_memory_remove_by_count(u32 lmbs_to_remove,
377 struct property *prop)
378{
379 return -EOPNOTSUPP;
380}
381static int dlpar_memory_remove_by_index(u32 drc_index, struct property *prop)
382{
383 return -EOPNOTSUPP;
384}
385
135#endif /* CONFIG_MEMORY_HOTREMOVE */ 386#endif /* CONFIG_MEMORY_HOTREMOVE */
136 387
388static int dlpar_add_lmb(struct of_drconf_cell *lmb)
389{
390 struct memory_block *mem_block;
391 unsigned long block_sz;
392 int nid, rc;
393
394 if (lmb->flags & DRCONF_MEM_ASSIGNED)
395 return -EINVAL;
396
397 block_sz = memory_block_size_bytes();
398
399 rc = dlpar_acquire_drc(lmb->drc_index);
400 if (rc)
401 return rc;
402
403 /* Find the node id for this address */
404 nid = memory_add_physaddr_to_nid(lmb->base_addr);
405
406 /* Add the memory */
407 rc = add_memory(nid, lmb->base_addr, block_sz);
408 if (rc) {
409 dlpar_release_drc(lmb->drc_index);
410 return rc;
411 }
412
413 /* Register this block of memory */
414 rc = memblock_add(lmb->base_addr, block_sz);
415 if (rc) {
416 remove_memory(nid, lmb->base_addr, block_sz);
417 dlpar_release_drc(lmb->drc_index);
418 return rc;
419 }
420
421 mem_block = lmb_to_memblock(lmb);
422 if (!mem_block) {
423 remove_memory(nid, lmb->base_addr, block_sz);
424 dlpar_release_drc(lmb->drc_index);
425 return -EINVAL;
426 }
427
428 rc = device_online(&mem_block->dev);
429 put_device(&mem_block->dev);
430 if (rc) {
431 remove_memory(nid, lmb->base_addr, block_sz);
432 dlpar_release_drc(lmb->drc_index);
433 return rc;
434 }
435
436 lmb->flags |= DRCONF_MEM_ASSIGNED;
437 return 0;
438}
439
440static int dlpar_memory_add_by_count(u32 lmbs_to_add, struct property *prop)
441{
442 struct of_drconf_cell *lmbs;
443 u32 num_lmbs, *p;
444 int lmbs_available = 0;
445 int lmbs_added = 0;
446 int i, rc;
447
448 pr_info("Attempting to hot-add %d LMB(s)\n", lmbs_to_add);
449
450 if (lmbs_to_add == 0)
451 return -EINVAL;
452
453 p = prop->value;
454 num_lmbs = *p++;
455 lmbs = (struct of_drconf_cell *)p;
456
457 /* Validate that there are enough LMBs to satisfy the request */
458 for (i = 0; i < num_lmbs; i++) {
459 if (!(lmbs[i].flags & DRCONF_MEM_ASSIGNED))
460 lmbs_available++;
461 }
462
463 if (lmbs_available < lmbs_to_add)
464 return -EINVAL;
465
466 for (i = 0; i < num_lmbs && lmbs_to_add != lmbs_added; i++) {
467 rc = dlpar_add_lmb(&lmbs[i]);
468 if (rc)
469 continue;
470
471 lmbs_added++;
472
473 /* Mark this lmb so we can remove it later if all of the
474 * requested LMBs cannot be added.
475 */
476 lmbs[i].reserved = 1;
477 }
478
479 if (lmbs_added != lmbs_to_add) {
480 pr_err("Memory hot-add failed, removing any added LMBs\n");
481
482 for (i = 0; i < num_lmbs; i++) {
483 if (!lmbs[i].reserved)
484 continue;
485
486 rc = dlpar_remove_lmb(&lmbs[i]);
487 if (rc)
488 pr_err("Failed to remove LMB, drc index %x\n",
489 be32_to_cpu(lmbs[i].drc_index));
490 }
491 rc = -EINVAL;
492 } else {
493 for (i = 0; i < num_lmbs; i++) {
494 if (!lmbs[i].reserved)
495 continue;
496
497 pr_info("Memory at %llx (drc index %x) was hot-added\n",
498 lmbs[i].base_addr, lmbs[i].drc_index);
499 lmbs[i].reserved = 0;
500 }
501 }
502
503 return rc;
504}
505
506static int dlpar_memory_add_by_index(u32 drc_index, struct property *prop)
507{
508 struct of_drconf_cell *lmbs;
509 u32 num_lmbs, *p;
510 int i, lmb_found;
511 int rc;
512
513 pr_info("Attempting to hot-add LMB, drc index %x\n", drc_index);
514
515 p = prop->value;
516 num_lmbs = *p++;
517 lmbs = (struct of_drconf_cell *)p;
518
519 lmb_found = 0;
520 for (i = 0; i < num_lmbs; i++) {
521 if (lmbs[i].drc_index == drc_index) {
522 lmb_found = 1;
523 rc = dlpar_add_lmb(&lmbs[i]);
524 break;
525 }
526 }
527
528 if (!lmb_found)
529 rc = -EINVAL;
530
531 if (rc)
532 pr_info("Failed to hot-add memory, drc index %x\n", drc_index);
533 else
534 pr_info("Memory at %llx (drc index %x) was hot-added\n",
535 lmbs[i].base_addr, drc_index);
536
537 return rc;
538}
539
540static void dlpar_update_drconf_property(struct device_node *dn,
541 struct property *prop)
542{
543 struct of_drconf_cell *lmbs;
544 u32 num_lmbs, *p;
545 int i;
546
547 /* Convert the property back to BE */
548 p = prop->value;
549 num_lmbs = *p;
550 *p = cpu_to_be32(*p);
551 p++;
552
553 lmbs = (struct of_drconf_cell *)p;
554 for (i = 0; i < num_lmbs; i++) {
555 lmbs[i].base_addr = cpu_to_be64(lmbs[i].base_addr);
556 lmbs[i].drc_index = cpu_to_be32(lmbs[i].drc_index);
557 lmbs[i].flags = cpu_to_be32(lmbs[i].flags);
558 }
559
560 rtas_hp_event = true;
561 of_update_property(dn, prop);
562 rtas_hp_event = false;
563}
564
565int dlpar_memory(struct pseries_hp_errorlog *hp_elog)
566{
567 struct device_node *dn;
568 struct property *prop;
569 u32 count, drc_index;
570 int rc;
571
572 count = hp_elog->_drc_u.drc_count;
573 drc_index = hp_elog->_drc_u.drc_index;
574
575 lock_device_hotplug();
576
577 dn = of_find_node_by_path("/ibm,dynamic-reconfiguration-memory");
578 if (!dn) {
579 rc = -EINVAL;
580 goto dlpar_memory_out;
581 }
582
583 prop = dlpar_clone_drconf_property(dn);
584 if (!prop) {
585 rc = -EINVAL;
586 goto dlpar_memory_out;
587 }
588
589 switch (hp_elog->action) {
590 case PSERIES_HP_ELOG_ACTION_ADD:
591 if (hp_elog->id_type == PSERIES_HP_ELOG_ID_DRC_COUNT)
592 rc = dlpar_memory_add_by_count(count, prop);
593 else if (hp_elog->id_type == PSERIES_HP_ELOG_ID_DRC_INDEX)
594 rc = dlpar_memory_add_by_index(drc_index, prop);
595 else
596 rc = -EINVAL;
597 break;
598 case PSERIES_HP_ELOG_ACTION_REMOVE:
599 if (hp_elog->id_type == PSERIES_HP_ELOG_ID_DRC_COUNT)
600 rc = dlpar_memory_remove_by_count(count, prop);
601 else if (hp_elog->id_type == PSERIES_HP_ELOG_ID_DRC_INDEX)
602 rc = dlpar_memory_remove_by_index(drc_index, prop);
603 else
604 rc = -EINVAL;
605 break;
606 default:
607 pr_err("Invalid action (%d) specified\n", hp_elog->action);
608 rc = -EINVAL;
609 break;
610 }
611
612 if (rc)
613 dlpar_free_drconf_property(prop);
614 else
615 dlpar_update_drconf_property(dn, prop);
616
617dlpar_memory_out:
618 of_node_put(dn);
619 unlock_device_hotplug();
620 return rc;
621}
622
137static int pseries_add_mem_node(struct device_node *np) 623static int pseries_add_mem_node(struct device_node *np)
138{ 624{
139 const char *type; 625 const char *type;
@@ -174,6 +660,9 @@ static int pseries_update_drconf_memory(struct of_reconfig_data *pr)
174 __be32 *p; 660 __be32 *p;
175 int i, rc = -EINVAL; 661 int i, rc = -EINVAL;
176 662
663 if (rtas_hp_event)
664 return 0;
665
177 memblock_size = pseries_memory_block_size(); 666 memblock_size = pseries_memory_block_size();
178 if (!memblock_size) 667 if (!memblock_size)
179 return -EINVAL; 668 return -EINVAL;
diff --git a/arch/powerpc/platforms/pseries/iommu.c b/arch/powerpc/platforms/pseries/iommu.c
index 7803a19adb31..61d5a17f45c0 100644
--- a/arch/powerpc/platforms/pseries/iommu.c
+++ b/arch/powerpc/platforms/pseries/iommu.c
@@ -49,6 +49,7 @@
49#include <asm/mmzone.h> 49#include <asm/mmzone.h>
50#include <asm/plpar_wrappers.h> 50#include <asm/plpar_wrappers.h>
51 51
52#include "pseries.h"
52 53
53static void tce_invalidate_pSeries_sw(struct iommu_table *tbl, 54static void tce_invalidate_pSeries_sw(struct iommu_table *tbl,
54 __be64 *startp, __be64 *endp) 55 __be64 *startp, __be64 *endp)
@@ -1307,16 +1308,16 @@ void iommu_init_early_pSeries(void)
1307 ppc_md.tce_free = tce_free_pSeriesLP; 1308 ppc_md.tce_free = tce_free_pSeriesLP;
1308 } 1309 }
1309 ppc_md.tce_get = tce_get_pSeriesLP; 1310 ppc_md.tce_get = tce_get_pSeriesLP;
1310 ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pSeriesLP; 1311 pseries_pci_controller_ops.dma_bus_setup = pci_dma_bus_setup_pSeriesLP;
1311 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_pSeriesLP; 1312 pseries_pci_controller_ops.dma_dev_setup = pci_dma_dev_setup_pSeriesLP;
1312 ppc_md.dma_set_mask = dma_set_mask_pSeriesLP; 1313 ppc_md.dma_set_mask = dma_set_mask_pSeriesLP;
1313 ppc_md.dma_get_required_mask = dma_get_required_mask_pSeriesLP; 1314 ppc_md.dma_get_required_mask = dma_get_required_mask_pSeriesLP;
1314 } else { 1315 } else {
1315 ppc_md.tce_build = tce_build_pSeries; 1316 ppc_md.tce_build = tce_build_pSeries;
1316 ppc_md.tce_free = tce_free_pSeries; 1317 ppc_md.tce_free = tce_free_pSeries;
1317 ppc_md.tce_get = tce_get_pseries; 1318 ppc_md.tce_get = tce_get_pseries;
1318 ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pSeries; 1319 pseries_pci_controller_ops.dma_bus_setup = pci_dma_bus_setup_pSeries;
1319 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_pSeries; 1320 pseries_pci_controller_ops.dma_dev_setup = pci_dma_dev_setup_pSeries;
1320 } 1321 }
1321 1322
1322 1323
diff --git a/arch/powerpc/platforms/pseries/mobility.c b/arch/powerpc/platforms/pseries/mobility.c
index 8f35d525cede..ceb18d349459 100644
--- a/arch/powerpc/platforms/pseries/mobility.c
+++ b/arch/powerpc/platforms/pseries/mobility.c
@@ -320,28 +320,34 @@ static ssize_t migrate_store(struct class *class, struct class_attribute *attr,
320{ 320{
321 u64 streamid; 321 u64 streamid;
322 int rc; 322 int rc;
323 int vasi_rc = 0;
324 323
325 rc = kstrtou64(buf, 0, &streamid); 324 rc = kstrtou64(buf, 0, &streamid);
326 if (rc) 325 if (rc)
327 return rc; 326 return rc;
328 327
329 do { 328 do {
330 rc = rtas_ibm_suspend_me(streamid, &vasi_rc); 329 rc = rtas_ibm_suspend_me(streamid);
331 if (!rc && vasi_rc == RTAS_NOT_SUSPENDABLE) 330 if (rc == -EAGAIN)
332 ssleep(1); 331 ssleep(1);
333 } while (!rc && vasi_rc == RTAS_NOT_SUSPENDABLE); 332 } while (rc == -EAGAIN);
334 333
335 if (rc) 334 if (rc)
336 return rc; 335 return rc;
337 if (vasi_rc)
338 return vasi_rc;
339 336
340 post_mobility_fixup(); 337 post_mobility_fixup();
341 return count; 338 return count;
342} 339}
343 340
341/*
342 * Used by drmgr to determine the kernel behavior of the migration interface.
343 *
344 * Version 1: Performs all PAPR requirements for migration including
345 * firmware activation and device tree update.
346 */
347#define MIGRATION_API_VERSION 1
348
344static CLASS_ATTR(migration, S_IWUSR, NULL, migrate_store); 349static CLASS_ATTR(migration, S_IWUSR, NULL, migrate_store);
350static CLASS_ATTR_STRING(api_version, S_IRUGO, __stringify(MIGRATION_API_VERSION));
345 351
346static int __init mobility_sysfs_init(void) 352static int __init mobility_sysfs_init(void)
347{ 353{
@@ -352,7 +358,13 @@ static int __init mobility_sysfs_init(void)
352 return -ENOMEM; 358 return -ENOMEM;
353 359
354 rc = sysfs_create_file(mobility_kobj, &class_attr_migration.attr); 360 rc = sysfs_create_file(mobility_kobj, &class_attr_migration.attr);
361 if (rc)
362 pr_err("mobility: unable to create migration sysfs file (%d)\n", rc);
355 363
356 return rc; 364 rc = sysfs_create_file(mobility_kobj, &class_attr_api_version.attr.attr);
365 if (rc)
366 pr_err("mobility: unable to create api_version sysfs file (%d)\n", rc);
367
368 return 0;
357} 369}
358machine_device_initcall(pseries, mobility_sysfs_init); 370machine_device_initcall(pseries, mobility_sysfs_init);
diff --git a/arch/powerpc/platforms/pseries/msi.c b/arch/powerpc/platforms/pseries/msi.c
index 691a154c286d..c8d24f9a6948 100644
--- a/arch/powerpc/platforms/pseries/msi.c
+++ b/arch/powerpc/platforms/pseries/msi.c
@@ -195,6 +195,7 @@ static struct device_node *find_pe_total_msi(struct pci_dev *dev, int *total)
195static struct device_node *find_pe_dn(struct pci_dev *dev, int *total) 195static struct device_node *find_pe_dn(struct pci_dev *dev, int *total)
196{ 196{
197 struct device_node *dn; 197 struct device_node *dn;
198 struct pci_dn *pdn;
198 struct eeh_dev *edev; 199 struct eeh_dev *edev;
199 200
200 /* Found our PE and assume 8 at that point. */ 201 /* Found our PE and assume 8 at that point. */
@@ -204,10 +205,11 @@ static struct device_node *find_pe_dn(struct pci_dev *dev, int *total)
204 return NULL; 205 return NULL;
205 206
206 /* Get the top level device in the PE */ 207 /* Get the top level device in the PE */
207 edev = of_node_to_eeh_dev(dn); 208 edev = pdn_to_eeh_dev(PCI_DN(dn));
208 if (edev->pe) 209 if (edev->pe)
209 edev = list_first_entry(&edev->pe->edevs, struct eeh_dev, list); 210 edev = list_first_entry(&edev->pe->edevs, struct eeh_dev, list);
210 dn = eeh_dev_to_of_node(edev); 211 pdn = eeh_dev_to_pdn(edev);
212 dn = pdn ? pdn->node : NULL;
211 if (!dn) 213 if (!dn)
212 return NULL; 214 return NULL;
213 215
diff --git a/arch/powerpc/platforms/pseries/nvram.c b/arch/powerpc/platforms/pseries/nvram.c
index 054a0ed5c7ee..9f8184175c86 100644
--- a/arch/powerpc/platforms/pseries/nvram.c
+++ b/arch/powerpc/platforms/pseries/nvram.c
@@ -20,7 +20,6 @@
20#include <linux/kmsg_dump.h> 20#include <linux/kmsg_dump.h>
21#include <linux/pstore.h> 21#include <linux/pstore.h>
22#include <linux/ctype.h> 22#include <linux/ctype.h>
23#include <linux/zlib.h>
24#include <asm/uaccess.h> 23#include <asm/uaccess.h>
25#include <asm/nvram.h> 24#include <asm/nvram.h>
26#include <asm/rtas.h> 25#include <asm/rtas.h>
@@ -30,129 +29,17 @@
30/* Max bytes to read/write in one go */ 29/* Max bytes to read/write in one go */
31#define NVRW_CNT 0x20 30#define NVRW_CNT 0x20
32 31
33/*
34 * Set oops header version to distinguish between old and new format header.
35 * lnx,oops-log partition max size is 4000, header version > 4000 will
36 * help in identifying new header.
37 */
38#define OOPS_HDR_VERSION 5000
39
40static unsigned int nvram_size; 32static unsigned int nvram_size;
41static int nvram_fetch, nvram_store; 33static int nvram_fetch, nvram_store;
42static char nvram_buf[NVRW_CNT]; /* assume this is in the first 4GB */ 34static char nvram_buf[NVRW_CNT]; /* assume this is in the first 4GB */
43static DEFINE_SPINLOCK(nvram_lock); 35static DEFINE_SPINLOCK(nvram_lock);
44 36
45struct err_log_info {
46 __be32 error_type;
47 __be32 seq_num;
48};
49
50struct nvram_os_partition {
51 const char *name;
52 int req_size; /* desired size, in bytes */
53 int min_size; /* minimum acceptable size (0 means req_size) */
54 long size; /* size of data portion (excluding err_log_info) */
55 long index; /* offset of data portion of partition */
56 bool os_partition; /* partition initialized by OS, not FW */
57};
58
59static struct nvram_os_partition rtas_log_partition = {
60 .name = "ibm,rtas-log",
61 .req_size = 2079,
62 .min_size = 1055,
63 .index = -1,
64 .os_partition = true
65};
66
67static struct nvram_os_partition oops_log_partition = {
68 .name = "lnx,oops-log",
69 .req_size = 4000,
70 .min_size = 2000,
71 .index = -1,
72 .os_partition = true
73};
74
75static const char *pseries_nvram_os_partitions[] = {
76 "ibm,rtas-log",
77 "lnx,oops-log",
78 NULL
79};
80
81struct oops_log_info {
82 __be16 version;
83 __be16 report_length;
84 __be64 timestamp;
85} __attribute__((packed));
86
87static void oops_to_nvram(struct kmsg_dumper *dumper,
88 enum kmsg_dump_reason reason);
89
90static struct kmsg_dumper nvram_kmsg_dumper = {
91 .dump = oops_to_nvram
92};
93
94/* See clobbering_unread_rtas_event() */ 37/* See clobbering_unread_rtas_event() */
95#define NVRAM_RTAS_READ_TIMEOUT 5 /* seconds */ 38#define NVRAM_RTAS_READ_TIMEOUT 5 /* seconds */
96static unsigned long last_unread_rtas_event; /* timestamp */ 39static time64_t last_unread_rtas_event; /* timestamp */
97
98/*
99 * For capturing and compressing an oops or panic report...
100
101 * big_oops_buf[] holds the uncompressed text we're capturing.
102 *
103 * oops_buf[] holds the compressed text, preceded by a oops header.
104 * oops header has u16 holding the version of oops header (to differentiate
105 * between old and new format header) followed by u16 holding the length of
106 * the compressed* text (*Or uncompressed, if compression fails.) and u64
107 * holding the timestamp. oops_buf[] gets written to NVRAM.
108 *
109 * oops_log_info points to the header. oops_data points to the compressed text.
110 *
111 * +- oops_buf
112 * | +- oops_data
113 * v v
114 * +-----------+-----------+-----------+------------------------+
115 * | version | length | timestamp | text |
116 * | (2 bytes) | (2 bytes) | (8 bytes) | (oops_data_sz bytes) |
117 * +-----------+-----------+-----------+------------------------+
118 * ^
119 * +- oops_log_info
120 *
121 * We preallocate these buffers during init to avoid kmalloc during oops/panic.
122 */
123static size_t big_oops_buf_sz;
124static char *big_oops_buf, *oops_buf;
125static char *oops_data;
126static size_t oops_data_sz;
127
128/* Compression parameters */
129#define COMPR_LEVEL 6
130#define WINDOW_BITS 12
131#define MEM_LEVEL 4
132static struct z_stream_s stream;
133 40
134#ifdef CONFIG_PSTORE 41#ifdef CONFIG_PSTORE
135static struct nvram_os_partition of_config_partition = { 42time64_t last_rtas_event;
136 .name = "of-config",
137 .index = -1,
138 .os_partition = false
139};
140
141static struct nvram_os_partition common_partition = {
142 .name = "common",
143 .index = -1,
144 .os_partition = false
145};
146
147static enum pstore_type_id nvram_type_ids[] = {
148 PSTORE_TYPE_DMESG,
149 PSTORE_TYPE_PPC_RTAS,
150 PSTORE_TYPE_PPC_OF,
151 PSTORE_TYPE_PPC_COMMON,
152 -1
153};
154static int read_type;
155static unsigned long last_rtas_event;
156#endif 43#endif
157 44
158static ssize_t pSeries_nvram_read(char *buf, size_t count, loff_t *index) 45static ssize_t pSeries_nvram_read(char *buf, size_t count, loff_t *index)
@@ -246,132 +133,26 @@ static ssize_t pSeries_nvram_get_size(void)
246 return nvram_size ? nvram_size : -ENODEV; 133 return nvram_size ? nvram_size : -ENODEV;
247} 134}
248 135
249 136/* nvram_write_error_log
250/* nvram_write_os_partition, nvram_write_error_log
251 * 137 *
252 * We need to buffer the error logs into nvram to ensure that we have 138 * We need to buffer the error logs into nvram to ensure that we have
253 * the failure information to decode. If we have a severe error there 139 * the failure information to decode.
254 * is no way to guarantee that the OS or the machine is in a state to
255 * get back to user land and write the error to disk. For example if
256 * the SCSI device driver causes a Machine Check by writing to a bad
257 * IO address, there is no way of guaranteeing that the device driver
258 * is in any state that is would also be able to write the error data
259 * captured to disk, thus we buffer it in NVRAM for analysis on the
260 * next boot.
261 *
262 * In NVRAM the partition containing the error log buffer will looks like:
263 * Header (in bytes):
264 * +-----------+----------+--------+------------+------------------+
265 * | signature | checksum | length | name | data |
266 * |0 |1 |2 3|4 15|16 length-1|
267 * +-----------+----------+--------+------------+------------------+
268 *
269 * The 'data' section would look like (in bytes):
270 * +--------------+------------+-----------------------------------+
271 * | event_logged | sequence # | error log |
272 * |0 3|4 7|8 error_log_size-1|
273 * +--------------+------------+-----------------------------------+
274 *
275 * event_logged: 0 if event has not been logged to syslog, 1 if it has
276 * sequence #: The unique sequence # for each event. (until it wraps)
277 * error log: The error log from event_scan
278 */ 140 */
279static int nvram_write_os_partition(struct nvram_os_partition *part,
280 char *buff, int length,
281 unsigned int err_type,
282 unsigned int error_log_cnt)
283{
284 int rc;
285 loff_t tmp_index;
286 struct err_log_info info;
287
288 if (part->index == -1) {
289 return -ESPIPE;
290 }
291
292 if (length > part->size) {
293 length = part->size;
294 }
295
296 info.error_type = cpu_to_be32(err_type);
297 info.seq_num = cpu_to_be32(error_log_cnt);
298
299 tmp_index = part->index;
300
301 rc = ppc_md.nvram_write((char *)&info, sizeof(struct err_log_info), &tmp_index);
302 if (rc <= 0) {
303 pr_err("%s: Failed nvram_write (%d)\n", __func__, rc);
304 return rc;
305 }
306
307 rc = ppc_md.nvram_write(buff, length, &tmp_index);
308 if (rc <= 0) {
309 pr_err("%s: Failed nvram_write (%d)\n", __func__, rc);
310 return rc;
311 }
312
313 return 0;
314}
315
316int nvram_write_error_log(char * buff, int length, 141int nvram_write_error_log(char * buff, int length,
317 unsigned int err_type, unsigned int error_log_cnt) 142 unsigned int err_type, unsigned int error_log_cnt)
318{ 143{
319 int rc = nvram_write_os_partition(&rtas_log_partition, buff, length, 144 int rc = nvram_write_os_partition(&rtas_log_partition, buff, length,
320 err_type, error_log_cnt); 145 err_type, error_log_cnt);
321 if (!rc) { 146 if (!rc) {
322 last_unread_rtas_event = get_seconds(); 147 last_unread_rtas_event = ktime_get_real_seconds();
323#ifdef CONFIG_PSTORE 148#ifdef CONFIG_PSTORE
324 last_rtas_event = get_seconds(); 149 last_rtas_event = ktime_get_real_seconds();
325#endif 150#endif
326 } 151 }
327 152
328 return rc; 153 return rc;
329} 154}
330 155
331/* nvram_read_partition
332 *
333 * Reads nvram partition for at most 'length'
334 */
335static int nvram_read_partition(struct nvram_os_partition *part, char *buff,
336 int length, unsigned int *err_type,
337 unsigned int *error_log_cnt)
338{
339 int rc;
340 loff_t tmp_index;
341 struct err_log_info info;
342
343 if (part->index == -1)
344 return -1;
345
346 if (length > part->size)
347 length = part->size;
348
349 tmp_index = part->index;
350
351 if (part->os_partition) {
352 rc = ppc_md.nvram_read((char *)&info,
353 sizeof(struct err_log_info),
354 &tmp_index);
355 if (rc <= 0) {
356 pr_err("%s: Failed nvram_read (%d)\n", __func__, rc);
357 return rc;
358 }
359 }
360
361 rc = ppc_md.nvram_read(buff, length, &tmp_index);
362 if (rc <= 0) {
363 pr_err("%s: Failed nvram_read (%d)\n", __func__, rc);
364 return rc;
365 }
366
367 if (part->os_partition) {
368 *error_log_cnt = be32_to_cpu(info.seq_num);
369 *err_type = be32_to_cpu(info.error_type);
370 }
371
372 return 0;
373}
374
375/* nvram_read_error_log 156/* nvram_read_error_log
376 * 157 *
377 * Reads nvram for error log for at most 'length' 158 * Reads nvram for error log for at most 'length'
@@ -407,67 +188,6 @@ int nvram_clear_error_log(void)
407 return 0; 188 return 0;
408} 189}
409 190
410/* pseries_nvram_init_os_partition
411 *
412 * This sets up a partition with an "OS" signature.
413 *
414 * The general strategy is the following:
415 * 1.) If a partition with the indicated name already exists...
416 * - If it's large enough, use it.
417 * - Otherwise, recycle it and keep going.
418 * 2.) Search for a free partition that is large enough.
419 * 3.) If there's not a free partition large enough, recycle any obsolete
420 * OS partitions and try again.
421 * 4.) Will first try getting a chunk that will satisfy the requested size.
422 * 5.) If a chunk of the requested size cannot be allocated, then try finding
423 * a chunk that will satisfy the minum needed.
424 *
425 * Returns 0 on success, else -1.
426 */
427static int __init pseries_nvram_init_os_partition(struct nvram_os_partition
428 *part)
429{
430 loff_t p;
431 int size;
432
433 /* Look for ours */
434 p = nvram_find_partition(part->name, NVRAM_SIG_OS, &size);
435
436 /* Found one but too small, remove it */
437 if (p && size < part->min_size) {
438 pr_info("nvram: Found too small %s partition,"
439 " removing it...\n", part->name);
440 nvram_remove_partition(part->name, NVRAM_SIG_OS, NULL);
441 p = 0;
442 }
443
444 /* Create one if we didn't find */
445 if (!p) {
446 p = nvram_create_partition(part->name, NVRAM_SIG_OS,
447 part->req_size, part->min_size);
448 if (p == -ENOSPC) {
449 pr_info("nvram: No room to create %s partition, "
450 "deleting any obsolete OS partitions...\n",
451 part->name);
452 nvram_remove_partition(NULL, NVRAM_SIG_OS,
453 pseries_nvram_os_partitions);
454 p = nvram_create_partition(part->name, NVRAM_SIG_OS,
455 part->req_size, part->min_size);
456 }
457 }
458
459 if (p <= 0) {
460 pr_err("nvram: Failed to find or create %s"
461 " partition, err %d\n", part->name, (int)p);
462 return -1;
463 }
464
465 part->index = p;
466 part->size = nvram_get_partition_size(p) - sizeof(struct err_log_info);
467
468 return 0;
469}
470
471/* 191/*
472 * Are we using the ibm,rtas-log for oops/panic reports? And if so, 192 * Are we using the ibm,rtas-log for oops/panic reports? And if so,
473 * would logging this oops/panic overwrite an RTAS event that rtas_errd 193 * would logging this oops/panic overwrite an RTAS event that rtas_errd
@@ -476,321 +196,14 @@ static int __init pseries_nvram_init_os_partition(struct nvram_os_partition
476 * We assume that if rtas_errd hasn't read the RTAS event in 196 * We assume that if rtas_errd hasn't read the RTAS event in
477 * NVRAM_RTAS_READ_TIMEOUT seconds, it's probably not going to. 197 * NVRAM_RTAS_READ_TIMEOUT seconds, it's probably not going to.
478 */ 198 */
479static int clobbering_unread_rtas_event(void) 199int clobbering_unread_rtas_event(void)
480{ 200{
481 return (oops_log_partition.index == rtas_log_partition.index 201 return (oops_log_partition.index == rtas_log_partition.index
482 && last_unread_rtas_event 202 && last_unread_rtas_event
483 && get_seconds() - last_unread_rtas_event <= 203 && ktime_get_real_seconds() - last_unread_rtas_event <=
484 NVRAM_RTAS_READ_TIMEOUT); 204 NVRAM_RTAS_READ_TIMEOUT);
485} 205}
486 206
487/* Derived from logfs_compress() */
488static int nvram_compress(const void *in, void *out, size_t inlen,
489 size_t outlen)
490{
491 int err, ret;
492
493 ret = -EIO;
494 err = zlib_deflateInit2(&stream, COMPR_LEVEL, Z_DEFLATED, WINDOW_BITS,
495 MEM_LEVEL, Z_DEFAULT_STRATEGY);
496 if (err != Z_OK)
497 goto error;
498
499 stream.next_in = in;
500 stream.avail_in = inlen;
501 stream.total_in = 0;
502 stream.next_out = out;
503 stream.avail_out = outlen;
504 stream.total_out = 0;
505
506 err = zlib_deflate(&stream, Z_FINISH);
507 if (err != Z_STREAM_END)
508 goto error;
509
510 err = zlib_deflateEnd(&stream);
511 if (err != Z_OK)
512 goto error;
513
514 if (stream.total_out >= stream.total_in)
515 goto error;
516
517 ret = stream.total_out;
518error:
519 return ret;
520}
521
522/* Compress the text from big_oops_buf into oops_buf. */
523static int zip_oops(size_t text_len)
524{
525 struct oops_log_info *oops_hdr = (struct oops_log_info *)oops_buf;
526 int zipped_len = nvram_compress(big_oops_buf, oops_data, text_len,
527 oops_data_sz);
528 if (zipped_len < 0) {
529 pr_err("nvram: compression failed; returned %d\n", zipped_len);
530 pr_err("nvram: logging uncompressed oops/panic report\n");
531 return -1;
532 }
533 oops_hdr->version = cpu_to_be16(OOPS_HDR_VERSION);
534 oops_hdr->report_length = cpu_to_be16(zipped_len);
535 oops_hdr->timestamp = cpu_to_be64(get_seconds());
536 return 0;
537}
538
539#ifdef CONFIG_PSTORE
540static int nvram_pstore_open(struct pstore_info *psi)
541{
542 /* Reset the iterator to start reading partitions again */
543 read_type = -1;
544 return 0;
545}
546
547/**
548 * nvram_pstore_write - pstore write callback for nvram
549 * @type: Type of message logged
550 * @reason: reason behind dump (oops/panic)
551 * @id: identifier to indicate the write performed
552 * @part: pstore writes data to registered buffer in parts,
553 * part number will indicate the same.
554 * @count: Indicates oops count
555 * @compressed: Flag to indicate the log is compressed
556 * @size: number of bytes written to the registered buffer
557 * @psi: registered pstore_info structure
558 *
559 * Called by pstore_dump() when an oops or panic report is logged in the
560 * printk buffer.
561 * Returns 0 on successful write.
562 */
563static int nvram_pstore_write(enum pstore_type_id type,
564 enum kmsg_dump_reason reason,
565 u64 *id, unsigned int part, int count,
566 bool compressed, size_t size,
567 struct pstore_info *psi)
568{
569 int rc;
570 unsigned int err_type = ERR_TYPE_KERNEL_PANIC;
571 struct oops_log_info *oops_hdr = (struct oops_log_info *) oops_buf;
572
573 /* part 1 has the recent messages from printk buffer */
574 if (part > 1 || type != PSTORE_TYPE_DMESG ||
575 clobbering_unread_rtas_event())
576 return -1;
577
578 oops_hdr->version = cpu_to_be16(OOPS_HDR_VERSION);
579 oops_hdr->report_length = cpu_to_be16(size);
580 oops_hdr->timestamp = cpu_to_be64(get_seconds());
581
582 if (compressed)
583 err_type = ERR_TYPE_KERNEL_PANIC_GZ;
584
585 rc = nvram_write_os_partition(&oops_log_partition, oops_buf,
586 (int) (sizeof(*oops_hdr) + size), err_type, count);
587
588 if (rc != 0)
589 return rc;
590
591 *id = part;
592 return 0;
593}
594
595/*
596 * Reads the oops/panic report, rtas, of-config and common partition.
597 * Returns the length of the data we read from each partition.
598 * Returns 0 if we've been called before.
599 */
600static ssize_t nvram_pstore_read(u64 *id, enum pstore_type_id *type,
601 int *count, struct timespec *time, char **buf,
602 bool *compressed, struct pstore_info *psi)
603{
604 struct oops_log_info *oops_hdr;
605 unsigned int err_type, id_no, size = 0;
606 struct nvram_os_partition *part = NULL;
607 char *buff = NULL;
608 int sig = 0;
609 loff_t p;
610
611 read_type++;
612
613 switch (nvram_type_ids[read_type]) {
614 case PSTORE_TYPE_DMESG:
615 part = &oops_log_partition;
616 *type = PSTORE_TYPE_DMESG;
617 break;
618 case PSTORE_TYPE_PPC_RTAS:
619 part = &rtas_log_partition;
620 *type = PSTORE_TYPE_PPC_RTAS;
621 time->tv_sec = last_rtas_event;
622 time->tv_nsec = 0;
623 break;
624 case PSTORE_TYPE_PPC_OF:
625 sig = NVRAM_SIG_OF;
626 part = &of_config_partition;
627 *type = PSTORE_TYPE_PPC_OF;
628 *id = PSTORE_TYPE_PPC_OF;
629 time->tv_sec = 0;
630 time->tv_nsec = 0;
631 break;
632 case PSTORE_TYPE_PPC_COMMON:
633 sig = NVRAM_SIG_SYS;
634 part = &common_partition;
635 *type = PSTORE_TYPE_PPC_COMMON;
636 *id = PSTORE_TYPE_PPC_COMMON;
637 time->tv_sec = 0;
638 time->tv_nsec = 0;
639 break;
640 default:
641 return 0;
642 }
643
644 if (!part->os_partition) {
645 p = nvram_find_partition(part->name, sig, &size);
646 if (p <= 0) {
647 pr_err("nvram: Failed to find partition %s, "
648 "err %d\n", part->name, (int)p);
649 return 0;
650 }
651 part->index = p;
652 part->size = size;
653 }
654
655 buff = kmalloc(part->size, GFP_KERNEL);
656
657 if (!buff)
658 return -ENOMEM;
659
660 if (nvram_read_partition(part, buff, part->size, &err_type, &id_no)) {
661 kfree(buff);
662 return 0;
663 }
664
665 *count = 0;
666
667 if (part->os_partition)
668 *id = id_no;
669
670 if (nvram_type_ids[read_type] == PSTORE_TYPE_DMESG) {
671 size_t length, hdr_size;
672
673 oops_hdr = (struct oops_log_info *)buff;
674 if (be16_to_cpu(oops_hdr->version) < OOPS_HDR_VERSION) {
675 /* Old format oops header had 2-byte record size */
676 hdr_size = sizeof(u16);
677 length = be16_to_cpu(oops_hdr->version);
678 time->tv_sec = 0;
679 time->tv_nsec = 0;
680 } else {
681 hdr_size = sizeof(*oops_hdr);
682 length = be16_to_cpu(oops_hdr->report_length);
683 time->tv_sec = be64_to_cpu(oops_hdr->timestamp);
684 time->tv_nsec = 0;
685 }
686 *buf = kmalloc(length, GFP_KERNEL);
687 if (*buf == NULL)
688 return -ENOMEM;
689 memcpy(*buf, buff + hdr_size, length);
690 kfree(buff);
691
692 if (err_type == ERR_TYPE_KERNEL_PANIC_GZ)
693 *compressed = true;
694 else
695 *compressed = false;
696 return length;
697 }
698
699 *buf = buff;
700 return part->size;
701}
702
703static struct pstore_info nvram_pstore_info = {
704 .owner = THIS_MODULE,
705 .name = "nvram",
706 .open = nvram_pstore_open,
707 .read = nvram_pstore_read,
708 .write = nvram_pstore_write,
709};
710
711static int nvram_pstore_init(void)
712{
713 int rc = 0;
714
715 nvram_pstore_info.buf = oops_data;
716 nvram_pstore_info.bufsize = oops_data_sz;
717
718 spin_lock_init(&nvram_pstore_info.buf_lock);
719
720 rc = pstore_register(&nvram_pstore_info);
721 if (rc != 0)
722 pr_err("nvram: pstore_register() failed, defaults to "
723 "kmsg_dump; returned %d\n", rc);
724
725 return rc;
726}
727#else
728static int nvram_pstore_init(void)
729{
730 return -1;
731}
732#endif
733
734static void __init nvram_init_oops_partition(int rtas_partition_exists)
735{
736 int rc;
737
738 rc = pseries_nvram_init_os_partition(&oops_log_partition);
739 if (rc != 0) {
740 if (!rtas_partition_exists)
741 return;
742 pr_notice("nvram: Using %s partition to log both"
743 " RTAS errors and oops/panic reports\n",
744 rtas_log_partition.name);
745 memcpy(&oops_log_partition, &rtas_log_partition,
746 sizeof(rtas_log_partition));
747 }
748 oops_buf = kmalloc(oops_log_partition.size, GFP_KERNEL);
749 if (!oops_buf) {
750 pr_err("nvram: No memory for %s partition\n",
751 oops_log_partition.name);
752 return;
753 }
754 oops_data = oops_buf + sizeof(struct oops_log_info);
755 oops_data_sz = oops_log_partition.size - sizeof(struct oops_log_info);
756
757 rc = nvram_pstore_init();
758
759 if (!rc)
760 return;
761
762 /*
763 * Figure compression (preceded by elimination of each line's <n>
764 * severity prefix) will reduce the oops/panic report to at most
765 * 45% of its original size.
766 */
767 big_oops_buf_sz = (oops_data_sz * 100) / 45;
768 big_oops_buf = kmalloc(big_oops_buf_sz, GFP_KERNEL);
769 if (big_oops_buf) {
770 stream.workspace = kmalloc(zlib_deflate_workspacesize(
771 WINDOW_BITS, MEM_LEVEL), GFP_KERNEL);
772 if (!stream.workspace) {
773 pr_err("nvram: No memory for compression workspace; "
774 "skipping compression of %s partition data\n",
775 oops_log_partition.name);
776 kfree(big_oops_buf);
777 big_oops_buf = NULL;
778 }
779 } else {
780 pr_err("No memory for uncompressed %s data; "
781 "skipping compression\n", oops_log_partition.name);
782 stream.workspace = NULL;
783 }
784
785 rc = kmsg_dump_register(&nvram_kmsg_dumper);
786 if (rc != 0) {
787 pr_err("nvram: kmsg_dump_register() failed; returned %d\n", rc);
788 kfree(oops_buf);
789 kfree(big_oops_buf);
790 kfree(stream.workspace);
791 }
792}
793
794static int __init pseries_nvram_init_log_partitions(void) 207static int __init pseries_nvram_init_log_partitions(void)
795{ 208{
796 int rc; 209 int rc;
@@ -798,7 +211,7 @@ static int __init pseries_nvram_init_log_partitions(void)
798 /* Scan nvram for partitions */ 211 /* Scan nvram for partitions */
799 nvram_scan_partitions(); 212 nvram_scan_partitions();
800 213
801 rc = pseries_nvram_init_os_partition(&rtas_log_partition); 214 rc = nvram_init_os_partition(&rtas_log_partition);
802 nvram_init_oops_partition(rc == 0); 215 nvram_init_oops_partition(rc == 0);
803 return 0; 216 return 0;
804} 217}
@@ -834,72 +247,3 @@ int __init pSeries_nvram_init(void)
834 return 0; 247 return 0;
835} 248}
836 249
837
838/*
839 * This is our kmsg_dump callback, called after an oops or panic report
840 * has been written to the printk buffer. We want to capture as much
841 * of the printk buffer as possible. First, capture as much as we can
842 * that we think will compress sufficiently to fit in the lnx,oops-log
843 * partition. If that's too much, go back and capture uncompressed text.
844 */
845static void oops_to_nvram(struct kmsg_dumper *dumper,
846 enum kmsg_dump_reason reason)
847{
848 struct oops_log_info *oops_hdr = (struct oops_log_info *)oops_buf;
849 static unsigned int oops_count = 0;
850 static bool panicking = false;
851 static DEFINE_SPINLOCK(lock);
852 unsigned long flags;
853 size_t text_len;
854 unsigned int err_type = ERR_TYPE_KERNEL_PANIC_GZ;
855 int rc = -1;
856
857 switch (reason) {
858 case KMSG_DUMP_RESTART:
859 case KMSG_DUMP_HALT:
860 case KMSG_DUMP_POWEROFF:
861 /* These are almost always orderly shutdowns. */
862 return;
863 case KMSG_DUMP_OOPS:
864 break;
865 case KMSG_DUMP_PANIC:
866 panicking = true;
867 break;
868 case KMSG_DUMP_EMERG:
869 if (panicking)
870 /* Panic report already captured. */
871 return;
872 break;
873 default:
874 pr_err("%s: ignoring unrecognized KMSG_DUMP_* reason %d\n",
875 __func__, (int) reason);
876 return;
877 }
878
879 if (clobbering_unread_rtas_event())
880 return;
881
882 if (!spin_trylock_irqsave(&lock, flags))
883 return;
884
885 if (big_oops_buf) {
886 kmsg_dump_get_buffer(dumper, false,
887 big_oops_buf, big_oops_buf_sz, &text_len);
888 rc = zip_oops(text_len);
889 }
890 if (rc != 0) {
891 kmsg_dump_rewind(dumper);
892 kmsg_dump_get_buffer(dumper, false,
893 oops_data, oops_data_sz, &text_len);
894 err_type = ERR_TYPE_KERNEL_PANIC;
895 oops_hdr->version = cpu_to_be16(OOPS_HDR_VERSION);
896 oops_hdr->report_length = cpu_to_be16(text_len);
897 oops_hdr->timestamp = cpu_to_be64(get_seconds());
898 }
899
900 (void) nvram_write_os_partition(&oops_log_partition, oops_buf,
901 (int) (sizeof(*oops_hdr) + text_len), err_type,
902 ++oops_count);
903
904 spin_unlock_irqrestore(&lock, flags);
905}
diff --git a/arch/powerpc/platforms/pseries/pci_dlpar.c b/arch/powerpc/platforms/pseries/pci_dlpar.c
index 89e23811199c..5d4a3df59d0c 100644
--- a/arch/powerpc/platforms/pseries/pci_dlpar.c
+++ b/arch/powerpc/platforms/pseries/pci_dlpar.c
@@ -32,6 +32,8 @@
32#include <asm/firmware.h> 32#include <asm/firmware.h>
33#include <asm/eeh.h> 33#include <asm/eeh.h>
34 34
35#include "pseries.h"
36
35static struct pci_bus * 37static struct pci_bus *
36find_bus_among_children(struct pci_bus *bus, 38find_bus_among_children(struct pci_bus *bus,
37 struct device_node *dn) 39 struct device_node *dn)
@@ -75,6 +77,7 @@ struct pci_controller *init_phb_dynamic(struct device_node *dn)
75 return NULL; 77 return NULL;
76 rtas_setup_phb(phb); 78 rtas_setup_phb(phb);
77 pci_process_bridge_OF_ranges(phb, dn, 0); 79 pci_process_bridge_OF_ranges(phb, dn, 0);
80 phb->controller_ops = pseries_pci_controller_ops;
78 81
79 pci_devs_phb_init_dynamic(phb); 82 pci_devs_phb_init_dynamic(phb);
80 83
@@ -82,7 +85,7 @@ struct pci_controller *init_phb_dynamic(struct device_node *dn)
82 eeh_dev_phb_init_dynamic(phb); 85 eeh_dev_phb_init_dynamic(phb);
83 86
84 if (dn->child) 87 if (dn->child)
85 eeh_add_device_tree_early(dn); 88 eeh_add_device_tree_early(PCI_DN(dn));
86 89
87 pcibios_scan_phb(phb); 90 pcibios_scan_phb(phb);
88 pcibios_finish_adding_to_bus(phb->bus); 91 pcibios_finish_adding_to_bus(phb->bus);
diff --git a/arch/powerpc/platforms/pseries/pseries.h b/arch/powerpc/platforms/pseries/pseries.h
index 1796c5438cc6..8411c27293e4 100644
--- a/arch/powerpc/platforms/pseries/pseries.h
+++ b/arch/powerpc/platforms/pseries/pseries.h
@@ -11,6 +11,7 @@
11#define _PSERIES_PSERIES_H 11#define _PSERIES_PSERIES_H
12 12
13#include <linux/interrupt.h> 13#include <linux/interrupt.h>
14#include <asm/rtas.h>
14 15
15struct device_node; 16struct device_node;
16 17
@@ -60,11 +61,24 @@ extern struct device_node *dlpar_configure_connector(__be32,
60 struct device_node *); 61 struct device_node *);
61extern int dlpar_attach_node(struct device_node *); 62extern int dlpar_attach_node(struct device_node *);
62extern int dlpar_detach_node(struct device_node *); 63extern int dlpar_detach_node(struct device_node *);
64extern int dlpar_acquire_drc(u32 drc_index);
65extern int dlpar_release_drc(u32 drc_index);
66
67#ifdef CONFIG_MEMORY_HOTPLUG
68int dlpar_memory(struct pseries_hp_errorlog *hp_elog);
69#else
70static inline int dlpar_memory(struct pseries_hp_errorlog *hp_elog)
71{
72 return -EOPNOTSUPP;
73}
74#endif
63 75
64/* PCI root bridge prepare function override for pseries */ 76/* PCI root bridge prepare function override for pseries */
65struct pci_host_bridge; 77struct pci_host_bridge;
66int pseries_root_bridge_prepare(struct pci_host_bridge *bridge); 78int pseries_root_bridge_prepare(struct pci_host_bridge *bridge);
67 79
80extern struct pci_controller_ops pseries_pci_controller_ops;
81
68unsigned long pseries_memory_block_size(void); 82unsigned long pseries_memory_block_size(void);
69 83
70#endif /* _PSERIES_PSERIES_H */ 84#endif /* _PSERIES_PSERIES_H */
diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c
index e445b6701f50..df6a7041922b 100644
--- a/arch/powerpc/platforms/pseries/setup.c
+++ b/arch/powerpc/platforms/pseries/setup.c
@@ -265,7 +265,7 @@ static int pci_dn_reconfig_notifier(struct notifier_block *nb, unsigned long act
265 update_dn_pci_info(np, pci->phb); 265 update_dn_pci_info(np, pci->phb);
266 266
267 /* Create EEH device for the OF node */ 267 /* Create EEH device for the OF node */
268 eeh_dev_init(np, pci->phb); 268 eeh_dev_init(PCI_DN(np), pci->phb);
269 } 269 }
270 break; 270 break;
271 default: 271 default:
@@ -461,6 +461,47 @@ static long pseries_little_endian_exceptions(void)
461} 461}
462#endif 462#endif
463 463
464static void __init find_and_init_phbs(void)
465{
466 struct device_node *node;
467 struct pci_controller *phb;
468 struct device_node *root = of_find_node_by_path("/");
469
470 for_each_child_of_node(root, node) {
471 if (node->type == NULL || (strcmp(node->type, "pci") != 0 &&
472 strcmp(node->type, "pciex") != 0))
473 continue;
474
475 phb = pcibios_alloc_controller(node);
476 if (!phb)
477 continue;
478 rtas_setup_phb(phb);
479 pci_process_bridge_OF_ranges(phb, node, 0);
480 isa_bridge_find_early(phb);
481 phb->controller_ops = pseries_pci_controller_ops;
482 }
483
484 of_node_put(root);
485 pci_devs_phb_init();
486
487 /*
488 * PCI_PROBE_ONLY and PCI_REASSIGN_ALL_BUS can be set via properties
489 * in chosen.
490 */
491 if (of_chosen) {
492 const int *prop;
493
494 prop = of_get_property(of_chosen,
495 "linux,pci-probe-only", NULL);
496 if (prop) {
497 if (*prop)
498 pci_add_flags(PCI_PROBE_ONLY);
499 else
500 pci_clear_flags(PCI_PROBE_ONLY);
501 }
502 }
503}
504
464static void __init pSeries_setup_arch(void) 505static void __init pSeries_setup_arch(void)
465{ 506{
466 set_arch_panic_timeout(10, ARCH_PANIC_TIMEOUT); 507 set_arch_panic_timeout(10, ARCH_PANIC_TIMEOUT);
@@ -793,6 +834,10 @@ static int pSeries_pci_probe_mode(struct pci_bus *bus)
793void pSeries_final_fixup(void) { } 834void pSeries_final_fixup(void) { }
794#endif 835#endif
795 836
837struct pci_controller_ops pseries_pci_controller_ops = {
838 .probe_mode = pSeries_pci_probe_mode,
839};
840
796define_machine(pseries) { 841define_machine(pseries) {
797 .name = "pSeries", 842 .name = "pSeries",
798 .probe = pSeries_probe, 843 .probe = pSeries_probe,
@@ -801,7 +846,6 @@ define_machine(pseries) {
801 .show_cpuinfo = pSeries_show_cpuinfo, 846 .show_cpuinfo = pSeries_show_cpuinfo,
802 .log_error = pSeries_log_error, 847 .log_error = pSeries_log_error,
803 .pcibios_fixup = pSeries_final_fixup, 848 .pcibios_fixup = pSeries_final_fixup,
804 .pci_probe_mode = pSeries_pci_probe_mode,
805 .restart = rtas_restart, 849 .restart = rtas_restart,
806 .halt = rtas_halt, 850 .halt = rtas_halt,
807 .panic = rtas_os_term, 851 .panic = rtas_os_term,
diff --git a/arch/powerpc/platforms/pseries/smp.c b/arch/powerpc/platforms/pseries/smp.c
index a3555b10c1a5..6932ea803e33 100644
--- a/arch/powerpc/platforms/pseries/smp.c
+++ b/arch/powerpc/platforms/pseries/smp.c
@@ -197,16 +197,14 @@ static void pSeries_cause_ipi_mux(int cpu, unsigned long data)
197 xics_cause_ipi(cpu, data); 197 xics_cause_ipi(cpu, data);
198} 198}
199 199
200static __init int pSeries_smp_probe(void) 200static __init void pSeries_smp_probe(void)
201{ 201{
202 int ret = xics_smp_probe(); 202 xics_smp_probe();
203 203
204 if (cpu_has_feature(CPU_FTR_DBELL)) { 204 if (cpu_has_feature(CPU_FTR_DBELL)) {
205 xics_cause_ipi = smp_ops->cause_ipi; 205 xics_cause_ipi = smp_ops->cause_ipi;
206 smp_ops->cause_ipi = pSeries_cause_ipi_mux; 206 smp_ops->cause_ipi = pSeries_cause_ipi_mux;
207 } 207 }
208
209 return ret;
210} 208}
211 209
212static struct smp_ops_t pSeries_mpic_smp_ops = { 210static struct smp_ops_t pSeries_mpic_smp_ops = {
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-16 07:43:10 -0500