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authorMasato Noguchi <Masato.Noguchi@jp.sony.com>2007-12-20 02:39:59 -0500
committerPaul Mackerras <paulus@samba.org>2007-12-21 03:46:20 -0500
commit9476141c185aa131fa8b4b6ccc5c0ccf92300225 (patch)
treef3a594fa7c3945d9cd527d6df3cff30d0b2e6ab7 /arch/powerpc/platforms
parentb192541b39ed29ff82f9f2d5427f451e89617f1c (diff)
[POWERPC] spufs: don't set reserved bits in spu interrupt status
This changes the spu context switch code to not write to reserved bits of spu interrupt status register. The architecture book says the reserved fields should be set to zero. Signed-off-by: Masato Noguchi <Masato.Noguchi@jp.sony.com> Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc/platforms')
-rw-r--r--arch/powerpc/platforms/cell/spufs/switch.c20
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/powerpc/platforms/cell/spufs/switch.c b/arch/powerpc/platforms/cell/spufs/switch.c
index 1a7d7a0f66fc..6063c88c26d2 100644
--- a/arch/powerpc/platforms/cell/spufs/switch.c
+++ b/arch/powerpc/platforms/cell/spufs/switch.c
@@ -740,9 +740,9 @@ static inline void enable_interrupts(struct spu_state *csa, struct spu *spu)
740 * (translation) interrupts. 740 * (translation) interrupts.
741 */ 741 */
742 spin_lock_irq(&spu->register_lock); 742 spin_lock_irq(&spu->register_lock);
743 spu_int_stat_clear(spu, 0, ~0ul); 743 spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK);
744 spu_int_stat_clear(spu, 1, ~0ul); 744 spu_int_stat_clear(spu, 1, CLASS1_INTR_MASK);
745 spu_int_stat_clear(spu, 2, ~0ul); 745 spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK);
746 spu_int_mask_set(spu, 0, 0ul); 746 spu_int_mask_set(spu, 0, 0ul);
747 spu_int_mask_set(spu, 1, class1_mask); 747 spu_int_mask_set(spu, 1, class1_mask);
748 spu_int_mask_set(spu, 2, 0ul); 748 spu_int_mask_set(spu, 2, 0ul);
@@ -899,8 +899,8 @@ static inline void wait_tag_complete(struct spu_state *csa, struct spu *spu)
899 POLL_WHILE_FALSE(in_be32(&prob->dma_tagstatus_R) & mask); 899 POLL_WHILE_FALSE(in_be32(&prob->dma_tagstatus_R) & mask);
900 900
901 local_irq_save(flags); 901 local_irq_save(flags);
902 spu_int_stat_clear(spu, 0, ~(0ul)); 902 spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK);
903 spu_int_stat_clear(spu, 2, ~(0ul)); 903 spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK);
904 local_irq_restore(flags); 904 local_irq_restore(flags);
905} 905}
906 906
@@ -918,8 +918,8 @@ static inline void wait_spu_stopped(struct spu_state *csa, struct spu *spu)
918 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING); 918 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING);
919 919
920 local_irq_save(flags); 920 local_irq_save(flags);
921 spu_int_stat_clear(spu, 0, ~(0ul)); 921 spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK);
922 spu_int_stat_clear(spu, 2, ~(0ul)); 922 spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK);
923 local_irq_restore(flags); 923 local_irq_restore(flags);
924} 924}
925 925
@@ -1395,9 +1395,9 @@ static inline void clear_interrupts(struct spu_state *csa, struct spu *spu)
1395 spu_int_mask_set(spu, 0, 0ul); 1395 spu_int_mask_set(spu, 0, 0ul);
1396 spu_int_mask_set(spu, 1, 0ul); 1396 spu_int_mask_set(spu, 1, 0ul);
1397 spu_int_mask_set(spu, 2, 0ul); 1397 spu_int_mask_set(spu, 2, 0ul);
1398 spu_int_stat_clear(spu, 0, ~0ul); 1398 spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK);
1399 spu_int_stat_clear(spu, 1, ~0ul); 1399 spu_int_stat_clear(spu, 1, CLASS1_INTR_MASK);
1400 spu_int_stat_clear(spu, 2, ~0ul); 1400 spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK);
1401 spin_unlock_irq(&spu->register_lock); 1401 spin_unlock_irq(&spu->register_lock);
1402} 1402}
1403 1403