aboutsummaryrefslogtreecommitdiffstats
path: root/arch/powerpc/platforms
diff options
context:
space:
mode:
authorGerhard Sittig <gsi@denx.de>2013-11-30 17:51:27 -0500
committerAnatolij Gustschin <agust@denx.de>2014-01-12 12:53:04 -0500
commit7d71d5b2e80623242b0c0823ce6cb635d089c8b2 (patch)
treee3bb8e7e73deb9d0a3463d89d1d46de85957b678 /arch/powerpc/platforms
parent124fe7c561ecba872f67b686e976e5c557fb52d5 (diff)
clk: mpc5xxx: switch to COMMON_CLK, retire PPC_CLOCK
the setup before the change was - arch/powerpc/Kconfig had the PPC_CLOCK option, off by default - depending on the PPC_CLOCK option the arch/powerpc/kernel/clock.c file was built, which implements the clk.h API but always returns -ENOSYS unless a platform registers specific callbacks - the MPC52xx platform selected PPC_CLOCK but did not register any callbacks, thus all clk.h API calls keep resulting in -ENOSYS errors (which is OK, all peripheral drivers deal with the situation) - the MPC512x platform selected PPC_CLOCK and registered specific callbacks implemented in arch/powerpc/platforms/512x/clock.c, thus provided real support for the clock API - no other powerpc platform did select PPC_CLOCK the situation after the change is - the MPC512x platform implements the COMMON_CLK interface, and thus the PPC_CLOCK approach in arch/powerpc/platforms/512x/clock.c has become obsolete - the MPC52xx platform still lacks genuine support for the clk.h API while this is not a change against the previous situation (the error code returned from COMMON_CLK stubs differs but every call still results in an error) - with all references gone, the arch/powerpc/kernel/clock.c wrapper and the PPC_CLOCK option have become obsolete, as did the clk_interface.h header file the switch from PPC_CLOCK to COMMON_CLK is done for all platforms within the same commit such that multiplatform kernels (the combination of 512x and 52xx within one executable) keep working Cc: Mike Turquette <mturquette@linaro.org> Cc: Anatolij Gustschin <agust@denx.de> Cc: linux-arm-kernel@lists.infradead.org Cc: linuxppc-dev@lists.ozlabs.org Signed-off-by: Gerhard Sittig <gsi@denx.de> Signed-off-by: Anatolij Gustschin <agust@denx.de>
Diffstat (limited to 'arch/powerpc/platforms')
-rw-r--r--arch/powerpc/platforms/512x/Kconfig2
-rw-r--r--arch/powerpc/platforms/512x/Makefile1
-rw-r--r--arch/powerpc/platforms/512x/clock.c754
-rw-r--r--arch/powerpc/platforms/52xx/Kconfig2
4 files changed, 2 insertions, 757 deletions
diff --git a/arch/powerpc/platforms/512x/Kconfig b/arch/powerpc/platforms/512x/Kconfig
index fc9c1cbfcb1d..5aa3f4b5332c 100644
--- a/arch/powerpc/platforms/512x/Kconfig
+++ b/arch/powerpc/platforms/512x/Kconfig
@@ -1,9 +1,9 @@
1config PPC_MPC512x 1config PPC_MPC512x
2 bool "512x-based boards" 2 bool "512x-based boards"
3 depends on 6xx 3 depends on 6xx
4 select COMMON_CLK
4 select FSL_SOC 5 select FSL_SOC
5 select IPIC 6 select IPIC
6 select PPC_CLOCK
7 select PPC_PCI_CHOICE 7 select PPC_PCI_CHOICE
8 select FSL_PCI if PCI 8 select FSL_PCI if PCI
9 select ARCH_WANT_OPTIONAL_GPIOLIB 9 select ARCH_WANT_OPTIONAL_GPIOLIB
diff --git a/arch/powerpc/platforms/512x/Makefile b/arch/powerpc/platforms/512x/Makefile
index 1e05f9def8a4..01693121a2b1 100644
--- a/arch/powerpc/platforms/512x/Makefile
+++ b/arch/powerpc/platforms/512x/Makefile
@@ -1,7 +1,6 @@
1# 1#
2# Makefile for the Freescale PowerPC 512x linux kernel. 2# Makefile for the Freescale PowerPC 512x linux kernel.
3# 3#
4obj-$(CONFIG_PPC_CLOCK) += clock.o
5obj-$(CONFIG_COMMON_CLK) += clock-commonclk.o 4obj-$(CONFIG_COMMON_CLK) += clock-commonclk.o
6obj-y += mpc512x_shared.o 5obj-y += mpc512x_shared.o
7obj-$(CONFIG_MPC5121_ADS) += mpc5121_ads.o mpc5121_ads_cpld.o 6obj-$(CONFIG_MPC5121_ADS) += mpc5121_ads.o mpc5121_ads_cpld.o
diff --git a/arch/powerpc/platforms/512x/clock.c b/arch/powerpc/platforms/512x/clock.c
deleted file mode 100644
index fd8a37653417..000000000000
--- a/arch/powerpc/platforms/512x/clock.c
+++ /dev/null
@@ -1,754 +0,0 @@
1/*
2 * Copyright (C) 2007,2008 Freescale Semiconductor, Inc. All rights reserved.
3 *
4 * Author: John Rigby <jrigby@freescale.com>
5 *
6 * Implements the clk api defined in include/linux/clk.h
7 *
8 * Original based on linux/arch/arm/mach-integrator/clock.c
9 *
10 * Copyright (C) 2004 ARM Limited.
11 * Written by Deep Blue Solutions Limited.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17#include <linux/kernel.h>
18#include <linux/list.h>
19#include <linux/errno.h>
20#include <linux/err.h>
21#include <linux/module.h>
22#include <linux/string.h>
23#include <linux/clk.h>
24#include <linux/mutex.h>
25#include <linux/io.h>
26
27#include <linux/of_address.h>
28#include <linux/of_platform.h>
29#include <asm/mpc5xxx.h>
30#include <asm/mpc5121.h>
31#include <asm/clk_interface.h>
32
33#include "mpc512x.h"
34
35#undef CLK_DEBUG
36
37static int clocks_initialized;
38
39#define CLK_HAS_RATE 0x1 /* has rate in MHz */
40#define CLK_HAS_CTRL 0x2 /* has control reg and bit */
41
42struct clk {
43 struct list_head node;
44 char name[32];
45 int flags;
46 struct device *dev;
47 unsigned long rate;
48 struct module *owner;
49 void (*calc) (struct clk *);
50 struct clk *parent;
51 int reg, bit; /* CLK_HAS_CTRL */
52 int div_shift; /* only used by generic_div_clk_calc */
53};
54
55static LIST_HEAD(clocks);
56static DEFINE_MUTEX(clocks_mutex);
57
58static struct clk *mpc5121_clk_get(struct device *dev, const char *id)
59{
60 struct clk *p, *clk = ERR_PTR(-ENOENT);
61 int dev_match;
62 int id_match;
63
64 if (dev == NULL || id == NULL)
65 return clk;
66
67 mutex_lock(&clocks_mutex);
68 list_for_each_entry(p, &clocks, node) {
69 dev_match = id_match = 0;
70
71 if (dev == p->dev)
72 dev_match++;
73 if (strcmp(id, p->name) == 0)
74 id_match++;
75 if ((dev_match || id_match) && try_module_get(p->owner)) {
76 clk = p;
77 break;
78 }
79 }
80 mutex_unlock(&clocks_mutex);
81
82 return clk;
83}
84
85#ifdef CLK_DEBUG
86static void dump_clocks(void)
87{
88 struct clk *p;
89
90 mutex_lock(&clocks_mutex);
91 printk(KERN_INFO "CLOCKS:\n");
92 list_for_each_entry(p, &clocks, node) {
93 pr_info(" %s=%ld", p->name, p->rate);
94 if (p->parent)
95 pr_cont(" %s=%ld", p->parent->name,
96 p->parent->rate);
97 if (p->flags & CLK_HAS_CTRL)
98 pr_cont(" reg/bit=%d/%d", p->reg, p->bit);
99 pr_cont("\n");
100 }
101 mutex_unlock(&clocks_mutex);
102}
103#define DEBUG_CLK_DUMP() dump_clocks()
104#else
105#define DEBUG_CLK_DUMP()
106#endif
107
108
109static void mpc5121_clk_put(struct clk *clk)
110{
111 module_put(clk->owner);
112}
113
114#define NRPSC 12
115
116struct mpc512x_clockctl {
117 u32 spmr; /* System PLL Mode Reg */
118 u32 sccr[2]; /* System Clk Ctrl Reg 1 & 2 */
119 u32 scfr1; /* System Clk Freq Reg 1 */
120 u32 scfr2; /* System Clk Freq Reg 2 */
121 u32 reserved;
122 u32 bcr; /* Bread Crumb Reg */
123 u32 pccr[NRPSC]; /* PSC Clk Ctrl Reg 0-11 */
124 u32 spccr; /* SPDIF Clk Ctrl Reg */
125 u32 cccr; /* CFM Clk Ctrl Reg */
126 u32 dccr; /* DIU Clk Cnfg Reg */
127};
128
129static struct mpc512x_clockctl __iomem *clockctl;
130
131static int mpc5121_clk_enable(struct clk *clk)
132{
133 unsigned int mask;
134
135 if (clk->flags & CLK_HAS_CTRL) {
136 mask = in_be32(&clockctl->sccr[clk->reg]);
137 mask |= 1 << clk->bit;
138 out_be32(&clockctl->sccr[clk->reg], mask);
139 }
140 return 0;
141}
142
143static void mpc5121_clk_disable(struct clk *clk)
144{
145 unsigned int mask;
146
147 if (clk->flags & CLK_HAS_CTRL) {
148 mask = in_be32(&clockctl->sccr[clk->reg]);
149 mask &= ~(1 << clk->bit);
150 out_be32(&clockctl->sccr[clk->reg], mask);
151 }
152}
153
154static unsigned long mpc5121_clk_get_rate(struct clk *clk)
155{
156 if (clk->flags & CLK_HAS_RATE)
157 return clk->rate;
158 else
159 return 0;
160}
161
162static long mpc5121_clk_round_rate(struct clk *clk, unsigned long rate)
163{
164 return rate;
165}
166
167static int mpc5121_clk_set_rate(struct clk *clk, unsigned long rate)
168{
169 return 0;
170}
171
172static int clk_register(struct clk *clk)
173{
174 mutex_lock(&clocks_mutex);
175 list_add(&clk->node, &clocks);
176 mutex_unlock(&clocks_mutex);
177 return 0;
178}
179
180static unsigned long spmf_mult(void)
181{
182 /*
183 * Convert spmf to multiplier
184 */
185 static int spmf_to_mult[] = {
186 68, 1, 12, 16,
187 20, 24, 28, 32,
188 36, 40, 44, 48,
189 52, 56, 60, 64
190 };
191 int spmf = (in_be32(&clockctl->spmr) >> 24) & 0xf;
192 return spmf_to_mult[spmf];
193}
194
195static unsigned long sysdiv_div_x_2(void)
196{
197 /*
198 * Convert sysdiv to divisor x 2
199 * Some divisors have fractional parts so
200 * multiply by 2 then divide by this value
201 */
202 static int sysdiv_to_div_x_2[] = {
203 4, 5, 6, 7,
204 8, 9, 10, 14,
205 12, 16, 18, 22,
206 20, 24, 26, 30,
207 28, 32, 34, 38,
208 36, 40, 42, 46,
209 44, 48, 50, 54,
210 52, 56, 58, 62,
211 60, 64, 66,
212 };
213 int sysdiv = (in_be32(&clockctl->scfr2) >> 26) & 0x3f;
214 return sysdiv_to_div_x_2[sysdiv];
215}
216
217static unsigned long ref_to_sys(unsigned long rate)
218{
219 rate *= spmf_mult();
220 rate *= 2;
221 rate /= sysdiv_div_x_2();
222
223 return rate;
224}
225
226static unsigned long sys_to_ref(unsigned long rate)
227{
228 rate *= sysdiv_div_x_2();
229 rate /= 2;
230 rate /= spmf_mult();
231
232 return rate;
233}
234
235static long ips_to_ref(unsigned long rate)
236{
237 int ips_div = (in_be32(&clockctl->scfr1) >> 23) & 0x7;
238
239 rate *= ips_div; /* csb_clk = ips_clk * ips_div */
240 rate *= 2; /* sys_clk = csb_clk * 2 */
241 return sys_to_ref(rate);
242}
243
244static unsigned long devtree_getfreq(char *clockname)
245{
246 struct device_node *np;
247 const unsigned int *prop;
248 unsigned int val = 0;
249
250 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-immr");
251 if (np) {
252 prop = of_get_property(np, clockname, NULL);
253 if (prop)
254 val = *prop;
255 of_node_put(np);
256 }
257 return val;
258}
259
260static void ref_clk_calc(struct clk *clk)
261{
262 unsigned long rate;
263
264 rate = devtree_getfreq("bus-frequency");
265 if (rate == 0) {
266 printk(KERN_ERR "No bus-frequency in dev tree\n");
267 clk->rate = 0;
268 return;
269 }
270 clk->rate = ips_to_ref(rate);
271}
272
273static struct clk ref_clk = {
274 .name = "ref_clk",
275 .calc = ref_clk_calc,
276};
277
278
279static void sys_clk_calc(struct clk *clk)
280{
281 clk->rate = ref_to_sys(ref_clk.rate);
282}
283
284static struct clk sys_clk = {
285 .name = "sys_clk",
286 .calc = sys_clk_calc,
287};
288
289static void diu_clk_calc(struct clk *clk)
290{
291 int diudiv_x_2 = in_be32(&clockctl->scfr1) & 0xff;
292 unsigned long rate;
293
294 rate = sys_clk.rate;
295
296 rate *= 2;
297 rate /= diudiv_x_2;
298
299 clk->rate = rate;
300}
301
302static void viu_clk_calc(struct clk *clk)
303{
304 unsigned long rate;
305
306 rate = sys_clk.rate;
307 rate /= 2;
308 clk->rate = rate;
309}
310
311static void half_clk_calc(struct clk *clk)
312{
313 clk->rate = clk->parent->rate / 2;
314}
315
316static void generic_div_clk_calc(struct clk *clk)
317{
318 int div = (in_be32(&clockctl->scfr1) >> clk->div_shift) & 0x7;
319
320 clk->rate = clk->parent->rate / div;
321}
322
323static void unity_clk_calc(struct clk *clk)
324{
325 clk->rate = clk->parent->rate;
326}
327
328static struct clk csb_clk = {
329 .name = "csb_clk",
330 .calc = half_clk_calc,
331 .parent = &sys_clk,
332};
333
334static void e300_clk_calc(struct clk *clk)
335{
336 int spmf = (in_be32(&clockctl->spmr) >> 16) & 0xf;
337 int ratex2 = clk->parent->rate * spmf;
338
339 clk->rate = ratex2 / 2;
340}
341
342static struct clk e300_clk = {
343 .name = "e300_clk",
344 .calc = e300_clk_calc,
345 .parent = &csb_clk,
346};
347
348static struct clk ips_clk = {
349 .name = "ips_clk",
350 .calc = generic_div_clk_calc,
351 .parent = &csb_clk,
352 .div_shift = 23,
353};
354
355/*
356 * Clocks controlled by SCCR1 (.reg = 0)
357 */
358static struct clk lpc_clk = {
359 .name = "lpc_clk",
360 .flags = CLK_HAS_CTRL,
361 .reg = 0,
362 .bit = 30,
363 .calc = generic_div_clk_calc,
364 .parent = &ips_clk,
365 .div_shift = 11,
366};
367
368static struct clk nfc_clk = {
369 .name = "nfc_clk",
370 .flags = CLK_HAS_CTRL,
371 .reg = 0,
372 .bit = 29,
373 .calc = generic_div_clk_calc,
374 .parent = &ips_clk,
375 .div_shift = 8,
376};
377
378static struct clk pata_clk = {
379 .name = "pata_clk",
380 .flags = CLK_HAS_CTRL,
381 .reg = 0,
382 .bit = 28,
383 .calc = unity_clk_calc,
384 .parent = &ips_clk,
385};
386
387/*
388 * PSC clocks (bits 27 - 16)
389 * are setup elsewhere
390 */
391
392static struct clk sata_clk = {
393 .name = "sata_clk",
394 .flags = CLK_HAS_CTRL,
395 .reg = 0,
396 .bit = 14,
397 .calc = unity_clk_calc,
398 .parent = &ips_clk,
399};
400
401static struct clk fec_clk = {
402 .name = "fec_clk",
403 .flags = CLK_HAS_CTRL,
404 .reg = 0,
405 .bit = 13,
406 .calc = unity_clk_calc,
407 .parent = &ips_clk,
408};
409
410static struct clk pci_clk = {
411 .name = "pci_clk",
412 .flags = CLK_HAS_CTRL,
413 .reg = 0,
414 .bit = 11,
415 .calc = generic_div_clk_calc,
416 .parent = &csb_clk,
417 .div_shift = 20,
418};
419
420/*
421 * Clocks controlled by SCCR2 (.reg = 1)
422 */
423static struct clk diu_clk = {
424 .name = "diu_clk",
425 .flags = CLK_HAS_CTRL,
426 .reg = 1,
427 .bit = 31,
428 .calc = diu_clk_calc,
429};
430
431static struct clk viu_clk = {
432 .name = "viu_clk",
433 .flags = CLK_HAS_CTRL,
434 .reg = 1,
435 .bit = 18,
436 .calc = viu_clk_calc,
437};
438
439static struct clk axe_clk = {
440 .name = "axe_clk",
441 .flags = CLK_HAS_CTRL,
442 .reg = 1,
443 .bit = 30,
444 .calc = unity_clk_calc,
445 .parent = &csb_clk,
446};
447
448static struct clk usb1_clk = {
449 .name = "usb1_clk",
450 .flags = CLK_HAS_CTRL,
451 .reg = 1,
452 .bit = 28,
453 .calc = unity_clk_calc,
454 .parent = &csb_clk,
455};
456
457static struct clk usb2_clk = {
458 .name = "usb2_clk",
459 .flags = CLK_HAS_CTRL,
460 .reg = 1,
461 .bit = 27,
462 .calc = unity_clk_calc,
463 .parent = &csb_clk,
464};
465
466static struct clk i2c_clk = {
467 .name = "i2c_clk",
468 .flags = CLK_HAS_CTRL,
469 .reg = 1,
470 .bit = 26,
471 .calc = unity_clk_calc,
472 .parent = &ips_clk,
473};
474
475static struct clk mscan_clk = {
476 .name = "mscan_clk",
477 .flags = CLK_HAS_CTRL,
478 .reg = 1,
479 .bit = 25,
480 .calc = unity_clk_calc,
481 .parent = &ips_clk,
482};
483
484static struct clk sdhc_clk = {
485 .name = "sdhc_clk",
486 .flags = CLK_HAS_CTRL,
487 .reg = 1,
488 .bit = 24,
489 .calc = unity_clk_calc,
490 .parent = &ips_clk,
491};
492
493static struct clk mbx_bus_clk = {
494 .name = "mbx_bus_clk",
495 .flags = CLK_HAS_CTRL,
496 .reg = 1,
497 .bit = 22,
498 .calc = half_clk_calc,
499 .parent = &csb_clk,
500};
501
502static struct clk mbx_clk = {
503 .name = "mbx_clk",
504 .flags = CLK_HAS_CTRL,
505 .reg = 1,
506 .bit = 21,
507 .calc = unity_clk_calc,
508 .parent = &csb_clk,
509};
510
511static struct clk mbx_3d_clk = {
512 .name = "mbx_3d_clk",
513 .flags = CLK_HAS_CTRL,
514 .reg = 1,
515 .bit = 20,
516 .calc = generic_div_clk_calc,
517 .parent = &mbx_bus_clk,
518 .div_shift = 14,
519};
520
521static void psc_mclk_in_calc(struct clk *clk)
522{
523 clk->rate = devtree_getfreq("psc_mclk_in");
524 if (!clk->rate)
525 clk->rate = 25000000;
526}
527
528static struct clk psc_mclk_in = {
529 .name = "psc_mclk_in",
530 .calc = psc_mclk_in_calc,
531};
532
533static struct clk spdif_txclk = {
534 .name = "spdif_txclk",
535 .flags = CLK_HAS_CTRL,
536 .reg = 1,
537 .bit = 23,
538};
539
540static struct clk spdif_rxclk = {
541 .name = "spdif_rxclk",
542 .flags = CLK_HAS_CTRL,
543 .reg = 1,
544 .bit = 23,
545};
546
547static void ac97_clk_calc(struct clk *clk)
548{
549 /* ac97 bit clock is always 24.567 MHz */
550 clk->rate = 24567000;
551}
552
553static struct clk ac97_clk = {
554 .name = "ac97_clk_in",
555 .calc = ac97_clk_calc,
556};
557
558static struct clk *rate_clks[] = {
559 &ref_clk,
560 &sys_clk,
561 &diu_clk,
562 &viu_clk,
563 &csb_clk,
564 &e300_clk,
565 &ips_clk,
566 &fec_clk,
567 &sata_clk,
568 &pata_clk,
569 &nfc_clk,
570 &lpc_clk,
571 &mbx_bus_clk,
572 &mbx_clk,
573 &mbx_3d_clk,
574 &axe_clk,
575 &usb1_clk,
576 &usb2_clk,
577 &i2c_clk,
578 &mscan_clk,
579 &sdhc_clk,
580 &pci_clk,
581 &psc_mclk_in,
582 &spdif_txclk,
583 &spdif_rxclk,
584 &ac97_clk,
585 NULL
586};
587
588static void rate_clk_init(struct clk *clk)
589{
590 if (clk->calc) {
591 clk->calc(clk);
592 clk->flags |= CLK_HAS_RATE;
593 clk_register(clk);
594 } else {
595 printk(KERN_WARNING
596 "Could not initialize clk %s without a calc routine\n",
597 clk->name);
598 }
599}
600
601static void rate_clks_init(void)
602{
603 struct clk **cpp, *clk;
604
605 cpp = rate_clks;
606 while ((clk = *cpp++))
607 rate_clk_init(clk);
608}
609
610/*
611 * There are two clk enable registers with 32 enable bits each
612 * psc clocks and device clocks are all stored in dev_clks
613 */
614static struct clk dev_clks[2][32];
615
616/*
617 * Given a psc number return the dev_clk
618 * associated with it
619 */
620static struct clk *psc_dev_clk(int pscnum)
621{
622 int reg, bit;
623 struct clk *clk;
624
625 reg = 0;
626 bit = 27 - pscnum;
627
628 clk = &dev_clks[reg][bit];
629 clk->reg = 0;
630 clk->bit = bit;
631 return clk;
632}
633
634/*
635 * PSC clock rate calculation
636 */
637static void psc_calc_rate(struct clk *clk, int pscnum, struct device_node *np)
638{
639 unsigned long mclk_src = sys_clk.rate;
640 unsigned long mclk_div;
641
642 /*
643 * Can only change value of mclk divider
644 * when the divider is disabled.
645 *
646 * Zero is not a valid divider so minimum
647 * divider is 1
648 *
649 * disable/set divider/enable
650 */
651 out_be32(&clockctl->pccr[pscnum], 0);
652 out_be32(&clockctl->pccr[pscnum], 0x00020000);
653 out_be32(&clockctl->pccr[pscnum], 0x00030000);
654
655 if (in_be32(&clockctl->pccr[pscnum]) & 0x80) {
656 clk->rate = spdif_rxclk.rate;
657 return;
658 }
659
660 switch ((in_be32(&clockctl->pccr[pscnum]) >> 14) & 0x3) {
661 case 0:
662 mclk_src = sys_clk.rate;
663 break;
664 case 1:
665 mclk_src = ref_clk.rate;
666 break;
667 case 2:
668 mclk_src = psc_mclk_in.rate;
669 break;
670 case 3:
671 mclk_src = spdif_txclk.rate;
672 break;
673 }
674
675 mclk_div = ((in_be32(&clockctl->pccr[pscnum]) >> 17) & 0x7fff) + 1;
676 clk->rate = mclk_src / mclk_div;
677}
678
679/*
680 * Find all psc nodes in device tree and assign a clock
681 * with name "psc%d_mclk" and dev pointing at the device
682 * returned from of_find_device_by_node
683 */
684static void psc_clks_init(void)
685{
686 struct device_node *np;
687 struct platform_device *ofdev;
688 u32 reg;
689 const char *psc_compat;
690
691 psc_compat = mpc512x_select_psc_compat();
692 if (!psc_compat)
693 return;
694
695 for_each_compatible_node(np, NULL, psc_compat) {
696 if (!of_property_read_u32(np, "reg", &reg)) {
697 int pscnum = (reg & 0xf00) >> 8;
698 struct clk *clk = psc_dev_clk(pscnum);
699
700 clk->flags = CLK_HAS_RATE | CLK_HAS_CTRL;
701 ofdev = of_find_device_by_node(np);
702 clk->dev = &ofdev->dev;
703 /*
704 * AC97 is special rate clock does
705 * not go through normal path
706 */
707 if (of_device_is_compatible(np, "fsl,mpc5121-psc-ac97"))
708 clk->rate = ac97_clk.rate;
709 else
710 psc_calc_rate(clk, pscnum, np);
711 sprintf(clk->name, "psc%d_mclk", pscnum);
712 clk_register(clk);
713 clk_enable(clk);
714 }
715 }
716}
717
718static struct clk_interface mpc5121_clk_functions = {
719 .clk_get = mpc5121_clk_get,
720 .clk_enable = mpc5121_clk_enable,
721 .clk_disable = mpc5121_clk_disable,
722 .clk_get_rate = mpc5121_clk_get_rate,
723 .clk_put = mpc5121_clk_put,
724 .clk_round_rate = mpc5121_clk_round_rate,
725 .clk_set_rate = mpc5121_clk_set_rate,
726 .clk_set_parent = NULL,
727 .clk_get_parent = NULL,
728};
729
730int __init mpc5121_clk_init(void)
731{
732 struct device_node *np;
733
734 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-clock");
735 if (np) {
736 clockctl = of_iomap(np, 0);
737 of_node_put(np);
738 }
739
740 if (!clockctl) {
741 printk(KERN_ERR "Could not map clock control registers\n");
742 return 0;
743 }
744
745 rate_clks_init();
746 psc_clks_init();
747
748 /* leave clockctl mapped forever */
749 /*iounmap(clockctl); */
750 DEBUG_CLK_DUMP();
751 clocks_initialized++;
752 clk_functions = mpc5121_clk_functions;
753 return 0;
754}
diff --git a/arch/powerpc/platforms/52xx/Kconfig b/arch/powerpc/platforms/52xx/Kconfig
index af54174801f7..b625a2c6f4f2 100644
--- a/arch/powerpc/platforms/52xx/Kconfig
+++ b/arch/powerpc/platforms/52xx/Kconfig
@@ -1,7 +1,7 @@
1config PPC_MPC52xx 1config PPC_MPC52xx
2 bool "52xx-based boards" 2 bool "52xx-based boards"
3 depends on 6xx 3 depends on 6xx
4 select PPC_CLOCK 4 select COMMON_CLK
5 select PPC_PCI_CHOICE 5 select PPC_PCI_CHOICE
6 6
7config PPC_MPC5200_SIMPLE 7config PPC_MPC5200_SIMPLE
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-16 20:26:51 -0400