[POWERPC] 4xx: EP405 boards support for arch/powerpc

Brings EP405 support to arch/powerpc. The IRQ routing for the CPLD
comes from a device-tree property, PCI is working to the point where
I can see the video card, USB device, and south bridge.

This should work with both EP405 and EP405PC.

I've not totally figured out how IRQs are wired on this hardware
though, thus at this stage, expect only USB interrupts working,
pretty much the same as what arch/ppc did.

Also, the flash, nvram, rtc and temp control still have to be wired.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>

3 files changed, 133 insertions, 14 deletions

diff --git a/arch/powerpc/platforms/40x/Kconfig b/arch/powerpc/platforms/40x/Kconfig
index 8f6699fcc145..b8f0a6c16486 100644
--- a/arch/powerpc/platforms/40x/Kconfig
+++ b/arch/powerpc/platforms/40x/Kconfig
@@ -14,20 +14,14 @@
 #       help
 #         This option enables support for the CPCI405 board.
 
-#config EP405
-#       bool "EP405/EP405PC"
-#       depends on 40x
-#       default n
-#       select 405GP
-#       help
-#         This option enables support for the EP405/EP405PC boards.
-
-#config EP405PC
-#       bool "EP405PC Support"
-#       depends on EP405
-#       default y
-#       help
-#         This option enables support for the extra features of the EP405PC board.
+config EP405
+        bool "EP405/EP405PC"
+        depends on 40x
+        default n
+        select 405GP
+        select PCI
+        help
+          This option enables support for the EP405/EP405PC boards.
 
 config KILAUEA
         bool "Kilauea"
diff --git a/arch/powerpc/platforms/40x/Makefile b/arch/powerpc/platforms/40x/Makefile
index 51dadeee6fc6..0f42fd481c77 100644
--- a/arch/powerpc/platforms/40x/Makefile
+++ b/arch/powerpc/platforms/40x/Makefile
@@ -1,3 +1,4 @@
 obj-$(CONFIG_KILAUEA)                           += kilauea.o
 obj-$(CONFIG_WALNUT)                            += walnut.o
 obj-$(CONFIG_XILINX_VIRTEX_GENERIC_BOARD)       += virtex.o
+obj-$(CONFIG_EP405)                             += ep405.o
diff --git a/arch/powerpc/platforms/40x/ep405.c b/arch/powerpc/platforms/40x/ep405.c
new file mode 100644
index 000000000000..ba84a41e63e6
--- /dev/null
+++ b/arch/powerpc/platforms/40x/ep405.c
@@ -0,0 +1,124 @@
+/*
+ * Architecture- / platform-specific boot-time initialization code for
+ * IBM PowerPC 4xx based boards. Adapted from original
+ * code by Gary Thomas, Cort Dougan <cort@fsmlabs.com>, and Dan Malek
+ * <dan@net4x.com>.
+ *
+ * Copyright(c) 1999-2000 Grant Erickson <grant@lcse.umn.edu>
+ *
+ * Rewritten and ported to the merged powerpc tree:
+ * Copyright 2007 IBM Corporation
+ * Josh Boyer <jwboyer@linux.vnet.ibm.com>
+ *
+ * Adapted to EP405 by Ben. Herrenschmidt <benh@kernel.crashing.org>
+ *
+ * TODO: Wire up the PCI IRQ mux and the southbridge interrupts
+ *
+ * 2002 (c) MontaVista, Software, Inc.  This file is licensed under
+ * the terms of the GNU General Public License version 2.  This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#include <linux/init.h>
+#include <linux/of_platform.h>
+
+#include <asm/machdep.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/time.h>
+#include <asm/uic.h>
+#include <asm/pci-bridge.h>
+
+static struct device_node *bcsr_node;
+static void __iomem *bcsr_regs;
+
+/* BCSR registers  */
+#define BCSR_ID                 0
+#define BCSR_PCI_CTRL           1
+#define BCSR_FLASH_NV_POR_CTRL  2
+#define BCSR_FENET_UART_CTRL    3
+#define BCSR_PCI_IRQ            4
+#define BCSR_XIRQ_SELECT        5
+#define BCSR_XIRQ_ROUTING       6
+#define BCSR_XIRQ_STATUS        7
+#define BCSR_XIRQ_STATUS2       8
+#define BCSR_SW_STAT_LED_CTRL   9
+#define BCSR_GPIO_IRQ_PAR_CTRL  10
+/* there's more, can't be bothered typing them tho */
+
+
+static struct of_device_id ep405_of_bus[] = {
+        { .compatible = "ibm,plb3", },
+        { .compatible = "ibm,opb", },
+        { .compatible = "ibm,ebc", },
+        {},
+};
+
+static int __init ep405_device_probe(void)
+{
+        if (!machine_is(ep405))
+                return 0;
+
+        of_platform_bus_probe(NULL, ep405_of_bus, NULL);
+
+        return 0;
+}
+device_initcall(ep405_device_probe);
+
+static void __init ep405_init_bcsr(void)
+{
+        const u8 *irq_routing;
+        int i;
+
+        /* Find the bloody thing & map it */
+        bcsr_node = of_find_compatible_node(NULL, NULL, "ep405-bcsr");
+        if (bcsr_node == NULL) {
+                printk(KERN_ERR "EP405 BCSR not found !\n");
+                return;
+        }
+        bcsr_regs = of_iomap(bcsr_node, 0);
+        if (bcsr_regs == NULL) {
+                printk(KERN_ERR "EP405 BCSR failed to map !\n");
+                return;
+        }
+
+        /* Get the irq-routing property and apply the routing to the CPLD */
+        irq_routing = of_get_property(bcsr_node, "irq-routing", NULL);
+        if (irq_routing == NULL)
+                return;
+        for (i = 0; i < 16; i++) {
+                u8 irq = irq_routing[i];
+                out_8(bcsr_regs + BCSR_XIRQ_SELECT, i);
+                out_8(bcsr_regs + BCSR_XIRQ_ROUTING, irq);
+        }
+        in_8(bcsr_regs + BCSR_XIRQ_SELECT);
+        mb();
+        out_8(bcsr_regs + BCSR_GPIO_IRQ_PAR_CTRL, 0xfe);
+}
+
+static void __init ep405_setup_arch(void)
+{
+        /* Find & init the BCSR CPLD */
+        ep405_init_bcsr();
+}
+
+static int __init ep405_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+
+        if (!of_flat_dt_is_compatible(root, "ep405"))
+                return 0;
+
+        return 1;
+}
+
+define_machine(ep405) {
+        .name                   = "EP405",
+        .probe                  = ep405_probe,
+        .setup_arch             = ep405_setup_arch,
+        .progress               = udbg_progress,
+        .init_IRQ               = uic_init_tree,
+        .get_irq                = uic_get_irq,
+        .calibrate_decr         = generic_calibrate_decr,
+};