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authorKevin Hao <haokexin@gmail.com>2013-09-25 21:42:26 -0400
committerScott Wood <scottwood@freescale.com>2013-10-28 22:11:20 -0400
commit512e267f3594b5a3b4937a00666241cb994ef55a (patch)
tree1c5257bd43a9d1a535d621d4fade43c3e2254b2a /arch/powerpc/platforms
parent8f4a9e525a91d5903165167f1a7dbb22e97edcd0 (diff)
powerpc/85xx: introduce corenet_generic machine
In the current kernel, the board files for p2041rdb, p3041ds, p4080ds, p5020ds, p5040ds, t4240qds and b4qds are almost the same except the machine name. So this introduces a cornet_generic machine to support all these boards to avoid the code duplication. With these changes the file corenet_ds.h becomes useless. Just delete it. Signed-off-by: Kevin Hao <haokexin@gmail.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'arch/powerpc/platforms')
-rw-r--r--arch/powerpc/platforms/85xx/Kconfig10
-rw-r--r--arch/powerpc/platforms/85xx/Makefile8
-rw-r--r--arch/powerpc/platforms/85xx/b4_qds.c97
-rw-r--r--arch/powerpc/platforms/85xx/corenet_ds.c86
-rw-r--r--arch/powerpc/platforms/85xx/corenet_ds.h19
-rw-r--r--arch/powerpc/platforms/85xx/p2041_rdb.c87
-rw-r--r--arch/powerpc/platforms/85xx/p3041_ds.c89
-rw-r--r--arch/powerpc/platforms/85xx/p4080_ds.c87
-rw-r--r--arch/powerpc/platforms/85xx/p5020_ds.c93
-rw-r--r--arch/powerpc/platforms/85xx/p5040_ds.c84
-rw-r--r--arch/powerpc/platforms/85xx/t4240_qds.c93
11 files changed, 97 insertions, 656 deletions
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index de2eb9320993..3bee94398ec3 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -228,6 +228,7 @@ config P2041_RDB
228 select GPIO_MPC8XXX 228 select GPIO_MPC8XXX
229 select HAS_RAPIDIO 229 select HAS_RAPIDIO
230 select PPC_EPAPR_HV_PIC 230 select PPC_EPAPR_HV_PIC
231 select CORENET_GENERIC
231 help 232 help
232 This option enables support for the P2041 RDB board 233 This option enables support for the P2041 RDB board
233 234
@@ -241,6 +242,7 @@ config P3041_DS
241 select GPIO_MPC8XXX 242 select GPIO_MPC8XXX
242 select HAS_RAPIDIO 243 select HAS_RAPIDIO
243 select PPC_EPAPR_HV_PIC 244 select PPC_EPAPR_HV_PIC
245 select CORENET_GENERIC
244 help 246 help
245 This option enables support for the P3041 DS board 247 This option enables support for the P3041 DS board
246 248
@@ -254,6 +256,7 @@ config P4080_DS
254 select GPIO_MPC8XXX 256 select GPIO_MPC8XXX
255 select HAS_RAPIDIO 257 select HAS_RAPIDIO
256 select PPC_EPAPR_HV_PIC 258 select PPC_EPAPR_HV_PIC
259 select CORENET_GENERIC
257 help 260 help
258 This option enables support for the P4080 DS board 261 This option enables support for the P4080 DS board
259 262
@@ -278,6 +281,7 @@ config P5020_DS
278 select GPIO_MPC8XXX 281 select GPIO_MPC8XXX
279 select HAS_RAPIDIO 282 select HAS_RAPIDIO
280 select PPC_EPAPR_HV_PIC 283 select PPC_EPAPR_HV_PIC
284 select CORENET_GENERIC
281 help 285 help
282 This option enables support for the P5020 DS board 286 This option enables support for the P5020 DS board
283 287
@@ -292,6 +296,7 @@ config P5040_DS
292 select GPIO_MPC8XXX 296 select GPIO_MPC8XXX
293 select HAS_RAPIDIO 297 select HAS_RAPIDIO
294 select PPC_EPAPR_HV_PIC 298 select PPC_EPAPR_HV_PIC
299 select CORENET_GENERIC
295 help 300 help
296 This option enables support for the P5040 DS board 301 This option enables support for the P5040 DS board
297 302
@@ -323,6 +328,7 @@ config T4240_QDS
323 select GPIO_MPC8XXX 328 select GPIO_MPC8XXX
324 select HAS_RAPIDIO 329 select HAS_RAPIDIO
325 select PPC_EPAPR_HV_PIC 330 select PPC_EPAPR_HV_PIC
331 select CORENET_GENERIC
326 help 332 help
327 This option enables support for the T4240 QDS board 333 This option enables support for the T4240 QDS board
328 334
@@ -337,6 +343,7 @@ config B4_QDS
337 select ARCH_REQUIRE_GPIOLIB 343 select ARCH_REQUIRE_GPIOLIB
338 select HAS_RAPIDIO 344 select HAS_RAPIDIO
339 select PPC_EPAPR_HV_PIC 345 select PPC_EPAPR_HV_PIC
346 select CORENET_GENERIC
340 help 347 help
341 This option enables support for the B4 QDS board 348 This option enables support for the B4 QDS board
342 The B4 application development system B4 QDS is a complete 349 The B4 application development system B4 QDS is a complete
@@ -348,3 +355,6 @@ endif # FSL_SOC_BOOKE
348 355
349config TQM85xx 356config TQM85xx
350 bool 357 bool
358
359config CORENET_GENERIC
360 bool
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 53c9f75a6907..a6c281d596e8 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -18,13 +18,7 @@ obj-$(CONFIG_P1010_RDB) += p1010rdb.o
18obj-$(CONFIG_P1022_DS) += p1022_ds.o 18obj-$(CONFIG_P1022_DS) += p1022_ds.o
19obj-$(CONFIG_P1022_RDK) += p1022_rdk.o 19obj-$(CONFIG_P1022_RDK) += p1022_rdk.o
20obj-$(CONFIG_P1023_RDS) += p1023_rds.o 20obj-$(CONFIG_P1023_RDS) += p1023_rds.o
21obj-$(CONFIG_P2041_RDB) += p2041_rdb.o corenet_ds.o 21obj-$(CONFIG_CORENET_GENERIC) += corenet_ds.o
22obj-$(CONFIG_P3041_DS) += p3041_ds.o corenet_ds.o
23obj-$(CONFIG_P4080_DS) += p4080_ds.o corenet_ds.o
24obj-$(CONFIG_P5020_DS) += p5020_ds.o corenet_ds.o
25obj-$(CONFIG_P5040_DS) += p5040_ds.o corenet_ds.o
26obj-$(CONFIG_T4240_QDS) += t4240_qds.o corenet_ds.o
27obj-$(CONFIG_B4_QDS) += b4_qds.o corenet_ds.o
28obj-$(CONFIG_STX_GP3) += stx_gp3.o 22obj-$(CONFIG_STX_GP3) += stx_gp3.o
29obj-$(CONFIG_TQM85xx) += tqm85xx.o 23obj-$(CONFIG_TQM85xx) += tqm85xx.o
30obj-$(CONFIG_SBC8548) += sbc8548.o 24obj-$(CONFIG_SBC8548) += sbc8548.o
diff --git a/arch/powerpc/platforms/85xx/b4_qds.c b/arch/powerpc/platforms/85xx/b4_qds.c
deleted file mode 100644
index 0f18663f3a76..000000000000
--- a/arch/powerpc/platforms/85xx/b4_qds.c
+++ /dev/null
@@ -1,97 +0,0 @@
1/*
2 * B4 QDS Setup
3 * Should apply for QDS platform of B4860 and it's personalities.
4 * viz B4860/B4420/B4220QDS
5 *
6 * Copyright 2012 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/kernel.h>
15#include <linux/pci.h>
16#include <linux/kdev_t.h>
17#include <linux/delay.h>
18#include <linux/interrupt.h>
19#include <linux/phy.h>
20
21#include <asm/time.h>
22#include <asm/machdep.h>
23#include <asm/pci-bridge.h>
24#include <mm/mmu_decl.h>
25#include <asm/prom.h>
26#include <asm/udbg.h>
27#include <asm/mpic.h>
28
29#include <linux/of_platform.h>
30#include <sysdev/fsl_soc.h>
31#include <sysdev/fsl_pci.h>
32#include <asm/ehv_pic.h>
33
34#include "corenet_ds.h"
35
36/*
37 * Called very early, device-tree isn't unflattened
38 */
39static int __init b4_qds_probe(void)
40{
41 unsigned long root = of_get_flat_dt_root();
42#ifdef CONFIG_SMP
43 extern struct smp_ops_t smp_85xx_ops;
44#endif
45
46 if ((of_flat_dt_is_compatible(root, "fsl,B4860QDS")) ||
47 (of_flat_dt_is_compatible(root, "fsl,B4420QDS")) ||
48 (of_flat_dt_is_compatible(root, "fsl,B4220QDS")))
49 return 1;
50
51 /* Check if we're running under the Freescale hypervisor */
52 if ((of_flat_dt_is_compatible(root, "fsl,B4860QDS-hv")) ||
53 (of_flat_dt_is_compatible(root, "fsl,B4420QDS-hv")) ||
54 (of_flat_dt_is_compatible(root, "fsl,B4220QDS-hv"))) {
55 ppc_md.init_IRQ = ehv_pic_init;
56 ppc_md.get_irq = ehv_pic_get_irq;
57 ppc_md.restart = fsl_hv_restart;
58 ppc_md.power_off = fsl_hv_halt;
59 ppc_md.halt = fsl_hv_halt;
60#ifdef CONFIG_SMP
61 /*
62 * Disable the timebase sync operations because we can't write
63 * to the timebase registers under the hypervisor.
64 */
65 smp_85xx_ops.give_timebase = NULL;
66 smp_85xx_ops.take_timebase = NULL;
67#endif
68 return 1;
69 }
70
71 return 0;
72}
73
74define_machine(b4_qds) {
75 .name = "B4 QDS",
76 .probe = b4_qds_probe,
77 .setup_arch = corenet_ds_setup_arch,
78 .init_IRQ = corenet_ds_pic_init,
79#ifdef CONFIG_PCI
80 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
81#endif
82 .get_irq = mpic_get_coreint_irq,
83 .restart = fsl_rstcr_restart,
84 .calibrate_decr = generic_calibrate_decr,
85 .progress = udbg_progress,
86#ifdef CONFIG_PPC64
87 .power_save = book3e_idle,
88#else
89 .power_save = e500_idle,
90#endif
91};
92
93machine_arch_initcall(b4_qds, corenet_ds_publish_devices);
94
95#ifdef CONFIG_SWIOTLB
96machine_arch_initcall(b4_qds, swiotlb_setup_bus_notifier);
97#endif
diff --git a/arch/powerpc/platforms/85xx/corenet_ds.c b/arch/powerpc/platforms/85xx/corenet_ds.c
index aa3690bae415..8e0285adeb45 100644
--- a/arch/powerpc/platforms/85xx/corenet_ds.c
+++ b/arch/powerpc/platforms/85xx/corenet_ds.c
@@ -25,6 +25,7 @@
25#include <asm/prom.h> 25#include <asm/prom.h>
26#include <asm/udbg.h> 26#include <asm/udbg.h>
27#include <asm/mpic.h> 27#include <asm/mpic.h>
28#include <asm/ehv_pic.h>
28 29
29#include <linux/of_platform.h> 30#include <linux/of_platform.h>
30#include <sysdev/fsl_soc.h> 31#include <sysdev/fsl_soc.h>
@@ -94,3 +95,88 @@ int __init corenet_ds_publish_devices(void)
94{ 95{
95 return of_platform_bus_probe(NULL, of_device_ids, NULL); 96 return of_platform_bus_probe(NULL, of_device_ids, NULL);
96} 97}
98
99static const char * const boards[] __initconst = {
100 "fsl,P2041RDB",
101 "fsl,P3041DS",
102 "fsl,P4080DS",
103 "fsl,P5020DS",
104 "fsl,P5040DS",
105 "fsl,T4240QDS",
106 "fsl,B4860QDS",
107 "fsl,B4420QDS",
108 "fsl,B4220QDS",
109 NULL
110};
111
112static const char * const hv_boards[] __initconst = {
113 "fsl,P2041RDB-hv",
114 "fsl,P3041DS-hv",
115 "fsl,P4080DS-hv",
116 "fsl,P5020DS-hv",
117 "fsl,P5040DS-hv",
118 "fsl,T4240QDS-hv",
119 "fsl,B4860QDS-hv",
120 "fsl,B4420QDS-hv",
121 "fsl,B4220QDS-hv",
122 NULL
123};
124
125/*
126 * Called very early, device-tree isn't unflattened
127 */
128static int __init corenet_generic_probe(void)
129{
130 unsigned long root = of_get_flat_dt_root();
131#ifdef CONFIG_SMP
132 extern struct smp_ops_t smp_85xx_ops;
133#endif
134
135 if (of_flat_dt_match(root, boards))
136 return 1;
137
138 /* Check if we're running under the Freescale hypervisor */
139 if (of_flat_dt_match(root, hv_boards)) {
140 ppc_md.init_IRQ = ehv_pic_init;
141 ppc_md.get_irq = ehv_pic_get_irq;
142 ppc_md.restart = fsl_hv_restart;
143 ppc_md.power_off = fsl_hv_halt;
144 ppc_md.halt = fsl_hv_halt;
145#ifdef CONFIG_SMP
146 /*
147 * Disable the timebase sync operations because we can't write
148 * to the timebase registers under the hypervisor.
149 */
150 smp_85xx_ops.give_timebase = NULL;
151 smp_85xx_ops.take_timebase = NULL;
152#endif
153 return 1;
154 }
155
156 return 0;
157}
158
159define_machine(corenet_generic) {
160 .name = "CoreNet Generic",
161 .probe = corenet_generic_probe,
162 .setup_arch = corenet_ds_setup_arch,
163 .init_IRQ = corenet_ds_pic_init,
164#ifdef CONFIG_PCI
165 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
166#endif
167 .get_irq = mpic_get_coreint_irq,
168 .restart = fsl_rstcr_restart,
169 .calibrate_decr = generic_calibrate_decr,
170 .progress = udbg_progress,
171#ifdef CONFIG_PPC64
172 .power_save = book3e_idle,
173#else
174 .power_save = e500_idle,
175#endif
176};
177
178machine_arch_initcall(corenet_generic, corenet_ds_publish_devices);
179
180#ifdef CONFIG_SWIOTLB
181machine_arch_initcall(corenet_generic, swiotlb_setup_bus_notifier);
182#endif
diff --git a/arch/powerpc/platforms/85xx/corenet_ds.h b/arch/powerpc/platforms/85xx/corenet_ds.h
deleted file mode 100644
index ddd700b23031..000000000000
--- a/arch/powerpc/platforms/85xx/corenet_ds.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * Corenet based SoC DS Setup
3 *
4 * Copyright 2009 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#ifndef CORENET_DS_H
13#define CORENET_DS_H
14
15extern void __init corenet_ds_pic_init(void);
16extern void __init corenet_ds_setup_arch(void);
17extern int __init corenet_ds_publish_devices(void);
18
19#endif
diff --git a/arch/powerpc/platforms/85xx/p2041_rdb.c b/arch/powerpc/platforms/85xx/p2041_rdb.c
deleted file mode 100644
index 000c0892fc40..000000000000
--- a/arch/powerpc/platforms/85xx/p2041_rdb.c
+++ /dev/null
@@ -1,87 +0,0 @@
1/*
2 * P2041 RDB Setup
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#include <linux/kernel.h>
13#include <linux/pci.h>
14#include <linux/kdev_t.h>
15#include <linux/delay.h>
16#include <linux/interrupt.h>
17#include <linux/phy.h>
18
19#include <asm/time.h>
20#include <asm/machdep.h>
21#include <asm/pci-bridge.h>
22#include <mm/mmu_decl.h>
23#include <asm/prom.h>
24#include <asm/udbg.h>
25#include <asm/mpic.h>
26
27#include <linux/of_platform.h>
28#include <sysdev/fsl_soc.h>
29#include <sysdev/fsl_pci.h>
30#include <asm/ehv_pic.h>
31
32#include "corenet_ds.h"
33
34/*
35 * Called very early, device-tree isn't unflattened
36 */
37static int __init p2041_rdb_probe(void)
38{
39 unsigned long root = of_get_flat_dt_root();
40#ifdef CONFIG_SMP
41 extern struct smp_ops_t smp_85xx_ops;
42#endif
43
44 if (of_flat_dt_is_compatible(root, "fsl,P2041RDB"))
45 return 1;
46
47 /* Check if we're running under the Freescale hypervisor */
48 if (of_flat_dt_is_compatible(root, "fsl,P2041RDB-hv")) {
49 ppc_md.init_IRQ = ehv_pic_init;
50 ppc_md.get_irq = ehv_pic_get_irq;
51 ppc_md.restart = fsl_hv_restart;
52 ppc_md.power_off = fsl_hv_halt;
53 ppc_md.halt = fsl_hv_halt;
54#ifdef CONFIG_SMP
55 /*
56 * Disable the timebase sync operations because we can't write
57 * to the timebase registers under the hypervisor.
58 */
59 smp_85xx_ops.give_timebase = NULL;
60 smp_85xx_ops.take_timebase = NULL;
61#endif
62 return 1;
63 }
64
65 return 0;
66}
67
68define_machine(p2041_rdb) {
69 .name = "P2041 RDB",
70 .probe = p2041_rdb_probe,
71 .setup_arch = corenet_ds_setup_arch,
72 .init_IRQ = corenet_ds_pic_init,
73#ifdef CONFIG_PCI
74 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
75#endif
76 .get_irq = mpic_get_coreint_irq,
77 .restart = fsl_rstcr_restart,
78 .calibrate_decr = generic_calibrate_decr,
79 .progress = udbg_progress,
80 .power_save = e500_idle,
81};
82
83machine_arch_initcall(p2041_rdb, corenet_ds_publish_devices);
84
85#ifdef CONFIG_SWIOTLB
86machine_arch_initcall(p2041_rdb, swiotlb_setup_bus_notifier);
87#endif
diff --git a/arch/powerpc/platforms/85xx/p3041_ds.c b/arch/powerpc/platforms/85xx/p3041_ds.c
deleted file mode 100644
index b3edc205daa9..000000000000
--- a/arch/powerpc/platforms/85xx/p3041_ds.c
+++ /dev/null
@@ -1,89 +0,0 @@
1/*
2 * P3041 DS Setup
3 *
4 * Maintained by Kumar Gala (see MAINTAINERS for contact information)
5 *
6 * Copyright 2009-2010 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/kernel.h>
15#include <linux/pci.h>
16#include <linux/kdev_t.h>
17#include <linux/delay.h>
18#include <linux/interrupt.h>
19#include <linux/phy.h>
20
21#include <asm/time.h>
22#include <asm/machdep.h>
23#include <asm/pci-bridge.h>
24#include <mm/mmu_decl.h>
25#include <asm/prom.h>
26#include <asm/udbg.h>
27#include <asm/mpic.h>
28
29#include <linux/of_platform.h>
30#include <sysdev/fsl_soc.h>
31#include <sysdev/fsl_pci.h>
32#include <asm/ehv_pic.h>
33
34#include "corenet_ds.h"
35
36/*
37 * Called very early, device-tree isn't unflattened
38 */
39static int __init p3041_ds_probe(void)
40{
41 unsigned long root = of_get_flat_dt_root();
42#ifdef CONFIG_SMP
43 extern struct smp_ops_t smp_85xx_ops;
44#endif
45
46 if (of_flat_dt_is_compatible(root, "fsl,P3041DS"))
47 return 1;
48
49 /* Check if we're running under the Freescale hypervisor */
50 if (of_flat_dt_is_compatible(root, "fsl,P3041DS-hv")) {
51 ppc_md.init_IRQ = ehv_pic_init;
52 ppc_md.get_irq = ehv_pic_get_irq;
53 ppc_md.restart = fsl_hv_restart;
54 ppc_md.power_off = fsl_hv_halt;
55 ppc_md.halt = fsl_hv_halt;
56#ifdef CONFIG_SMP
57 /*
58 * Disable the timebase sync operations because we can't write
59 * to the timebase registers under the hypervisor.
60 */
61 smp_85xx_ops.give_timebase = NULL;
62 smp_85xx_ops.take_timebase = NULL;
63#endif
64 return 1;
65 }
66
67 return 0;
68}
69
70define_machine(p3041_ds) {
71 .name = "P3041 DS",
72 .probe = p3041_ds_probe,
73 .setup_arch = corenet_ds_setup_arch,
74 .init_IRQ = corenet_ds_pic_init,
75#ifdef CONFIG_PCI
76 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
77#endif
78 .get_irq = mpic_get_coreint_irq,
79 .restart = fsl_rstcr_restart,
80 .calibrate_decr = generic_calibrate_decr,
81 .progress = udbg_progress,
82 .power_save = e500_idle,
83};
84
85machine_arch_initcall(p3041_ds, corenet_ds_publish_devices);
86
87#ifdef CONFIG_SWIOTLB
88machine_arch_initcall(p3041_ds, swiotlb_setup_bus_notifier);
89#endif
diff --git a/arch/powerpc/platforms/85xx/p4080_ds.c b/arch/powerpc/platforms/85xx/p4080_ds.c
deleted file mode 100644
index 54df10632aea..000000000000
--- a/arch/powerpc/platforms/85xx/p4080_ds.c
+++ /dev/null
@@ -1,87 +0,0 @@
1/*
2 * P4080 DS Setup
3 *
4 * Maintained by Kumar Gala (see MAINTAINERS for contact information)
5 *
6 * Copyright 2009 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/kernel.h>
15#include <linux/pci.h>
16#include <linux/kdev_t.h>
17#include <linux/delay.h>
18#include <linux/interrupt.h>
19
20#include <asm/time.h>
21#include <asm/machdep.h>
22#include <asm/pci-bridge.h>
23#include <mm/mmu_decl.h>
24#include <asm/prom.h>
25#include <asm/udbg.h>
26#include <asm/mpic.h>
27
28#include <linux/of_platform.h>
29#include <sysdev/fsl_soc.h>
30#include <sysdev/fsl_pci.h>
31#include <asm/ehv_pic.h>
32
33#include "corenet_ds.h"
34
35/*
36 * Called very early, device-tree isn't unflattened
37 */
38static int __init p4080_ds_probe(void)
39{
40 unsigned long root = of_get_flat_dt_root();
41#ifdef CONFIG_SMP
42 extern struct smp_ops_t smp_85xx_ops;
43#endif
44
45 if (of_flat_dt_is_compatible(root, "fsl,P4080DS"))
46 return 1;
47
48 /* Check if we're running under the Freescale hypervisor */
49 if (of_flat_dt_is_compatible(root, "fsl,P4080DS-hv")) {
50 ppc_md.init_IRQ = ehv_pic_init;
51 ppc_md.get_irq = ehv_pic_get_irq;
52 ppc_md.restart = fsl_hv_restart;
53 ppc_md.power_off = fsl_hv_halt;
54 ppc_md.halt = fsl_hv_halt;
55#ifdef CONFIG_SMP
56 /*
57 * Disable the timebase sync operations because we can't write
58 * to the timebase registers under the hypervisor.
59 */
60 smp_85xx_ops.give_timebase = NULL;
61 smp_85xx_ops.take_timebase = NULL;
62#endif
63 return 1;
64 }
65
66 return 0;
67}
68
69define_machine(p4080_ds) {
70 .name = "P4080 DS",
71 .probe = p4080_ds_probe,
72 .setup_arch = corenet_ds_setup_arch,
73 .init_IRQ = corenet_ds_pic_init,
74#ifdef CONFIG_PCI
75 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
76#endif
77 .get_irq = mpic_get_coreint_irq,
78 .restart = fsl_rstcr_restart,
79 .calibrate_decr = generic_calibrate_decr,
80 .progress = udbg_progress,
81 .power_save = e500_idle,
82};
83
84machine_arch_initcall(p4080_ds, corenet_ds_publish_devices);
85#ifdef CONFIG_SWIOTLB
86machine_arch_initcall(p4080_ds, swiotlb_setup_bus_notifier);
87#endif
diff --git a/arch/powerpc/platforms/85xx/p5020_ds.c b/arch/powerpc/platforms/85xx/p5020_ds.c
deleted file mode 100644
index 39cfa4044e6c..000000000000
--- a/arch/powerpc/platforms/85xx/p5020_ds.c
+++ /dev/null
@@ -1,93 +0,0 @@
1/*
2 * P5020 DS Setup
3 *
4 * Maintained by Kumar Gala (see MAINTAINERS for contact information)
5 *
6 * Copyright 2009-2010 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/kernel.h>
15#include <linux/pci.h>
16#include <linux/kdev_t.h>
17#include <linux/delay.h>
18#include <linux/interrupt.h>
19#include <linux/phy.h>
20
21#include <asm/time.h>
22#include <asm/machdep.h>
23#include <asm/pci-bridge.h>
24#include <mm/mmu_decl.h>
25#include <asm/prom.h>
26#include <asm/udbg.h>
27#include <asm/mpic.h>
28
29#include <linux/of_platform.h>
30#include <sysdev/fsl_soc.h>
31#include <sysdev/fsl_pci.h>
32#include <asm/ehv_pic.h>
33
34#include "corenet_ds.h"
35
36/*
37 * Called very early, device-tree isn't unflattened
38 */
39static int __init p5020_ds_probe(void)
40{
41 unsigned long root = of_get_flat_dt_root();
42#ifdef CONFIG_SMP
43 extern struct smp_ops_t smp_85xx_ops;
44#endif
45
46 if (of_flat_dt_is_compatible(root, "fsl,P5020DS"))
47 return 1;
48
49 /* Check if we're running under the Freescale hypervisor */
50 if (of_flat_dt_is_compatible(root, "fsl,P5020DS-hv")) {
51 ppc_md.init_IRQ = ehv_pic_init;
52 ppc_md.get_irq = ehv_pic_get_irq;
53 ppc_md.restart = fsl_hv_restart;
54 ppc_md.power_off = fsl_hv_halt;
55 ppc_md.halt = fsl_hv_halt;
56#ifdef CONFIG_SMP
57 /*
58 * Disable the timebase sync operations because we can't write
59 * to the timebase registers under the hypervisor.
60 */
61 smp_85xx_ops.give_timebase = NULL;
62 smp_85xx_ops.take_timebase = NULL;
63#endif
64 return 1;
65 }
66
67 return 0;
68}
69
70define_machine(p5020_ds) {
71 .name = "P5020 DS",
72 .probe = p5020_ds_probe,
73 .setup_arch = corenet_ds_setup_arch,
74 .init_IRQ = corenet_ds_pic_init,
75#ifdef CONFIG_PCI
76 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
77#endif
78 .get_irq = mpic_get_coreint_irq,
79 .restart = fsl_rstcr_restart,
80 .calibrate_decr = generic_calibrate_decr,
81 .progress = udbg_progress,
82#ifdef CONFIG_PPC64
83 .power_save = book3e_idle,
84#else
85 .power_save = e500_idle,
86#endif
87};
88
89machine_arch_initcall(p5020_ds, corenet_ds_publish_devices);
90
91#ifdef CONFIG_SWIOTLB
92machine_arch_initcall(p5020_ds, swiotlb_setup_bus_notifier);
93#endif
diff --git a/arch/powerpc/platforms/85xx/p5040_ds.c b/arch/powerpc/platforms/85xx/p5040_ds.c
deleted file mode 100644
index f70e74cddf97..000000000000
--- a/arch/powerpc/platforms/85xx/p5040_ds.c
+++ /dev/null
@@ -1,84 +0,0 @@
1/*
2 * P5040 DS Setup
3 *
4 * Copyright 2009-2010 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#include <linux/kernel.h>
13#include <linux/pci.h>
14
15#include <asm/machdep.h>
16#include <asm/udbg.h>
17#include <asm/mpic.h>
18
19#include <linux/of_fdt.h>
20
21#include <sysdev/fsl_soc.h>
22#include <sysdev/fsl_pci.h>
23#include <asm/ehv_pic.h>
24
25#include "corenet_ds.h"
26
27/*
28 * Called very early, device-tree isn't unflattened
29 */
30static int __init p5040_ds_probe(void)
31{
32 unsigned long root = of_get_flat_dt_root();
33#ifdef CONFIG_SMP
34 extern struct smp_ops_t smp_85xx_ops;
35#endif
36
37 if (of_flat_dt_is_compatible(root, "fsl,P5040DS"))
38 return 1;
39
40 /* Check if we're running under the Freescale hypervisor */
41 if (of_flat_dt_is_compatible(root, "fsl,P5040DS-hv")) {
42 ppc_md.init_IRQ = ehv_pic_init;
43 ppc_md.get_irq = ehv_pic_get_irq;
44 ppc_md.restart = fsl_hv_restart;
45 ppc_md.power_off = fsl_hv_halt;
46 ppc_md.halt = fsl_hv_halt;
47#ifdef CONFIG_SMP
48 /*
49 * Disable the timebase sync operations because we can't write
50 * to the timebase registers under the hypervisor.
51 */
52 smp_85xx_ops.give_timebase = NULL;
53 smp_85xx_ops.take_timebase = NULL;
54#endif
55 return 1;
56 }
57
58 return 0;
59}
60
61define_machine(p5040_ds) {
62 .name = "P5040 DS",
63 .probe = p5040_ds_probe,
64 .setup_arch = corenet_ds_setup_arch,
65 .init_IRQ = corenet_ds_pic_init,
66#ifdef CONFIG_PCI
67 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
68#endif
69 .get_irq = mpic_get_coreint_irq,
70 .restart = fsl_rstcr_restart,
71 .calibrate_decr = generic_calibrate_decr,
72 .progress = udbg_progress,
73#ifdef CONFIG_PPC64
74 .power_save = book3e_idle,
75#else
76 .power_save = e500_idle,
77#endif
78};
79
80machine_arch_initcall(p5040_ds, corenet_ds_publish_devices);
81
82#ifdef CONFIG_SWIOTLB
83machine_arch_initcall(p5040_ds, swiotlb_setup_bus_notifier);
84#endif
diff --git a/arch/powerpc/platforms/85xx/t4240_qds.c b/arch/powerpc/platforms/85xx/t4240_qds.c
deleted file mode 100644
index 91ead6b1b8af..000000000000
--- a/arch/powerpc/platforms/85xx/t4240_qds.c
+++ /dev/null
@@ -1,93 +0,0 @@
1/*
2 * T4240 QDS Setup
3 *
4 * Maintained by Kumar Gala (see MAINTAINERS for contact information)
5 *
6 * Copyright 2012 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/kernel.h>
15#include <linux/pci.h>
16#include <linux/kdev_t.h>
17#include <linux/delay.h>
18#include <linux/interrupt.h>
19#include <linux/phy.h>
20
21#include <asm/time.h>
22#include <asm/machdep.h>
23#include <asm/pci-bridge.h>
24#include <mm/mmu_decl.h>
25#include <asm/prom.h>
26#include <asm/udbg.h>
27#include <asm/mpic.h>
28
29#include <linux/of_platform.h>
30#include <sysdev/fsl_soc.h>
31#include <sysdev/fsl_pci.h>
32#include <asm/ehv_pic.h>
33
34#include "corenet_ds.h"
35
36/*
37 * Called very early, device-tree isn't unflattened
38 */
39static int __init t4240_qds_probe(void)
40{
41 unsigned long root = of_get_flat_dt_root();
42#ifdef CONFIG_SMP
43 extern struct smp_ops_t smp_85xx_ops;
44#endif
45
46 if (of_flat_dt_is_compatible(root, "fsl,T4240QDS"))
47 return 1;
48
49 /* Check if we're running under the Freescale hypervisor */
50 if (of_flat_dt_is_compatible(root, "fsl,T4240QDS-hv")) {
51 ppc_md.init_IRQ = ehv_pic_init;
52 ppc_md.get_irq = ehv_pic_get_irq;
53 ppc_md.restart = fsl_hv_restart;
54 ppc_md.power_off = fsl_hv_halt;
55 ppc_md.halt = fsl_hv_halt;
56#ifdef CONFIG_SMP
57 /*
58 * Disable the timebase sync operations because we can't write
59 * to the timebase registers under the hypervisor.
60 */
61 smp_85xx_ops.give_timebase = NULL;
62 smp_85xx_ops.take_timebase = NULL;
63#endif
64 return 1;
65 }
66
67 return 0;
68}
69
70define_machine(t4240_qds) {
71 .name = "T4240 QDS",
72 .probe = t4240_qds_probe,
73 .setup_arch = corenet_ds_setup_arch,
74 .init_IRQ = corenet_ds_pic_init,
75#ifdef CONFIG_PCI
76 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
77#endif
78 .get_irq = mpic_get_coreint_irq,
79 .restart = fsl_rstcr_restart,
80 .calibrate_decr = generic_calibrate_decr,
81 .progress = udbg_progress,
82#ifdef CONFIG_PPC64
83 .power_save = book3e_idle,
84#else
85 .power_save = e500_idle,
86#endif
87};
88
89machine_arch_initcall(t4240_qds, corenet_ds_publish_devices);
90
91#ifdef CONFIG_SWIOTLB
92machine_arch_initcall(t4240_qds, swiotlb_setup_bus_notifier);
93#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-21 07:51:10 -0500