aboutsummaryrefslogtreecommitdiffstats
path: root/arch/powerpc/platforms
diff options
context:
space:
mode:
authorPaul Mackerras <paulus@samba.org>2007-08-28 01:56:11 -0400
committerPaul Mackerras <paulus@samba.org>2007-08-28 01:56:11 -0400
commit35438c4327df18dbf5e7f597b69299119f4a14de (patch)
treea4589d731015db93f2eba8f84ffb1f48a8084020 /arch/powerpc/platforms
parent2f6c9d961081dc7b109eb19166244bcb2a5dfc28 (diff)
parentb07d68b5ca4d55a16fab223d63d5fb36f89ff42f (diff)
Merge branch 'linux-2.6' into for-2.6.24
Diffstat (limited to 'arch/powerpc/platforms')
-rw-r--r--arch/powerpc/platforms/85xx/Kconfig1
-rw-r--r--arch/powerpc/platforms/85xx/mpc8544_ds.c214
-rw-r--r--arch/powerpc/platforms/86xx/Kconfig1
-rw-r--r--arch/powerpc/platforms/86xx/mpc86xx_hpcn.c224
-rw-r--r--arch/powerpc/platforms/Kconfig8
-rw-r--r--arch/powerpc/platforms/Makefile3
-rw-r--r--arch/powerpc/platforms/cell/cbe_regs.h8
-rw-r--r--arch/powerpc/platforms/cell/cbe_thermal.c6
-rw-r--r--arch/powerpc/platforms/cell/pervasive.c26
-rw-r--r--arch/powerpc/platforms/cell/spu_manage.c2
-rw-r--r--arch/powerpc/platforms/fsl_uli1575.c255
-rw-r--r--arch/powerpc/platforms/pasemi/iommu.c6
12 files changed, 336 insertions, 418 deletions
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index f58184086c8c..f620171ad6b1 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -33,6 +33,7 @@ config MPC8544_DS
33 bool "Freescale MPC8544 DS" 33 bool "Freescale MPC8544 DS"
34 select PPC_I8259 34 select PPC_I8259
35 select DEFAULT_UIMAGE 35 select DEFAULT_UIMAGE
36 select FSL_ULI1575
36 help 37 help
37 This option enables support for the MPC8544 DS board 38 This option enables support for the MPC8544 DS board
38 39
diff --git a/arch/powerpc/platforms/85xx/mpc8544_ds.c b/arch/powerpc/platforms/85xx/mpc8544_ds.c
index 4905f6f8903b..0f834d8be444 100644
--- a/arch/powerpc/platforms/85xx/mpc8544_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc8544_ds.c
@@ -114,211 +114,25 @@ void __init mpc8544_ds_pic_init(void)
114} 114}
115 115
116#ifdef CONFIG_PCI 116#ifdef CONFIG_PCI
117enum pirq { PIRQA = 8, PIRQB, PIRQC, PIRQD, PIRQE, PIRQF, PIRQG, PIRQH }; 117extern int uses_fsl_uli_m1575;
118extern int uli_exclude_device(struct pci_controller *hose,
119 u_char bus, u_char devfn);
118 120
119/* 121static int mpc85xx_exclude_device(struct pci_controller *hose,
120 * Value in table -- IRQ number 122 u_char bus, u_char devfn)
121 */
122const unsigned char uli1575_irq_route_table[16] = {
123 0, /* 0: Reserved */
124 0x8,
125 0, /* 2: Reserved */
126 0x2,
127 0x4,
128 0x5,
129 0x7,
130 0x6,
131 0, /* 8: Reserved */
132 0x1,
133 0x3,
134 0x9,
135 0xb,
136 0, /* 13: Reserved */
137 0xd,
138 0xf,
139};
140
141static int __devinit
142get_pci_irq_from_of(struct pci_controller *hose, int slot, int pin)
143{
144 struct of_irq oirq;
145 u32 laddr[3];
146 struct device_node *hosenode = hose ? hose->arch_data : NULL;
147
148 if (!hosenode)
149 return -EINVAL;
150
151 laddr[0] = (hose->first_busno << 16) | (PCI_DEVFN(slot, 0) << 8);
152 laddr[1] = laddr[2] = 0;
153 of_irq_map_raw(hosenode, &pin, 1, laddr, &oirq);
154 DBG("mpc8544_ds: pci irq addr %x, slot %d, pin %d, irq %d\n",
155 laddr[0], slot, pin, oirq.specifier[0]);
156 return oirq.specifier[0];
157}
158
159/*8259*/
160static void __devinit quirk_uli1575(struct pci_dev *dev)
161{
162 unsigned short temp;
163 struct pci_controller *hose = pci_bus_to_host(dev->bus);
164 unsigned char irq2pin[16];
165 unsigned long pirq_map_word = 0;
166 u32 irq;
167 int i;
168
169 /*
170 * ULI1575 interrupts route setup
171 */
172 memset(irq2pin, 0, 16); /* Initialize default value 0 */
173
174 irq2pin[6]=PIRQA+3; /* enabled mapping for IRQ6 to PIRQD, used by SATA */
175
176 /*
177 * PIRQE -> PIRQF mapping set manually
178 *
179 * IRQ pin IRQ#
180 * PIRQE ---- 9
181 * PIRQF ---- 10
182 * PIRQG ---- 11
183 * PIRQH ---- 12
184 */
185 for (i = 0; i < 4; i++)
186 irq2pin[i + 9] = PIRQE + i;
187
188 /* Set IRQ-PIRQ Mapping to ULI1575 */
189 for (i = 0; i < 16; i++)
190 if (irq2pin[i])
191 pirq_map_word |= (uli1575_irq_route_table[i] & 0xf)
192 << ((irq2pin[i] - PIRQA) * 4);
193
194 pirq_map_word |= 1<<26; /* disable INTx in EP mode*/
195
196 /* ULI1575 IRQ mapping conf register default value is 0xb9317542 */
197 DBG("Setup ULI1575 IRQ mapping configuration register value = 0x%x\n",
198 (int)pirq_map_word);
199 pci_write_config_dword(dev, 0x48, pirq_map_word);
200
201#define ULI1575_SET_DEV_IRQ(slot, pin, reg) \
202 do { \
203 int irq; \
204 irq = get_pci_irq_from_of(hose, slot, pin); \
205 if (irq > 0 && irq < 16) \
206 pci_write_config_byte(dev, reg, irq2pin[irq]); \
207 else \
208 printk(KERN_WARNING "ULI1575 device" \
209 "(slot %d, pin %d) irq %d is invalid.\n", \
210 slot, pin, irq); \
211 } while(0)
212
213 /* USB 1.1 OHCI controller 1, slot 28, pin 1 */
214 ULI1575_SET_DEV_IRQ(28, 1, 0x86);
215
216 /* USB 1.1 OHCI controller 2, slot 28, pin 2 */
217 ULI1575_SET_DEV_IRQ(28, 2, 0x87);
218
219 /* USB 1.1 OHCI controller 3, slot 28, pin 3 */
220 ULI1575_SET_DEV_IRQ(28, 3, 0x88);
221
222 /* USB 2.0 controller, slot 28, pin 4 */
223 irq = get_pci_irq_from_of(hose, 28, 4);
224 if (irq >= 0 && irq <= 15)
225 pci_write_config_dword(dev, 0x74, uli1575_irq_route_table[irq]);
226
227 /* Audio controller, slot 29, pin 1 */
228 ULI1575_SET_DEV_IRQ(29, 1, 0x8a);
229
230 /* Modem controller, slot 29, pin 2 */
231 ULI1575_SET_DEV_IRQ(29, 2, 0x8b);
232
233 /* HD audio controller, slot 29, pin 3 */
234 ULI1575_SET_DEV_IRQ(29, 3, 0x8c);
235
236 /* SMB interrupt: slot 30, pin 1 */
237 ULI1575_SET_DEV_IRQ(30, 1, 0x8e);
238
239 /* PMU ACPI SCI interrupt: slot 30, pin 2 */
240 ULI1575_SET_DEV_IRQ(30, 2, 0x8f);
241
242 /* Serial ATA interrupt: slot 31, pin 1 */
243 ULI1575_SET_DEV_IRQ(31, 1, 0x8d);
244
245 /* Primary PATA IDE IRQ: 14
246 * Secondary PATA IDE IRQ: 15
247 */
248 pci_write_config_byte(dev, 0x44, 0x30 | uli1575_irq_route_table[14]);
249 pci_write_config_byte(dev, 0x75, uli1575_irq_route_table[15]);
250
251 /* Set IRQ14 and IRQ15 to legacy IRQs */
252 pci_read_config_word(dev, 0x46, &temp);
253 temp |= 0xc000;
254 pci_write_config_word(dev, 0x46, temp);
255
256 /* Set i8259 interrupt trigger
257 * IRQ 3: Level
258 * IRQ 4: Level
259 * IRQ 5: Level
260 * IRQ 6: Level
261 * IRQ 7: Level
262 * IRQ 9: Level
263 * IRQ 10: Level
264 * IRQ 11: Level
265 * IRQ 12: Level
266 * IRQ 14: Edge
267 * IRQ 15: Edge
268 */
269 outb(0xfa, 0x4d0);
270 outb(0x1e, 0x4d1);
271
272#undef ULI1575_SET_DEV_IRQ
273}
274
275/* SATA */
276static void __devinit quirk_uli5288(struct pci_dev *dev)
277{ 123{
278 unsigned char c; 124 struct device_node* node;
279 125 struct resource rsrc;
280 pci_read_config_byte(dev, 0x83, &c);
281 c |= 0x80; /* read/write lock */
282 pci_write_config_byte(dev, 0x83, c);
283
284 pci_write_config_byte(dev, 0x09, 0x01); /* Base class code: storage */
285 pci_write_config_byte(dev, 0x0a, 0x06); /* IDE disk */
286 126
287 pci_read_config_byte(dev, 0x83, &c); 127 node = (struct device_node *)hose->arch_data;
288 c &= 0x7f; 128 of_address_to_resource(node, 0, &rsrc);
289 pci_write_config_byte(dev, 0x83, c);
290
291 pci_read_config_byte(dev, 0x84, &c);
292 c |= 0x01; /* emulated PATA mode enabled */
293 pci_write_config_byte(dev, 0x84, c);
294}
295 129
296/* PATA */ 130 if ((rsrc.start & 0xfffff) == 0xb000) {
297static void __devinit quirk_uli5229(struct pci_dev *dev) 131 return uli_exclude_device(hose, bus, devfn);
298{ 132 }
299 unsigned short temp;
300 pci_write_config_word(dev, 0x04, 0x0405); /* MEM IO MSI */
301 pci_read_config_word(dev, 0x4a, &temp);
302 temp |= 0x1000; /* Enable Native IRQ 14/15 */
303 pci_write_config_word(dev, 0x4a, temp);
304}
305 133
306/*Bridge*/ 134 return PCIBIOS_SUCCESSFUL;
307static void __devinit early_uli5249(struct pci_dev *dev)
308{
309 unsigned char temp;
310 pci_write_config_word(dev, 0x04, 0x0007); /* mem access */
311 pci_read_config_byte(dev, 0x7c, &temp);
312 pci_write_config_byte(dev, 0x7c, 0x80); /* R/W lock control */
313 pci_write_config_byte(dev, 0x09, 0x01); /* set as pci-pci bridge */
314 pci_write_config_byte(dev, 0x7c, temp); /* restore pci bus debug control */
315 dev->class |= 0x1;
316} 135}
317
318DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_uli1575);
319DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288);
320DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
321DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, 0x5249, early_uli5249);
322#endif /* CONFIG_PCI */ 136#endif /* CONFIG_PCI */
323 137
324/* 138/*
@@ -342,6 +156,8 @@ static void __init mpc8544_ds_setup_arch(void)
342 else 156 else
343 fsl_add_bridge(np, 0); 157 fsl_add_bridge(np, 0);
344 } 158 }
159 uses_fsl_uli_m1575 = 1;
160 ppc_md.pci_exclude_device = mpc85xx_exclude_device;
345#endif 161#endif
346 162
347 printk("MPC8544 DS board from Freescale Semiconductor\n"); 163 printk("MPC8544 DS board from Freescale Semiconductor\n");
diff --git a/arch/powerpc/platforms/86xx/Kconfig b/arch/powerpc/platforms/86xx/Kconfig
index 343b76d0d793..685b2fbbbe00 100644
--- a/arch/powerpc/platforms/86xx/Kconfig
+++ b/arch/powerpc/platforms/86xx/Kconfig
@@ -7,6 +7,7 @@ config MPC8641_HPCN
7 bool "Freescale MPC8641 HPCN" 7 bool "Freescale MPC8641 HPCN"
8 select PPC_I8259 8 select PPC_I8259
9 select DEFAULT_UIMAGE 9 select DEFAULT_UIMAGE
10 select FSL_ULI1575
10 help 11 help
11 This option enables support for the MPC8641 HPCN board. 12 This option enables support for the MPC8641 HPCN board.
12 13
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
index e9eaa0749ae6..56b27caf7a27 100644
--- a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
+++ b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
@@ -107,220 +107,25 @@ mpc86xx_hpcn_init_irq(void)
107} 107}
108 108
109#ifdef CONFIG_PCI 109#ifdef CONFIG_PCI
110extern int uses_fsl_uli_m1575;
111extern int uli_exclude_device(struct pci_controller *hose,
112 u_char bus, u_char devfn);
110 113
111enum pirq{PIRQA = 8, PIRQB, PIRQC, PIRQD, PIRQE, PIRQF, PIRQG, PIRQH}; 114static int mpc86xx_exclude_device(struct pci_controller *hose,
112const unsigned char uli1575_irq_route_table[16] = { 115 u_char bus, u_char devfn)
113 0, /* 0: Reserved */
114 0x8, /* 1: 0b1000 */
115 0, /* 2: Reserved */
116 0x2, /* 3: 0b0010 */
117 0x4, /* 4: 0b0100 */
118 0x5, /* 5: 0b0101 */
119 0x7, /* 6: 0b0111 */
120 0x6, /* 7: 0b0110 */
121 0, /* 8: Reserved */
122 0x1, /* 9: 0b0001 */
123 0x3, /* 10: 0b0011 */
124 0x9, /* 11: 0b1001 */
125 0xb, /* 12: 0b1011 */
126 0, /* 13: Reserved */
127 0xd, /* 14, 0b1101 */
128 0xf, /* 15, 0b1111 */
129};
130
131static int __devinit
132get_pci_irq_from_of(struct pci_controller *hose, int slot, int pin)
133{
134 struct of_irq oirq;
135 u32 laddr[3];
136 struct device_node *hosenode = hose ? hose->arch_data : NULL;
137
138 if (!hosenode) return -EINVAL;
139
140 laddr[0] = (hose->first_busno << 16) | (PCI_DEVFN(slot, 0) << 8);
141 laddr[1] = laddr[2] = 0;
142 of_irq_map_raw(hosenode, &pin, 1, laddr, &oirq);
143 DBG("mpc86xx_hpcn: pci irq addr %x, slot %d, pin %d, irq %d\n",
144 laddr[0], slot, pin, oirq.specifier[0]);
145 return oirq.specifier[0];
146}
147
148static void __devinit quirk_uli1575(struct pci_dev *dev)
149{
150 unsigned short temp;
151 struct pci_controller *hose = pci_bus_to_host(dev->bus);
152 unsigned char irq2pin[16], c;
153 unsigned long pirq_map_word = 0;
154 u32 irq;
155 int i;
156
157 /*
158 * ULI1575 interrupts route setup
159 */
160 memset(irq2pin, 0, 16); /* Initialize default value 0 */
161
162 /*
163 * PIRQA -> PIRQD mapping read from OF-tree
164 *
165 * interrupts for PCI slot0 -- PIRQA / PIRQB / PIRQC / PIRQD
166 * PCI slot1 -- PIRQB / PIRQC / PIRQD / PIRQA
167 */
168 for (i = 0; i < 4; i++){
169 irq = get_pci_irq_from_of(hose, 17, i + 1);
170 if (irq > 0 && irq < 16)
171 irq2pin[irq] = PIRQA + i;
172 else
173 printk(KERN_WARNING "ULI1575 device"
174 "(slot %d, pin %d) irq %d is invalid.\n",
175 17, i, irq);
176 }
177
178 /*
179 * PIRQE -> PIRQF mapping set manually
180 *
181 * IRQ pin IRQ#
182 * PIRQE ---- 9
183 * PIRQF ---- 10
184 * PIRQG ---- 11
185 * PIRQH ---- 12
186 */
187 for (i = 0; i < 4; i++) irq2pin[i + 9] = PIRQE + i;
188
189 /* Set IRQ-PIRQ Mapping to ULI1575 */
190 for (i = 0; i < 16; i++)
191 if (irq2pin[i])
192 pirq_map_word |= (uli1575_irq_route_table[i] & 0xf)
193 << ((irq2pin[i] - PIRQA) * 4);
194
195 /* ULI1575 IRQ mapping conf register default value is 0xb9317542 */
196 DBG("Setup ULI1575 IRQ mapping configuration register value = 0x%x\n",
197 pirq_map_word);
198 pci_write_config_dword(dev, 0x48, pirq_map_word);
199
200#define ULI1575_SET_DEV_IRQ(slot, pin, reg) \
201 do { \
202 int irq; \
203 irq = get_pci_irq_from_of(hose, slot, pin); \
204 if (irq > 0 && irq < 16) \
205 pci_write_config_byte(dev, reg, irq2pin[irq]); \
206 else \
207 printk(KERN_WARNING "ULI1575 device" \
208 "(slot %d, pin %d) irq %d is invalid.\n", \
209 slot, pin, irq); \
210 } while(0)
211
212 /* USB 1.1 OHCI controller 1, slot 28, pin 1 */
213 ULI1575_SET_DEV_IRQ(28, 1, 0x86);
214
215 /* USB 1.1 OHCI controller 2, slot 28, pin 2 */
216 ULI1575_SET_DEV_IRQ(28, 2, 0x87);
217
218 /* USB 1.1 OHCI controller 3, slot 28, pin 3 */
219 ULI1575_SET_DEV_IRQ(28, 3, 0x88);
220
221 /* USB 2.0 controller, slot 28, pin 4 */
222 irq = get_pci_irq_from_of(hose, 28, 4);
223 if (irq >= 0 && irq <=15)
224 pci_write_config_dword(dev, 0x74, uli1575_irq_route_table[irq]);
225
226 /* Audio controller, slot 29, pin 1 */
227 ULI1575_SET_DEV_IRQ(29, 1, 0x8a);
228
229 /* Modem controller, slot 29, pin 2 */
230 ULI1575_SET_DEV_IRQ(29, 2, 0x8b);
231
232 /* HD audio controller, slot 29, pin 3 */
233 ULI1575_SET_DEV_IRQ(29, 3, 0x8c);
234
235 /* SMB interrupt: slot 30, pin 1 */
236 ULI1575_SET_DEV_IRQ(30, 1, 0x8e);
237
238 /* PMU ACPI SCI interrupt: slot 30, pin 2 */
239 ULI1575_SET_DEV_IRQ(30, 2, 0x8f);
240
241 /* Serial ATA interrupt: slot 31, pin 1 */
242 ULI1575_SET_DEV_IRQ(31, 1, 0x8d);
243
244 /* Primary PATA IDE IRQ: 14
245 * Secondary PATA IDE IRQ: 15
246 */
247 pci_write_config_byte(dev, 0x44, 0x30 | uli1575_irq_route_table[14]);
248 pci_write_config_byte(dev, 0x75, uli1575_irq_route_table[15]);
249
250 /* Set IRQ14 and IRQ15 to legacy IRQs */
251 pci_read_config_word(dev, 0x46, &temp);
252 temp |= 0xc000;
253 pci_write_config_word(dev, 0x46, temp);
254
255 /* Set i8259 interrupt trigger
256 * IRQ 3: Level
257 * IRQ 4: Level
258 * IRQ 5: Level
259 * IRQ 6: Level
260 * IRQ 7: Level
261 * IRQ 9: Level
262 * IRQ 10: Level
263 * IRQ 11: Level
264 * IRQ 12: Level
265 * IRQ 14: Edge
266 * IRQ 15: Edge
267 */
268 outb(0xfa, 0x4d0);
269 outb(0x1e, 0x4d1);
270
271#undef ULI1575_SET_DEV_IRQ
272
273 /* Disable the HD interface and enable the AC97 interface. */
274 pci_read_config_byte(dev, 0xb8, &c);
275 c &= 0x7f;
276 pci_write_config_byte(dev, 0xb8, c);
277}
278
279static void __devinit quirk_uli5288(struct pci_dev *dev)
280{ 116{
281 unsigned char c; 117 struct device_node* node;
118 struct resource rsrc;
282 119
283 pci_read_config_byte(dev,0x83,&c); 120 node = (struct device_node *)hose->arch_data;
284 c |= 0x80; 121 of_address_to_resource(node, 0, &rsrc);
285 pci_write_config_byte(dev, 0x83, c);
286 122
287 pci_write_config_byte(dev, 0x09, 0x01); 123 if ((rsrc.start & 0xfffff) == 0x8000) {
288 pci_write_config_byte(dev, 0x0a, 0x06); 124 return uli_exclude_device(hose, bus, devfn);
289 125 }
290 pci_read_config_byte(dev,0x83,&c);
291 c &= 0x7f;
292 pci_write_config_byte(dev, 0x83, c);
293
294 pci_read_config_byte(dev,0x84,&c);
295 c |= 0x01;
296 pci_write_config_byte(dev, 0x84, c);
297}
298
299static void __devinit quirk_uli5229(struct pci_dev *dev)
300{
301 unsigned short temp;
302 pci_write_config_word(dev, 0x04, 0x0405);
303 dev->class &= ~0x5;
304 pci_read_config_word(dev, 0x4a, &temp);
305 temp |= 0x1000;
306 pci_write_config_word(dev, 0x4a, temp);
307}
308 126
309static void __devinit early_uli5249(struct pci_dev *dev) 127 return PCIBIOS_SUCCESSFUL;
310{
311 unsigned char temp;
312 pci_write_config_word(dev, 0x04, 0x0007);
313 pci_read_config_byte(dev, 0x7c, &temp);
314 pci_write_config_byte(dev, 0x7c, 0x80);
315 pci_write_config_byte(dev, 0x09, 0x01);
316 pci_write_config_byte(dev, 0x7c, temp);
317 dev->class |= 0x1;
318} 128}
319
320DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_uli1575);
321DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288);
322DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
323DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, 0x5249, early_uli5249);
324#endif /* CONFIG_PCI */ 129#endif /* CONFIG_PCI */
325 130
326 131
@@ -353,6 +158,9 @@ mpc86xx_hpcn_setup_arch(void)
353 else 158 else
354 fsl_add_bridge(np, 0); 159 fsl_add_bridge(np, 0);
355 } 160 }
161 uses_fsl_uli_m1575 = 1;
162 ppc_md.pci_exclude_device = mpc86xx_exclude_device;
163
356#endif 164#endif
357 165
358 printk("MPC86xx HPCN board from Freescale Semiconductor\n"); 166 printk("MPC86xx HPCN board from Freescale Semiconductor\n");
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index 2c937fb207fe..041df77ec117 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -283,4 +283,12 @@ config AXON_RAM
283 minor numbers are available in /proc/devices, /proc/partitions or 283 minor numbers are available in /proc/devices, /proc/partitions or
284 in /sys/block/axonram?/dev. 284 in /sys/block/axonram?/dev.
285 285
286config FSL_ULI1575
287 bool
288 default n
289 help
290 Supports for the ULI1575 PCIe south bridge that exists on some
291 Freescale reference boards. The boards all use the ULI in pretty
292 much the same way.
293
286endmenu 294endmenu
diff --git a/arch/powerpc/platforms/Makefile b/arch/powerpc/platforms/Makefile
index d6e041a46d25..d44e832b01f2 100644
--- a/arch/powerpc/platforms/Makefile
+++ b/arch/powerpc/platforms/Makefile
@@ -1,3 +1,6 @@
1
2obj-$(CONFIG_FSL_ULI1575) += fsl_uli1575.o
3
1ifeq ($(CONFIG_PPC_MERGE),y) 4ifeq ($(CONFIG_PPC_MERGE),y)
2obj-$(CONFIG_PPC_PMAC) += powermac/ 5obj-$(CONFIG_PPC_PMAC) += powermac/
3else 6else
diff --git a/arch/powerpc/platforms/cell/cbe_regs.h b/arch/powerpc/platforms/cell/cbe_regs.h
index 17d597144877..b24025f2ac7a 100644
--- a/arch/powerpc/platforms/cell/cbe_regs.h
+++ b/arch/powerpc/platforms/cell/cbe_regs.h
@@ -113,10 +113,14 @@ struct cbe_pmd_regs {
113 u64 checkstop_fir; /* 0x0c00 */ 113 u64 checkstop_fir; /* 0x0c00 */
114 u64 recoverable_fir; /* 0x0c08 */ 114 u64 recoverable_fir; /* 0x0c08 */
115 u64 spec_att_mchk_fir; /* 0x0c10 */ 115 u64 spec_att_mchk_fir; /* 0x0c10 */
116 u64 fir_mode_reg; /* 0x0c18 */ 116 u32 fir_mode_reg; /* 0x0c18 */
117 u8 pad_0x0c1c_0x0c20 [4]; /* 0x0c1c */
118#define CBE_PMD_FIR_MODE_M8 0x00800
117 u64 fir_enable_mask; /* 0x0c20 */ 119 u64 fir_enable_mask; /* 0x0c20 */
118 120
119 u8 pad_0x0c28_0x1000 [0x1000 - 0x0c28]; /* 0x0c28 */ 121 u8 pad_0x0c28_0x0ca8 [0x0ca8 - 0x0c28]; /* 0x0c28 */
122 u64 ras_esc_0; /* 0x0ca8 */
123 u8 pad_0x0cb0_0x1000 [0x1000 - 0x0cb0]; /* 0x0cb0 */
120}; 124};
121 125
122extern struct cbe_pmd_regs __iomem *cbe_get_pmd_regs(struct device_node *np); 126extern struct cbe_pmd_regs __iomem *cbe_get_pmd_regs(struct device_node *np);
diff --git a/arch/powerpc/platforms/cell/cbe_thermal.c b/arch/powerpc/platforms/cell/cbe_thermal.c
index e4132f8f51b3..fb5eda48467d 100644
--- a/arch/powerpc/platforms/cell/cbe_thermal.c
+++ b/arch/powerpc/platforms/cell/cbe_thermal.c
@@ -88,17 +88,13 @@ static struct cbe_pmd_regs __iomem *get_pmd_regs(struct sys_device *sysdev)
88/* returns the value for a given spu in a given register */ 88/* returns the value for a given spu in a given register */
89static u8 spu_read_register_value(struct sys_device *sysdev, union spe_reg __iomem *reg) 89static u8 spu_read_register_value(struct sys_device *sysdev, union spe_reg __iomem *reg)
90{ 90{
91 const unsigned int *id;
92 union spe_reg value; 91 union spe_reg value;
93 struct spu *spu; 92 struct spu *spu;
94 93
95 /* getting the id from the reg attribute will not work on future device-tree layouts
96 * in future we should store the id to the spu struct and use it here */
97 spu = container_of(sysdev, struct spu, sysdev); 94 spu = container_of(sysdev, struct spu, sysdev);
98 id = of_get_property(spu_devnode(spu), "reg", NULL);
99 value.val = in_be64(&reg->val); 95 value.val = in_be64(&reg->val);
100 96
101 return value.spe[*id]; 97 return value.spe[spu->spe_id];
102} 98}
103 99
104static ssize_t spu_show_temp(struct sys_device *sysdev, char *buf) 100static ssize_t spu_show_temp(struct sys_device *sysdev, char *buf)
diff --git a/arch/powerpc/platforms/cell/pervasive.c b/arch/powerpc/platforms/cell/pervasive.c
index 812bf563ed65..4ede22d363fa 100644
--- a/arch/powerpc/platforms/cell/pervasive.c
+++ b/arch/powerpc/platforms/cell/pervasive.c
@@ -38,6 +38,8 @@
38#include "pervasive.h" 38#include "pervasive.h"
39#include "cbe_regs.h" 39#include "cbe_regs.h"
40 40
41static int sysreset_hack;
42
41static void cbe_power_save(void) 43static void cbe_power_save(void)
42{ 44{
43 unsigned long ctrl, thread_switch_control; 45 unsigned long ctrl, thread_switch_control;
@@ -85,6 +87,9 @@ static void cbe_power_save(void)
85 87
86static int cbe_system_reset_exception(struct pt_regs *regs) 88static int cbe_system_reset_exception(struct pt_regs *regs)
87{ 89{
90 int cpu;
91 struct cbe_pmd_regs __iomem *pmd;
92
88 switch (regs->msr & SRR1_WAKEMASK) { 93 switch (regs->msr & SRR1_WAKEMASK) {
89 case SRR1_WAKEEE: 94 case SRR1_WAKEEE:
90 do_IRQ(regs); 95 do_IRQ(regs);
@@ -93,6 +98,18 @@ static int cbe_system_reset_exception(struct pt_regs *regs)
93 timer_interrupt(regs); 98 timer_interrupt(regs);
94 break; 99 break;
95 case SRR1_WAKEMT: 100 case SRR1_WAKEMT:
101 /*
102 * The BMC can inject user triggered system reset exceptions,
103 * but cannot set the system reset reason in srr1,
104 * so check an extra register here.
105 */
106 if (sysreset_hack && (cpu = smp_processor_id()) == 0) {
107 pmd = cbe_get_cpu_pmd_regs(cpu);
108 if (in_be64(&pmd->ras_esc_0) & 0xffff) {
109 out_be64(&pmd->ras_esc_0, 0);
110 return 0;
111 }
112 }
96 break; 113 break;
97#ifdef CONFIG_CBE_RAS 114#ifdef CONFIG_CBE_RAS
98 case SRR1_WAKESYSERR: 115 case SRR1_WAKESYSERR:
@@ -113,9 +130,12 @@ static int cbe_system_reset_exception(struct pt_regs *regs)
113void __init cbe_pervasive_init(void) 130void __init cbe_pervasive_init(void)
114{ 131{
115 int cpu; 132 int cpu;
133
116 if (!cpu_has_feature(CPU_FTR_PAUSE_ZERO)) 134 if (!cpu_has_feature(CPU_FTR_PAUSE_ZERO))
117 return; 135 return;
118 136
137 sysreset_hack = machine_is_compatible("IBM,CBPLUS-1.0");
138
119 for_each_possible_cpu(cpu) { 139 for_each_possible_cpu(cpu) {
120 struct cbe_pmd_regs __iomem *regs = cbe_get_cpu_pmd_regs(cpu); 140 struct cbe_pmd_regs __iomem *regs = cbe_get_cpu_pmd_regs(cpu);
121 if (!regs) 141 if (!regs)
@@ -124,6 +144,12 @@ void __init cbe_pervasive_init(void)
124 /* Enable Pause(0) control bit */ 144 /* Enable Pause(0) control bit */
125 out_be64(&regs->pmcr, in_be64(&regs->pmcr) | 145 out_be64(&regs->pmcr, in_be64(&regs->pmcr) |
126 CBE_PMD_PAUSE_ZERO_CONTROL); 146 CBE_PMD_PAUSE_ZERO_CONTROL);
147
148 /* Enable JTAG system-reset hack */
149 if (sysreset_hack)
150 out_be32(&regs->fir_mode_reg,
151 in_be32(&regs->fir_mode_reg) |
152 CBE_PMD_FIR_MODE_M8);
127 } 153 }
128 154
129 ppc_md.power_save = cbe_power_save; 155 ppc_md.power_save = cbe_power_save;
diff --git a/arch/powerpc/platforms/cell/spu_manage.c b/arch/powerpc/platforms/cell/spu_manage.c
index 5eb88346181a..7c0668a9dcc7 100644
--- a/arch/powerpc/platforms/cell/spu_manage.c
+++ b/arch/powerpc/platforms/cell/spu_manage.c
@@ -48,7 +48,7 @@ static u64 __init find_spu_unit_number(struct device_node *spe)
48{ 48{
49 const unsigned int *prop; 49 const unsigned int *prop;
50 int proplen; 50 int proplen;
51 prop = of_get_property(spe, "unit-id", &proplen); 51 prop = of_get_property(spe, "physical-id", &proplen);
52 if (proplen == 4) 52 if (proplen == 4)
53 return (u64)*prop; 53 return (u64)*prop;
54 54
diff --git a/arch/powerpc/platforms/fsl_uli1575.c b/arch/powerpc/platforms/fsl_uli1575.c
new file mode 100644
index 000000000000..afc9141be63e
--- /dev/null
+++ b/arch/powerpc/platforms/fsl_uli1575.c
@@ -0,0 +1,255 @@
1/*
2 * ULI M1575 setup code - specific to Freescale boards
3 *
4 * Copyright 2007 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#include <linux/stddef.h>
13#include <linux/kernel.h>
14#include <linux/pci.h>
15#include <linux/interrupt.h>
16#include <linux/mc146818rtc.h>
17
18#include <asm/system.h>
19#include <asm/pci-bridge.h>
20
21#define ULI_PIRQA 0x08
22#define ULI_PIRQB 0x09
23#define ULI_PIRQC 0x0a
24#define ULI_PIRQD 0x0b
25#define ULI_PIRQE 0x0c
26#define ULI_PIRQF 0x0d
27#define ULI_PIRQG 0x0e
28
29#define ULI_8259_NONE 0x00
30#define ULI_8259_IRQ1 0x08
31#define ULI_8259_IRQ3 0x02
32#define ULI_8259_IRQ4 0x04
33#define ULI_8259_IRQ5 0x05
34#define ULI_8259_IRQ6 0x07
35#define ULI_8259_IRQ7 0x06
36#define ULI_8259_IRQ9 0x01
37#define ULI_8259_IRQ10 0x03
38#define ULI_8259_IRQ11 0x09
39#define ULI_8259_IRQ12 0x0b
40#define ULI_8259_IRQ14 0x0d
41#define ULI_8259_IRQ15 0x0f
42
43u8 uli_pirq_to_irq[8] = {
44 ULI_8259_IRQ9, /* PIRQA */
45 ULI_8259_IRQ10, /* PIRQB */
46 ULI_8259_IRQ11, /* PIRQC */
47 ULI_8259_IRQ12, /* PIRQD */
48 ULI_8259_IRQ5, /* PIRQE */
49 ULI_8259_IRQ6, /* PIRQF */
50 ULI_8259_IRQ7, /* PIRQG */
51 ULI_8259_NONE, /* PIRQH */
52};
53
54/* set in board code if you want this quirks to do something */
55int uses_fsl_uli_m1575;
56
57/* Bridge */
58static void __devinit early_uli5249(struct pci_dev *dev)
59{
60 unsigned char temp;
61
62 if (!uses_fsl_uli_m1575)
63 return;
64
65 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO |
66 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
67
68 /* read/write lock */
69 pci_read_config_byte(dev, 0x7c, &temp);
70 pci_write_config_byte(dev, 0x7c, 0x80);
71
72 /* set as P2P bridge */
73 pci_write_config_byte(dev, PCI_CLASS_PROG, 0x01);
74 dev->class |= 0x1;
75
76 /* restore lock */
77 pci_write_config_byte(dev, 0x7c, temp);
78}
79
80
81static void __devinit quirk_uli1575(struct pci_dev *dev)
82{
83 int i;
84
85 if (!uses_fsl_uli_m1575)
86 return;
87
88 /*
89 * ULI1575 interrupts route setup
90 */
91
92 /* ULI1575 IRQ mapping conf register maps PIRQx to IRQn */
93 for (i = 0; i < 4; i++) {
94 u8 val = uli_pirq_to_irq[i*2] | (uli_pirq_to_irq[i*2+1] << 4);
95 pci_write_config_byte(dev, 0x48 + i, val);
96 }
97
98 /* USB 1.1 OHCI controller 1: dev 28, func 0 - IRQ12 */
99 pci_write_config_byte(dev, 0x86, ULI_PIRQD);
100
101 /* USB 1.1 OHCI controller 2: dev 28, func 1 - IRQ9 */
102 pci_write_config_byte(dev, 0x87, ULI_PIRQA);
103
104 /* USB 1.1 OHCI controller 3: dev 28, func 2 - IRQ10 */
105 pci_write_config_byte(dev, 0x88, ULI_PIRQB);
106
107 /* Lan controller: dev 27, func 0 - IRQ6 */
108 pci_write_config_byte(dev, 0x89, ULI_PIRQF);
109
110 /* AC97 Audio controller: dev 29, func 0 - IRQ6 */
111 pci_write_config_byte(dev, 0x8a, ULI_PIRQF);
112
113 /* Modem controller: dev 29, func 1 - IRQ6 */
114 pci_write_config_byte(dev, 0x8b, ULI_PIRQF);
115
116 /* HD Audio controller: dev 29, func 2 - IRQ6 */
117 pci_write_config_byte(dev, 0x8c, ULI_PIRQF);
118
119 /* SATA controller: dev 31, func 1 - IRQ5 */
120 pci_write_config_byte(dev, 0x8d, ULI_PIRQE);
121
122 /* SMB interrupt: dev 30, func 1 - IRQ7 */
123 pci_write_config_byte(dev, 0x8e, ULI_PIRQG);
124
125 /* PMU ACPI SCI interrupt: dev 30, func 2 - IRQ7 */
126 pci_write_config_byte(dev, 0x8f, ULI_PIRQG);
127
128 /* USB 2.0 controller: dev 28, func 3 */
129 pci_write_config_byte(dev, 0x74, ULI_8259_IRQ11);
130
131 /* Primary PATA IDE IRQ: 14
132 * Secondary PATA IDE IRQ: 15
133 */
134 pci_write_config_byte(dev, 0x44, 0x30 | ULI_8259_IRQ14);
135 pci_write_config_byte(dev, 0x75, ULI_8259_IRQ15);
136}
137
138static void __devinit quirk_final_uli1575(struct pci_dev *dev)
139{
140 /* Set i8259 interrupt trigger
141 * IRQ 3: Level
142 * IRQ 4: Level
143 * IRQ 5: Level
144 * IRQ 6: Level
145 * IRQ 7: Level
146 * IRQ 9: Level
147 * IRQ 10: Level
148 * IRQ 11: Level
149 * IRQ 12: Level
150 * IRQ 14: Edge
151 * IRQ 15: Edge
152 */
153 if (!uses_fsl_uli_m1575)
154 return;
155
156 outb(0xfa, 0x4d0);
157 outb(0x1e, 0x4d1);
158
159 /* setup RTC */
160 CMOS_WRITE(RTC_SET, RTC_CONTROL);
161 CMOS_WRITE(RTC_24H, RTC_CONTROL);
162
163 /* ensure month, date, and week alarm fields are ignored */
164 CMOS_WRITE(0, RTC_VALID);
165
166 outb_p(0x7c, 0x72);
167 outb_p(RTC_ALARM_DONT_CARE, 0x73);
168
169 outb_p(0x7d, 0x72);
170 outb_p(RTC_ALARM_DONT_CARE, 0x73);
171}
172
173/* SATA */
174static void __devinit quirk_uli5288(struct pci_dev *dev)
175{
176 unsigned char c;
177 unsigned int d;
178
179 if (!uses_fsl_uli_m1575)
180 return;
181
182 /* read/write lock */
183 pci_read_config_byte(dev, 0x83, &c);
184 pci_write_config_byte(dev, 0x83, c|0x80);
185
186 pci_read_config_dword(dev, PCI_CLASS_REVISION, &d);
187 d = (d & 0xff) | (PCI_CLASS_STORAGE_SATA_AHCI << 8);
188 pci_write_config_dword(dev, PCI_CLASS_REVISION, d);
189
190 /* restore lock */
191 pci_write_config_byte(dev, 0x83, c);
192
193 /* disable emulated PATA mode enabled */
194 pci_read_config_byte(dev, 0x84, &c);
195 pci_write_config_byte(dev, 0x84, c & ~0x01);
196}
197
198/* PATA */
199static void __devinit quirk_uli5229(struct pci_dev *dev)
200{
201 unsigned short temp;
202
203 if (!uses_fsl_uli_m1575)
204 return;
205
206 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE |
207 PCI_COMMAND_MASTER | PCI_COMMAND_IO);
208
209 /* Enable Native IRQ 14/15 */
210 pci_read_config_word(dev, 0x4a, &temp);
211 pci_write_config_word(dev, 0x4a, temp | 0x1000);
212}
213
214/* We have to do a dummy read on the P2P for the RTC to work, WTF */
215static void __devinit quirk_final_uli5249(struct pci_dev *dev)
216{
217 int i;
218 u8 *dummy;
219 struct pci_bus *bus = dev->bus;
220
221 for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
222 if ((bus->resource[i]) &&
223 (bus->resource[i]->flags & IORESOURCE_MEM)) {
224 dummy = ioremap(bus->resource[i]->start, 0x4);
225 if (dummy) {
226 in_8(dummy);
227 iounmap(dummy);
228 }
229 break;
230 }
231 }
232}
233
234DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, 0x5249, early_uli5249);
235DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_uli1575);
236DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288);
237DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
238DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x5249, quirk_final_uli5249);
239DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x1575, quirk_final_uli1575);
240
241int uli_exclude_device(struct pci_controller *hose,
242 u_char bus, u_char devfn)
243{
244 if (bus == (hose->first_busno + 2)) {
245 /* exclude Modem controller */
246 if ((PCI_SLOT(devfn) == 29) && (PCI_FUNC(devfn) == 1))
247 return PCIBIOS_DEVICE_NOT_FOUND;
248
249 /* exclude HD Audio controller */
250 if ((PCI_SLOT(devfn) == 29) && (PCI_FUNC(devfn) == 2))
251 return PCIBIOS_DEVICE_NOT_FOUND;
252 }
253
254 return PCIBIOS_SUCCESSFUL;
255}
diff --git a/arch/powerpc/platforms/pasemi/iommu.c b/arch/powerpc/platforms/pasemi/iommu.c
index c910ec9c2bdf..6c42787fb382 100644
--- a/arch/powerpc/platforms/pasemi/iommu.c
+++ b/arch/powerpc/platforms/pasemi/iommu.c
@@ -93,7 +93,7 @@ static void iobmap_build(struct iommu_table *tbl, long index,
93 93
94 pr_debug("iobmap: build at: %lx, %lx, addr: %lx\n", index, npages, uaddr); 94 pr_debug("iobmap: build at: %lx, %lx, addr: %lx\n", index, npages, uaddr);
95 95
96 bus_addr = (tbl->it_offset + index) << PAGE_SHIFT; 96 bus_addr = (tbl->it_offset + index) << IOBMAP_PAGE_SHIFT;
97 97
98 ip = ((u32 *)tbl->it_base) + index; 98 ip = ((u32 *)tbl->it_base) + index;
99 99
@@ -118,7 +118,7 @@ static void iobmap_free(struct iommu_table *tbl, long index,
118 118
119 pr_debug("iobmap: free at: %lx, %lx\n", index, npages); 119 pr_debug("iobmap: free at: %lx, %lx\n", index, npages);
120 120
121 bus_addr = (tbl->it_offset + index) << PAGE_SHIFT; 121 bus_addr = (tbl->it_offset + index) << IOBMAP_PAGE_SHIFT;
122 122
123 ip = ((u32 *)tbl->it_base) + index; 123 ip = ((u32 *)tbl->it_base) + index;
124 124
@@ -137,7 +137,7 @@ static void iommu_table_iobmap_setup(void)
137 iommu_table_iobmap.it_busno = 0; 137 iommu_table_iobmap.it_busno = 0;
138 iommu_table_iobmap.it_offset = 0; 138 iommu_table_iobmap.it_offset = 0;
139 /* it_size is in number of entries */ 139 /* it_size is in number of entries */
140 iommu_table_iobmap.it_size = 0x80000000 >> PAGE_SHIFT; 140 iommu_table_iobmap.it_size = 0x80000000 >> IOBMAP_PAGE_SHIFT;
141 141
142 /* Initialize the common IOMMU code */ 142 /* Initialize the common IOMMU code */
143 iommu_table_iobmap.it_base = (unsigned long)iob_l2_base; 143 iommu_table_iobmap.it_base = (unsigned long)iob_l2_base;
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 18:58:30 -0500