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authorPaul Mackerras <paulus@samba.org>2005-09-26 02:04:21 -0400
committerPaul Mackerras <paulus@samba.org>2005-09-26 02:04:21 -0400
commit14cf11af6cf608eb8c23e989ddb17a715ddce109 (patch)
tree271a97ce73e265f39c569cb159c195c5b4bb3f8c /arch/powerpc/platforms
parente5baa396af7560382d2cf3f0871d616b61fc284c (diff)
powerpc: Merge enough to start building in arch/powerpc.
This creates the directory structure under arch/powerpc and a bunch of Kconfig files. It does a first-cut merge of arch/powerpc/mm, arch/powerpc/lib and arch/powerpc/platforms/powermac. This is enough to build a 32-bit powermac kernel with ARCH=powerpc. For now we are getting some unmerged files from arch/ppc/kernel and arch/ppc/syslib, or arch/ppc64/kernel. This makes some minor changes to files in those directories and files outside arch/powerpc. The boot directory is still not merged. That's going to be interesting. Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc/platforms')
-rw-r--r--arch/powerpc/platforms/4xx/Kconfig280
-rw-r--r--arch/powerpc/platforms/85xx/Kconfig86
-rw-r--r--arch/powerpc/platforms/8xx/Kconfig352
-rw-r--r--arch/powerpc/platforms/apus/Kconfig130
-rw-r--r--arch/powerpc/platforms/embedded6xx/Kconfig313
-rw-r--r--arch/powerpc/platforms/iseries/Kconfig31
-rw-r--r--arch/powerpc/platforms/powermac/Makefile9
-rw-r--r--arch/powerpc/platforms/powermac/pmac.h31
-rw-r--r--arch/powerpc/platforms/powermac/pmac_backlight.c202
-rw-r--r--arch/powerpc/platforms/powermac/pmac_cache.S359
-rw-r--r--arch/powerpc/platforms/powermac/pmac_cpufreq.c728
-rw-r--r--arch/powerpc/platforms/powermac/pmac_feature.c3062
-rw-r--r--arch/powerpc/platforms/powermac/pmac_low_i2c.c523
-rw-r--r--arch/powerpc/platforms/powermac/pmac_nvram.c584
-rw-r--r--arch/powerpc/platforms/powermac/pmac_pci.c1341
-rw-r--r--arch/powerpc/platforms/powermac/pmac_pic.c655
-rw-r--r--arch/powerpc/platforms/powermac/pmac_pic.h11
-rw-r--r--arch/powerpc/platforms/powermac/pmac_setup.c662
-rw-r--r--arch/powerpc/platforms/powermac/pmac_sleep.S396
-rw-r--r--arch/powerpc/platforms/powermac/pmac_smp.c716
-rw-r--r--arch/powerpc/platforms/powermac/pmac_time.c291
-rw-r--r--arch/powerpc/platforms/prep/Kconfig22
-rw-r--r--arch/powerpc/platforms/pseries/Kconfig47
23 files changed, 10831 insertions, 0 deletions
diff --git a/arch/powerpc/platforms/4xx/Kconfig b/arch/powerpc/platforms/4xx/Kconfig
new file mode 100644
index 000000000000..ed39d6a3d22a
--- /dev/null
+++ b/arch/powerpc/platforms/4xx/Kconfig
@@ -0,0 +1,280 @@
1config 4xx
2 bool
3 depends on 40x || 44x
4 default y
5
6config WANT_EARLY_SERIAL
7 bool
8 select SERIAL_8250
9 default n
10
11menu "AMCC 4xx options"
12 depends on 4xx
13
14choice
15 prompt "Machine Type"
16 depends on 40x
17 default WALNUT
18
19config BUBINGA
20 bool "Bubinga"
21 select WANT_EARLY_SERIAL
22 help
23 This option enables support for the IBM 405EP evaluation board.
24
25config CPCI405
26 bool "CPCI405"
27 help
28 This option enables support for the CPCI405 board.
29
30config EP405
31 bool "EP405/EP405PC"
32 help
33 This option enables support for the EP405/EP405PC boards.
34
35config REDWOOD_5
36 bool "Redwood-5"
37 help
38 This option enables support for the IBM STB04 evaluation board.
39
40config REDWOOD_6
41 bool "Redwood-6"
42 help
43 This option enables support for the IBM STBx25xx evaluation board.
44
45config SYCAMORE
46 bool "Sycamore"
47 help
48 This option enables support for the IBM PPC405GPr evaluation board.
49
50config WALNUT
51 bool "Walnut"
52 help
53 This option enables support for the IBM PPC405GP evaluation board.
54
55config XILINX_ML300
56 bool "Xilinx-ML300"
57 help
58 This option enables support for the Xilinx ML300 evaluation board.
59
60endchoice
61
62choice
63 prompt "Machine Type"
64 depends on 44x
65 default EBONY
66
67config BAMBOO
68 bool "Bamboo"
69 select WANT_EARLY_SERIAL
70 help
71 This option enables support for the IBM PPC440EP evaluation board.
72
73config EBONY
74 bool "Ebony"
75 select WANT_EARLY_SERIAL
76 help
77 This option enables support for the IBM PPC440GP evaluation board.
78
79config LUAN
80 bool "Luan"
81 select WANT_EARLY_SERIAL
82 help
83 This option enables support for the IBM PPC440SP evaluation board.
84
85config OCOTEA
86 bool "Ocotea"
87 select WANT_EARLY_SERIAL
88 help
89 This option enables support for the IBM PPC440GX evaluation board.
90
91endchoice
92
93config EP405PC
94 bool "EP405PC Support"
95 depends on EP405
96
97
98# It's often necessary to know the specific 4xx processor type.
99# Fortunately, it is impled (so far) from the board type, so we
100# don't need to ask more redundant questions.
101config NP405H
102 bool
103 depends on ASH
104 default y
105
106config 440EP
107 bool
108 depends on BAMBOO
109 select PPC_FPU
110 default y
111
112config 440GP
113 bool
114 depends on EBONY
115 default y
116
117config 440GX
118 bool
119 depends on OCOTEA
120 default y
121
122config 440SP
123 bool
124 depends on LUAN
125 default y
126
127config 440
128 bool
129 depends on 440GP || 440SP || 440EP
130 default y
131
132config 440A
133 bool
134 depends on 440GX
135 default y
136
137config IBM440EP_ERR42
138 bool
139 depends on 440EP
140 default y
141
142# All 405-based cores up until the 405GPR and 405EP have this errata.
143config IBM405_ERR77
144 bool
145 depends on 40x && !403GCX && !405GPR && !405EP
146 default y
147
148# All 40x-based cores, up until the 405GPR and 405EP have this errata.
149config IBM405_ERR51
150 bool
151 depends on 40x && !405GPR && !405EP
152 default y
153
154config BOOKE
155 bool
156 depends on 44x
157 default y
158
159config IBM_OCP
160 bool
161 depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT
162 default y
163
164config XILINX_OCP
165 bool
166 depends on XILINX_ML300
167 default y
168
169config IBM_EMAC4
170 bool
171 depends on 440GX || 440SP
172 default y
173
174config BIOS_FIXUP
175 bool
176 depends on BUBINGA || EP405 || SYCAMORE || WALNUT
177 default y
178
179# OAK doesn't exist but wanted to keep this around for any future 403GCX boards
180config 403GCX
181 bool
182 depends OAK
183 default y
184
185config 405EP
186 bool
187 depends on BUBINGA
188 default y
189
190config 405GP
191 bool
192 depends on CPCI405 || EP405 || WALNUT
193 default y
194
195config 405GPR
196 bool
197 depends on SYCAMORE
198 default y
199
200config VIRTEX_II_PRO
201 bool
202 depends on XILINX_ML300
203 default y
204
205config STB03xxx
206 bool
207 depends on REDWOOD_5 || REDWOOD_6
208 default y
209
210config EMBEDDEDBOOT
211 bool
212 depends on EP405 || XILINX_ML300
213 default y
214
215config IBM_OPENBIOS
216 bool
217 depends on ASH || BUBINGA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT
218 default y
219
220config PPC4xx_DMA
221 bool "PPC4xx DMA controller support"
222 depends on 4xx
223
224config PPC4xx_EDMA
225 bool
226 depends on !STB03xxx && PPC4xx_DMA
227 default y
228
229config PPC_GEN550
230 bool
231 depends on 4xx
232 default y
233
234choice
235 prompt "TTYS0 device and default console"
236 depends on 40x
237 default UART0_TTYS0
238
239config UART0_TTYS0
240 bool "UART0"
241
242config UART0_TTYS1
243 bool "UART1"
244
245endchoice
246
247config SERIAL_SICC
248 bool "SICC Serial port support"
249 depends on STB03xxx
250
251config UART1_DFLT_CONSOLE
252 bool
253 depends on SERIAL_SICC && UART0_TTYS1
254 default y
255
256config SERIAL_SICC_CONSOLE
257 bool
258 depends on SERIAL_SICC && UART0_TTYS1
259 default y
260endmenu
261
262
263menu "IBM 40x options"
264 depends on 40x
265
266config SERIAL_SICC
267 bool "SICC Serial port"
268 depends on STB03xxx
269
270config UART1_DFLT_CONSOLE
271 bool
272 depends on SERIAL_SICC && UART0_TTYS1
273 default y
274
275config SERIAL_SICC_CONSOLE
276 bool
277 depends on SERIAL_SICC && UART0_TTYS1
278 default y
279
280endmenu
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
new file mode 100644
index 000000000000..c5bc2821d991
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -0,0 +1,86 @@
1config 85xx
2 bool
3 depends on E500
4 default y
5
6config PPC_INDIRECT_PCI_BE
7 bool
8 depends on 85xx
9 default y
10
11menu "Freescale 85xx options"
12 depends on E500
13
14choice
15 prompt "Machine Type"
16 depends on 85xx
17 default MPC8540_ADS
18
19config MPC8540_ADS
20 bool "Freescale MPC8540 ADS"
21 help
22 This option enables support for the MPC 8540 ADS evaluation board.
23
24config MPC8548_CDS
25 bool "Freescale MPC8548 CDS"
26 help
27 This option enablese support for the MPC8548 CDS evaluation board.
28
29config MPC8555_CDS
30 bool "Freescale MPC8555 CDS"
31 help
32 This option enablese support for the MPC8555 CDS evaluation board.
33
34config MPC8560_ADS
35 bool "Freescale MPC8560 ADS"
36 help
37 This option enables support for the MPC 8560 ADS evaluation board.
38
39config SBC8560
40 bool "WindRiver PowerQUICC III SBC8560"
41 help
42 This option enables support for the WindRiver PowerQUICC III
43 SBC8560 board.
44
45config STX_GP3
46 bool "Silicon Turnkey Express GP3"
47 help
48 This option enables support for the Silicon Turnkey Express GP3
49 board.
50
51endchoice
52
53# It's often necessary to know the specific 85xx processor type.
54# Fortunately, it is implied (so far) from the board type, so we
55# don't need to ask more redundant questions.
56config MPC8540
57 bool
58 depends on MPC8540_ADS
59 default y
60
61config MPC8548
62 bool
63 depends on MPC8548_CDS
64 default y
65
66config MPC8555
67 bool
68 depends on MPC8555_CDS
69 default y
70
71config MPC8560
72 bool
73 depends on SBC8560 || MPC8560_ADS || STX_GP3
74 default y
75
76config 85xx_PCI2
77 bool "Supprt for 2nd PCI host controller"
78 depends on MPC8555_CDS
79 default y
80
81config PPC_GEN550
82 bool
83 depends on MPC8540 || SBC8560 || MPC8555
84 default y
85
86endmenu
diff --git a/arch/powerpc/platforms/8xx/Kconfig b/arch/powerpc/platforms/8xx/Kconfig
new file mode 100644
index 000000000000..c8c0ba3cf8e8
--- /dev/null
+++ b/arch/powerpc/platforms/8xx/Kconfig
@@ -0,0 +1,352 @@
1config FADS
2 bool
3
4choice
5 prompt "8xx Machine Type"
6 depends on 8xx
7 default RPXLITE
8
9config RPXLITE
10 bool "RPX-Lite"
11 ---help---
12 Single-board computers based around the PowerPC MPC8xx chips and
13 intended for embedded applications. The following types are
14 supported:
15
16 RPX-Lite:
17 Embedded Planet RPX Lite. PC104 form-factor SBC based on the MPC823.
18
19 RPX-Classic:
20 Embedded Planet RPX Classic Low-fat. Credit-card-size SBC based on
21 the MPC 860
22
23 BSE-IP:
24 Bright Star Engineering ip-Engine.
25
26 TQM823L:
27 TQM850L:
28 TQM855L:
29 TQM860L:
30 MPC8xx based family of mini modules, half credit card size,
31 up to 64 MB of RAM, 8 MB Flash, (Fast) Ethernet, 2 x serial ports,
32 2 x CAN bus interface, ...
33 Manufacturer: TQ Components, www.tq-group.de
34 Date of Release: October (?) 1999
35 End of Life: not yet :-)
36 URL:
37 - module: <http://www.denx.de/PDF/TQM8xxLHWM201.pdf>
38 - starter kit: <http://www.denx.de/PDF/STK8xxLHWM201.pdf>
39 - images: <http://www.denx.de/embedded-ppc-en.html>
40
41 FPS850L:
42 FingerPrint Sensor System (based on TQM850L)
43 Manufacturer: IKENDI AG, <http://www.ikendi.com/>
44 Date of Release: November 1999
45 End of life: end 2000 ?
46 URL: see TQM850L
47
48 IVMS8:
49 MPC860 based board used in the "Integrated Voice Mail System",
50 Small Version (8 voice channels)
51 Manufacturer: Speech Design, <http://www.speech-design.de/>
52 Date of Release: December 2000 (?)
53 End of life: -
54 URL: <http://www.speech-design.de/>
55
56 IVML24:
57 MPC860 based board used in the "Integrated Voice Mail System",
58 Large Version (24 voice channels)
59 Manufacturer: Speech Design, <http://www.speech-design.de/>
60 Date of Release: March 2001 (?)
61 End of life: -
62 URL: <http://www.speech-design.de/>
63
64 HERMES:
65 Hermes-Pro ISDN/LAN router with integrated 8 x hub
66 Manufacturer: Multidata Gesellschaft fur Datentechnik und Informatik
67 <http://www.multidata.de/>
68 Date of Release: 2000 (?)
69 End of life: -
70 URL: <http://www.multidata.de/english/products/hpro.htm>
71
72 IP860:
73 VMEBus IP (Industry Pack) carrier board with MPC860
74 Manufacturer: MicroSys GmbH, <http://www.microsys.de/>
75 Date of Release: ?
76 End of life: -
77 URL: <http://www.microsys.de/html/ip860.html>
78
79 PCU_E:
80 PCU = Peripheral Controller Unit, Extended
81 Manufacturer: Siemens AG, ICN (Information and Communication Networks)
82 <http://www.siemens.de/page/1,3771,224315-1-999_2_226207-0,00.html>
83 Date of Release: April 2001
84 End of life: August 2001
85 URL: n. a.
86
87config RPXCLASSIC
88 bool "RPX-Classic"
89 help
90 The RPX-Classic is a single-board computer based on the Motorola
91 MPC860. It features 16MB of DRAM and a variable amount of flash,
92 I2C EEPROM, thermal monitoring, a PCMCIA slot, a DIP switch and two
93 LEDs. Variants with Ethernet ports exist. Say Y here to support it
94 directly.
95
96config BSEIP
97 bool "BSE-IP"
98 help
99 Say Y here to support the Bright Star Engineering ipEngine SBC.
100 This is a credit-card-sized device featuring a MPC823 processor,
101 26MB DRAM, 4MB flash, Ethernet, a 16K-gate FPGA, USB, an LCD/video
102 controller, and two RS232 ports.
103
104config MPC8XXFADS
105 bool "FADS"
106 select FADS
107
108config MPC86XADS
109 bool "MPC86XADS"
110 help
111 MPC86x Application Development System by Freescale Semiconductor.
112 The MPC86xADS is meant to serve as a platform for s/w and h/w
113 development around the MPC86X processor families.
114 select FADS
115
116config MPC885ADS
117 bool "MPC885ADS"
118 help
119 Freescale Semiconductor MPC885 Application Development System (ADS).
120 Also known as DUET.
121 The MPC885ADS is meant to serve as a platform for s/w and h/w
122 development around the MPC885 processor family.
123
124config TQM823L
125 bool "TQM823L"
126 help
127 Say Y here to support the TQM823L, one of an MPC8xx-based family of
128 mini SBCs (half credit-card size) from TQ Components first released
129 in late 1999. Technical references are at
130 <http://www.denx.de/PDF/TQM8xxLHWM201.pdf>, and
131 <http://www.denx.de/PDF/STK8xxLHWM201.pdf>, and an image at
132 <http://www.denx.de/embedded-ppc-en.html>.
133
134config TQM850L
135 bool "TQM850L"
136 help
137 Say Y here to support the TQM850L, one of an MPC8xx-based family of
138 mini SBCs (half credit-card size) from TQ Components first released
139 in late 1999. Technical references are at
140 <http://www.denx.de/PDF/TQM8xxLHWM201.pdf>, and
141 <http://www.denx.de/PDF/STK8xxLHWM201.pdf>, and an image at
142 <http://www.denx.de/embedded-ppc-en.html>.
143
144config TQM855L
145 bool "TQM855L"
146 help
147 Say Y here to support the TQM855L, one of an MPC8xx-based family of
148 mini SBCs (half credit-card size) from TQ Components first released
149 in late 1999. Technical references are at
150 <http://www.denx.de/PDF/TQM8xxLHWM201.pdf>, and
151 <http://www.denx.de/PDF/STK8xxLHWM201.pdf>, and an image at
152 <http://www.denx.de/embedded-ppc-en.html>.
153
154config TQM860L
155 bool "TQM860L"
156 help
157 Say Y here to support the TQM860L, one of an MPC8xx-based family of
158 mini SBCs (half credit-card size) from TQ Components first released
159 in late 1999. Technical references are at
160 <http://www.denx.de/PDF/TQM8xxLHWM201.pdf>, and
161 <http://www.denx.de/PDF/STK8xxLHWM201.pdf>, and an image at
162 <http://www.denx.de/embedded-ppc-en.html>.
163
164config FPS850L
165 bool "FPS850L"
166
167config IVMS8
168 bool "IVMS8"
169 help
170 Say Y here to support the Integrated Voice-Mail Small 8-channel SBC
171 from Speech Design, released March 2001. The manufacturer's website
172 is at <http://www.speech-design.de/>.
173
174config IVML24
175 bool "IVML24"
176 help
177 Say Y here to support the Integrated Voice-Mail Large 24-channel SBC
178 from Speech Design, released March 2001. The manufacturer's website
179 is at <http://www.speech-design.de/>.
180
181config HERMES_PRO
182 bool "HERMES"
183
184config IP860
185 bool "IP860"
186
187config LWMON
188 bool "LWMON"
189
190config PCU_E
191 bool "PCU_E"
192
193config CCM
194 bool "CCM"
195
196config LANTEC
197 bool "LANTEC"
198
199config MBX
200 bool "MBX"
201 help
202 MBX is a line of Motorola single-board computer based around the
203 MPC821 and MPC860 processors, and intended for embedded-controller
204 applications. Say Y here to support these boards directly.
205
206config WINCEPT
207 bool "WinCept"
208 help
209 The Wincept 100/110 is a Motorola single-board computer based on the
210 MPC821 PowerPC, introduced in 1998 and designed to be used in
211 thin-client machines. Say Y to support it directly.
212
213endchoice
214
215#
216# MPC8xx Communication options
217#
218
219menu "MPC8xx CPM Options"
220 depends on 8xx
221
222config SCC_ENET
223 bool "CPM SCC Ethernet"
224 depends on NET_ETHERNET
225 help
226 Enable Ethernet support via the Motorola MPC8xx serial
227 communications controller.
228
229choice
230 prompt "SCC used for Ethernet"
231 depends on SCC_ENET
232 default SCC1_ENET
233
234config SCC1_ENET
235 bool "SCC1"
236 help
237 Use MPC8xx serial communications controller 1 to drive Ethernet
238 (default).
239
240config SCC2_ENET
241 bool "SCC2"
242 help
243 Use MPC8xx serial communications controller 2 to drive Ethernet.
244
245config SCC3_ENET
246 bool "SCC3"
247 help
248 Use MPC8xx serial communications controller 3 to drive Ethernet.
249
250endchoice
251
252config FEC_ENET
253 bool "860T FEC Ethernet"
254 depends on NET_ETHERNET
255 help
256 Enable Ethernet support via the Fast Ethernet Controller (FCC) on
257 the Motorola MPC8260.
258
259config USE_MDIO
260 bool "Use MDIO for PHY configuration"
261 depends on FEC_ENET
262 help
263 On some boards the hardware configuration of the ethernet PHY can be
264 used without any software interaction over the MDIO interface, so
265 all MII code can be omitted. Say N here if unsure or if you don't
266 need link status reports.
267
268config FEC_AM79C874
269 bool "Support AMD79C874 PHY"
270 depends on USE_MDIO
271
272config FEC_LXT970
273 bool "Support LXT970 PHY"
274 depends on USE_MDIO
275
276config FEC_LXT971
277 bool "Support LXT971 PHY"
278 depends on USE_MDIO
279
280config FEC_QS6612
281 bool "Support QS6612 PHY"
282 depends on USE_MDIO
283
284config ENET_BIG_BUFFERS
285 bool "Use Big CPM Ethernet Buffers"
286 depends on SCC_ENET || FEC_ENET
287 help
288 Allocate large buffers for MPC8xx Ethernet. Increases throughput
289 and decreases the likelihood of dropped packets, but costs memory.
290
291config HTDMSOUND
292 bool "Embedded Planet HIOX Audio"
293 depends on SOUND=y
294
295# This doesn't really belong here, but it is convenient to ask
296# 8xx specific questions.
297comment "Generic MPC8xx Options"
298
299config 8xx_COPYBACK
300 bool "Copy-Back Data Cache (else Writethrough)"
301 help
302 Saying Y here will cause the cache on an MPC8xx processor to be used
303 in Copy-Back mode. If you say N here, it is used in Writethrough
304 mode.
305
306 If in doubt, say Y here.
307
308config 8xx_CPU6
309 bool "CPU6 Silicon Errata (860 Pre Rev. C)"
310 help
311 MPC860 CPUs, prior to Rev C have some bugs in the silicon, which
312 require workarounds for Linux (and most other OSes to work). If you
313 get a BUG() very early in boot, this might fix the problem. For
314 more details read the document entitled "MPC860 Family Device Errata
315 Reference" on Motorola's website. This option also incurs a
316 performance hit.
317
318 If in doubt, say N here.
319
320choice
321 prompt "Microcode patch selection"
322 default NO_UCODE_PATCH
323 help
324 Help not implemented yet, coming soon.
325
326config NO_UCODE_PATCH
327 bool "None"
328
329config USB_SOF_UCODE_PATCH
330 bool "USB SOF patch"
331 help
332 Help not implemented yet, coming soon.
333
334config I2C_SPI_UCODE_PATCH
335 bool "I2C/SPI relocation patch"
336 help
337 Help not implemented yet, coming soon.
338
339config I2C_SPI_SMC1_UCODE_PATCH
340 bool "I2C/SPI/SMC1 relocation patch"
341 help
342 Help not implemented yet, coming soon.
343
344endchoice
345
346config UCODE_PATCH
347 bool
348 default y
349 depends on !NO_UCODE_PATCH
350
351endmenu
352
diff --git a/arch/powerpc/platforms/apus/Kconfig b/arch/powerpc/platforms/apus/Kconfig
new file mode 100644
index 000000000000..6bde3bffed86
--- /dev/null
+++ b/arch/powerpc/platforms/apus/Kconfig
@@ -0,0 +1,130 @@
1
2config AMIGA
3 bool
4 depends on APUS
5 default y
6 help
7 This option enables support for the Amiga series of computers.
8
9config ZORRO
10 bool
11 depends on APUS
12 default y
13 help
14 This enables support for the Zorro bus in the Amiga. If you have
15 expansion cards in your Amiga that conform to the Amiga
16 AutoConfig(tm) specification, say Y, otherwise N. Note that even
17 expansion cards that do not fit in the Zorro slots but fit in e.g.
18 the CPU slot may fall in this category, so you have to say Y to let
19 Linux use these.
20
21config ABSTRACT_CONSOLE
22 bool
23 depends on APUS
24 default y
25
26config APUS_FAST_EXCEPT
27 bool
28 depends on APUS
29 default y
30
31config AMIGA_PCMCIA
32 bool "Amiga 1200/600 PCMCIA support"
33 depends on APUS && EXPERIMENTAL
34 help
35 Include support in the kernel for pcmcia on Amiga 1200 and Amiga
36 600. If you intend to use pcmcia cards say Y; otherwise say N.
37
38config AMIGA_BUILTIN_SERIAL
39 tristate "Amiga builtin serial support"
40 depends on APUS
41 help
42 If you want to use your Amiga's built-in serial port in Linux,
43 answer Y.
44
45 To compile this driver as a module, choose M here.
46
47config GVPIOEXT
48 tristate "GVP IO-Extender support"
49 depends on APUS
50 help
51 If you want to use a GVP IO-Extender serial card in Linux, say Y.
52 Otherwise, say N.
53
54config GVPIOEXT_LP
55 tristate "GVP IO-Extender parallel printer support"
56 depends on GVPIOEXT
57 help
58 Say Y to enable driving a printer from the parallel port on your
59 GVP IO-Extender card, N otherwise.
60
61config GVPIOEXT_PLIP
62 tristate "GVP IO-Extender PLIP support"
63 depends on GVPIOEXT
64 help
65 Say Y to enable doing IP over the parallel port on your GVP
66 IO-Extender card, N otherwise.
67
68config MULTIFACE_III_TTY
69 tristate "Multiface Card III serial support"
70 depends on APUS
71 help
72 If you want to use a Multiface III card's serial port in Linux,
73 answer Y.
74
75 To compile this driver as a module, choose M here.
76
77config A2232
78 tristate "Commodore A2232 serial support (EXPERIMENTAL)"
79 depends on EXPERIMENTAL && APUS
80 ---help---
81 This option supports the 2232 7-port serial card shipped with the
82 Amiga 2000 and other Zorro-bus machines, dating from 1989. At
83 a max of 19,200 bps, the ports are served by a 6551 ACIA UART chip
84 each, plus a 8520 CIA, and a master 6502 CPU and buffer as well. The
85 ports were connected with 8 pin DIN connectors on the card bracket,
86 for which 8 pin to DB25 adapters were supplied. The card also had
87 jumpers internally to toggle various pinning configurations.
88
89 This driver can be built as a module; but then "generic_serial"
90 will also be built as a module. This has to be loaded before
91 "ser_a2232". If you want to do this, answer M here.
92
93config WHIPPET_SERIAL
94 tristate "Hisoft Whippet PCMCIA serial support"
95 depends on AMIGA_PCMCIA
96 help
97 HiSoft has a web page at <http://www.hisoft.co.uk/>, but there
98 is no listing for the Whippet in their Amiga section.
99
100config APNE
101 tristate "PCMCIA NE2000 support"
102 depends on AMIGA_PCMCIA
103 help
104 If you have a PCMCIA NE2000 compatible adapter, say Y. Otherwise,
105 say N.
106
107 To compile this driver as a module, choose M here: the
108 module will be called apne.
109
110config SERIAL_CONSOLE
111 bool "Support for serial port console"
112 depends on APUS && (AMIGA_BUILTIN_SERIAL=y || GVPIOEXT=y || MULTIFACE_III_TTY=y)
113
114config HEARTBEAT
115 bool "Use power LED as a heartbeat"
116 depends on APUS
117 help
118 Use the power-on LED on your machine as a load meter. The exact
119 behavior is platform-dependent, but normally the flash frequency is
120 a hyperbolic function of the 5-minute load average.
121
122config PROC_HARDWARE
123 bool "/proc/hardware support"
124 depends on APUS
125
126source "drivers/zorro/Kconfig"
127
128config PCI_PERMEDIA
129 bool "PCI for Permedia2"
130 depends on !4xx && !8xx && APUS
diff --git a/arch/powerpc/platforms/embedded6xx/Kconfig b/arch/powerpc/platforms/embedded6xx/Kconfig
new file mode 100644
index 000000000000..4f3551430596
--- /dev/null
+++ b/arch/powerpc/platforms/embedded6xx/Kconfig
@@ -0,0 +1,313 @@
1choice
2 prompt "Machine Type"
3 depends on EMBEDDED6xx
4
5config APUS
6 bool "Amiga-APUS"
7 depends on BROKEN
8 help
9 Select APUS if configuring for a PowerUP Amiga.
10 More information is available at:
11 <http://linux-apus.sourceforge.net/>.
12
13config KATANA
14 bool "Artesyn-Katana"
15 help
16 Select KATANA if configuring an Artesyn KATANA 750i or 3750
17 cPCI board.
18
19config WILLOW
20 bool "Cogent-Willow"
21
22config CPCI690
23 bool "Force-CPCI690"
24 help
25 Select CPCI690 if configuring a Force CPCI690 cPCI board.
26
27config POWERPMC250
28 bool "Force-PowerPMC250"
29
30config CHESTNUT
31 bool "IBM 750FX Eval board or 750GX Eval board"
32 help
33 Select CHESTNUT if configuring an IBM 750FX Eval Board or a
34 IBM 750GX Eval board.
35
36config SPRUCE
37 bool "IBM-Spruce"
38
39config HDPU
40 bool "Sky-HDPU"
41 help
42 Select HDPU if configuring a Sky Computers Compute Blade.
43
44config HDPU_FEATURES
45 depends HDPU
46 tristate "HDPU-Features"
47 help
48 Select to enable HDPU enhanced features.
49
50config EV64260
51 bool "Marvell-EV64260BP"
52 help
53 Select EV64260 if configuring a Marvell (formerly Galileo)
54 EV64260BP Evaluation platform.
55
56config LOPEC
57 bool "Motorola-LoPEC"
58
59config MVME5100
60 bool "Motorola-MVME5100"
61
62config PPLUS
63 bool "Motorola-PowerPlus"
64
65config PRPMC750
66 bool "Motorola-PrPMC750"
67
68config PRPMC800
69 bool "Motorola-PrPMC800"
70
71config SANDPOINT
72 bool "Motorola-Sandpoint"
73 help
74 Select SANDPOINT if configuring for a Motorola Sandpoint X3
75 (any flavor).
76
77config RADSTONE_PPC7D
78 bool "Radstone Technology PPC7D board"
79
80config PAL4
81 bool "SBS-Palomar4"
82
83config GEMINI
84 bool "Synergy-Gemini"
85 depends on BROKEN
86 help
87 Select Gemini if configuring for a Synergy Microsystems' Gemini
88 series Single Board Computer. More information is available at:
89 <http://www.synergymicro.com/PressRel/97_10_15.html>.
90
91config EST8260
92 bool "EST8260"
93 ---help---
94 The EST8260 is a single-board computer manufactured by Wind River
95 Systems, Inc. (formerly Embedded Support Tools Corp.) and based on
96 the MPC8260. Wind River Systems has a website at
97 <http://www.windriver.com/>, but the EST8260 cannot be found on it
98 and has probably been discontinued or rebadged.
99
100config SBC82xx
101 bool "SBC82xx"
102 ---help---
103 SBC PowerQUICC II, single-board computer with MPC82xx CPU
104 Manufacturer: Wind River Systems, Inc.
105 Date of Release: May 2003
106 End of Life: -
107 URL: <http://www.windriver.com/>
108
109config SBS8260
110 bool "SBS8260"
111
112config RPX8260
113 bool "RPXSUPER"
114
115config TQM8260
116 bool "TQM8260"
117 ---help---
118 MPC8260 based module, little larger than credit card,
119 up to 128 MB global + 64 MB local RAM, 32 MB Flash,
120 32 kB EEPROM, 256 kB L@ Cache, 10baseT + 100baseT Ethernet,
121 2 x serial ports, ...
122 Manufacturer: TQ Components, www.tq-group.de
123 Date of Release: June 2001
124 End of Life: not yet :-)
125 URL: <http://www.denx.de/PDF/TQM82xx_SPEC_Rev005.pdf>
126
127config ADS8272
128 bool "ADS8272"
129
130config PQ2FADS
131 bool "Freescale-PQ2FADS"
132 help
133 Select PQ2FADS if you wish to configure for a Freescale
134 PQ2FADS board (-VR or -ZU).
135
136config LITE5200
137 bool "Freescale LITE5200 / (IceCube)"
138 select PPC_MPC52xx
139 help
140 Support for the LITE5200 dev board for the MPC5200 from Freescale.
141 This is for the LITE5200 version 2.0 board. Don't know if it changes
142 much but it's only been tested on this board version. I think this
143 board is also known as IceCube.
144
145config MPC834x_SYS
146 bool "Freescale MPC834x SYS"
147 help
148 This option enables support for the MPC 834x SYS evaluation board.
149
150 Be aware that PCI buses can only function when SYS board is plugged
151 into the PIB (Platform IO Board) board from Freescale which provide
152 3 PCI slots. The PIBs PCI initialization is the bootloader's
153 responsiblilty.
154
155config EV64360
156 bool "Marvell-EV64360BP"
157 help
158 Select EV64360 if configuring a Marvell EV64360BP Evaluation
159 platform.
160endchoice
161
162config PQ2ADS
163 bool
164 depends on ADS8272
165 default y
166
167config TQM8xxL
168 bool
169 depends on 8xx && (TQM823L || TQM850L || FPS850L || TQM855L || TQM860L)
170 default y
171
172config PPC_MPC52xx
173 bool
174
175config 8260
176 bool "CPM2 Support" if WILLOW
177 depends on 6xx
178 default y if TQM8260 || RPX8260 || EST8260 || SBS8260 || SBC82xx || PQ2FADS
179 help
180 The MPC8260 is a typical embedded CPU made by Motorola. Selecting
181 this option means that you wish to build a kernel for a machine with
182 an 8260 class CPU.
183
184config 8272
185 bool
186 depends on 6xx
187 default y if ADS8272
188 select 8260
189 help
190 The MPC8272 CPM has a different internal dpram setup than other CPM2
191 devices
192
193config 83xx
194 bool
195 default y if MPC834x_SYS
196
197config MPC834x
198 bool
199 default y if MPC834x_SYS
200
201config CPM2
202 bool
203 depends on 8260 || MPC8560 || MPC8555
204 default y
205 help
206 The CPM2 (Communications Processor Module) is a coprocessor on
207 embedded CPUs made by Motorola. Selecting this option means that
208 you wish to build a kernel for a machine with a CPM2 coprocessor
209 on it (826x, 827x, 8560).
210
211config PPC_GEN550
212 bool
213 depends on SANDPOINT || SPRUCE || PPLUS || \
214 PRPMC750 || PRPMC800 || LOPEC || \
215 (EV64260 && !SERIAL_MPSC) || CHESTNUT || RADSTONE_PPC7D || \
216 83xx
217 default y
218
219config FORCE
220 bool
221 depends on 6xx && POWERPMC250
222 default y
223
224config GT64260
225 bool
226 depends on EV64260 || CPCI690
227 default y
228
229config MV64360 # Really MV64360 & MV64460
230 bool
231 depends on CHESTNUT || KATANA || RADSTONE_PPC7D || HDPU || EV64360
232 default y
233
234config MV64X60
235 bool
236 depends on (GT64260 || MV64360)
237 default y
238
239menu "Set bridge options"
240 depends on MV64X60
241
242config NOT_COHERENT_CACHE
243 bool "Turn off Cache Coherency"
244 default n
245 help
246 Some 64x60 bridges lock up when trying to enforce cache coherency.
247 When this option is selected, cache coherency will be turned off.
248 Note that this can cause other problems (e.g., stale data being
249 speculatively loaded via a cached mapping). Use at your own risk.
250
251config MV64X60_BASE
252 hex "Set bridge base used by firmware"
253 default "0xf1000000"
254 help
255 A firmware can leave the base address of the bridge's registers at
256 a non-standard location. If so, set this value to reflect the
257 address of that non-standard location.
258
259config MV64X60_NEW_BASE
260 hex "Set bridge base used by kernel"
261 default "0xf1000000"
262 help
263 If the current base address of the bridge's registers is not where
264 you want it, set this value to the address that you want it moved to.
265
266endmenu
267
268config NONMONARCH_SUPPORT
269 bool "Enable Non-Monarch Support"
270 depends on PRPMC800
271
272config HARRIER
273 bool
274 depends on PRPMC800
275 default y
276
277config EPIC_SERIAL_MODE
278 bool
279 depends on 6xx && (LOPEC || SANDPOINT)
280 default y
281
282config MPC10X_BRIDGE
283 bool
284 depends on POWERPMC250 || LOPEC || SANDPOINT
285 default y
286
287config MPC10X_OPENPIC
288 bool
289 depends on POWERPMC250 || LOPEC || SANDPOINT
290 default y
291
292config MPC10X_STORE_GATHERING
293 bool "Enable MPC10x store gathering"
294 depends on MPC10X_BRIDGE
295
296config SANDPOINT_ENABLE_UART1
297 bool "Enable DUART mode on Sandpoint"
298 depends on SANDPOINT
299 help
300 If this option is enabled then the MPC824x processor will run
301 in DUART mode instead of UART mode.
302
303config HARRIER_STORE_GATHERING
304 bool "Enable Harrier store gathering"
305 depends on HARRIER
306
307config MVME5100_IPMC761_PRESENT
308 bool "MVME5100 configured with an IPMC761"
309 depends on MVME5100
310
311config SPRUCE_BAUD_33M
312 bool "Spruce baud clock support"
313 depends on SPRUCE
diff --git a/arch/powerpc/platforms/iseries/Kconfig b/arch/powerpc/platforms/iseries/Kconfig
new file mode 100644
index 000000000000..3d957a30c8c2
--- /dev/null
+++ b/arch/powerpc/platforms/iseries/Kconfig
@@ -0,0 +1,31 @@
1
2menu "iSeries device drivers"
3 depends on PPC_ISERIES
4
5config VIOCONS
6 tristate "iSeries Virtual Console Support"
7
8config VIODASD
9 tristate "iSeries Virtual I/O disk support"
10 help
11 If you are running on an iSeries system and you want to use
12 virtual disks created and managed by OS/400, say Y.
13
14config VIOCD
15 tristate "iSeries Virtual I/O CD support"
16 help
17 If you are running Linux on an IBM iSeries system and you want to
18 read a CD drive owned by OS/400, say Y here.
19
20config VIOTAPE
21 tristate "iSeries Virtual Tape Support"
22 help
23 If you are running Linux on an iSeries system and you want Linux
24 to read and/or write a tape drive owned by OS/400, say Y here.
25
26endmenu
27
28config VIOPATH
29 bool
30 depends on VIOCONS || VIODASD || VIOCD || VIOTAPE || VETH
31 default y
diff --git a/arch/powerpc/platforms/powermac/Makefile b/arch/powerpc/platforms/powermac/Makefile
new file mode 100644
index 000000000000..37b7341396e4
--- /dev/null
+++ b/arch/powerpc/platforms/powermac/Makefile
@@ -0,0 +1,9 @@
1obj-$(CONFIG_PPC_PMAC) += pmac_pic.o pmac_setup.o pmac_time.o \
2 pmac_feature.o pmac_pci.o pmac_sleep.o \
3 pmac_low_i2c.o pmac_cache.o
4obj-$(CONFIG_PMAC_BACKLIGHT) += pmac_backlight.o
5obj-$(CONFIG_CPU_FREQ_PMAC) += pmac_cpufreq.o
6ifeq ($(CONFIG_PPC_PMAC),y)
7obj-$(CONFIG_NVRAM) += pmac_nvram.o
8obj-$(CONFIG_SMP) += pmac_smp.o
9endif
diff --git a/arch/powerpc/platforms/powermac/pmac.h b/arch/powerpc/platforms/powermac/pmac.h
new file mode 100644
index 000000000000..40e1c5030f74
--- /dev/null
+++ b/arch/powerpc/platforms/powermac/pmac.h
@@ -0,0 +1,31 @@
1#ifndef __PMAC_H__
2#define __PMAC_H__
3
4#include <linux/pci.h>
5#include <linux/ide.h>
6
7/*
8 * Declaration for the various functions exported by the
9 * pmac_* files. Mostly for use by pmac_setup
10 */
11
12extern void pmac_get_boot_time(struct rtc_time *tm);
13extern void pmac_get_rtc_time(struct rtc_time *tm);
14extern int pmac_set_rtc_time(struct rtc_time *tm);
15extern void pmac_read_rtc_time(void);
16extern void pmac_calibrate_decr(void);
17
18extern void pmac_pcibios_fixup(void);
19extern void pmac_pci_init(void);
20extern void pmac_setup_pci_dma(void);
21extern void pmac_check_ht_link(void);
22
23extern void pmac_setup_smp(void);
24
25extern unsigned long pmac_ide_get_base(int index);
26extern void pmac_ide_init_hwif_ports(hw_regs_t *hw,
27 unsigned long data_port, unsigned long ctrl_port, int *irq);
28
29extern void pmac_nvram_init(void);
30
31#endif /* __PMAC_H__ */
diff --git a/arch/powerpc/platforms/powermac/pmac_backlight.c b/arch/powerpc/platforms/powermac/pmac_backlight.c
new file mode 100644
index 000000000000..8be2f7d071f0
--- /dev/null
+++ b/arch/powerpc/platforms/powermac/pmac_backlight.c
@@ -0,0 +1,202 @@
1/*
2 * Miscellaneous procedures for dealing with the PowerMac hardware.
3 * Contains support for the backlight.
4 *
5 * Copyright (C) 2000 Benjamin Herrenschmidt
6 *
7 */
8
9#include <linux/config.h>
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/stddef.h>
13#include <linux/reboot.h>
14#include <linux/nvram.h>
15#include <linux/console.h>
16#include <asm/sections.h>
17#include <asm/ptrace.h>
18#include <asm/io.h>
19#include <asm/pgtable.h>
20#include <asm/system.h>
21#include <asm/prom.h>
22#include <asm/machdep.h>
23#include <asm/nvram.h>
24#include <asm/backlight.h>
25
26#include <linux/adb.h>
27#include <linux/pmu.h>
28
29static struct backlight_controller *backlighter;
30static void* backlighter_data;
31static int backlight_autosave;
32static int backlight_level = BACKLIGHT_MAX;
33static int backlight_enabled = 1;
34static int backlight_req_level = -1;
35static int backlight_req_enable = -1;
36
37static void backlight_callback(void *);
38static DECLARE_WORK(backlight_work, backlight_callback, NULL);
39
40void register_backlight_controller(struct backlight_controller *ctrler,
41 void *data, char *type)
42{
43 struct device_node* bk_node;
44 char *prop;
45 int valid = 0;
46
47 /* There's already a matching controller, bail out */
48 if (backlighter != NULL)
49 return;
50
51 bk_node = find_devices("backlight");
52
53#ifdef CONFIG_ADB_PMU
54 /* Special case for the old PowerBook since I can't test on it */
55 backlight_autosave = machine_is_compatible("AAPL,3400/2400")
56 || machine_is_compatible("AAPL,3500");
57 if ((backlight_autosave
58 || machine_is_compatible("AAPL,PowerBook1998")
59 || machine_is_compatible("PowerBook1,1"))
60 && !strcmp(type, "pmu"))
61 valid = 1;
62#endif
63 if (bk_node) {
64 prop = get_property(bk_node, "backlight-control", NULL);
65 if (prop && !strncmp(prop, type, strlen(type)))
66 valid = 1;
67 }
68 if (!valid)
69 return;
70 backlighter = ctrler;
71 backlighter_data = data;
72
73 if (bk_node && !backlight_autosave)
74 prop = get_property(bk_node, "bklt", NULL);
75 else
76 prop = NULL;
77 if (prop) {
78 backlight_level = ((*prop)+1) >> 1;
79 if (backlight_level > BACKLIGHT_MAX)
80 backlight_level = BACKLIGHT_MAX;
81 }
82
83#ifdef CONFIG_ADB_PMU
84 if (backlight_autosave) {
85 struct adb_request req;
86 pmu_request(&req, NULL, 2, 0xd9, 0);
87 while (!req.complete)
88 pmu_poll();
89 backlight_level = req.reply[0] >> 4;
90 }
91#endif
92 acquire_console_sem();
93 if (!backlighter->set_enable(1, backlight_level, data))
94 backlight_enabled = 1;
95 release_console_sem();
96
97 printk(KERN_INFO "Registered \"%s\" backlight controller,"
98 "level: %d/15\n", type, backlight_level);
99}
100EXPORT_SYMBOL(register_backlight_controller);
101
102void unregister_backlight_controller(struct backlight_controller
103 *ctrler, void *data)
104{
105 /* We keep the current backlight level (for now) */
106 if (ctrler == backlighter && data == backlighter_data)
107 backlighter = NULL;
108}
109EXPORT_SYMBOL(unregister_backlight_controller);
110
111static int __set_backlight_enable(int enable)
112{
113 int rc;
114
115 if (!backlighter)
116 return -ENODEV;
117 acquire_console_sem();
118 rc = backlighter->set_enable(enable, backlight_level,
119 backlighter_data);
120 if (!rc)
121 backlight_enabled = enable;
122 release_console_sem();
123 return rc;
124}
125int set_backlight_enable(int enable)
126{
127 if (!backlighter)
128 return -ENODEV;
129 backlight_req_enable = enable;
130 schedule_work(&backlight_work);
131 return 0;
132}
133
134EXPORT_SYMBOL(set_backlight_enable);
135
136int get_backlight_enable(void)
137{
138 if (!backlighter)
139 return -ENODEV;
140 return backlight_enabled;
141}
142EXPORT_SYMBOL(get_backlight_enable);
143
144static int __set_backlight_level(int level)
145{
146 int rc = 0;
147
148 if (!backlighter)
149 return -ENODEV;
150 if (level < BACKLIGHT_MIN)
151 level = BACKLIGHT_OFF;
152 if (level > BACKLIGHT_MAX)
153 level = BACKLIGHT_MAX;
154 acquire_console_sem();
155 if (backlight_enabled)
156 rc = backlighter->set_level(level, backlighter_data);
157 if (!rc)
158 backlight_level = level;
159 release_console_sem();
160 if (!rc && !backlight_autosave) {
161 level <<=1;
162 if (level & 0x10)
163 level |= 0x01;
164 // -- todo: save to property "bklt"
165 }
166 return rc;
167}
168int set_backlight_level(int level)
169{
170 if (!backlighter)
171 return -ENODEV;
172 backlight_req_level = level;
173 schedule_work(&backlight_work);
174 return 0;
175}
176
177EXPORT_SYMBOL(set_backlight_level);
178
179int get_backlight_level(void)
180{
181 if (!backlighter)
182 return -ENODEV;
183 return backlight_level;
184}
185EXPORT_SYMBOL(get_backlight_level);
186
187static void backlight_callback(void *dummy)
188{
189 int level, enable;
190
191 do {
192 level = backlight_req_level;
193 enable = backlight_req_enable;
194 mb();
195
196 if (level >= 0)
197 __set_backlight_level(level);
198 if (enable >= 0)
199 __set_backlight_enable(enable);
200 } while(cmpxchg(&backlight_req_level, level, -1) != level ||
201 cmpxchg(&backlight_req_enable, enable, -1) != enable);
202}
diff --git a/arch/powerpc/platforms/powermac/pmac_cache.S b/arch/powerpc/platforms/powermac/pmac_cache.S
new file mode 100644
index 000000000000..fb977de6b704
--- /dev/null
+++ b/arch/powerpc/platforms/powermac/pmac_cache.S
@@ -0,0 +1,359 @@
1/*
2 * This file contains low-level cache management functions
3 * used for sleep and CPU speed changes on Apple machines.
4 * (In fact the only thing that is Apple-specific is that we assume
5 * that we can read from ROM at physical address 0xfff00000.)
6 *
7 * Copyright (C) 2004 Paul Mackerras (paulus@samba.org) and
8 * Benjamin Herrenschmidt (benh@kernel.crashing.org)
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 *
15 */
16
17#include <linux/config.h>
18#include <asm/processor.h>
19#include <asm/ppc_asm.h>
20#include <asm/cputable.h>
21
22/*
23 * Flush and disable all data caches (dL1, L2, L3). This is used
24 * when going to sleep, when doing a PMU based cpufreq transition,
25 * or when "offlining" a CPU on SMP machines. This code is over
26 * paranoid, but I've had enough issues with various CPU revs and
27 * bugs that I decided it was worth beeing over cautious
28 */
29
30_GLOBAL(flush_disable_caches)
31#ifndef CONFIG_6xx
32 blr
33#else
34BEGIN_FTR_SECTION
35 b flush_disable_745x
36END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
37BEGIN_FTR_SECTION
38 b flush_disable_75x
39END_FTR_SECTION_IFSET(CPU_FTR_L2CR)
40 b __flush_disable_L1
41
42/* This is the code for G3 and 74[01]0 */
43flush_disable_75x:
44 mflr r10
45
46 /* Turn off EE and DR in MSR */
47 mfmsr r11
48 rlwinm r0,r11,0,~MSR_EE
49 rlwinm r0,r0,0,~MSR_DR
50 sync
51 mtmsr r0
52 isync
53
54 /* Stop DST streams */
55BEGIN_FTR_SECTION
56 DSSALL
57 sync
58END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
59
60 /* Stop DPM */
61 mfspr r8,SPRN_HID0 /* Save SPRN_HID0 in r8 */
62 rlwinm r4,r8,0,12,10 /* Turn off HID0[DPM] */
63 sync
64 mtspr SPRN_HID0,r4 /* Disable DPM */
65 sync
66
67 /* Disp-flush L1. We have a weird problem here that I never
68 * totally figured out. On 750FX, using the ROM for the flush
69 * results in a non-working flush. We use that workaround for
70 * now until I finally understand what's going on. --BenH
71 */
72
73 /* ROM base by default */
74 lis r4,0xfff0
75 mfpvr r3
76 srwi r3,r3,16
77 cmplwi cr0,r3,0x7000
78 bne+ 1f
79 /* RAM base on 750FX */
80 li r4,0
811: li r4,0x4000
82 mtctr r4
831: lwz r0,0(r4)
84 addi r4,r4,32
85 bdnz 1b
86 sync
87 isync
88
89 /* Disable / invalidate / enable L1 data */
90 mfspr r3,SPRN_HID0
91 rlwinm r3,r3,0,~(HID0_DCE | HID0_ICE)
92 mtspr SPRN_HID0,r3
93 sync
94 isync
95 ori r3,r3,(HID0_DCE|HID0_DCI|HID0_ICE|HID0_ICFI)
96 sync
97 isync
98 mtspr SPRN_HID0,r3
99 xori r3,r3,(HID0_DCI|HID0_ICFI)
100 mtspr SPRN_HID0,r3
101 sync
102
103 /* Get the current enable bit of the L2CR into r4 */
104 mfspr r5,SPRN_L2CR
105 /* Set to data-only (pre-745x bit) */
106 oris r3,r5,L2CR_L2DO@h
107 b 2f
108 /* When disabling L2, code must be in L1 */
109 .balign 32
1101: mtspr SPRN_L2CR,r3
1113: sync
112 isync
113 b 1f
1142: b 3f
1153: sync
116 isync
117 b 1b
1181: /* disp-flush L2. The interesting thing here is that the L2 can be
119 * up to 2Mb ... so using the ROM, we'll end up wrapping back to memory
120 * but that is probbaly fine. We disp-flush over 4Mb to be safe
121 */
122 lis r4,2
123 mtctr r4
124 lis r4,0xfff0
1251: lwz r0,0(r4)
126 addi r4,r4,32
127 bdnz 1b
128 sync
129 isync
130 lis r4,2
131 mtctr r4
132 lis r4,0xfff0
1331: dcbf 0,r4
134 addi r4,r4,32
135 bdnz 1b
136 sync
137 isync
138
139 /* now disable L2 */
140 rlwinm r5,r5,0,~L2CR_L2E
141 b 2f
142 /* When disabling L2, code must be in L1 */
143 .balign 32
1441: mtspr SPRN_L2CR,r5
1453: sync
146 isync
147 b 1f
1482: b 3f
1493: sync
150 isync
151 b 1b
1521: sync
153 isync
154 /* Invalidate L2. This is pre-745x, we clear the L2I bit ourselves */
155 oris r4,r5,L2CR_L2I@h
156 mtspr SPRN_L2CR,r4
157 sync
158 isync
159
160 /* Wait for the invalidation to complete */
1611: mfspr r3,SPRN_L2CR
162 rlwinm. r0,r3,0,31,31
163 bne 1b
164
165 /* Clear L2I */
166 xoris r4,r4,L2CR_L2I@h
167 sync
168 mtspr SPRN_L2CR,r4
169 sync
170
171 /* now disable the L1 data cache */
172 mfspr r0,SPRN_HID0
173 rlwinm r0,r0,0,~(HID0_DCE|HID0_ICE)
174 mtspr SPRN_HID0,r0
175 sync
176 isync
177
178 /* Restore HID0[DPM] to whatever it was before */
179 sync
180 mfspr r0,SPRN_HID0
181 rlwimi r0,r8,0,11,11 /* Turn back HID0[DPM] */
182 mtspr SPRN_HID0,r0
183 sync
184
185 /* restore DR and EE */
186 sync
187 mtmsr r11
188 isync
189
190 mtlr r10
191 blr
192
193/* This code is for 745x processors */
194flush_disable_745x:
195 /* Turn off EE and DR in MSR */
196 mfmsr r11
197 rlwinm r0,r11,0,~MSR_EE
198 rlwinm r0,r0,0,~MSR_DR
199 sync
200 mtmsr r0
201 isync
202
203 /* Stop prefetch streams */
204 DSSALL
205 sync
206
207 /* Disable L2 prefetching */
208 mfspr r0,SPRN_MSSCR0
209 rlwinm r0,r0,0,0,29
210 mtspr SPRN_MSSCR0,r0
211 sync
212 isync
213 lis r4,0
214 dcbf 0,r4
215 dcbf 0,r4
216 dcbf 0,r4
217 dcbf 0,r4
218 dcbf 0,r4
219 dcbf 0,r4
220 dcbf 0,r4
221 dcbf 0,r4
222
223 /* Due to a bug with the HW flush on some CPU revs, we occasionally
224 * experience data corruption. I'm adding a displacement flush along
225 * with a dcbf loop over a few Mb to "help". The problem isn't totally
226 * fixed by this in theory, but at least, in practice, I couldn't reproduce
227 * it even with a big hammer...
228 */
229
230 lis r4,0x0002
231 mtctr r4
232 li r4,0
2331:
234 lwz r0,0(r4)
235 addi r4,r4,32 /* Go to start of next cache line */
236 bdnz 1b
237 isync
238
239 /* Now, flush the first 4MB of memory */
240 lis r4,0x0002
241 mtctr r4
242 li r4,0
243 sync
2441:
245 dcbf 0,r4
246 addi r4,r4,32 /* Go to start of next cache line */
247 bdnz 1b
248
249 /* Flush and disable the L1 data cache */
250 mfspr r6,SPRN_LDSTCR
251 lis r3,0xfff0 /* read from ROM for displacement flush */
252 li r4,0xfe /* start with only way 0 unlocked */
253 li r5,128 /* 128 lines in each way */
2541: mtctr r5
255 rlwimi r6,r4,0,24,31
256 mtspr SPRN_LDSTCR,r6
257 sync
258 isync
2592: lwz r0,0(r3) /* touch each cache line */
260 addi r3,r3,32
261 bdnz 2b
262 rlwinm r4,r4,1,24,30 /* move on to the next way */
263 ori r4,r4,1
264 cmpwi r4,0xff /* all done? */
265 bne 1b
266 /* now unlock the L1 data cache */
267 li r4,0
268 rlwimi r6,r4,0,24,31
269 sync
270 mtspr SPRN_LDSTCR,r6
271 sync
272 isync
273
274 /* Flush the L2 cache using the hardware assist */
275 mfspr r3,SPRN_L2CR
276 cmpwi r3,0 /* check if it is enabled first */
277 bge 4f
278 oris r0,r3,(L2CR_L2IO_745x|L2CR_L2DO_745x)@h
279 b 2f
280 /* When disabling/locking L2, code must be in L1 */
281 .balign 32
2821: mtspr SPRN_L2CR,r0 /* lock the L2 cache */
2833: sync
284 isync
285 b 1f
2862: b 3f
2873: sync
288 isync
289 b 1b
2901: sync
291 isync
292 ori r0,r3,L2CR_L2HWF_745x
293 sync
294 mtspr SPRN_L2CR,r0 /* set the hardware flush bit */
2953: mfspr r0,SPRN_L2CR /* wait for it to go to 0 */
296 andi. r0,r0,L2CR_L2HWF_745x
297 bne 3b
298 sync
299 rlwinm r3,r3,0,~L2CR_L2E
300 b 2f
301 /* When disabling L2, code must be in L1 */
302 .balign 32
3031: mtspr SPRN_L2CR,r3 /* disable the L2 cache */
3043: sync
305 isync
306 b 1f
3072: b 3f
3083: sync
309 isync
310 b 1b
3111: sync
312 isync
313 oris r4,r3,L2CR_L2I@h
314 mtspr SPRN_L2CR,r4
315 sync
316 isync
3171: mfspr r4,SPRN_L2CR
318 andis. r0,r4,L2CR_L2I@h
319 bne 1b
320 sync
321
322BEGIN_FTR_SECTION
323 /* Flush the L3 cache using the hardware assist */
3244: mfspr r3,SPRN_L3CR
325 cmpwi r3,0 /* check if it is enabled */
326 bge 6f
327 oris r0,r3,L3CR_L3IO@h
328 ori r0,r0,L3CR_L3DO
329 sync
330 mtspr SPRN_L3CR,r0 /* lock the L3 cache */
331 sync
332 isync
333 ori r0,r0,L3CR_L3HWF
334 sync
335 mtspr SPRN_L3CR,r0 /* set the hardware flush bit */
3365: mfspr r0,SPRN_L3CR /* wait for it to go to zero */
337 andi. r0,r0,L3CR_L3HWF
338 bne 5b
339 rlwinm r3,r3,0,~L3CR_L3E
340 sync
341 mtspr SPRN_L3CR,r3 /* disable the L3 cache */
342 sync
343 ori r4,r3,L3CR_L3I
344 mtspr SPRN_L3CR,r4
3451: mfspr r4,SPRN_L3CR
346 andi. r0,r4,L3CR_L3I
347 bne 1b
348 sync
349END_FTR_SECTION_IFSET(CPU_FTR_L3CR)
350
3516: mfspr r0,SPRN_HID0 /* now disable the L1 data cache */
352 rlwinm r0,r0,0,~HID0_DCE
353 mtspr SPRN_HID0,r0
354 sync
355 isync
356 mtmsr r11 /* restore DR and EE */
357 isync
358 blr
359#endif /* CONFIG_6xx */
diff --git a/arch/powerpc/platforms/powermac/pmac_cpufreq.c b/arch/powerpc/platforms/powermac/pmac_cpufreq.c
new file mode 100644
index 000000000000..6d32d99402be
--- /dev/null
+++ b/arch/powerpc/platforms/powermac/pmac_cpufreq.c
@@ -0,0 +1,728 @@
1/*
2 * arch/ppc/platforms/pmac_cpufreq.c
3 *
4 * Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 * Copyright (C) 2004 John Steele Scott <toojays@toojays.net>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * TODO: Need a big cleanup here. Basically, we need to have different
12 * cpufreq_driver structures for the different type of HW instead of the
13 * current mess. We also need to better deal with the detection of the
14 * type of machine.
15 *
16 */
17
18#include <linux/config.h>
19#include <linux/module.h>
20#include <linux/types.h>
21#include <linux/errno.h>
22#include <linux/kernel.h>
23#include <linux/delay.h>
24#include <linux/sched.h>
25#include <linux/adb.h>
26#include <linux/pmu.h>
27#include <linux/slab.h>
28#include <linux/cpufreq.h>
29#include <linux/init.h>
30#include <linux/sysdev.h>
31#include <linux/i2c.h>
32#include <linux/hardirq.h>
33#include <asm/prom.h>
34#include <asm/machdep.h>
35#include <asm/irq.h>
36#include <asm/pmac_feature.h>
37#include <asm/mmu_context.h>
38#include <asm/sections.h>
39#include <asm/cputable.h>
40#include <asm/time.h>
41#include <asm/system.h>
42#include <asm/mpic.h>
43#include <asm/keylargo.h>
44
45/* WARNING !!! This will cause calibrate_delay() to be called,
46 * but this is an __init function ! So you MUST go edit
47 * init/main.c to make it non-init before enabling DEBUG_FREQ
48 */
49#undef DEBUG_FREQ
50
51/*
52 * There is a problem with the core cpufreq code on SMP kernels,
53 * it won't recalculate the Bogomips properly
54 */
55#ifdef CONFIG_SMP
56#warning "WARNING, CPUFREQ not recommended on SMP kernels"
57#endif
58
59extern void low_choose_7447a_dfs(int dfs);
60extern void low_choose_750fx_pll(int pll);
61extern void low_sleep_handler(void);
62
63/*
64 * Currently, PowerMac cpufreq supports only high & low frequencies
65 * that are set by the firmware
66 */
67static unsigned int low_freq;
68static unsigned int hi_freq;
69static unsigned int cur_freq;
70static unsigned int sleep_freq;
71
72/*
73 * Different models uses different mecanisms to switch the frequency
74 */
75static int (*set_speed_proc)(int low_speed);
76static unsigned int (*get_speed_proc)(void);
77
78/*
79 * Some definitions used by the various speedprocs
80 */
81static u32 voltage_gpio;
82static u32 frequency_gpio;
83static u32 slew_done_gpio;
84static int no_schedule;
85static int has_cpu_l2lve;
86static int is_pmu_based;
87
88/* There are only two frequency states for each processor. Values
89 * are in kHz for the time being.
90 */
91#define CPUFREQ_HIGH 0
92#define CPUFREQ_LOW 1
93
94static struct cpufreq_frequency_table pmac_cpu_freqs[] = {
95 {CPUFREQ_HIGH, 0},
96 {CPUFREQ_LOW, 0},
97 {0, CPUFREQ_TABLE_END},
98};
99
100static struct freq_attr* pmac_cpu_freqs_attr[] = {
101 &cpufreq_freq_attr_scaling_available_freqs,
102 NULL,
103};
104
105static inline void local_delay(unsigned long ms)
106{
107 if (no_schedule)
108 mdelay(ms);
109 else
110 msleep(ms);
111}
112
113static inline void wakeup_decrementer(void)
114{
115 set_dec(tb_ticks_per_jiffy);
116 /* No currently-supported powerbook has a 601,
117 * so use get_tbl, not native
118 */
119 last_jiffy_stamp(0) = tb_last_stamp = get_tbl();
120}
121
122#ifdef DEBUG_FREQ
123static inline void debug_calc_bogomips(void)
124{
125 /* This will cause a recalc of bogomips and display the
126 * result. We backup/restore the value to avoid affecting the
127 * core cpufreq framework's own calculation.
128 */
129 extern void calibrate_delay(void);
130
131 unsigned long save_lpj = loops_per_jiffy;
132 calibrate_delay();
133 loops_per_jiffy = save_lpj;
134}
135#endif /* DEBUG_FREQ */
136
137/* Switch CPU speed under 750FX CPU control
138 */
139static int cpu_750fx_cpu_speed(int low_speed)
140{
141 u32 hid2;
142
143 if (low_speed == 0) {
144 /* ramping up, set voltage first */
145 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x05);
146 /* Make sure we sleep for at least 1ms */
147 local_delay(10);
148
149 /* tweak L2 for high voltage */
150 if (has_cpu_l2lve) {
151 hid2 = mfspr(SPRN_HID2);
152 hid2 &= ~0x2000;
153 mtspr(SPRN_HID2, hid2);
154 }
155 }
156#ifdef CONFIG_6xx
157 low_choose_750fx_pll(low_speed);
158#endif
159 if (low_speed == 1) {
160 /* tweak L2 for low voltage */
161 if (has_cpu_l2lve) {
162 hid2 = mfspr(SPRN_HID2);
163 hid2 |= 0x2000;
164 mtspr(SPRN_HID2, hid2);
165 }
166
167 /* ramping down, set voltage last */
168 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x04);
169 local_delay(10);
170 }
171
172 return 0;
173}
174
175static unsigned int cpu_750fx_get_cpu_speed(void)
176{
177 if (mfspr(SPRN_HID1) & HID1_PS)
178 return low_freq;
179 else
180 return hi_freq;
181}
182
183/* Switch CPU speed using DFS */
184static int dfs_set_cpu_speed(int low_speed)
185{
186 if (low_speed == 0) {
187 /* ramping up, set voltage first */
188 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x05);
189 /* Make sure we sleep for at least 1ms */
190 local_delay(1);
191 }
192
193 /* set frequency */
194#ifdef CONFIG_6xx
195 low_choose_7447a_dfs(low_speed);
196#endif
197 udelay(100);
198
199 if (low_speed == 1) {
200 /* ramping down, set voltage last */
201 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x04);
202 local_delay(1);
203 }
204
205 return 0;
206}
207
208static unsigned int dfs_get_cpu_speed(void)
209{
210 if (mfspr(SPRN_HID1) & HID1_DFS)
211 return low_freq;
212 else
213 return hi_freq;
214}
215
216
217/* Switch CPU speed using slewing GPIOs
218 */
219static int gpios_set_cpu_speed(int low_speed)
220{
221 int gpio, timeout = 0;
222
223 /* If ramping up, set voltage first */
224 if (low_speed == 0) {
225 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x05);
226 /* Delay is way too big but it's ok, we schedule */
227 local_delay(10);
228 }
229
230 /* Set frequency */
231 gpio = pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, frequency_gpio, 0);
232 if (low_speed == ((gpio & 0x01) == 0))
233 goto skip;
234
235 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, frequency_gpio,
236 low_speed ? 0x04 : 0x05);
237 udelay(200);
238 do {
239 if (++timeout > 100)
240 break;
241 local_delay(1);
242 gpio = pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, slew_done_gpio, 0);
243 } while((gpio & 0x02) == 0);
244 skip:
245 /* If ramping down, set voltage last */
246 if (low_speed == 1) {
247 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x04);
248 /* Delay is way too big but it's ok, we schedule */
249 local_delay(10);
250 }
251
252#ifdef DEBUG_FREQ
253 debug_calc_bogomips();
254#endif
255
256 return 0;
257}
258
259/* Switch CPU speed under PMU control
260 */
261static int pmu_set_cpu_speed(int low_speed)
262{
263 struct adb_request req;
264 unsigned long save_l2cr;
265 unsigned long save_l3cr;
266 unsigned int pic_prio;
267 unsigned long flags;
268
269 preempt_disable();
270
271#ifdef DEBUG_FREQ
272 printk(KERN_DEBUG "HID1, before: %x\n", mfspr(SPRN_HID1));
273#endif
274 pmu_suspend();
275
276 /* Disable all interrupt sources on openpic */
277 pic_prio = mpic_cpu_get_priority();
278 mpic_cpu_set_priority(0xf);
279
280 /* Make sure the decrementer won't interrupt us */
281 asm volatile("mtdec %0" : : "r" (0x7fffffff));
282 /* Make sure any pending DEC interrupt occuring while we did
283 * the above didn't re-enable the DEC */
284 mb();
285 asm volatile("mtdec %0" : : "r" (0x7fffffff));
286
287 /* We can now disable MSR_EE */
288 local_irq_save(flags);
289
290 /* Giveup the FPU & vec */
291 enable_kernel_fp();
292
293#ifdef CONFIG_ALTIVEC
294 if (cpu_has_feature(CPU_FTR_ALTIVEC))
295 enable_kernel_altivec();
296#endif /* CONFIG_ALTIVEC */
297
298 /* Save & disable L2 and L3 caches */
299 save_l3cr = _get_L3CR(); /* (returns -1 if not available) */
300 save_l2cr = _get_L2CR(); /* (returns -1 if not available) */
301
302 /* Send the new speed command. My assumption is that this command
303 * will cause PLL_CFG[0..3] to be changed next time CPU goes to sleep
304 */
305 pmu_request(&req, NULL, 6, PMU_CPU_SPEED, 'W', 'O', 'O', 'F', low_speed);
306 while (!req.complete)
307 pmu_poll();
308
309 /* Prepare the northbridge for the speed transition */
310 pmac_call_feature(PMAC_FTR_SLEEP_STATE,NULL,1,1);
311
312 /* Call low level code to backup CPU state and recover from
313 * hardware reset
314 */
315 low_sleep_handler();
316
317 /* Restore the northbridge */
318 pmac_call_feature(PMAC_FTR_SLEEP_STATE,NULL,1,0);
319
320 /* Restore L2 cache */
321 if (save_l2cr != 0xffffffff && (save_l2cr & L2CR_L2E) != 0)
322 _set_L2CR(save_l2cr);
323 /* Restore L3 cache */
324 if (save_l3cr != 0xffffffff && (save_l3cr & L3CR_L3E) != 0)
325 _set_L3CR(save_l3cr);
326
327 /* Restore userland MMU context */
328 set_context(current->active_mm->context, current->active_mm->pgd);
329
330#ifdef DEBUG_FREQ
331 printk(KERN_DEBUG "HID1, after: %x\n", mfspr(SPRN_HID1));
332#endif
333
334 /* Restore low level PMU operations */
335 pmu_unlock();
336
337 /* Restore decrementer */
338 wakeup_decrementer();
339
340 /* Restore interrupts */
341 mpic_cpu_set_priority(pic_prio);
342
343 /* Let interrupts flow again ... */
344 local_irq_restore(flags);
345
346#ifdef DEBUG_FREQ
347 debug_calc_bogomips();
348#endif
349
350 pmu_resume();
351
352 preempt_enable();
353
354 return 0;
355}
356
357static int do_set_cpu_speed(int speed_mode, int notify)
358{
359 struct cpufreq_freqs freqs;
360 unsigned long l3cr;
361 static unsigned long prev_l3cr;
362
363 freqs.old = cur_freq;
364 freqs.new = (speed_mode == CPUFREQ_HIGH) ? hi_freq : low_freq;
365 freqs.cpu = smp_processor_id();
366
367 if (freqs.old == freqs.new)
368 return 0;
369
370 if (notify)
371 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
372 if (speed_mode == CPUFREQ_LOW &&
373 cpu_has_feature(CPU_FTR_L3CR)) {
374 l3cr = _get_L3CR();
375 if (l3cr & L3CR_L3E) {
376 prev_l3cr = l3cr;
377 _set_L3CR(0);
378 }
379 }
380 set_speed_proc(speed_mode == CPUFREQ_LOW);
381 if (speed_mode == CPUFREQ_HIGH &&
382 cpu_has_feature(CPU_FTR_L3CR)) {
383 l3cr = _get_L3CR();
384 if ((prev_l3cr & L3CR_L3E) && l3cr != prev_l3cr)
385 _set_L3CR(prev_l3cr);
386 }
387 if (notify)
388 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
389 cur_freq = (speed_mode == CPUFREQ_HIGH) ? hi_freq : low_freq;
390
391 return 0;
392}
393
394static unsigned int pmac_cpufreq_get_speed(unsigned int cpu)
395{
396 return cur_freq;
397}
398
399static int pmac_cpufreq_verify(struct cpufreq_policy *policy)
400{
401 return cpufreq_frequency_table_verify(policy, pmac_cpu_freqs);
402}
403
404static int pmac_cpufreq_target( struct cpufreq_policy *policy,
405 unsigned int target_freq,
406 unsigned int relation)
407{
408 unsigned int newstate = 0;
409
410 if (cpufreq_frequency_table_target(policy, pmac_cpu_freqs,
411 target_freq, relation, &newstate))
412 return -EINVAL;
413
414 return do_set_cpu_speed(newstate, 1);
415}
416
417unsigned int pmac_get_one_cpufreq(int i)
418{
419 /* Supports only one CPU for now */
420 return (i == 0) ? cur_freq : 0;
421}
422
423static int pmac_cpufreq_cpu_init(struct cpufreq_policy *policy)
424{
425 if (policy->cpu != 0)
426 return -ENODEV;
427
428 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
429 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
430 policy->cur = cur_freq;
431
432 cpufreq_frequency_table_get_attr(pmac_cpu_freqs, policy->cpu);
433 return cpufreq_frequency_table_cpuinfo(policy, pmac_cpu_freqs);
434}
435
436static u32 read_gpio(struct device_node *np)
437{
438 u32 *reg = (u32 *)get_property(np, "reg", NULL);
439 u32 offset;
440
441 if (reg == NULL)
442 return 0;
443 /* That works for all keylargos but shall be fixed properly
444 * some day... The problem is that it seems we can't rely
445 * on the "reg" property of the GPIO nodes, they are either
446 * relative to the base of KeyLargo or to the base of the
447 * GPIO space, and the device-tree doesn't help.
448 */
449 offset = *reg;
450 if (offset < KEYLARGO_GPIO_LEVELS0)
451 offset += KEYLARGO_GPIO_LEVELS0;
452 return offset;
453}
454
455static int pmac_cpufreq_suspend(struct cpufreq_policy *policy, pm_message_t pmsg)
456{
457 /* Ok, this could be made a bit smarter, but let's be robust for now. We
458 * always force a speed change to high speed before sleep, to make sure
459 * we have appropriate voltage and/or bus speed for the wakeup process,
460 * and to make sure our loops_per_jiffies are "good enough", that is will
461 * not cause too short delays if we sleep in low speed and wake in high
462 * speed..
463 */
464 no_schedule = 1;
465 sleep_freq = cur_freq;
466 if (cur_freq == low_freq && !is_pmu_based)
467 do_set_cpu_speed(CPUFREQ_HIGH, 0);
468 return 0;
469}
470
471static int pmac_cpufreq_resume(struct cpufreq_policy *policy)
472{
473 /* If we resume, first check if we have a get() function */
474 if (get_speed_proc)
475 cur_freq = get_speed_proc();
476 else
477 cur_freq = 0;
478
479 /* We don't, hrm... we don't really know our speed here, best
480 * is that we force a switch to whatever it was, which is
481 * probably high speed due to our suspend() routine
482 */
483 do_set_cpu_speed(sleep_freq == low_freq ?
484 CPUFREQ_LOW : CPUFREQ_HIGH, 0);
485
486 no_schedule = 0;
487 return 0;
488}
489
490static struct cpufreq_driver pmac_cpufreq_driver = {
491 .verify = pmac_cpufreq_verify,
492 .target = pmac_cpufreq_target,
493 .get = pmac_cpufreq_get_speed,
494 .init = pmac_cpufreq_cpu_init,
495 .suspend = pmac_cpufreq_suspend,
496 .resume = pmac_cpufreq_resume,
497 .flags = CPUFREQ_PM_NO_WARN,
498 .attr = pmac_cpu_freqs_attr,
499 .name = "powermac",
500 .owner = THIS_MODULE,
501};
502
503
504static int pmac_cpufreq_init_MacRISC3(struct device_node *cpunode)
505{
506 struct device_node *volt_gpio_np = of_find_node_by_name(NULL,
507 "voltage-gpio");
508 struct device_node *freq_gpio_np = of_find_node_by_name(NULL,
509 "frequency-gpio");
510 struct device_node *slew_done_gpio_np = of_find_node_by_name(NULL,
511 "slewing-done");
512 u32 *value;
513
514 /*
515 * Check to see if it's GPIO driven or PMU only
516 *
517 * The way we extract the GPIO address is slightly hackish, but it
518 * works well enough for now. We need to abstract the whole GPIO
519 * stuff sooner or later anyway
520 */
521
522 if (volt_gpio_np)
523 voltage_gpio = read_gpio(volt_gpio_np);
524 if (freq_gpio_np)
525 frequency_gpio = read_gpio(freq_gpio_np);
526 if (slew_done_gpio_np)
527 slew_done_gpio = read_gpio(slew_done_gpio_np);
528
529 /* If we use the frequency GPIOs, calculate the min/max speeds based
530 * on the bus frequencies
531 */
532 if (frequency_gpio && slew_done_gpio) {
533 int lenp, rc;
534 u32 *freqs, *ratio;
535
536 freqs = (u32 *)get_property(cpunode, "bus-frequencies", &lenp);
537 lenp /= sizeof(u32);
538 if (freqs == NULL || lenp != 2) {
539 printk(KERN_ERR "cpufreq: bus-frequencies incorrect or missing\n");
540 return 1;
541 }
542 ratio = (u32 *)get_property(cpunode, "processor-to-bus-ratio*2", NULL);
543 if (ratio == NULL) {
544 printk(KERN_ERR "cpufreq: processor-to-bus-ratio*2 missing\n");
545 return 1;
546 }
547
548 /* Get the min/max bus frequencies */
549 low_freq = min(freqs[0], freqs[1]);
550 hi_freq = max(freqs[0], freqs[1]);
551
552 /* Grrrr.. It _seems_ that the device-tree is lying on the low bus
553 * frequency, it claims it to be around 84Mhz on some models while
554 * it appears to be approx. 101Mhz on all. Let's hack around here...
555 * fortunately, we don't need to be too precise
556 */
557 if (low_freq < 98000000)
558 low_freq = 101000000;
559
560 /* Convert those to CPU core clocks */
561 low_freq = (low_freq * (*ratio)) / 2000;
562 hi_freq = (hi_freq * (*ratio)) / 2000;
563
564 /* Now we get the frequencies, we read the GPIO to see what is out current
565 * speed
566 */
567 rc = pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, frequency_gpio, 0);
568 cur_freq = (rc & 0x01) ? hi_freq : low_freq;
569
570 set_speed_proc = gpios_set_cpu_speed;
571 return 1;
572 }
573
574 /* If we use the PMU, look for the min & max frequencies in the
575 * device-tree
576 */
577 value = (u32 *)get_property(cpunode, "min-clock-frequency", NULL);
578 if (!value)
579 return 1;
580 low_freq = (*value) / 1000;
581 /* The PowerBook G4 12" (PowerBook6,1) has an error in the device-tree
582 * here */
583 if (low_freq < 100000)
584 low_freq *= 10;
585
586 value = (u32 *)get_property(cpunode, "max-clock-frequency", NULL);
587 if (!value)
588 return 1;
589 hi_freq = (*value) / 1000;
590 set_speed_proc = pmu_set_cpu_speed;
591 is_pmu_based = 1;
592
593 return 0;
594}
595
596static int pmac_cpufreq_init_7447A(struct device_node *cpunode)
597{
598 struct device_node *volt_gpio_np;
599
600 if (get_property(cpunode, "dynamic-power-step", NULL) == NULL)
601 return 1;
602
603 volt_gpio_np = of_find_node_by_name(NULL, "cpu-vcore-select");
604 if (volt_gpio_np)
605 voltage_gpio = read_gpio(volt_gpio_np);
606 if (!voltage_gpio){
607 printk(KERN_ERR "cpufreq: missing cpu-vcore-select gpio\n");
608 return 1;
609 }
610
611 /* OF only reports the high frequency */
612 hi_freq = cur_freq;
613 low_freq = cur_freq/2;
614
615 /* Read actual frequency from CPU */
616 cur_freq = dfs_get_cpu_speed();
617 set_speed_proc = dfs_set_cpu_speed;
618 get_speed_proc = dfs_get_cpu_speed;
619
620 return 0;
621}
622
623static int pmac_cpufreq_init_750FX(struct device_node *cpunode)
624{
625 struct device_node *volt_gpio_np;
626 u32 pvr, *value;
627
628 if (get_property(cpunode, "dynamic-power-step", NULL) == NULL)
629 return 1;
630
631 hi_freq = cur_freq;
632 value = (u32 *)get_property(cpunode, "reduced-clock-frequency", NULL);
633 if (!value)
634 return 1;
635 low_freq = (*value) / 1000;
636
637 volt_gpio_np = of_find_node_by_name(NULL, "cpu-vcore-select");
638 if (volt_gpio_np)
639 voltage_gpio = read_gpio(volt_gpio_np);
640
641 pvr = mfspr(SPRN_PVR);
642 has_cpu_l2lve = !((pvr & 0xf00) == 0x100);
643
644 set_speed_proc = cpu_750fx_cpu_speed;
645 get_speed_proc = cpu_750fx_get_cpu_speed;
646 cur_freq = cpu_750fx_get_cpu_speed();
647
648 return 0;
649}
650
651/* Currently, we support the following machines:
652 *
653 * - Titanium PowerBook 1Ghz (PMU based, 667Mhz & 1Ghz)
654 * - Titanium PowerBook 800 (PMU based, 667Mhz & 800Mhz)
655 * - Titanium PowerBook 400 (PMU based, 300Mhz & 400Mhz)
656 * - Titanium PowerBook 500 (PMU based, 300Mhz & 500Mhz)
657 * - iBook2 500/600 (PMU based, 400Mhz & 500/600Mhz)
658 * - iBook2 700 (CPU based, 400Mhz & 700Mhz, support low voltage)
659 * - Recent MacRISC3 laptops
660 * - All new machines with 7447A CPUs
661 */
662static int __init pmac_cpufreq_setup(void)
663{
664 struct device_node *cpunode;
665 u32 *value;
666
667 if (strstr(cmd_line, "nocpufreq"))
668 return 0;
669
670 /* Assume only one CPU */
671 cpunode = find_type_devices("cpu");
672 if (!cpunode)
673 goto out;
674
675 /* Get current cpu clock freq */
676 value = (u32 *)get_property(cpunode, "clock-frequency", NULL);
677 if (!value)
678 goto out;
679 cur_freq = (*value) / 1000;
680
681 /* Check for 7447A based MacRISC3 */
682 if (machine_is_compatible("MacRISC3") &&
683 get_property(cpunode, "dynamic-power-step", NULL) &&
684 PVR_VER(mfspr(SPRN_PVR)) == 0x8003) {
685 pmac_cpufreq_init_7447A(cpunode);
686 /* Check for other MacRISC3 machines */
687 } else if (machine_is_compatible("PowerBook3,4") ||
688 machine_is_compatible("PowerBook3,5") ||
689 machine_is_compatible("MacRISC3")) {
690 pmac_cpufreq_init_MacRISC3(cpunode);
691 /* Else check for iBook2 500/600 */
692 } else if (machine_is_compatible("PowerBook4,1")) {
693 hi_freq = cur_freq;
694 low_freq = 400000;
695 set_speed_proc = pmu_set_cpu_speed;
696 is_pmu_based = 1;
697 }
698 /* Else check for TiPb 400 & 500 */
699 else if (machine_is_compatible("PowerBook3,2")) {
700 /* We only know about the 400 MHz and the 500Mhz model
701 * they both have 300 MHz as low frequency
702 */
703 if (cur_freq < 350000 || cur_freq > 550000)
704 goto out;
705 hi_freq = cur_freq;
706 low_freq = 300000;
707 set_speed_proc = pmu_set_cpu_speed;
708 is_pmu_based = 1;
709 }
710 /* Else check for 750FX */
711 else if (PVR_VER(mfspr(SPRN_PVR)) == 0x7000)
712 pmac_cpufreq_init_750FX(cpunode);
713out:
714 if (set_speed_proc == NULL)
715 return -ENODEV;
716
717 pmac_cpu_freqs[CPUFREQ_LOW].frequency = low_freq;
718 pmac_cpu_freqs[CPUFREQ_HIGH].frequency = hi_freq;
719
720 printk(KERN_INFO "Registering PowerMac CPU frequency driver\n");
721 printk(KERN_INFO "Low: %d Mhz, High: %d Mhz, Boot: %d Mhz\n",
722 low_freq/1000, hi_freq/1000, cur_freq/1000);
723
724 return cpufreq_register_driver(&pmac_cpufreq_driver);
725}
726
727module_init(pmac_cpufreq_setup);
728
diff --git a/arch/powerpc/platforms/powermac/pmac_feature.c b/arch/powerpc/platforms/powermac/pmac_feature.c
new file mode 100644
index 000000000000..2cba670c71b7
--- /dev/null
+++ b/arch/powerpc/platforms/powermac/pmac_feature.c
@@ -0,0 +1,3062 @@
1/*
2 * arch/ppc/platforms/pmac_feature.c
3 *
4 * Copyright (C) 1996-2001 Paul Mackerras (paulus@cs.anu.edu.au)
5 * Ben. Herrenschmidt (benh@kernel.crashing.org)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 *
12 * TODO:
13 *
14 * - Replace mdelay with some schedule loop if possible
15 * - Shorten some obfuscated delays on some routines (like modem
16 * power)
17 * - Refcount some clocks (see darwin)
18 * - Split split split...
19 *
20 */
21#include <linux/config.h>
22#include <linux/types.h>
23#include <linux/init.h>
24#include <linux/delay.h>
25#include <linux/kernel.h>
26#include <linux/sched.h>
27#include <linux/spinlock.h>
28#include <linux/adb.h>
29#include <linux/pmu.h>
30#include <linux/ioport.h>
31#include <linux/pci.h>
32#include <asm/sections.h>
33#include <asm/errno.h>
34#include <asm/ohare.h>
35#include <asm/heathrow.h>
36#include <asm/keylargo.h>
37#include <asm/uninorth.h>
38#include <asm/io.h>
39#include <asm/prom.h>
40#include <asm/machdep.h>
41#include <asm/pmac_feature.h>
42#include <asm/dbdma.h>
43#include <asm/pci-bridge.h>
44#include <asm/pmac_low_i2c.h>
45
46#undef DEBUG_FEATURE
47
48#ifdef DEBUG_FEATURE
49#define DBG(fmt...) printk(KERN_DEBUG fmt)
50#else
51#define DBG(fmt...)
52#endif
53
54#ifdef CONFIG_6xx
55extern int powersave_lowspeed;
56#endif
57
58extern int powersave_nap;
59extern struct device_node *k2_skiplist[2];
60
61
62/*
63 * We use a single global lock to protect accesses. Each driver has
64 * to take care of its own locking
65 */
66static DEFINE_SPINLOCK(feature_lock);
67
68#define LOCK(flags) spin_lock_irqsave(&feature_lock, flags);
69#define UNLOCK(flags) spin_unlock_irqrestore(&feature_lock, flags);
70
71
72/*
73 * Instance of some macio stuffs
74 */
75struct macio_chip macio_chips[MAX_MACIO_CHIPS];
76
77struct macio_chip *macio_find(struct device_node *child, int type)
78{
79 while(child) {
80 int i;
81
82 for (i=0; i < MAX_MACIO_CHIPS && macio_chips[i].of_node; i++)
83 if (child == macio_chips[i].of_node &&
84 (!type || macio_chips[i].type == type))
85 return &macio_chips[i];
86 child = child->parent;
87 }
88 return NULL;
89}
90EXPORT_SYMBOL_GPL(macio_find);
91
92static const char *macio_names[] =
93{
94 "Unknown",
95 "Grand Central",
96 "OHare",
97 "OHareII",
98 "Heathrow",
99 "Gatwick",
100 "Paddington",
101 "Keylargo",
102 "Pangea",
103 "Intrepid",
104 "K2"
105};
106
107
108
109/*
110 * Uninorth reg. access. Note that Uni-N regs are big endian
111 */
112
113#define UN_REG(r) (uninorth_base + ((r) >> 2))
114#define UN_IN(r) (in_be32(UN_REG(r)))
115#define UN_OUT(r,v) (out_be32(UN_REG(r), (v)))
116#define UN_BIS(r,v) (UN_OUT((r), UN_IN(r) | (v)))
117#define UN_BIC(r,v) (UN_OUT((r), UN_IN(r) & ~(v)))
118
119static struct device_node *uninorth_node;
120static u32 __iomem *uninorth_base;
121static u32 uninorth_rev;
122static int uninorth_u3;
123static void __iomem *u3_ht;
124
125/*
126 * For each motherboard family, we have a table of functions pointers
127 * that handle the various features.
128 */
129
130typedef long (*feature_call)(struct device_node *node, long param, long value);
131
132struct feature_table_entry {
133 unsigned int selector;
134 feature_call function;
135};
136
137struct pmac_mb_def
138{
139 const char* model_string;
140 const char* model_name;
141 int model_id;
142 struct feature_table_entry* features;
143 unsigned long board_flags;
144};
145static struct pmac_mb_def pmac_mb;
146
147/*
148 * Here are the chip specific feature functions
149 */
150
151static inline int simple_feature_tweak(struct device_node *node, int type,
152 int reg, u32 mask, int value)
153{
154 struct macio_chip* macio;
155 unsigned long flags;
156
157 macio = macio_find(node, type);
158 if (!macio)
159 return -ENODEV;
160 LOCK(flags);
161 if (value)
162 MACIO_BIS(reg, mask);
163 else
164 MACIO_BIC(reg, mask);
165 (void)MACIO_IN32(reg);
166 UNLOCK(flags);
167
168 return 0;
169}
170
171#ifndef CONFIG_POWER4
172
173static long ohare_htw_scc_enable(struct device_node *node, long param,
174 long value)
175{
176 struct macio_chip* macio;
177 unsigned long chan_mask;
178 unsigned long fcr;
179 unsigned long flags;
180 int htw, trans;
181 unsigned long rmask;
182
183 macio = macio_find(node, 0);
184 if (!macio)
185 return -ENODEV;
186 if (!strcmp(node->name, "ch-a"))
187 chan_mask = MACIO_FLAG_SCCA_ON;
188 else if (!strcmp(node->name, "ch-b"))
189 chan_mask = MACIO_FLAG_SCCB_ON;
190 else
191 return -ENODEV;
192
193 htw = (macio->type == macio_heathrow || macio->type == macio_paddington
194 || macio->type == macio_gatwick);
195 /* On these machines, the HRW_SCC_TRANS_EN_N bit mustn't be touched */
196 trans = (pmac_mb.model_id != PMAC_TYPE_YOSEMITE &&
197 pmac_mb.model_id != PMAC_TYPE_YIKES);
198 if (value) {
199#ifdef CONFIG_ADB_PMU
200 if ((param & 0xfff) == PMAC_SCC_IRDA)
201 pmu_enable_irled(1);
202#endif /* CONFIG_ADB_PMU */
203 LOCK(flags);
204 fcr = MACIO_IN32(OHARE_FCR);
205 /* Check if scc cell need enabling */
206 if (!(fcr & OH_SCC_ENABLE)) {
207 fcr |= OH_SCC_ENABLE;
208 if (htw) {
209 /* Side effect: this will also power up the
210 * modem, but it's too messy to figure out on which
211 * ports this controls the tranceiver and on which
212 * it controls the modem
213 */
214 if (trans)
215 fcr &= ~HRW_SCC_TRANS_EN_N;
216 MACIO_OUT32(OHARE_FCR, fcr);
217 fcr |= (rmask = HRW_RESET_SCC);
218 MACIO_OUT32(OHARE_FCR, fcr);
219 } else {
220 fcr |= (rmask = OH_SCC_RESET);
221 MACIO_OUT32(OHARE_FCR, fcr);
222 }
223 UNLOCK(flags);
224 (void)MACIO_IN32(OHARE_FCR);
225 mdelay(15);
226 LOCK(flags);
227 fcr &= ~rmask;
228 MACIO_OUT32(OHARE_FCR, fcr);
229 }
230 if (chan_mask & MACIO_FLAG_SCCA_ON)
231 fcr |= OH_SCCA_IO;
232 if (chan_mask & MACIO_FLAG_SCCB_ON)
233 fcr |= OH_SCCB_IO;
234 MACIO_OUT32(OHARE_FCR, fcr);
235 macio->flags |= chan_mask;
236 UNLOCK(flags);
237 if (param & PMAC_SCC_FLAG_XMON)
238 macio->flags |= MACIO_FLAG_SCC_LOCKED;
239 } else {
240 if (macio->flags & MACIO_FLAG_SCC_LOCKED)
241 return -EPERM;
242 LOCK(flags);
243 fcr = MACIO_IN32(OHARE_FCR);
244 if (chan_mask & MACIO_FLAG_SCCA_ON)
245 fcr &= ~OH_SCCA_IO;
246 if (chan_mask & MACIO_FLAG_SCCB_ON)
247 fcr &= ~OH_SCCB_IO;
248 MACIO_OUT32(OHARE_FCR, fcr);
249 if ((fcr & (OH_SCCA_IO | OH_SCCB_IO)) == 0) {
250 fcr &= ~OH_SCC_ENABLE;
251 if (htw && trans)
252 fcr |= HRW_SCC_TRANS_EN_N;
253 MACIO_OUT32(OHARE_FCR, fcr);
254 }
255 macio->flags &= ~(chan_mask);
256 UNLOCK(flags);
257 mdelay(10);
258#ifdef CONFIG_ADB_PMU
259 if ((param & 0xfff) == PMAC_SCC_IRDA)
260 pmu_enable_irled(0);
261#endif /* CONFIG_ADB_PMU */
262 }
263 return 0;
264}
265
266static long ohare_floppy_enable(struct device_node *node, long param,
267 long value)
268{
269 return simple_feature_tweak(node, macio_ohare,
270 OHARE_FCR, OH_FLOPPY_ENABLE, value);
271}
272
273static long ohare_mesh_enable(struct device_node *node, long param, long value)
274{
275 return simple_feature_tweak(node, macio_ohare,
276 OHARE_FCR, OH_MESH_ENABLE, value);
277}
278
279static long ohare_ide_enable(struct device_node *node, long param, long value)
280{
281 switch(param) {
282 case 0:
283 /* For some reason, setting the bit in set_initial_features()
284 * doesn't stick. I'm still investigating... --BenH.
285 */
286 if (value)
287 simple_feature_tweak(node, macio_ohare,
288 OHARE_FCR, OH_IOBUS_ENABLE, 1);
289 return simple_feature_tweak(node, macio_ohare,
290 OHARE_FCR, OH_IDE0_ENABLE, value);
291 case 1:
292 return simple_feature_tweak(node, macio_ohare,
293 OHARE_FCR, OH_BAY_IDE_ENABLE, value);
294 default:
295 return -ENODEV;
296 }
297}
298
299static long ohare_ide_reset(struct device_node *node, long param, long value)
300{
301 switch(param) {
302 case 0:
303 return simple_feature_tweak(node, macio_ohare,
304 OHARE_FCR, OH_IDE0_RESET_N, !value);
305 case 1:
306 return simple_feature_tweak(node, macio_ohare,
307 OHARE_FCR, OH_IDE1_RESET_N, !value);
308 default:
309 return -ENODEV;
310 }
311}
312
313static long ohare_sleep_state(struct device_node *node, long param, long value)
314{
315 struct macio_chip* macio = &macio_chips[0];
316
317 if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0)
318 return -EPERM;
319 if (value == 1) {
320 MACIO_BIC(OHARE_FCR, OH_IOBUS_ENABLE);
321 } else if (value == 0) {
322 MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE);
323 }
324
325 return 0;
326}
327
328static long heathrow_modem_enable(struct device_node *node, long param,
329 long value)
330{
331 struct macio_chip* macio;
332 u8 gpio;
333 unsigned long flags;
334
335 macio = macio_find(node, macio_unknown);
336 if (!macio)
337 return -ENODEV;
338 gpio = MACIO_IN8(HRW_GPIO_MODEM_RESET) & ~1;
339 if (!value) {
340 LOCK(flags);
341 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio);
342 UNLOCK(flags);
343 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET);
344 mdelay(250);
345 }
346 if (pmac_mb.model_id != PMAC_TYPE_YOSEMITE &&
347 pmac_mb.model_id != PMAC_TYPE_YIKES) {
348 LOCK(flags);
349 if (value)
350 MACIO_BIC(HEATHROW_FCR, HRW_SCC_TRANS_EN_N);
351 else
352 MACIO_BIS(HEATHROW_FCR, HRW_SCC_TRANS_EN_N);
353 UNLOCK(flags);
354 (void)MACIO_IN32(HEATHROW_FCR);
355 mdelay(250);
356 }
357 if (value) {
358 LOCK(flags);
359 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio | 1);
360 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET);
361 UNLOCK(flags); mdelay(250); LOCK(flags);
362 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio);
363 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET);
364 UNLOCK(flags); mdelay(250); LOCK(flags);
365 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio | 1);
366 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET);
367 UNLOCK(flags); mdelay(250);
368 }
369 return 0;
370}
371
372static long heathrow_floppy_enable(struct device_node *node, long param,
373 long value)
374{
375 return simple_feature_tweak(node, macio_unknown,
376 HEATHROW_FCR,
377 HRW_SWIM_ENABLE|HRW_BAY_FLOPPY_ENABLE,
378 value);
379}
380
381static long heathrow_mesh_enable(struct device_node *node, long param,
382 long value)
383{
384 struct macio_chip* macio;
385 unsigned long flags;
386
387 macio = macio_find(node, macio_unknown);
388 if (!macio)
389 return -ENODEV;
390 LOCK(flags);
391 /* Set clear mesh cell enable */
392 if (value)
393 MACIO_BIS(HEATHROW_FCR, HRW_MESH_ENABLE);
394 else
395 MACIO_BIC(HEATHROW_FCR, HRW_MESH_ENABLE);
396 (void)MACIO_IN32(HEATHROW_FCR);
397 udelay(10);
398 /* Set/Clear termination power */
399 if (value)
400 MACIO_BIC(HEATHROW_MBCR, 0x04000000);
401 else
402 MACIO_BIS(HEATHROW_MBCR, 0x04000000);
403 (void)MACIO_IN32(HEATHROW_MBCR);
404 udelay(10);
405 UNLOCK(flags);
406
407 return 0;
408}
409
410static long heathrow_ide_enable(struct device_node *node, long param,
411 long value)
412{
413 switch(param) {
414 case 0:
415 return simple_feature_tweak(node, macio_unknown,
416 HEATHROW_FCR, HRW_IDE0_ENABLE, value);
417 case 1:
418 return simple_feature_tweak(node, macio_unknown,
419 HEATHROW_FCR, HRW_BAY_IDE_ENABLE, value);
420 default:
421 return -ENODEV;
422 }
423}
424
425static long heathrow_ide_reset(struct device_node *node, long param,
426 long value)
427{
428 switch(param) {
429 case 0:
430 return simple_feature_tweak(node, macio_unknown,
431 HEATHROW_FCR, HRW_IDE0_RESET_N, !value);
432 case 1:
433 return simple_feature_tweak(node, macio_unknown,
434 HEATHROW_FCR, HRW_IDE1_RESET_N, !value);
435 default:
436 return -ENODEV;
437 }
438}
439
440static long heathrow_bmac_enable(struct device_node *node, long param,
441 long value)
442{
443 struct macio_chip* macio;
444 unsigned long flags;
445
446 macio = macio_find(node, 0);
447 if (!macio)
448 return -ENODEV;
449 if (value) {
450 LOCK(flags);
451 MACIO_BIS(HEATHROW_FCR, HRW_BMAC_IO_ENABLE);
452 MACIO_BIS(HEATHROW_FCR, HRW_BMAC_RESET);
453 UNLOCK(flags);
454 (void)MACIO_IN32(HEATHROW_FCR);
455 mdelay(10);
456 LOCK(flags);
457 MACIO_BIC(HEATHROW_FCR, HRW_BMAC_RESET);
458 UNLOCK(flags);
459 (void)MACIO_IN32(HEATHROW_FCR);
460 mdelay(10);
461 } else {
462 LOCK(flags);
463 MACIO_BIC(HEATHROW_FCR, HRW_BMAC_IO_ENABLE);
464 UNLOCK(flags);
465 }
466 return 0;
467}
468
469static long heathrow_sound_enable(struct device_node *node, long param,
470 long value)
471{
472 struct macio_chip* macio;
473 unsigned long flags;
474
475 /* B&W G3 and Yikes don't support that properly (the
476 * sound appear to never come back after beeing shut down).
477 */
478 if (pmac_mb.model_id == PMAC_TYPE_YOSEMITE ||
479 pmac_mb.model_id == PMAC_TYPE_YIKES)
480 return 0;
481
482 macio = macio_find(node, 0);
483 if (!macio)
484 return -ENODEV;
485 if (value) {
486 LOCK(flags);
487 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE);
488 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_POWER_N);
489 UNLOCK(flags);
490 (void)MACIO_IN32(HEATHROW_FCR);
491 } else {
492 LOCK(flags);
493 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_POWER_N);
494 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE);
495 UNLOCK(flags);
496 }
497 return 0;
498}
499
500static u32 save_fcr[6];
501static u32 save_mbcr;
502static u32 save_gpio_levels[2];
503static u8 save_gpio_extint[KEYLARGO_GPIO_EXTINT_CNT];
504static u8 save_gpio_normal[KEYLARGO_GPIO_CNT];
505static u32 save_unin_clock_ctl;
506static struct dbdma_regs save_dbdma[13];
507static struct dbdma_regs save_alt_dbdma[13];
508
509static void dbdma_save(struct macio_chip *macio, struct dbdma_regs *save)
510{
511 int i;
512
513 /* Save state & config of DBDMA channels */
514 for (i = 0; i < 13; i++) {
515 volatile struct dbdma_regs __iomem * chan = (void __iomem *)
516 (macio->base + ((0x8000+i*0x100)>>2));
517 save[i].cmdptr_hi = in_le32(&chan->cmdptr_hi);
518 save[i].cmdptr = in_le32(&chan->cmdptr);
519 save[i].intr_sel = in_le32(&chan->intr_sel);
520 save[i].br_sel = in_le32(&chan->br_sel);
521 save[i].wait_sel = in_le32(&chan->wait_sel);
522 }
523}
524
525static void dbdma_restore(struct macio_chip *macio, struct dbdma_regs *save)
526{
527 int i;
528
529 /* Save state & config of DBDMA channels */
530 for (i = 0; i < 13; i++) {
531 volatile struct dbdma_regs __iomem * chan = (void __iomem *)
532 (macio->base + ((0x8000+i*0x100)>>2));
533 out_le32(&chan->control, (ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN)<<16);
534 while (in_le32(&chan->status) & ACTIVE)
535 mb();
536 out_le32(&chan->cmdptr_hi, save[i].cmdptr_hi);
537 out_le32(&chan->cmdptr, save[i].cmdptr);
538 out_le32(&chan->intr_sel, save[i].intr_sel);
539 out_le32(&chan->br_sel, save[i].br_sel);
540 out_le32(&chan->wait_sel, save[i].wait_sel);
541 }
542}
543
544static void heathrow_sleep(struct macio_chip *macio, int secondary)
545{
546 if (secondary) {
547 dbdma_save(macio, save_alt_dbdma);
548 save_fcr[2] = MACIO_IN32(0x38);
549 save_fcr[3] = MACIO_IN32(0x3c);
550 } else {
551 dbdma_save(macio, save_dbdma);
552 save_fcr[0] = MACIO_IN32(0x38);
553 save_fcr[1] = MACIO_IN32(0x3c);
554 save_mbcr = MACIO_IN32(0x34);
555 /* Make sure sound is shut down */
556 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_POWER_N);
557 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE);
558 /* This seems to be necessary as well or the fan
559 * keeps coming up and battery drains fast */
560 MACIO_BIC(HEATHROW_FCR, HRW_IOBUS_ENABLE);
561 MACIO_BIC(HEATHROW_FCR, HRW_IDE0_RESET_N);
562 /* Make sure eth is down even if module or sleep
563 * won't work properly */
564 MACIO_BIC(HEATHROW_FCR, HRW_BMAC_IO_ENABLE | HRW_BMAC_RESET);
565 }
566 /* Make sure modem is shut down */
567 MACIO_OUT8(HRW_GPIO_MODEM_RESET,
568 MACIO_IN8(HRW_GPIO_MODEM_RESET) & ~1);
569 MACIO_BIS(HEATHROW_FCR, HRW_SCC_TRANS_EN_N);
570 MACIO_BIC(HEATHROW_FCR, OH_SCCA_IO|OH_SCCB_IO|HRW_SCC_ENABLE);
571
572 /* Let things settle */
573 (void)MACIO_IN32(HEATHROW_FCR);
574}
575
576static void heathrow_wakeup(struct macio_chip *macio, int secondary)
577{
578 if (secondary) {
579 MACIO_OUT32(0x38, save_fcr[2]);
580 (void)MACIO_IN32(0x38);
581 mdelay(1);
582 MACIO_OUT32(0x3c, save_fcr[3]);
583 (void)MACIO_IN32(0x38);
584 mdelay(10);
585 dbdma_restore(macio, save_alt_dbdma);
586 } else {
587 MACIO_OUT32(0x38, save_fcr[0] | HRW_IOBUS_ENABLE);
588 (void)MACIO_IN32(0x38);
589 mdelay(1);
590 MACIO_OUT32(0x3c, save_fcr[1]);
591 (void)MACIO_IN32(0x38);
592 mdelay(1);
593 MACIO_OUT32(0x34, save_mbcr);
594 (void)MACIO_IN32(0x38);
595 mdelay(10);
596 dbdma_restore(macio, save_dbdma);
597 }
598}
599
600static long heathrow_sleep_state(struct device_node *node, long param,
601 long value)
602{
603 if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0)
604 return -EPERM;
605 if (value == 1) {
606 if (macio_chips[1].type == macio_gatwick)
607 heathrow_sleep(&macio_chips[0], 1);
608 heathrow_sleep(&macio_chips[0], 0);
609 } else if (value == 0) {
610 heathrow_wakeup(&macio_chips[0], 0);
611 if (macio_chips[1].type == macio_gatwick)
612 heathrow_wakeup(&macio_chips[0], 1);
613 }
614 return 0;
615}
616
617static long core99_scc_enable(struct device_node *node, long param, long value)
618{
619 struct macio_chip* macio;
620 unsigned long flags;
621 unsigned long chan_mask;
622 u32 fcr;
623
624 macio = macio_find(node, 0);
625 if (!macio)
626 return -ENODEV;
627 if (!strcmp(node->name, "ch-a"))
628 chan_mask = MACIO_FLAG_SCCA_ON;
629 else if (!strcmp(node->name, "ch-b"))
630 chan_mask = MACIO_FLAG_SCCB_ON;
631 else
632 return -ENODEV;
633
634 if (value) {
635 int need_reset_scc = 0;
636 int need_reset_irda = 0;
637
638 LOCK(flags);
639 fcr = MACIO_IN32(KEYLARGO_FCR0);
640 /* Check if scc cell need enabling */
641 if (!(fcr & KL0_SCC_CELL_ENABLE)) {
642 fcr |= KL0_SCC_CELL_ENABLE;
643 need_reset_scc = 1;
644 }
645 if (chan_mask & MACIO_FLAG_SCCA_ON) {
646 fcr |= KL0_SCCA_ENABLE;
647 /* Don't enable line drivers for I2S modem */
648 if ((param & 0xfff) == PMAC_SCC_I2S1)
649 fcr &= ~KL0_SCC_A_INTF_ENABLE;
650 else
651 fcr |= KL0_SCC_A_INTF_ENABLE;
652 }
653 if (chan_mask & MACIO_FLAG_SCCB_ON) {
654 fcr |= KL0_SCCB_ENABLE;
655 /* Perform irda specific inits */
656 if ((param & 0xfff) == PMAC_SCC_IRDA) {
657 fcr &= ~KL0_SCC_B_INTF_ENABLE;
658 fcr |= KL0_IRDA_ENABLE;
659 fcr |= KL0_IRDA_CLK32_ENABLE | KL0_IRDA_CLK19_ENABLE;
660 fcr |= KL0_IRDA_SOURCE1_SEL;
661 fcr &= ~(KL0_IRDA_FAST_CONNECT|KL0_IRDA_DEFAULT1|KL0_IRDA_DEFAULT0);
662 fcr &= ~(KL0_IRDA_SOURCE2_SEL|KL0_IRDA_HIGH_BAND);
663 need_reset_irda = 1;
664 } else
665 fcr |= KL0_SCC_B_INTF_ENABLE;
666 }
667 MACIO_OUT32(KEYLARGO_FCR0, fcr);
668 macio->flags |= chan_mask;
669 if (need_reset_scc) {
670 MACIO_BIS(KEYLARGO_FCR0, KL0_SCC_RESET);
671 (void)MACIO_IN32(KEYLARGO_FCR0);
672 UNLOCK(flags);
673 mdelay(15);
674 LOCK(flags);
675 MACIO_BIC(KEYLARGO_FCR0, KL0_SCC_RESET);
676 }
677 if (need_reset_irda) {
678 MACIO_BIS(KEYLARGO_FCR0, KL0_IRDA_RESET);
679 (void)MACIO_IN32(KEYLARGO_FCR0);
680 UNLOCK(flags);
681 mdelay(15);
682 LOCK(flags);
683 MACIO_BIC(KEYLARGO_FCR0, KL0_IRDA_RESET);
684 }
685 UNLOCK(flags);
686 if (param & PMAC_SCC_FLAG_XMON)
687 macio->flags |= MACIO_FLAG_SCC_LOCKED;
688 } else {
689 if (macio->flags & MACIO_FLAG_SCC_LOCKED)
690 return -EPERM;
691 LOCK(flags);
692 fcr = MACIO_IN32(KEYLARGO_FCR0);
693 if (chan_mask & MACIO_FLAG_SCCA_ON)
694 fcr &= ~KL0_SCCA_ENABLE;
695 if (chan_mask & MACIO_FLAG_SCCB_ON) {
696 fcr &= ~KL0_SCCB_ENABLE;
697 /* Perform irda specific clears */
698 if ((param & 0xfff) == PMAC_SCC_IRDA) {
699 fcr &= ~KL0_IRDA_ENABLE;
700 fcr &= ~(KL0_IRDA_CLK32_ENABLE | KL0_IRDA_CLK19_ENABLE);
701 fcr &= ~(KL0_IRDA_FAST_CONNECT|KL0_IRDA_DEFAULT1|KL0_IRDA_DEFAULT0);
702 fcr &= ~(KL0_IRDA_SOURCE1_SEL|KL0_IRDA_SOURCE2_SEL|KL0_IRDA_HIGH_BAND);
703 }
704 }
705 MACIO_OUT32(KEYLARGO_FCR0, fcr);
706 if ((fcr & (KL0_SCCA_ENABLE | KL0_SCCB_ENABLE)) == 0) {
707 fcr &= ~KL0_SCC_CELL_ENABLE;
708 MACIO_OUT32(KEYLARGO_FCR0, fcr);
709 }
710 macio->flags &= ~(chan_mask);
711 UNLOCK(flags);
712 mdelay(10);
713 }
714 return 0;
715}
716
717static long
718core99_modem_enable(struct device_node *node, long param, long value)
719{
720 struct macio_chip* macio;
721 u8 gpio;
722 unsigned long flags;
723
724 /* Hack for internal USB modem */
725 if (node == NULL) {
726 if (macio_chips[0].type != macio_keylargo)
727 return -ENODEV;
728 node = macio_chips[0].of_node;
729 }
730 macio = macio_find(node, 0);
731 if (!macio)
732 return -ENODEV;
733 gpio = MACIO_IN8(KL_GPIO_MODEM_RESET);
734 gpio |= KEYLARGO_GPIO_OUTPUT_ENABLE;
735 gpio &= ~KEYLARGO_GPIO_OUTOUT_DATA;
736
737 if (!value) {
738 LOCK(flags);
739 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio);
740 UNLOCK(flags);
741 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
742 mdelay(250);
743 }
744 LOCK(flags);
745 if (value) {
746 MACIO_BIC(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
747 UNLOCK(flags);
748 (void)MACIO_IN32(KEYLARGO_FCR2);
749 mdelay(250);
750 } else {
751 MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
752 UNLOCK(flags);
753 }
754 if (value) {
755 LOCK(flags);
756 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA);
757 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
758 UNLOCK(flags); mdelay(250); LOCK(flags);
759 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio);
760 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
761 UNLOCK(flags); mdelay(250); LOCK(flags);
762 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA);
763 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
764 UNLOCK(flags); mdelay(250);
765 }
766 return 0;
767}
768
769static long
770pangea_modem_enable(struct device_node *node, long param, long value)
771{
772 struct macio_chip* macio;
773 u8 gpio;
774 unsigned long flags;
775
776 /* Hack for internal USB modem */
777 if (node == NULL) {
778 if (macio_chips[0].type != macio_pangea &&
779 macio_chips[0].type != macio_intrepid)
780 return -ENODEV;
781 node = macio_chips[0].of_node;
782 }
783 macio = macio_find(node, 0);
784 if (!macio)
785 return -ENODEV;
786 gpio = MACIO_IN8(KL_GPIO_MODEM_RESET);
787 gpio |= KEYLARGO_GPIO_OUTPUT_ENABLE;
788 gpio &= ~KEYLARGO_GPIO_OUTOUT_DATA;
789
790 if (!value) {
791 LOCK(flags);
792 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio);
793 UNLOCK(flags);
794 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
795 mdelay(250);
796 }
797 LOCK(flags);
798 if (value) {
799 MACIO_OUT8(KL_GPIO_MODEM_POWER,
800 KEYLARGO_GPIO_OUTPUT_ENABLE);
801 UNLOCK(flags);
802 (void)MACIO_IN32(KEYLARGO_FCR2);
803 mdelay(250);
804 } else {
805 MACIO_OUT8(KL_GPIO_MODEM_POWER,
806 KEYLARGO_GPIO_OUTPUT_ENABLE | KEYLARGO_GPIO_OUTOUT_DATA);
807 UNLOCK(flags);
808 }
809 if (value) {
810 LOCK(flags);
811 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA);
812 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
813 UNLOCK(flags); mdelay(250); LOCK(flags);
814 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio);
815 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
816 UNLOCK(flags); mdelay(250); LOCK(flags);
817 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA);
818 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
819 UNLOCK(flags); mdelay(250);
820 }
821 return 0;
822}
823
824static long
825core99_ata100_enable(struct device_node *node, long value)
826{
827 unsigned long flags;
828 struct pci_dev *pdev = NULL;
829 u8 pbus, pid;
830
831 if (uninorth_rev < 0x24)
832 return -ENODEV;
833
834 LOCK(flags);
835 if (value)
836 UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_ATA100);
837 else
838 UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_ATA100);
839 (void)UN_IN(UNI_N_CLOCK_CNTL);
840 UNLOCK(flags);
841 udelay(20);
842
843 if (value) {
844 if (pci_device_from_OF_node(node, &pbus, &pid) == 0)
845 pdev = pci_find_slot(pbus, pid);
846 if (pdev == NULL)
847 return 0;
848 pci_enable_device(pdev);
849 pci_set_master(pdev);
850 }
851 return 0;
852}
853
854static long
855core99_ide_enable(struct device_node *node, long param, long value)
856{
857 /* Bus ID 0 to 2 are KeyLargo based IDE, busID 3 is U2
858 * based ata-100
859 */
860 switch(param) {
861 case 0:
862 return simple_feature_tweak(node, macio_unknown,
863 KEYLARGO_FCR1, KL1_EIDE0_ENABLE, value);
864 case 1:
865 return simple_feature_tweak(node, macio_unknown,
866 KEYLARGO_FCR1, KL1_EIDE1_ENABLE, value);
867 case 2:
868 return simple_feature_tweak(node, macio_unknown,
869 KEYLARGO_FCR1, KL1_UIDE_ENABLE, value);
870 case 3:
871 return core99_ata100_enable(node, value);
872 default:
873 return -ENODEV;
874 }
875}
876
877static long
878core99_ide_reset(struct device_node *node, long param, long value)
879{
880 switch(param) {
881 case 0:
882 return simple_feature_tweak(node, macio_unknown,
883 KEYLARGO_FCR1, KL1_EIDE0_RESET_N, !value);
884 case 1:
885 return simple_feature_tweak(node, macio_unknown,
886 KEYLARGO_FCR1, KL1_EIDE1_RESET_N, !value);
887 case 2:
888 return simple_feature_tweak(node, macio_unknown,
889 KEYLARGO_FCR1, KL1_UIDE_RESET_N, !value);
890 default:
891 return -ENODEV;
892 }
893}
894
895static long
896core99_gmac_enable(struct device_node *node, long param, long value)
897{
898 unsigned long flags;
899
900 LOCK(flags);
901 if (value)
902 UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_GMAC);
903 else
904 UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_GMAC);
905 (void)UN_IN(UNI_N_CLOCK_CNTL);
906 UNLOCK(flags);
907 udelay(20);
908
909 return 0;
910}
911
912static long
913core99_gmac_phy_reset(struct device_node *node, long param, long value)
914{
915 unsigned long flags;
916 struct macio_chip *macio;
917
918 macio = &macio_chips[0];
919 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
920 macio->type != macio_intrepid)
921 return -ENODEV;
922
923 LOCK(flags);
924 MACIO_OUT8(KL_GPIO_ETH_PHY_RESET, KEYLARGO_GPIO_OUTPUT_ENABLE);
925 (void)MACIO_IN8(KL_GPIO_ETH_PHY_RESET);
926 UNLOCK(flags);
927 mdelay(10);
928 LOCK(flags);
929 MACIO_OUT8(KL_GPIO_ETH_PHY_RESET, /*KEYLARGO_GPIO_OUTPUT_ENABLE | */
930 KEYLARGO_GPIO_OUTOUT_DATA);
931 UNLOCK(flags);
932 mdelay(10);
933
934 return 0;
935}
936
937static long
938core99_sound_chip_enable(struct device_node *node, long param, long value)
939{
940 struct macio_chip* macio;
941 unsigned long flags;
942
943 macio = macio_find(node, 0);
944 if (!macio)
945 return -ENODEV;
946
947 /* Do a better probe code, screamer G4 desktops &
948 * iMacs can do that too, add a recalibrate in
949 * the driver as well
950 */
951 if (pmac_mb.model_id == PMAC_TYPE_PISMO ||
952 pmac_mb.model_id == PMAC_TYPE_TITANIUM) {
953 LOCK(flags);
954 if (value)
955 MACIO_OUT8(KL_GPIO_SOUND_POWER,
956 KEYLARGO_GPIO_OUTPUT_ENABLE |
957 KEYLARGO_GPIO_OUTOUT_DATA);
958 else
959 MACIO_OUT8(KL_GPIO_SOUND_POWER,
960 KEYLARGO_GPIO_OUTPUT_ENABLE);
961 (void)MACIO_IN8(KL_GPIO_SOUND_POWER);
962 UNLOCK(flags);
963 }
964 return 0;
965}
966
967static long
968core99_airport_enable(struct device_node *node, long param, long value)
969{
970 struct macio_chip* macio;
971 unsigned long flags;
972 int state;
973
974 macio = macio_find(node, 0);
975 if (!macio)
976 return -ENODEV;
977
978 /* Hint: we allow passing of macio itself for the sake of the
979 * sleep code
980 */
981 if (node != macio->of_node &&
982 (!node->parent || node->parent != macio->of_node))
983 return -ENODEV;
984 state = (macio->flags & MACIO_FLAG_AIRPORT_ON) != 0;
985 if (value == state)
986 return 0;
987 if (value) {
988 /* This code is a reproduction of OF enable-cardslot
989 * and init-wireless methods, slightly hacked until
990 * I got it working.
991 */
992 LOCK(flags);
993 MACIO_OUT8(KEYLARGO_GPIO_0+0xf, 5);
994 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xf);
995 UNLOCK(flags);
996 mdelay(10);
997 LOCK(flags);
998 MACIO_OUT8(KEYLARGO_GPIO_0+0xf, 4);
999 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xf);
1000 UNLOCK(flags);
1001
1002 mdelay(10);
1003
1004 LOCK(flags);
1005 MACIO_BIC(KEYLARGO_FCR2, KL2_CARDSEL_16);
1006 (void)MACIO_IN32(KEYLARGO_FCR2);
1007 udelay(10);
1008 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xb, 0);
1009 (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xb);
1010 udelay(10);
1011 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xa, 0x28);
1012 (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xa);
1013 udelay(10);
1014 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xd, 0x28);
1015 (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xd);
1016 udelay(10);
1017 MACIO_OUT8(KEYLARGO_GPIO_0+0xd, 0x28);
1018 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xd);
1019 udelay(10);
1020 MACIO_OUT8(KEYLARGO_GPIO_0+0xe, 0x28);
1021 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xe);
1022 UNLOCK(flags);
1023 udelay(10);
1024 MACIO_OUT32(0x1c000, 0);
1025 mdelay(1);
1026 MACIO_OUT8(0x1a3e0, 0x41);
1027 (void)MACIO_IN8(0x1a3e0);
1028 udelay(10);
1029 LOCK(flags);
1030 MACIO_BIS(KEYLARGO_FCR2, KL2_CARDSEL_16);
1031 (void)MACIO_IN32(KEYLARGO_FCR2);
1032 UNLOCK(flags);
1033 mdelay(100);
1034
1035 macio->flags |= MACIO_FLAG_AIRPORT_ON;
1036 } else {
1037 LOCK(flags);
1038 MACIO_BIC(KEYLARGO_FCR2, KL2_CARDSEL_16);
1039 (void)MACIO_IN32(KEYLARGO_FCR2);
1040 MACIO_OUT8(KL_GPIO_AIRPORT_0, 0);
1041 MACIO_OUT8(KL_GPIO_AIRPORT_1, 0);
1042 MACIO_OUT8(KL_GPIO_AIRPORT_2, 0);
1043 MACIO_OUT8(KL_GPIO_AIRPORT_3, 0);
1044 MACIO_OUT8(KL_GPIO_AIRPORT_4, 0);
1045 (void)MACIO_IN8(KL_GPIO_AIRPORT_4);
1046 UNLOCK(flags);
1047
1048 macio->flags &= ~MACIO_FLAG_AIRPORT_ON;
1049 }
1050 return 0;
1051}
1052
1053#ifdef CONFIG_SMP
1054static long
1055core99_reset_cpu(struct device_node *node, long param, long value)
1056{
1057 unsigned int reset_io = 0;
1058 unsigned long flags;
1059 struct macio_chip *macio;
1060 struct device_node *np;
1061 const int dflt_reset_lines[] = { KL_GPIO_RESET_CPU0,
1062 KL_GPIO_RESET_CPU1,
1063 KL_GPIO_RESET_CPU2,
1064 KL_GPIO_RESET_CPU3 };
1065
1066 macio = &macio_chips[0];
1067 if (macio->type != macio_keylargo)
1068 return -ENODEV;
1069
1070 np = find_path_device("/cpus");
1071 if (np == NULL)
1072 return -ENODEV;
1073 for (np = np->child; np != NULL; np = np->sibling) {
1074 u32 *num = (u32 *)get_property(np, "reg", NULL);
1075 u32 *rst = (u32 *)get_property(np, "soft-reset", NULL);
1076 if (num == NULL || rst == NULL)
1077 continue;
1078 if (param == *num) {
1079 reset_io = *rst;
1080 break;
1081 }
1082 }
1083 if (np == NULL || reset_io == 0)
1084 reset_io = dflt_reset_lines[param];
1085
1086 LOCK(flags);
1087 MACIO_OUT8(reset_io, KEYLARGO_GPIO_OUTPUT_ENABLE);
1088 (void)MACIO_IN8(reset_io);
1089 udelay(1);
1090 MACIO_OUT8(reset_io, 0);
1091 (void)MACIO_IN8(reset_io);
1092 UNLOCK(flags);
1093
1094 return 0;
1095}
1096#endif /* CONFIG_SMP */
1097
1098static long
1099core99_usb_enable(struct device_node *node, long param, long value)
1100{
1101 struct macio_chip *macio;
1102 unsigned long flags;
1103 char *prop;
1104 int number;
1105 u32 reg;
1106
1107 macio = &macio_chips[0];
1108 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1109 macio->type != macio_intrepid)
1110 return -ENODEV;
1111
1112 prop = (char *)get_property(node, "AAPL,clock-id", NULL);
1113 if (!prop)
1114 return -ENODEV;
1115 if (strncmp(prop, "usb0u048", 8) == 0)
1116 number = 0;
1117 else if (strncmp(prop, "usb1u148", 8) == 0)
1118 number = 2;
1119 else if (strncmp(prop, "usb2u248", 8) == 0)
1120 number = 4;
1121 else
1122 return -ENODEV;
1123
1124 /* Sorry for the brute-force locking, but this is only used during
1125 * sleep and the timing seem to be critical
1126 */
1127 LOCK(flags);
1128 if (value) {
1129 /* Turn ON */
1130 if (number == 0) {
1131 MACIO_BIC(KEYLARGO_FCR0, (KL0_USB0_PAD_SUSPEND0 | KL0_USB0_PAD_SUSPEND1));
1132 (void)MACIO_IN32(KEYLARGO_FCR0);
1133 UNLOCK(flags);
1134 mdelay(1);
1135 LOCK(flags);
1136 MACIO_BIS(KEYLARGO_FCR0, KL0_USB0_CELL_ENABLE);
1137 } else if (number == 2) {
1138 MACIO_BIC(KEYLARGO_FCR0, (KL0_USB1_PAD_SUSPEND0 | KL0_USB1_PAD_SUSPEND1));
1139 UNLOCK(flags);
1140 (void)MACIO_IN32(KEYLARGO_FCR0);
1141 mdelay(1);
1142 LOCK(flags);
1143 MACIO_BIS(KEYLARGO_FCR0, KL0_USB1_CELL_ENABLE);
1144 } else if (number == 4) {
1145 MACIO_BIC(KEYLARGO_FCR1, (KL1_USB2_PAD_SUSPEND0 | KL1_USB2_PAD_SUSPEND1));
1146 UNLOCK(flags);
1147 (void)MACIO_IN32(KEYLARGO_FCR1);
1148 mdelay(1);
1149 LOCK(flags);
1150 MACIO_BIS(KEYLARGO_FCR1, KL1_USB2_CELL_ENABLE);
1151 }
1152 if (number < 4) {
1153 reg = MACIO_IN32(KEYLARGO_FCR4);
1154 reg &= ~(KL4_PORT_WAKEUP_ENABLE(number) | KL4_PORT_RESUME_WAKE_EN(number) |
1155 KL4_PORT_CONNECT_WAKE_EN(number) | KL4_PORT_DISCONNECT_WAKE_EN(number));
1156 reg &= ~(KL4_PORT_WAKEUP_ENABLE(number+1) | KL4_PORT_RESUME_WAKE_EN(number+1) |
1157 KL4_PORT_CONNECT_WAKE_EN(number+1) | KL4_PORT_DISCONNECT_WAKE_EN(number+1));
1158 MACIO_OUT32(KEYLARGO_FCR4, reg);
1159 (void)MACIO_IN32(KEYLARGO_FCR4);
1160 udelay(10);
1161 } else {
1162 reg = MACIO_IN32(KEYLARGO_FCR3);
1163 reg &= ~(KL3_IT_PORT_WAKEUP_ENABLE(0) | KL3_IT_PORT_RESUME_WAKE_EN(0) |
1164 KL3_IT_PORT_CONNECT_WAKE_EN(0) | KL3_IT_PORT_DISCONNECT_WAKE_EN(0));
1165 reg &= ~(KL3_IT_PORT_WAKEUP_ENABLE(1) | KL3_IT_PORT_RESUME_WAKE_EN(1) |
1166 KL3_IT_PORT_CONNECT_WAKE_EN(1) | KL3_IT_PORT_DISCONNECT_WAKE_EN(1));
1167 MACIO_OUT32(KEYLARGO_FCR3, reg);
1168 (void)MACIO_IN32(KEYLARGO_FCR3);
1169 udelay(10);
1170 }
1171 if (macio->type == macio_intrepid) {
1172 /* wait for clock stopped bits to clear */
1173 u32 test0 = 0, test1 = 0;
1174 u32 status0, status1;
1175 int timeout = 1000;
1176
1177 UNLOCK(flags);
1178 switch (number) {
1179 case 0:
1180 test0 = UNI_N_CLOCK_STOPPED_USB0;
1181 test1 = UNI_N_CLOCK_STOPPED_USB0PCI;
1182 break;
1183 case 2:
1184 test0 = UNI_N_CLOCK_STOPPED_USB1;
1185 test1 = UNI_N_CLOCK_STOPPED_USB1PCI;
1186 break;
1187 case 4:
1188 test0 = UNI_N_CLOCK_STOPPED_USB2;
1189 test1 = UNI_N_CLOCK_STOPPED_USB2PCI;
1190 break;
1191 }
1192 do {
1193 if (--timeout <= 0) {
1194 printk(KERN_ERR "core99_usb_enable: "
1195 "Timeout waiting for clocks\n");
1196 break;
1197 }
1198 mdelay(1);
1199 status0 = UN_IN(UNI_N_CLOCK_STOP_STATUS0);
1200 status1 = UN_IN(UNI_N_CLOCK_STOP_STATUS1);
1201 } while ((status0 & test0) | (status1 & test1));
1202 LOCK(flags);
1203 }
1204 } else {
1205 /* Turn OFF */
1206 if (number < 4) {
1207 reg = MACIO_IN32(KEYLARGO_FCR4);
1208 reg |= KL4_PORT_WAKEUP_ENABLE(number) | KL4_PORT_RESUME_WAKE_EN(number) |
1209 KL4_PORT_CONNECT_WAKE_EN(number) | KL4_PORT_DISCONNECT_WAKE_EN(number);
1210 reg |= KL4_PORT_WAKEUP_ENABLE(number+1) | KL4_PORT_RESUME_WAKE_EN(number+1) |
1211 KL4_PORT_CONNECT_WAKE_EN(number+1) | KL4_PORT_DISCONNECT_WAKE_EN(number+1);
1212 MACIO_OUT32(KEYLARGO_FCR4, reg);
1213 (void)MACIO_IN32(KEYLARGO_FCR4);
1214 udelay(1);
1215 } else {
1216 reg = MACIO_IN32(KEYLARGO_FCR3);
1217 reg |= KL3_IT_PORT_WAKEUP_ENABLE(0) | KL3_IT_PORT_RESUME_WAKE_EN(0) |
1218 KL3_IT_PORT_CONNECT_WAKE_EN(0) | KL3_IT_PORT_DISCONNECT_WAKE_EN(0);
1219 reg |= KL3_IT_PORT_WAKEUP_ENABLE(1) | KL3_IT_PORT_RESUME_WAKE_EN(1) |
1220 KL3_IT_PORT_CONNECT_WAKE_EN(1) | KL3_IT_PORT_DISCONNECT_WAKE_EN(1);
1221 MACIO_OUT32(KEYLARGO_FCR3, reg);
1222 (void)MACIO_IN32(KEYLARGO_FCR3);
1223 udelay(1);
1224 }
1225 if (number == 0) {
1226 if (macio->type != macio_intrepid)
1227 MACIO_BIC(KEYLARGO_FCR0, KL0_USB0_CELL_ENABLE);
1228 (void)MACIO_IN32(KEYLARGO_FCR0);
1229 udelay(1);
1230 MACIO_BIS(KEYLARGO_FCR0, (KL0_USB0_PAD_SUSPEND0 | KL0_USB0_PAD_SUSPEND1));
1231 (void)MACIO_IN32(KEYLARGO_FCR0);
1232 } else if (number == 2) {
1233 if (macio->type != macio_intrepid)
1234 MACIO_BIC(KEYLARGO_FCR0, KL0_USB1_CELL_ENABLE);
1235 (void)MACIO_IN32(KEYLARGO_FCR0);
1236 udelay(1);
1237 MACIO_BIS(KEYLARGO_FCR0, (KL0_USB1_PAD_SUSPEND0 | KL0_USB1_PAD_SUSPEND1));
1238 (void)MACIO_IN32(KEYLARGO_FCR0);
1239 } else if (number == 4) {
1240 udelay(1);
1241 MACIO_BIS(KEYLARGO_FCR1, (KL1_USB2_PAD_SUSPEND0 | KL1_USB2_PAD_SUSPEND1));
1242 (void)MACIO_IN32(KEYLARGO_FCR1);
1243 }
1244 udelay(1);
1245 }
1246 UNLOCK(flags);
1247
1248 return 0;
1249}
1250
1251static long
1252core99_firewire_enable(struct device_node *node, long param, long value)
1253{
1254 unsigned long flags;
1255 struct macio_chip *macio;
1256
1257 macio = &macio_chips[0];
1258 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1259 macio->type != macio_intrepid)
1260 return -ENODEV;
1261 if (!(macio->flags & MACIO_FLAG_FW_SUPPORTED))
1262 return -ENODEV;
1263
1264 LOCK(flags);
1265 if (value) {
1266 UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_FW);
1267 (void)UN_IN(UNI_N_CLOCK_CNTL);
1268 } else {
1269 UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_FW);
1270 (void)UN_IN(UNI_N_CLOCK_CNTL);
1271 }
1272 UNLOCK(flags);
1273 mdelay(1);
1274
1275 return 0;
1276}
1277
1278static long
1279core99_firewire_cable_power(struct device_node *node, long param, long value)
1280{
1281 unsigned long flags;
1282 struct macio_chip *macio;
1283
1284 /* Trick: we allow NULL node */
1285 if ((pmac_mb.board_flags & PMAC_MB_HAS_FW_POWER) == 0)
1286 return -ENODEV;
1287 macio = &macio_chips[0];
1288 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1289 macio->type != macio_intrepid)
1290 return -ENODEV;
1291 if (!(macio->flags & MACIO_FLAG_FW_SUPPORTED))
1292 return -ENODEV;
1293
1294 LOCK(flags);
1295 if (value) {
1296 MACIO_OUT8(KL_GPIO_FW_CABLE_POWER , 0);
1297 MACIO_IN8(KL_GPIO_FW_CABLE_POWER);
1298 udelay(10);
1299 } else {
1300 MACIO_OUT8(KL_GPIO_FW_CABLE_POWER , 4);
1301 MACIO_IN8(KL_GPIO_FW_CABLE_POWER); udelay(10);
1302 }
1303 UNLOCK(flags);
1304 mdelay(1);
1305
1306 return 0;
1307}
1308
1309static long
1310intrepid_aack_delay_enable(struct device_node *node, long param, long value)
1311{
1312 unsigned long flags;
1313
1314 if (uninorth_rev < 0xd2)
1315 return -ENODEV;
1316
1317 LOCK(flags);
1318 if (param)
1319 UN_BIS(UNI_N_AACK_DELAY, UNI_N_AACK_DELAY_ENABLE);
1320 else
1321 UN_BIC(UNI_N_AACK_DELAY, UNI_N_AACK_DELAY_ENABLE);
1322 UNLOCK(flags);
1323
1324 return 0;
1325}
1326
1327
1328#endif /* CONFIG_POWER4 */
1329
1330static long
1331core99_read_gpio(struct device_node *node, long param, long value)
1332{
1333 struct macio_chip *macio = &macio_chips[0];
1334
1335 return MACIO_IN8(param);
1336}
1337
1338
1339static long
1340core99_write_gpio(struct device_node *node, long param, long value)
1341{
1342 struct macio_chip *macio = &macio_chips[0];
1343
1344 MACIO_OUT8(param, (u8)(value & 0xff));
1345 return 0;
1346}
1347
1348#ifdef CONFIG_POWER4
1349static long g5_gmac_enable(struct device_node *node, long param, long value)
1350{
1351 struct macio_chip *macio = &macio_chips[0];
1352 unsigned long flags;
1353
1354 if (node == NULL)
1355 return -ENODEV;
1356
1357 LOCK(flags);
1358 if (value) {
1359 MACIO_BIS(KEYLARGO_FCR1, K2_FCR1_GMAC_CLK_ENABLE);
1360 mb();
1361 k2_skiplist[0] = NULL;
1362 } else {
1363 k2_skiplist[0] = node;
1364 mb();
1365 MACIO_BIC(KEYLARGO_FCR1, K2_FCR1_GMAC_CLK_ENABLE);
1366 }
1367
1368 UNLOCK(flags);
1369 mdelay(1);
1370
1371 return 0;
1372}
1373
1374static long g5_fw_enable(struct device_node *node, long param, long value)
1375{
1376 struct macio_chip *macio = &macio_chips[0];
1377 unsigned long flags;
1378
1379 if (node == NULL)
1380 return -ENODEV;
1381
1382 LOCK(flags);
1383 if (value) {
1384 MACIO_BIS(KEYLARGO_FCR1, K2_FCR1_FW_CLK_ENABLE);
1385 mb();
1386 k2_skiplist[1] = NULL;
1387 } else {
1388 k2_skiplist[1] = node;
1389 mb();
1390 MACIO_BIC(KEYLARGO_FCR1, K2_FCR1_FW_CLK_ENABLE);
1391 }
1392
1393 UNLOCK(flags);
1394 mdelay(1);
1395
1396 return 0;
1397}
1398
1399static long g5_mpic_enable(struct device_node *node, long param, long value)
1400{
1401 unsigned long flags;
1402
1403 if (node->parent == NULL || strcmp(node->parent->name, "u3"))
1404 return 0;
1405
1406 LOCK(flags);
1407 UN_BIS(U3_TOGGLE_REG, U3_MPIC_RESET | U3_MPIC_OUTPUT_ENABLE);
1408 UNLOCK(flags);
1409
1410 return 0;
1411}
1412
1413static long g5_eth_phy_reset(struct device_node *node, long param, long value)
1414{
1415 struct macio_chip *macio = &macio_chips[0];
1416 struct device_node *phy;
1417 int need_reset;
1418
1419 /*
1420 * We must not reset the combo PHYs, only the BCM5221 found in
1421 * the iMac G5.
1422 */
1423 phy = of_get_next_child(node, NULL);
1424 if (!phy)
1425 return -ENODEV;
1426 need_reset = device_is_compatible(phy, "B5221");
1427 of_node_put(phy);
1428 if (!need_reset)
1429 return 0;
1430
1431 /* PHY reset is GPIO 29, not in device-tree unfortunately */
1432 MACIO_OUT8(K2_GPIO_EXTINT_0 + 29,
1433 KEYLARGO_GPIO_OUTPUT_ENABLE | KEYLARGO_GPIO_OUTOUT_DATA);
1434 /* Thankfully, this is now always called at a time when we can
1435 * schedule by sungem.
1436 */
1437 msleep(10);
1438 MACIO_OUT8(K2_GPIO_EXTINT_0 + 29, 0);
1439
1440 return 0;
1441}
1442
1443static long g5_i2s_enable(struct device_node *node, long param, long value)
1444{
1445 /* Very crude implementation for now */
1446 struct macio_chip *macio = &macio_chips[0];
1447 unsigned long flags;
1448
1449 if (value == 0)
1450 return 0; /* don't disable yet */
1451
1452 LOCK(flags);
1453 MACIO_BIS(KEYLARGO_FCR3, KL3_CLK45_ENABLE | KL3_CLK49_ENABLE |
1454 KL3_I2S0_CLK18_ENABLE);
1455 udelay(10);
1456 MACIO_BIS(KEYLARGO_FCR1, K2_FCR1_I2S0_CELL_ENABLE |
1457 K2_FCR1_I2S0_CLK_ENABLE_BIT | K2_FCR1_I2S0_ENABLE);
1458 udelay(10);
1459 MACIO_BIC(KEYLARGO_FCR1, K2_FCR1_I2S0_RESET);
1460 UNLOCK(flags);
1461 udelay(10);
1462
1463 return 0;
1464}
1465
1466
1467#ifdef CONFIG_SMP
1468static long g5_reset_cpu(struct device_node *node, long param, long value)
1469{
1470 unsigned int reset_io = 0;
1471 unsigned long flags;
1472 struct macio_chip *macio;
1473 struct device_node *np;
1474
1475 macio = &macio_chips[0];
1476 if (macio->type != macio_keylargo2)
1477 return -ENODEV;
1478
1479 np = find_path_device("/cpus");
1480 if (np == NULL)
1481 return -ENODEV;
1482 for (np = np->child; np != NULL; np = np->sibling) {
1483 u32 *num = (u32 *)get_property(np, "reg", NULL);
1484 u32 *rst = (u32 *)get_property(np, "soft-reset", NULL);
1485 if (num == NULL || rst == NULL)
1486 continue;
1487 if (param == *num) {
1488 reset_io = *rst;
1489 break;
1490 }
1491 }
1492 if (np == NULL || reset_io == 0)
1493 return -ENODEV;
1494
1495 LOCK(flags);
1496 MACIO_OUT8(reset_io, KEYLARGO_GPIO_OUTPUT_ENABLE);
1497 (void)MACIO_IN8(reset_io);
1498 udelay(1);
1499 MACIO_OUT8(reset_io, 0);
1500 (void)MACIO_IN8(reset_io);
1501 UNLOCK(flags);
1502
1503 return 0;
1504}
1505#endif /* CONFIG_SMP */
1506
1507/*
1508 * This can be called from pmac_smp so isn't static
1509 *
1510 * This takes the second CPU off the bus on dual CPU machines
1511 * running UP
1512 */
1513void g5_phy_disable_cpu1(void)
1514{
1515 UN_OUT(U3_API_PHY_CONFIG_1, 0);
1516}
1517#endif /* CONFIG_POWER4 */
1518
1519#ifndef CONFIG_POWER4
1520
1521static void
1522keylargo_shutdown(struct macio_chip *macio, int sleep_mode)
1523{
1524 u32 temp;
1525
1526 if (sleep_mode) {
1527 mdelay(1);
1528 MACIO_BIS(KEYLARGO_FCR0, KL0_USB_REF_SUSPEND);
1529 (void)MACIO_IN32(KEYLARGO_FCR0);
1530 mdelay(1);
1531 }
1532
1533 MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE |
1534 KL0_SCC_CELL_ENABLE |
1535 KL0_IRDA_ENABLE | KL0_IRDA_CLK32_ENABLE |
1536 KL0_IRDA_CLK19_ENABLE);
1537
1538 MACIO_BIC(KEYLARGO_MBCR, KL_MBCR_MB0_DEV_MASK);
1539 MACIO_BIS(KEYLARGO_MBCR, KL_MBCR_MB0_IDE_ENABLE);
1540
1541 MACIO_BIC(KEYLARGO_FCR1,
1542 KL1_AUDIO_SEL_22MCLK | KL1_AUDIO_CLK_ENABLE_BIT |
1543 KL1_AUDIO_CLK_OUT_ENABLE | KL1_AUDIO_CELL_ENABLE |
1544 KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT |
1545 KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE |
1546 KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE |
1547 KL1_EIDE0_ENABLE | KL1_EIDE0_RESET_N |
1548 KL1_EIDE1_ENABLE | KL1_EIDE1_RESET_N |
1549 KL1_UIDE_ENABLE);
1550
1551 MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
1552 MACIO_BIC(KEYLARGO_FCR2, KL2_IOBUS_ENABLE);
1553
1554 temp = MACIO_IN32(KEYLARGO_FCR3);
1555 if (macio->rev >= 2) {
1556 temp |= KL3_SHUTDOWN_PLL2X;
1557 if (sleep_mode)
1558 temp |= KL3_SHUTDOWN_PLL_TOTAL;
1559 }
1560
1561 temp |= KL3_SHUTDOWN_PLLKW6 | KL3_SHUTDOWN_PLLKW4 |
1562 KL3_SHUTDOWN_PLLKW35;
1563 if (sleep_mode)
1564 temp |= KL3_SHUTDOWN_PLLKW12;
1565 temp &= ~(KL3_CLK66_ENABLE | KL3_CLK49_ENABLE | KL3_CLK45_ENABLE
1566 | KL3_CLK31_ENABLE | KL3_I2S1_CLK18_ENABLE | KL3_I2S0_CLK18_ENABLE);
1567 if (sleep_mode)
1568 temp &= ~(KL3_TIMER_CLK18_ENABLE | KL3_VIA_CLK16_ENABLE);
1569 MACIO_OUT32(KEYLARGO_FCR3, temp);
1570
1571 /* Flush posted writes & wait a bit */
1572 (void)MACIO_IN32(KEYLARGO_FCR0); mdelay(1);
1573}
1574
1575static void
1576pangea_shutdown(struct macio_chip *macio, int sleep_mode)
1577{
1578 u32 temp;
1579
1580 MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE |
1581 KL0_SCC_CELL_ENABLE |
1582 KL0_USB0_CELL_ENABLE | KL0_USB1_CELL_ENABLE);
1583
1584 MACIO_BIC(KEYLARGO_FCR1,
1585 KL1_AUDIO_SEL_22MCLK | KL1_AUDIO_CLK_ENABLE_BIT |
1586 KL1_AUDIO_CLK_OUT_ENABLE | KL1_AUDIO_CELL_ENABLE |
1587 KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT |
1588 KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE |
1589 KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE |
1590 KL1_UIDE_ENABLE);
1591 if (pmac_mb.board_flags & PMAC_MB_MOBILE)
1592 MACIO_BIC(KEYLARGO_FCR1, KL1_UIDE_RESET_N);
1593
1594 MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
1595
1596 temp = MACIO_IN32(KEYLARGO_FCR3);
1597 temp |= KL3_SHUTDOWN_PLLKW6 | KL3_SHUTDOWN_PLLKW4 |
1598 KL3_SHUTDOWN_PLLKW35;
1599 temp &= ~(KL3_CLK49_ENABLE | KL3_CLK45_ENABLE | KL3_CLK31_ENABLE
1600 | KL3_I2S0_CLK18_ENABLE | KL3_I2S1_CLK18_ENABLE);
1601 if (sleep_mode)
1602 temp &= ~(KL3_VIA_CLK16_ENABLE | KL3_TIMER_CLK18_ENABLE);
1603 MACIO_OUT32(KEYLARGO_FCR3, temp);
1604
1605 /* Flush posted writes & wait a bit */
1606 (void)MACIO_IN32(KEYLARGO_FCR0); mdelay(1);
1607}
1608
1609static void
1610intrepid_shutdown(struct macio_chip *macio, int sleep_mode)
1611{
1612 u32 temp;
1613
1614 MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE |
1615 KL0_SCC_CELL_ENABLE);
1616
1617 MACIO_BIC(KEYLARGO_FCR1,
1618 /*KL1_USB2_CELL_ENABLE |*/
1619 KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT |
1620 KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE |
1621 KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE);
1622 if (pmac_mb.board_flags & PMAC_MB_MOBILE)
1623 MACIO_BIC(KEYLARGO_FCR1, KL1_UIDE_RESET_N);
1624
1625 temp = MACIO_IN32(KEYLARGO_FCR3);
1626 temp &= ~(KL3_CLK49_ENABLE | KL3_CLK45_ENABLE |
1627 KL3_I2S1_CLK18_ENABLE | KL3_I2S0_CLK18_ENABLE);
1628 if (sleep_mode)
1629 temp &= ~(KL3_TIMER_CLK18_ENABLE | KL3_IT_VIA_CLK32_ENABLE);
1630 MACIO_OUT32(KEYLARGO_FCR3, temp);
1631
1632 /* Flush posted writes & wait a bit */
1633 (void)MACIO_IN32(KEYLARGO_FCR0);
1634 mdelay(10);
1635}
1636
1637
1638void pmac_tweak_clock_spreading(int enable)
1639{
1640 struct macio_chip *macio = &macio_chips[0];
1641
1642 /* Hack for doing clock spreading on some machines PowerBooks and
1643 * iBooks. This implements the "platform-do-clockspreading" OF
1644 * property as decoded manually on various models. For safety, we also
1645 * check the product ID in the device-tree in cases we'll whack the i2c
1646 * chip to make reasonably sure we won't set wrong values in there
1647 *
1648 * Of course, ultimately, we have to implement a real parser for
1649 * the platform-do-* stuff...
1650 */
1651
1652 if (macio->type == macio_intrepid) {
1653 if (enable)
1654 UN_OUT(UNI_N_CLOCK_SPREADING, 2);
1655 else
1656 UN_OUT(UNI_N_CLOCK_SPREADING, 0);
1657 mdelay(40);
1658 }
1659
1660 while (machine_is_compatible("PowerBook5,2") ||
1661 machine_is_compatible("PowerBook5,3") ||
1662 machine_is_compatible("PowerBook6,2") ||
1663 machine_is_compatible("PowerBook6,3")) {
1664 struct device_node *ui2c = of_find_node_by_type(NULL, "i2c");
1665 struct device_node *dt = of_find_node_by_name(NULL, "device-tree");
1666 u8 buffer[9];
1667 u32 *productID;
1668 int i, rc, changed = 0;
1669
1670 if (dt == NULL)
1671 break;
1672 productID = (u32 *)get_property(dt, "pid#", NULL);
1673 if (productID == NULL)
1674 break;
1675 while(ui2c) {
1676 struct device_node *p = of_get_parent(ui2c);
1677 if (p && !strcmp(p->name, "uni-n"))
1678 break;
1679 ui2c = of_find_node_by_type(ui2c, "i2c");
1680 }
1681 if (ui2c == NULL)
1682 break;
1683 DBG("Trying to bump clock speed for PID: %08x...\n", *productID);
1684 rc = pmac_low_i2c_open(ui2c, 1);
1685 if (rc != 0)
1686 break;
1687 pmac_low_i2c_setmode(ui2c, pmac_low_i2c_mode_combined);
1688 rc = pmac_low_i2c_xfer(ui2c, 0xd2 | pmac_low_i2c_read, 0x80, buffer, 9);
1689 DBG("read result: %d,", rc);
1690 if (rc != 0) {
1691 pmac_low_i2c_close(ui2c);
1692 break;
1693 }
1694 for (i=0; i<9; i++)
1695 DBG(" %02x", buffer[i]);
1696 DBG("\n");
1697
1698 switch(*productID) {
1699 case 0x1182: /* AlBook 12" rev 2 */
1700 case 0x1183: /* iBook G4 12" */
1701 buffer[0] = (buffer[0] & 0x8f) | 0x70;
1702 buffer[2] = (buffer[2] & 0x7f) | 0x00;
1703 buffer[5] = (buffer[5] & 0x80) | 0x31;
1704 buffer[6] = (buffer[6] & 0x40) | 0xb0;
1705 buffer[7] = (buffer[7] & 0x00) | (enable ? 0xc0 : 0xba);
1706 buffer[8] = (buffer[8] & 0x00) | 0x30;
1707 changed = 1;
1708 break;
1709 case 0x3142: /* AlBook 15" (ATI M10) */
1710 case 0x3143: /* AlBook 17" (ATI M10) */
1711 buffer[0] = (buffer[0] & 0xaf) | 0x50;
1712 buffer[2] = (buffer[2] & 0x7f) | 0x00;
1713 buffer[5] = (buffer[5] & 0x80) | 0x31;
1714 buffer[6] = (buffer[6] & 0x40) | 0xb0;
1715 buffer[7] = (buffer[7] & 0x00) | (enable ? 0xd0 : 0xc0);
1716 buffer[8] = (buffer[8] & 0x00) | 0x30;
1717 changed = 1;
1718 break;
1719 default:
1720 DBG("i2c-hwclock: Machine model not handled\n");
1721 break;
1722 }
1723 if (!changed) {
1724 pmac_low_i2c_close(ui2c);
1725 break;
1726 }
1727 pmac_low_i2c_setmode(ui2c, pmac_low_i2c_mode_stdsub);
1728 rc = pmac_low_i2c_xfer(ui2c, 0xd2 | pmac_low_i2c_write, 0x80, buffer, 9);
1729 DBG("write result: %d,", rc);
1730 pmac_low_i2c_setmode(ui2c, pmac_low_i2c_mode_combined);
1731 rc = pmac_low_i2c_xfer(ui2c, 0xd2 | pmac_low_i2c_read, 0x80, buffer, 9);
1732 DBG("read result: %d,", rc);
1733 if (rc != 0) {
1734 pmac_low_i2c_close(ui2c);
1735 break;
1736 }
1737 for (i=0; i<9; i++)
1738 DBG(" %02x", buffer[i]);
1739 pmac_low_i2c_close(ui2c);
1740 break;
1741 }
1742}
1743
1744
1745static int
1746core99_sleep(void)
1747{
1748 struct macio_chip *macio;
1749 int i;
1750
1751 macio = &macio_chips[0];
1752 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1753 macio->type != macio_intrepid)
1754 return -ENODEV;
1755
1756 /* We power off the wireless slot in case it was not done
1757 * by the driver. We don't power it on automatically however
1758 */
1759 if (macio->flags & MACIO_FLAG_AIRPORT_ON)
1760 core99_airport_enable(macio->of_node, 0, 0);
1761
1762 /* We power off the FW cable. Should be done by the driver... */
1763 if (macio->flags & MACIO_FLAG_FW_SUPPORTED) {
1764 core99_firewire_enable(NULL, 0, 0);
1765 core99_firewire_cable_power(NULL, 0, 0);
1766 }
1767
1768 /* We make sure int. modem is off (in case driver lost it) */
1769 if (macio->type == macio_keylargo)
1770 core99_modem_enable(macio->of_node, 0, 0);
1771 else
1772 pangea_modem_enable(macio->of_node, 0, 0);
1773
1774 /* We make sure the sound is off as well */
1775 core99_sound_chip_enable(macio->of_node, 0, 0);
1776
1777 /*
1778 * Save various bits of KeyLargo
1779 */
1780
1781 /* Save the state of the various GPIOs */
1782 save_gpio_levels[0] = MACIO_IN32(KEYLARGO_GPIO_LEVELS0);
1783 save_gpio_levels[1] = MACIO_IN32(KEYLARGO_GPIO_LEVELS1);
1784 for (i=0; i<KEYLARGO_GPIO_EXTINT_CNT; i++)
1785 save_gpio_extint[i] = MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+i);
1786 for (i=0; i<KEYLARGO_GPIO_CNT; i++)
1787 save_gpio_normal[i] = MACIO_IN8(KEYLARGO_GPIO_0+i);
1788
1789 /* Save the FCRs */
1790 if (macio->type == macio_keylargo)
1791 save_mbcr = MACIO_IN32(KEYLARGO_MBCR);
1792 save_fcr[0] = MACIO_IN32(KEYLARGO_FCR0);
1793 save_fcr[1] = MACIO_IN32(KEYLARGO_FCR1);
1794 save_fcr[2] = MACIO_IN32(KEYLARGO_FCR2);
1795 save_fcr[3] = MACIO_IN32(KEYLARGO_FCR3);
1796 save_fcr[4] = MACIO_IN32(KEYLARGO_FCR4);
1797 if (macio->type == macio_pangea || macio->type == macio_intrepid)
1798 save_fcr[5] = MACIO_IN32(KEYLARGO_FCR5);
1799
1800 /* Save state & config of DBDMA channels */
1801 dbdma_save(macio, save_dbdma);
1802
1803 /*
1804 * Turn off as much as we can
1805 */
1806 if (macio->type == macio_pangea)
1807 pangea_shutdown(macio, 1);
1808 else if (macio->type == macio_intrepid)
1809 intrepid_shutdown(macio, 1);
1810 else if (macio->type == macio_keylargo)
1811 keylargo_shutdown(macio, 1);
1812
1813 /*
1814 * Put the host bridge to sleep
1815 */
1816
1817 save_unin_clock_ctl = UN_IN(UNI_N_CLOCK_CNTL);
1818 /* Note: do not switch GMAC off, driver does it when necessary, WOL must keep it
1819 * enabled !
1820 */
1821 UN_OUT(UNI_N_CLOCK_CNTL, save_unin_clock_ctl &
1822 ~(/*UNI_N_CLOCK_CNTL_GMAC|*/UNI_N_CLOCK_CNTL_FW/*|UNI_N_CLOCK_CNTL_PCI*/));
1823 udelay(100);
1824 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_SLEEPING);
1825 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_SLEEP);
1826 mdelay(10);
1827
1828 /*
1829 * FIXME: A bit of black magic with OpenPIC (don't ask me why)
1830 */
1831 if (pmac_mb.model_id == PMAC_TYPE_SAWTOOTH) {
1832 MACIO_BIS(0x506e0, 0x00400000);
1833 MACIO_BIS(0x506e0, 0x80000000);
1834 }
1835 return 0;
1836}
1837
1838static int
1839core99_wake_up(void)
1840{
1841 struct macio_chip *macio;
1842 int i;
1843
1844 macio = &macio_chips[0];
1845 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1846 macio->type != macio_intrepid)
1847 return -ENODEV;
1848
1849 /*
1850 * Wakeup the host bridge
1851 */
1852 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_NORMAL);
1853 udelay(10);
1854 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_RUNNING);
1855 udelay(10);
1856
1857 /*
1858 * Restore KeyLargo
1859 */
1860
1861 if (macio->type == macio_keylargo) {
1862 MACIO_OUT32(KEYLARGO_MBCR, save_mbcr);
1863 (void)MACIO_IN32(KEYLARGO_MBCR); udelay(10);
1864 }
1865 MACIO_OUT32(KEYLARGO_FCR0, save_fcr[0]);
1866 (void)MACIO_IN32(KEYLARGO_FCR0); udelay(10);
1867 MACIO_OUT32(KEYLARGO_FCR1, save_fcr[1]);
1868 (void)MACIO_IN32(KEYLARGO_FCR1); udelay(10);
1869 MACIO_OUT32(KEYLARGO_FCR2, save_fcr[2]);
1870 (void)MACIO_IN32(KEYLARGO_FCR2); udelay(10);
1871 MACIO_OUT32(KEYLARGO_FCR3, save_fcr[3]);
1872 (void)MACIO_IN32(KEYLARGO_FCR3); udelay(10);
1873 MACIO_OUT32(KEYLARGO_FCR4, save_fcr[4]);
1874 (void)MACIO_IN32(KEYLARGO_FCR4); udelay(10);
1875 if (macio->type == macio_pangea || macio->type == macio_intrepid) {
1876 MACIO_OUT32(KEYLARGO_FCR5, save_fcr[5]);
1877 (void)MACIO_IN32(KEYLARGO_FCR5); udelay(10);
1878 }
1879
1880 dbdma_restore(macio, save_dbdma);
1881
1882 MACIO_OUT32(KEYLARGO_GPIO_LEVELS0, save_gpio_levels[0]);
1883 MACIO_OUT32(KEYLARGO_GPIO_LEVELS1, save_gpio_levels[1]);
1884 for (i=0; i<KEYLARGO_GPIO_EXTINT_CNT; i++)
1885 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+i, save_gpio_extint[i]);
1886 for (i=0; i<KEYLARGO_GPIO_CNT; i++)
1887 MACIO_OUT8(KEYLARGO_GPIO_0+i, save_gpio_normal[i]);
1888
1889 /* FIXME more black magic with OpenPIC ... */
1890 if (pmac_mb.model_id == PMAC_TYPE_SAWTOOTH) {
1891 MACIO_BIC(0x506e0, 0x00400000);
1892 MACIO_BIC(0x506e0, 0x80000000);
1893 }
1894
1895 UN_OUT(UNI_N_CLOCK_CNTL, save_unin_clock_ctl);
1896 udelay(100);
1897
1898 return 0;
1899}
1900
1901static long
1902core99_sleep_state(struct device_node *node, long param, long value)
1903{
1904 /* Param == 1 means to enter the "fake sleep" mode that is
1905 * used for CPU speed switch
1906 */
1907 if (param == 1) {
1908 if (value == 1) {
1909 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_SLEEPING);
1910 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_IDLE2);
1911 } else {
1912 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_NORMAL);
1913 udelay(10);
1914 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_RUNNING);
1915 udelay(10);
1916 }
1917 return 0;
1918 }
1919 if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0)
1920 return -EPERM;
1921
1922 if (value == 1)
1923 return core99_sleep();
1924 else if (value == 0)
1925 return core99_wake_up();
1926 return 0;
1927}
1928
1929#endif /* CONFIG_POWER4 */
1930
1931static long
1932generic_dev_can_wake(struct device_node *node, long param, long value)
1933{
1934 /* Todo: eventually check we are really dealing with on-board
1935 * video device ...
1936 */
1937
1938 if (pmac_mb.board_flags & PMAC_MB_MAY_SLEEP)
1939 pmac_mb.board_flags |= PMAC_MB_CAN_SLEEP;
1940 return 0;
1941}
1942
1943static long generic_get_mb_info(struct device_node *node, long param, long value)
1944{
1945 switch(param) {
1946 case PMAC_MB_INFO_MODEL:
1947 return pmac_mb.model_id;
1948 case PMAC_MB_INFO_FLAGS:
1949 return pmac_mb.board_flags;
1950 case PMAC_MB_INFO_NAME:
1951 /* hack hack hack... but should work */
1952 *((const char **)value) = pmac_mb.model_name;
1953 return 0;
1954 }
1955 return -EINVAL;
1956}
1957
1958
1959/*
1960 * Table definitions
1961 */
1962
1963/* Used on any machine
1964 */
1965static struct feature_table_entry any_features[] = {
1966 { PMAC_FTR_GET_MB_INFO, generic_get_mb_info },
1967 { PMAC_FTR_DEVICE_CAN_WAKE, generic_dev_can_wake },
1968 { 0, NULL }
1969};
1970
1971#ifndef CONFIG_POWER4
1972
1973/* OHare based motherboards. Currently, we only use these on the
1974 * 2400,3400 and 3500 series powerbooks. Some older desktops seem
1975 * to have issues with turning on/off those asic cells
1976 */
1977static struct feature_table_entry ohare_features[] = {
1978 { PMAC_FTR_SCC_ENABLE, ohare_htw_scc_enable },
1979 { PMAC_FTR_SWIM3_ENABLE, ohare_floppy_enable },
1980 { PMAC_FTR_MESH_ENABLE, ohare_mesh_enable },
1981 { PMAC_FTR_IDE_ENABLE, ohare_ide_enable},
1982 { PMAC_FTR_IDE_RESET, ohare_ide_reset},
1983 { PMAC_FTR_SLEEP_STATE, ohare_sleep_state },
1984 { 0, NULL }
1985};
1986
1987/* Heathrow desktop machines (Beige G3).
1988 * Separated as some features couldn't be properly tested
1989 * and the serial port control bits appear to confuse it.
1990 */
1991static struct feature_table_entry heathrow_desktop_features[] = {
1992 { PMAC_FTR_SWIM3_ENABLE, heathrow_floppy_enable },
1993 { PMAC_FTR_MESH_ENABLE, heathrow_mesh_enable },
1994 { PMAC_FTR_IDE_ENABLE, heathrow_ide_enable },
1995 { PMAC_FTR_IDE_RESET, heathrow_ide_reset },
1996 { PMAC_FTR_BMAC_ENABLE, heathrow_bmac_enable },
1997 { 0, NULL }
1998};
1999
2000/* Heathrow based laptop, that is the Wallstreet and mainstreet
2001 * powerbooks.
2002 */
2003static struct feature_table_entry heathrow_laptop_features[] = {
2004 { PMAC_FTR_SCC_ENABLE, ohare_htw_scc_enable },
2005 { PMAC_FTR_MODEM_ENABLE, heathrow_modem_enable },
2006 { PMAC_FTR_SWIM3_ENABLE, heathrow_floppy_enable },
2007 { PMAC_FTR_MESH_ENABLE, heathrow_mesh_enable },
2008 { PMAC_FTR_IDE_ENABLE, heathrow_ide_enable },
2009 { PMAC_FTR_IDE_RESET, heathrow_ide_reset },
2010 { PMAC_FTR_BMAC_ENABLE, heathrow_bmac_enable },
2011 { PMAC_FTR_SOUND_CHIP_ENABLE, heathrow_sound_enable },
2012 { PMAC_FTR_SLEEP_STATE, heathrow_sleep_state },
2013 { 0, NULL }
2014};
2015
2016/* Paddington based machines
2017 * The lombard (101) powerbook, first iMac models, B&W G3 and Yikes G4.
2018 */
2019static struct feature_table_entry paddington_features[] = {
2020 { PMAC_FTR_SCC_ENABLE, ohare_htw_scc_enable },
2021 { PMAC_FTR_MODEM_ENABLE, heathrow_modem_enable },
2022 { PMAC_FTR_SWIM3_ENABLE, heathrow_floppy_enable },
2023 { PMAC_FTR_MESH_ENABLE, heathrow_mesh_enable },
2024 { PMAC_FTR_IDE_ENABLE, heathrow_ide_enable },
2025 { PMAC_FTR_IDE_RESET, heathrow_ide_reset },
2026 { PMAC_FTR_BMAC_ENABLE, heathrow_bmac_enable },
2027 { PMAC_FTR_SOUND_CHIP_ENABLE, heathrow_sound_enable },
2028 { PMAC_FTR_SLEEP_STATE, heathrow_sleep_state },
2029 { 0, NULL }
2030};
2031
2032/* Core99 & MacRISC 2 machines (all machines released since the
2033 * iBook (included), that is all AGP machines, except pangea
2034 * chipset. The pangea chipset is the "combo" UniNorth/KeyLargo
2035 * used on iBook2 & iMac "flow power".
2036 */
2037static struct feature_table_entry core99_features[] = {
2038 { PMAC_FTR_SCC_ENABLE, core99_scc_enable },
2039 { PMAC_FTR_MODEM_ENABLE, core99_modem_enable },
2040 { PMAC_FTR_IDE_ENABLE, core99_ide_enable },
2041 { PMAC_FTR_IDE_RESET, core99_ide_reset },
2042 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable },
2043 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset },
2044 { PMAC_FTR_SOUND_CHIP_ENABLE, core99_sound_chip_enable },
2045 { PMAC_FTR_AIRPORT_ENABLE, core99_airport_enable },
2046 { PMAC_FTR_USB_ENABLE, core99_usb_enable },
2047 { PMAC_FTR_1394_ENABLE, core99_firewire_enable },
2048 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power },
2049 { PMAC_FTR_SLEEP_STATE, core99_sleep_state },
2050#ifdef CONFIG_SMP
2051 { PMAC_FTR_RESET_CPU, core99_reset_cpu },
2052#endif /* CONFIG_SMP */
2053 { PMAC_FTR_READ_GPIO, core99_read_gpio },
2054 { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
2055 { 0, NULL }
2056};
2057
2058/* RackMac
2059 */
2060static struct feature_table_entry rackmac_features[] = {
2061 { PMAC_FTR_SCC_ENABLE, core99_scc_enable },
2062 { PMAC_FTR_IDE_ENABLE, core99_ide_enable },
2063 { PMAC_FTR_IDE_RESET, core99_ide_reset },
2064 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable },
2065 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset },
2066 { PMAC_FTR_USB_ENABLE, core99_usb_enable },
2067 { PMAC_FTR_1394_ENABLE, core99_firewire_enable },
2068 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power },
2069 { PMAC_FTR_SLEEP_STATE, core99_sleep_state },
2070#ifdef CONFIG_SMP
2071 { PMAC_FTR_RESET_CPU, core99_reset_cpu },
2072#endif /* CONFIG_SMP */
2073 { PMAC_FTR_READ_GPIO, core99_read_gpio },
2074 { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
2075 { 0, NULL }
2076};
2077
2078/* Pangea features
2079 */
2080static struct feature_table_entry pangea_features[] = {
2081 { PMAC_FTR_SCC_ENABLE, core99_scc_enable },
2082 { PMAC_FTR_MODEM_ENABLE, pangea_modem_enable },
2083 { PMAC_FTR_IDE_ENABLE, core99_ide_enable },
2084 { PMAC_FTR_IDE_RESET, core99_ide_reset },
2085 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable },
2086 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset },
2087 { PMAC_FTR_SOUND_CHIP_ENABLE, core99_sound_chip_enable },
2088 { PMAC_FTR_AIRPORT_ENABLE, core99_airport_enable },
2089 { PMAC_FTR_USB_ENABLE, core99_usb_enable },
2090 { PMAC_FTR_1394_ENABLE, core99_firewire_enable },
2091 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power },
2092 { PMAC_FTR_SLEEP_STATE, core99_sleep_state },
2093 { PMAC_FTR_READ_GPIO, core99_read_gpio },
2094 { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
2095 { 0, NULL }
2096};
2097
2098/* Intrepid features
2099 */
2100static struct feature_table_entry intrepid_features[] = {
2101 { PMAC_FTR_SCC_ENABLE, core99_scc_enable },
2102 { PMAC_FTR_MODEM_ENABLE, pangea_modem_enable },
2103 { PMAC_FTR_IDE_ENABLE, core99_ide_enable },
2104 { PMAC_FTR_IDE_RESET, core99_ide_reset },
2105 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable },
2106 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset },
2107 { PMAC_FTR_SOUND_CHIP_ENABLE, core99_sound_chip_enable },
2108 { PMAC_FTR_AIRPORT_ENABLE, core99_airport_enable },
2109 { PMAC_FTR_USB_ENABLE, core99_usb_enable },
2110 { PMAC_FTR_1394_ENABLE, core99_firewire_enable },
2111 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power },
2112 { PMAC_FTR_SLEEP_STATE, core99_sleep_state },
2113 { PMAC_FTR_READ_GPIO, core99_read_gpio },
2114 { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
2115 { PMAC_FTR_AACK_DELAY_ENABLE, intrepid_aack_delay_enable },
2116 { 0, NULL }
2117};
2118
2119#else /* CONFIG_POWER4 */
2120
2121/* G5 features
2122 */
2123static struct feature_table_entry g5_features[] = {
2124 { PMAC_FTR_GMAC_ENABLE, g5_gmac_enable },
2125 { PMAC_FTR_1394_ENABLE, g5_fw_enable },
2126 { PMAC_FTR_ENABLE_MPIC, g5_mpic_enable },
2127 { PMAC_FTR_GMAC_PHY_RESET, g5_eth_phy_reset },
2128 { PMAC_FTR_SOUND_CHIP_ENABLE, g5_i2s_enable },
2129#ifdef CONFIG_SMP
2130 { PMAC_FTR_RESET_CPU, g5_reset_cpu },
2131#endif /* CONFIG_SMP */
2132 { PMAC_FTR_READ_GPIO, core99_read_gpio },
2133 { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
2134 { 0, NULL }
2135};
2136
2137#endif /* CONFIG_POWER4 */
2138
2139static struct pmac_mb_def pmac_mb_defs[] = {
2140#ifndef CONFIG_POWER4
2141 /*
2142 * Desktops
2143 */
2144
2145 { "AAPL,8500", "PowerMac 8500/8600",
2146 PMAC_TYPE_PSURGE, NULL,
2147 0
2148 },
2149 { "AAPL,9500", "PowerMac 9500/9600",
2150 PMAC_TYPE_PSURGE, NULL,
2151 0
2152 },
2153 { "AAPL,7200", "PowerMac 7200",
2154 PMAC_TYPE_PSURGE, NULL,
2155 0
2156 },
2157 { "AAPL,7300", "PowerMac 7200/7300",
2158 PMAC_TYPE_PSURGE, NULL,
2159 0
2160 },
2161 { "AAPL,7500", "PowerMac 7500",
2162 PMAC_TYPE_PSURGE, NULL,
2163 0
2164 },
2165 { "AAPL,ShinerESB", "Apple Network Server",
2166 PMAC_TYPE_ANS, NULL,
2167 0
2168 },
2169 { "AAPL,e407", "Alchemy",
2170 PMAC_TYPE_ALCHEMY, NULL,
2171 0
2172 },
2173 { "AAPL,e411", "Gazelle",
2174 PMAC_TYPE_GAZELLE, NULL,
2175 0
2176 },
2177 { "AAPL,Gossamer", "PowerMac G3 (Gossamer)",
2178 PMAC_TYPE_GOSSAMER, heathrow_desktop_features,
2179 0
2180 },
2181 { "AAPL,PowerMac G3", "PowerMac G3 (Silk)",
2182 PMAC_TYPE_SILK, heathrow_desktop_features,
2183 0
2184 },
2185 { "PowerMac1,1", "Blue&White G3",
2186 PMAC_TYPE_YOSEMITE, paddington_features,
2187 0
2188 },
2189 { "PowerMac1,2", "PowerMac G4 PCI Graphics",
2190 PMAC_TYPE_YIKES, paddington_features,
2191 0
2192 },
2193 { "PowerMac2,1", "iMac FireWire",
2194 PMAC_TYPE_FW_IMAC, core99_features,
2195 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
2196 },
2197 { "PowerMac2,2", "iMac FireWire",
2198 PMAC_TYPE_FW_IMAC, core99_features,
2199 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
2200 },
2201 { "PowerMac3,1", "PowerMac G4 AGP Graphics",
2202 PMAC_TYPE_SAWTOOTH, core99_features,
2203 PMAC_MB_OLD_CORE99
2204 },
2205 { "PowerMac3,2", "PowerMac G4 AGP Graphics",
2206 PMAC_TYPE_SAWTOOTH, core99_features,
2207 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
2208 },
2209 { "PowerMac3,3", "PowerMac G4 AGP Graphics",
2210 PMAC_TYPE_SAWTOOTH, core99_features,
2211 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
2212 },
2213 { "PowerMac3,4", "PowerMac G4 Silver",
2214 PMAC_TYPE_QUICKSILVER, core99_features,
2215 PMAC_MB_MAY_SLEEP
2216 },
2217 { "PowerMac3,5", "PowerMac G4 Silver",
2218 PMAC_TYPE_QUICKSILVER, core99_features,
2219 PMAC_MB_MAY_SLEEP
2220 },
2221 { "PowerMac3,6", "PowerMac G4 Windtunnel",
2222 PMAC_TYPE_WINDTUNNEL, core99_features,
2223 PMAC_MB_MAY_SLEEP,
2224 },
2225 { "PowerMac4,1", "iMac \"Flower Power\"",
2226 PMAC_TYPE_PANGEA_IMAC, pangea_features,
2227 PMAC_MB_MAY_SLEEP
2228 },
2229 { "PowerMac4,2", "Flat panel iMac",
2230 PMAC_TYPE_FLAT_PANEL_IMAC, pangea_features,
2231 PMAC_MB_CAN_SLEEP
2232 },
2233 { "PowerMac4,4", "eMac",
2234 PMAC_TYPE_EMAC, core99_features,
2235 PMAC_MB_MAY_SLEEP
2236 },
2237 { "PowerMac5,1", "PowerMac G4 Cube",
2238 PMAC_TYPE_CUBE, core99_features,
2239 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
2240 },
2241 { "PowerMac6,1", "Flat panel iMac",
2242 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2243 PMAC_MB_MAY_SLEEP,
2244 },
2245 { "PowerMac6,3", "Flat panel iMac",
2246 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2247 PMAC_MB_MAY_SLEEP,
2248 },
2249 { "PowerMac6,4", "eMac",
2250 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2251 PMAC_MB_MAY_SLEEP,
2252 },
2253 { "PowerMac10,1", "Mac mini",
2254 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2255 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER,
2256 },
2257 { "iMac,1", "iMac (first generation)",
2258 PMAC_TYPE_ORIG_IMAC, paddington_features,
2259 0
2260 },
2261
2262 /*
2263 * Xserve's
2264 */
2265
2266 { "RackMac1,1", "XServe",
2267 PMAC_TYPE_RACKMAC, rackmac_features,
2268 0,
2269 },
2270 { "RackMac1,2", "XServe rev. 2",
2271 PMAC_TYPE_RACKMAC, rackmac_features,
2272 0,
2273 },
2274
2275 /*
2276 * Laptops
2277 */
2278
2279 { "AAPL,3400/2400", "PowerBook 3400",
2280 PMAC_TYPE_HOOPER, ohare_features,
2281 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE
2282 },
2283 { "AAPL,3500", "PowerBook 3500",
2284 PMAC_TYPE_KANGA, ohare_features,
2285 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE
2286 },
2287 { "AAPL,PowerBook1998", "PowerBook Wallstreet",
2288 PMAC_TYPE_WALLSTREET, heathrow_laptop_features,
2289 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE
2290 },
2291 { "PowerBook1,1", "PowerBook 101 (Lombard)",
2292 PMAC_TYPE_101_PBOOK, paddington_features,
2293 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE
2294 },
2295 { "PowerBook2,1", "iBook (first generation)",
2296 PMAC_TYPE_ORIG_IBOOK, core99_features,
2297 PMAC_MB_CAN_SLEEP | PMAC_MB_OLD_CORE99 | PMAC_MB_MOBILE
2298 },
2299 { "PowerBook2,2", "iBook FireWire",
2300 PMAC_TYPE_FW_IBOOK, core99_features,
2301 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER |
2302 PMAC_MB_OLD_CORE99 | PMAC_MB_MOBILE
2303 },
2304 { "PowerBook3,1", "PowerBook Pismo",
2305 PMAC_TYPE_PISMO, core99_features,
2306 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER |
2307 PMAC_MB_OLD_CORE99 | PMAC_MB_MOBILE
2308 },
2309 { "PowerBook3,2", "PowerBook Titanium",
2310 PMAC_TYPE_TITANIUM, core99_features,
2311 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2312 },
2313 { "PowerBook3,3", "PowerBook Titanium II",
2314 PMAC_TYPE_TITANIUM2, core99_features,
2315 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2316 },
2317 { "PowerBook3,4", "PowerBook Titanium III",
2318 PMAC_TYPE_TITANIUM3, core99_features,
2319 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2320 },
2321 { "PowerBook3,5", "PowerBook Titanium IV",
2322 PMAC_TYPE_TITANIUM4, core99_features,
2323 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2324 },
2325 { "PowerBook4,1", "iBook 2",
2326 PMAC_TYPE_IBOOK2, pangea_features,
2327 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2328 },
2329 { "PowerBook4,2", "iBook 2",
2330 PMAC_TYPE_IBOOK2, pangea_features,
2331 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2332 },
2333 { "PowerBook4,3", "iBook 2 rev. 2",
2334 PMAC_TYPE_IBOOK2, pangea_features,
2335 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2336 },
2337 { "PowerBook5,1", "PowerBook G4 17\"",
2338 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2339 PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2340 },
2341 { "PowerBook5,2", "PowerBook G4 15\"",
2342 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2343 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2344 },
2345 { "PowerBook5,3", "PowerBook G4 17\"",
2346 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2347 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2348 },
2349 { "PowerBook5,4", "PowerBook G4 15\"",
2350 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2351 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2352 },
2353 { "PowerBook5,5", "PowerBook G4 17\"",
2354 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2355 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2356 },
2357 { "PowerBook5,6", "PowerBook G4 15\"",
2358 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2359 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2360 },
2361 { "PowerBook5,7", "PowerBook G4 17\"",
2362 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2363 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2364 },
2365 { "PowerBook6,1", "PowerBook G4 12\"",
2366 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2367 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2368 },
2369 { "PowerBook6,2", "PowerBook G4",
2370 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2371 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2372 },
2373 { "PowerBook6,3", "iBook G4",
2374 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2375 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2376 },
2377 { "PowerBook6,4", "PowerBook G4 12\"",
2378 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2379 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2380 },
2381 { "PowerBook6,5", "iBook G4",
2382 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2383 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2384 },
2385 { "PowerBook6,8", "PowerBook G4 12\"",
2386 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2387 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2388 },
2389#else /* CONFIG_POWER4 */
2390 { "PowerMac7,2", "PowerMac G5",
2391 PMAC_TYPE_POWERMAC_G5, g5_features,
2392 0,
2393 },
2394#ifdef CONFIG_PPC64
2395 { "PowerMac7,3", "PowerMac G5",
2396 PMAC_TYPE_POWERMAC_G5, g5_features,
2397 0,
2398 },
2399 { "PowerMac8,1", "iMac G5",
2400 PMAC_TYPE_IMAC_G5, g5_features,
2401 0,
2402 },
2403 { "PowerMac9,1", "PowerMac G5",
2404 PMAC_TYPE_POWERMAC_G5_U3L, g5_features,
2405 0,
2406 },
2407 { "RackMac3,1", "XServe G5",
2408 PMAC_TYPE_XSERVE_G5, g5_features,
2409 0,
2410 },
2411#endif /* CONFIG_PPC64 */
2412#endif /* CONFIG_POWER4 */
2413};
2414
2415/*
2416 * The toplevel feature_call callback
2417 */
2418long pmac_do_feature_call(unsigned int selector, ...)
2419{
2420 struct device_node *node;
2421 long param, value;
2422 int i;
2423 feature_call func = NULL;
2424 va_list args;
2425
2426 if (pmac_mb.features)
2427 for (i=0; pmac_mb.features[i].function; i++)
2428 if (pmac_mb.features[i].selector == selector) {
2429 func = pmac_mb.features[i].function;
2430 break;
2431 }
2432 if (!func)
2433 for (i=0; any_features[i].function; i++)
2434 if (any_features[i].selector == selector) {
2435 func = any_features[i].function;
2436 break;
2437 }
2438 if (!func)
2439 return -ENODEV;
2440
2441 va_start(args, selector);
2442 node = (struct device_node*)va_arg(args, void*);
2443 param = va_arg(args, long);
2444 value = va_arg(args, long);
2445 va_end(args);
2446
2447 return func(node, param, value);
2448}
2449
2450static int __init probe_motherboard(void)
2451{
2452 int i;
2453 struct macio_chip *macio = &macio_chips[0];
2454 const char *model = NULL;
2455 struct device_node *dt;
2456
2457 /* Lookup known motherboard type in device-tree. First try an
2458 * exact match on the "model" property, then try a "compatible"
2459 * match is none is found.
2460 */
2461 dt = find_devices("device-tree");
2462 if (dt != NULL)
2463 model = (const char *) get_property(dt, "model", NULL);
2464 for(i=0; model && i<(sizeof(pmac_mb_defs)/sizeof(struct pmac_mb_def)); i++) {
2465 if (strcmp(model, pmac_mb_defs[i].model_string) == 0) {
2466 pmac_mb = pmac_mb_defs[i];
2467 goto found;
2468 }
2469 }
2470 for(i=0; i<(sizeof(pmac_mb_defs)/sizeof(struct pmac_mb_def)); i++) {
2471 if (machine_is_compatible(pmac_mb_defs[i].model_string)) {
2472 pmac_mb = pmac_mb_defs[i];
2473 goto found;
2474 }
2475 }
2476
2477 /* Fallback to selection depending on mac-io chip type */
2478 switch(macio->type) {
2479#ifndef CONFIG_POWER4
2480 case macio_grand_central:
2481 pmac_mb.model_id = PMAC_TYPE_PSURGE;
2482 pmac_mb.model_name = "Unknown PowerSurge";
2483 break;
2484 case macio_ohare:
2485 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_OHARE;
2486 pmac_mb.model_name = "Unknown OHare-based";
2487 break;
2488 case macio_heathrow:
2489 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_HEATHROW;
2490 pmac_mb.model_name = "Unknown Heathrow-based";
2491 pmac_mb.features = heathrow_desktop_features;
2492 break;
2493 case macio_paddington:
2494 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_PADDINGTON;
2495 pmac_mb.model_name = "Unknown Paddington-based";
2496 pmac_mb.features = paddington_features;
2497 break;
2498 case macio_keylargo:
2499 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_CORE99;
2500 pmac_mb.model_name = "Unknown Keylargo-based";
2501 pmac_mb.features = core99_features;
2502 break;
2503 case macio_pangea:
2504 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_PANGEA;
2505 pmac_mb.model_name = "Unknown Pangea-based";
2506 pmac_mb.features = pangea_features;
2507 break;
2508 case macio_intrepid:
2509 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_INTREPID;
2510 pmac_mb.model_name = "Unknown Intrepid-based";
2511 pmac_mb.features = intrepid_features;
2512 break;
2513#else /* CONFIG_POWER4 */
2514 case macio_keylargo2:
2515 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_K2;
2516 pmac_mb.model_name = "Unknown K2-based";
2517 pmac_mb.features = g5_features;
2518 break;
2519#endif /* CONFIG_POWER4 */
2520 default:
2521 return -ENODEV;
2522 }
2523found:
2524#ifndef CONFIG_POWER4
2525 /* Fixup Hooper vs. Comet */
2526 if (pmac_mb.model_id == PMAC_TYPE_HOOPER) {
2527 u32 __iomem * mach_id_ptr = ioremap(0xf3000034, 4);
2528 if (!mach_id_ptr)
2529 return -ENODEV;
2530 /* Here, I used to disable the media-bay on comet. It
2531 * appears this is wrong, the floppy connector is actually
2532 * a kind of media-bay and works with the current driver.
2533 */
2534 if (__raw_readl(mach_id_ptr) & 0x20000000UL)
2535 pmac_mb.model_id = PMAC_TYPE_COMET;
2536 iounmap(mach_id_ptr);
2537 }
2538#endif /* CONFIG_POWER4 */
2539
2540#ifdef CONFIG_6xx
2541 /* Set default value of powersave_nap on machines that support it.
2542 * It appears that uninorth rev 3 has a problem with it, we don't
2543 * enable it on those. In theory, the flush-on-lock property is
2544 * supposed to be set when not supported, but I'm not very confident
2545 * that all Apple OF revs did it properly, I do it the paranoid way.
2546 */
2547 while (uninorth_base && uninorth_rev > 3) {
2548 struct device_node *np = find_path_device("/cpus");
2549 if (!np || !np->child) {
2550 printk(KERN_WARNING "Can't find CPU(s) in device tree !\n");
2551 break;
2552 }
2553 np = np->child;
2554 /* Nap mode not supported on SMP */
2555 if (np->sibling)
2556 break;
2557 /* Nap mode not supported if flush-on-lock property is present */
2558 if (get_property(np, "flush-on-lock", NULL))
2559 break;
2560 powersave_nap = 1;
2561 printk(KERN_INFO "Processor NAP mode on idle enabled.\n");
2562 break;
2563 }
2564
2565 /* On CPUs that support it (750FX), lowspeed by default during
2566 * NAP mode
2567 */
2568 powersave_lowspeed = 1;
2569#endif /* CONFIG_6xx */
2570#ifdef CONFIG_POWER4
2571 powersave_nap = 1;
2572#endif
2573 /* Check for "mobile" machine */
2574 if (model && (strncmp(model, "PowerBook", 9) == 0
2575 || strncmp(model, "iBook", 5) == 0))
2576 pmac_mb.board_flags |= PMAC_MB_MOBILE;
2577
2578
2579 printk(KERN_INFO "PowerMac motherboard: %s\n", pmac_mb.model_name);
2580 return 0;
2581}
2582
2583/* Initialize the Core99 UniNorth host bridge and memory controller
2584 */
2585static void __init probe_uninorth(void)
2586{
2587 unsigned long actrl;
2588
2589 /* Locate core99 Uni-N */
2590 uninorth_node = of_find_node_by_name(NULL, "uni-n");
2591 /* Locate G5 u3 */
2592 if (uninorth_node == NULL) {
2593 uninorth_node = of_find_node_by_name(NULL, "u3");
2594 uninorth_u3 = 1;
2595 }
2596 if (uninorth_node && uninorth_node->n_addrs > 0) {
2597 unsigned long address = uninorth_node->addrs[0].address;
2598 uninorth_base = ioremap(address, 0x40000);
2599 uninorth_rev = in_be32(UN_REG(UNI_N_VERSION));
2600 if (uninorth_u3)
2601 u3_ht = ioremap(address + U3_HT_CONFIG_BASE, 0x1000);
2602 } else
2603 uninorth_node = NULL;
2604
2605 if (!uninorth_node)
2606 return;
2607
2608 printk(KERN_INFO "Found %s memory controller & host bridge, revision: %d\n",
2609 uninorth_u3 ? "U3" : "UniNorth", uninorth_rev);
2610 printk(KERN_INFO "Mapped at 0x%08lx\n", (unsigned long)uninorth_base);
2611
2612 /* Set the arbitrer QAck delay according to what Apple does
2613 */
2614 if (uninorth_rev < 0x11) {
2615 actrl = UN_IN(UNI_N_ARB_CTRL) & ~UNI_N_ARB_CTRL_QACK_DELAY_MASK;
2616 actrl |= ((uninorth_rev < 3) ? UNI_N_ARB_CTRL_QACK_DELAY105 :
2617 UNI_N_ARB_CTRL_QACK_DELAY) << UNI_N_ARB_CTRL_QACK_DELAY_SHIFT;
2618 UN_OUT(UNI_N_ARB_CTRL, actrl);
2619 }
2620
2621 /* Some more magic as done by them in recent MacOS X on UniNorth
2622 * revs 1.5 to 2.O and Pangea. Seem to toggle the UniN Maxbus/PCI
2623 * memory timeout
2624 */
2625 if ((uninorth_rev >= 0x11 && uninorth_rev <= 0x24) || uninorth_rev == 0xc0)
2626 UN_OUT(0x2160, UN_IN(0x2160) & 0x00ffffff);
2627}
2628
2629static void __init probe_one_macio(const char *name, const char *compat, int type)
2630{
2631 struct device_node* node;
2632 int i;
2633 volatile u32 __iomem * base;
2634 u32* revp;
2635
2636 node = find_devices(name);
2637 if (!node || !node->n_addrs)
2638 return;
2639 if (compat)
2640 do {
2641 if (device_is_compatible(node, compat))
2642 break;
2643 node = node->next;
2644 } while (node);
2645 if (!node)
2646 return;
2647 for(i=0; i<MAX_MACIO_CHIPS; i++) {
2648 if (!macio_chips[i].of_node)
2649 break;
2650 if (macio_chips[i].of_node == node)
2651 return;
2652 }
2653 if (i >= MAX_MACIO_CHIPS) {
2654 printk(KERN_ERR "pmac_feature: Please increase MAX_MACIO_CHIPS !\n");
2655 printk(KERN_ERR "pmac_feature: %s skipped\n", node->full_name);
2656 return;
2657 }
2658 base = ioremap(node->addrs[0].address, node->addrs[0].size);
2659 if (!base) {
2660 printk(KERN_ERR "pmac_feature: Can't map mac-io chip !\n");
2661 return;
2662 }
2663 if (type == macio_keylargo) {
2664 u32 *did = (u32 *)get_property(node, "device-id", NULL);
2665 if (*did == 0x00000025)
2666 type = macio_pangea;
2667 if (*did == 0x0000003e)
2668 type = macio_intrepid;
2669 }
2670 macio_chips[i].of_node = node;
2671 macio_chips[i].type = type;
2672 macio_chips[i].base = base;
2673 macio_chips[i].flags = MACIO_FLAG_SCCB_ON | MACIO_FLAG_SCCB_ON;
2674 macio_chips[i].name = macio_names[type];
2675 revp = (u32 *)get_property(node, "revision-id", NULL);
2676 if (revp)
2677 macio_chips[i].rev = *revp;
2678 printk(KERN_INFO "Found a %s mac-io controller, rev: %d, mapped at 0x%p\n",
2679 macio_names[type], macio_chips[i].rev, macio_chips[i].base);
2680}
2681
2682static int __init
2683probe_macios(void)
2684{
2685 /* Warning, ordering is important */
2686 probe_one_macio("gc", NULL, macio_grand_central);
2687 probe_one_macio("ohare", NULL, macio_ohare);
2688 probe_one_macio("pci106b,7", NULL, macio_ohareII);
2689 probe_one_macio("mac-io", "keylargo", macio_keylargo);
2690 probe_one_macio("mac-io", "paddington", macio_paddington);
2691 probe_one_macio("mac-io", "gatwick", macio_gatwick);
2692 probe_one_macio("mac-io", "heathrow", macio_heathrow);
2693 probe_one_macio("mac-io", "K2-Keylargo", macio_keylargo2);
2694
2695 /* Make sure the "main" macio chip appear first */
2696 if (macio_chips[0].type == macio_gatwick
2697 && macio_chips[1].type == macio_heathrow) {
2698 struct macio_chip temp = macio_chips[0];
2699 macio_chips[0] = macio_chips[1];
2700 macio_chips[1] = temp;
2701 }
2702 if (macio_chips[0].type == macio_ohareII
2703 && macio_chips[1].type == macio_ohare) {
2704 struct macio_chip temp = macio_chips[0];
2705 macio_chips[0] = macio_chips[1];
2706 macio_chips[1] = temp;
2707 }
2708 macio_chips[0].lbus.index = 0;
2709 macio_chips[1].lbus.index = 1;
2710
2711 return (macio_chips[0].of_node == NULL) ? -ENODEV : 0;
2712}
2713
2714static void __init
2715initial_serial_shutdown(struct device_node *np)
2716{
2717 int len;
2718 struct slot_names_prop {
2719 int count;
2720 char name[1];
2721 } *slots;
2722 char *conn;
2723 int port_type = PMAC_SCC_ASYNC;
2724 int modem = 0;
2725
2726 slots = (struct slot_names_prop *)get_property(np, "slot-names", &len);
2727 conn = get_property(np, "AAPL,connector", &len);
2728 if (conn && (strcmp(conn, "infrared") == 0))
2729 port_type = PMAC_SCC_IRDA;
2730 else if (device_is_compatible(np, "cobalt"))
2731 modem = 1;
2732 else if (slots && slots->count > 0) {
2733 if (strcmp(slots->name, "IrDA") == 0)
2734 port_type = PMAC_SCC_IRDA;
2735 else if (strcmp(slots->name, "Modem") == 0)
2736 modem = 1;
2737 }
2738 if (modem)
2739 pmac_call_feature(PMAC_FTR_MODEM_ENABLE, np, 0, 0);
2740 pmac_call_feature(PMAC_FTR_SCC_ENABLE, np, port_type, 0);
2741}
2742
2743static void __init
2744set_initial_features(void)
2745{
2746 struct device_node *np;
2747
2748 /* That hack appears to be necessary for some StarMax motherboards
2749 * but I'm not too sure it was audited for side-effects on other
2750 * ohare based machines...
2751 * Since I still have difficulties figuring the right way to
2752 * differenciate them all and since that hack was there for a long
2753 * time, I'll keep it around
2754 */
2755 if (macio_chips[0].type == macio_ohare && !find_devices("via-pmu")) {
2756 struct macio_chip *macio = &macio_chips[0];
2757 MACIO_OUT32(OHARE_FCR, STARMAX_FEATURES);
2758 } else if (macio_chips[0].type == macio_ohare) {
2759 struct macio_chip *macio = &macio_chips[0];
2760 MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE);
2761 } else if (macio_chips[1].type == macio_ohare) {
2762 struct macio_chip *macio = &macio_chips[1];
2763 MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE);
2764 }
2765
2766#ifdef CONFIG_POWER4
2767 if (macio_chips[0].type == macio_keylargo2) {
2768#ifndef CONFIG_SMP
2769 /* On SMP machines running UP, we have the second CPU eating
2770 * bus cycles. We need to take it off the bus. This is done
2771 * from pmac_smp for SMP kernels running on one CPU
2772 */
2773 np = of_find_node_by_type(NULL, "cpu");
2774 if (np != NULL)
2775 np = of_find_node_by_type(np, "cpu");
2776 if (np != NULL) {
2777 g5_phy_disable_cpu1();
2778 of_node_put(np);
2779 }
2780#endif /* CONFIG_SMP */
2781 /* Enable GMAC for now for PCI probing. It will be disabled
2782 * later on after PCI probe
2783 */
2784 np = of_find_node_by_name(NULL, "ethernet");
2785 while(np) {
2786 if (device_is_compatible(np, "K2-GMAC"))
2787 g5_gmac_enable(np, 0, 1);
2788 np = of_find_node_by_name(np, "ethernet");
2789 }
2790
2791 /* Enable FW before PCI probe. Will be disabled later on
2792 * Note: We should have a batter way to check that we are
2793 * dealing with uninorth internal cell and not a PCI cell
2794 * on the external PCI. The code below works though.
2795 */
2796 np = of_find_node_by_name(NULL, "firewire");
2797 while(np) {
2798 if (device_is_compatible(np, "pci106b,5811")) {
2799 macio_chips[0].flags |= MACIO_FLAG_FW_SUPPORTED;
2800 g5_fw_enable(np, 0, 1);
2801 }
2802 np = of_find_node_by_name(np, "firewire");
2803 }
2804 }
2805#else /* CONFIG_POWER4 */
2806
2807 if (macio_chips[0].type == macio_keylargo ||
2808 macio_chips[0].type == macio_pangea ||
2809 macio_chips[0].type == macio_intrepid) {
2810 /* Enable GMAC for now for PCI probing. It will be disabled
2811 * later on after PCI probe
2812 */
2813 np = of_find_node_by_name(NULL, "ethernet");
2814 while(np) {
2815 if (np->parent
2816 && device_is_compatible(np->parent, "uni-north")
2817 && device_is_compatible(np, "gmac"))
2818 core99_gmac_enable(np, 0, 1);
2819 np = of_find_node_by_name(np, "ethernet");
2820 }
2821
2822 /* Enable FW before PCI probe. Will be disabled later on
2823 * Note: We should have a batter way to check that we are
2824 * dealing with uninorth internal cell and not a PCI cell
2825 * on the external PCI. The code below works though.
2826 */
2827 np = of_find_node_by_name(NULL, "firewire");
2828 while(np) {
2829 if (np->parent
2830 && device_is_compatible(np->parent, "uni-north")
2831 && (device_is_compatible(np, "pci106b,18") ||
2832 device_is_compatible(np, "pci106b,30") ||
2833 device_is_compatible(np, "pci11c1,5811"))) {
2834 macio_chips[0].flags |= MACIO_FLAG_FW_SUPPORTED;
2835 core99_firewire_enable(np, 0, 1);
2836 }
2837 np = of_find_node_by_name(np, "firewire");
2838 }
2839
2840 /* Enable ATA-100 before PCI probe. */
2841 np = of_find_node_by_name(NULL, "ata-6");
2842 while(np) {
2843 if (np->parent
2844 && device_is_compatible(np->parent, "uni-north")
2845 && device_is_compatible(np, "kauai-ata")) {
2846 core99_ata100_enable(np, 1);
2847 }
2848 np = of_find_node_by_name(np, "ata-6");
2849 }
2850
2851 /* Switch airport off */
2852 np = find_devices("radio");
2853 while(np) {
2854 if (np && np->parent == macio_chips[0].of_node) {
2855 macio_chips[0].flags |= MACIO_FLAG_AIRPORT_ON;
2856 core99_airport_enable(np, 0, 0);
2857 }
2858 np = np->next;
2859 }
2860 }
2861
2862 /* On all machines that support sound PM, switch sound off */
2863 if (macio_chips[0].of_node)
2864 pmac_do_feature_call(PMAC_FTR_SOUND_CHIP_ENABLE,
2865 macio_chips[0].of_node, 0, 0);
2866
2867 /* While on some desktop G3s, we turn it back on */
2868 if (macio_chips[0].of_node && macio_chips[0].type == macio_heathrow
2869 && (pmac_mb.model_id == PMAC_TYPE_GOSSAMER ||
2870 pmac_mb.model_id == PMAC_TYPE_SILK)) {
2871 struct macio_chip *macio = &macio_chips[0];
2872 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE);
2873 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_POWER_N);
2874 }
2875
2876 /* Some machine models need the clock chip to be properly setup for
2877 * clock spreading now. This should be a platform function but we
2878 * don't do these at the moment
2879 */
2880 pmac_tweak_clock_spreading(1);
2881
2882#endif /* CONFIG_POWER4 */
2883
2884 /* On all machines, switch modem & serial ports off */
2885 np = find_devices("ch-a");
2886 while(np) {
2887 initial_serial_shutdown(np);
2888 np = np->next;
2889 }
2890 np = find_devices("ch-b");
2891 while(np) {
2892 initial_serial_shutdown(np);
2893 np = np->next;
2894 }
2895}
2896
2897void __init
2898pmac_feature_init(void)
2899{
2900 /* Detect the UniNorth memory controller */
2901 probe_uninorth();
2902
2903 /* Probe mac-io controllers */
2904 if (probe_macios()) {
2905 printk(KERN_WARNING "No mac-io chip found\n");
2906 return;
2907 }
2908
2909 /* Setup low-level i2c stuffs */
2910 pmac_init_low_i2c();
2911
2912 /* Probe machine type */
2913 if (probe_motherboard())
2914 printk(KERN_WARNING "Unknown PowerMac !\n");
2915
2916 /* Set some initial features (turn off some chips that will
2917 * be later turned on)
2918 */
2919 set_initial_features();
2920}
2921
2922int __init pmac_feature_late_init(void)
2923{
2924#if 0
2925 struct device_node *np;
2926
2927 /* Request some resources late */
2928 if (uninorth_node)
2929 request_OF_resource(uninorth_node, 0, NULL);
2930 np = find_devices("hammerhead");
2931 if (np)
2932 request_OF_resource(np, 0, NULL);
2933 np = find_devices("interrupt-controller");
2934 if (np)
2935 request_OF_resource(np, 0, NULL);
2936#endif
2937 return 0;
2938}
2939
2940device_initcall(pmac_feature_late_init);
2941
2942#if 0
2943static void dump_HT_speeds(char *name, u32 cfg, u32 frq)
2944{
2945 int freqs[16] = { 200,300,400,500,600,800,1000,0,0,0,0,0,0,0,0,0 };
2946 int bits[8] = { 8,16,0,32,2,4,0,0 };
2947 int freq = (frq >> 8) & 0xf;
2948
2949 if (freqs[freq] == 0)
2950 printk("%s: Unknown HT link frequency %x\n", name, freq);
2951 else
2952 printk("%s: %d MHz on main link, (%d in / %d out) bits width\n",
2953 name, freqs[freq],
2954 bits[(cfg >> 28) & 0x7], bits[(cfg >> 24) & 0x7]);
2955}
2956
2957void __init pmac_check_ht_link(void)
2958{
2959#if 0 /* Disabled for now */
2960 u32 ufreq, freq, ucfg, cfg;
2961 struct device_node *pcix_node;
2962 u8 px_bus, px_devfn;
2963 struct pci_controller *px_hose;
2964
2965 (void)in_be32(u3_ht + U3_HT_LINK_COMMAND);
2966 ucfg = cfg = in_be32(u3_ht + U3_HT_LINK_CONFIG);
2967 ufreq = freq = in_be32(u3_ht + U3_HT_LINK_FREQ);
2968 dump_HT_speeds("U3 HyperTransport", cfg, freq);
2969
2970 pcix_node = of_find_compatible_node(NULL, "pci", "pci-x");
2971 if (pcix_node == NULL) {
2972 printk("No PCI-X bridge found\n");
2973 return;
2974 }
2975 if (pci_device_from_OF_node(pcix_node, &px_bus, &px_devfn) != 0) {
2976 printk("PCI-X bridge found but not matched to pci\n");
2977 return;
2978 }
2979 px_hose = pci_find_hose_for_OF_device(pcix_node);
2980 if (px_hose == NULL) {
2981 printk("PCI-X bridge found but not matched to host\n");
2982 return;
2983 }
2984 early_read_config_dword(px_hose, px_bus, px_devfn, 0xc4, &cfg);
2985 early_read_config_dword(px_hose, px_bus, px_devfn, 0xcc, &freq);
2986 dump_HT_speeds("PCI-X HT Uplink", cfg, freq);
2987 early_read_config_dword(px_hose, px_bus, px_devfn, 0xc8, &cfg);
2988 early_read_config_dword(px_hose, px_bus, px_devfn, 0xd0, &freq);
2989 dump_HT_speeds("PCI-X HT Downlink", cfg, freq);
2990#endif
2991}
2992
2993#endif /* CONFIG_POWER4 */
2994
2995/*
2996 * Early video resume hook
2997 */
2998
2999static void (*pmac_early_vresume_proc)(void *data);
3000static void *pmac_early_vresume_data;
3001
3002void pmac_set_early_video_resume(void (*proc)(void *data), void *data)
3003{
3004 if (_machine != _MACH_Pmac)
3005 return;
3006 preempt_disable();
3007 pmac_early_vresume_proc = proc;
3008 pmac_early_vresume_data = data;
3009 preempt_enable();
3010}
3011EXPORT_SYMBOL(pmac_set_early_video_resume);
3012
3013void pmac_call_early_video_resume(void)
3014{
3015 if (pmac_early_vresume_proc)
3016 pmac_early_vresume_proc(pmac_early_vresume_data);
3017}
3018
3019/*
3020 * AGP related suspend/resume code
3021 */
3022
3023static struct pci_dev *pmac_agp_bridge;
3024static int (*pmac_agp_suspend)(struct pci_dev *bridge);
3025static int (*pmac_agp_resume)(struct pci_dev *bridge);
3026
3027void pmac_register_agp_pm(struct pci_dev *bridge,
3028 int (*suspend)(struct pci_dev *bridge),
3029 int (*resume)(struct pci_dev *bridge))
3030{
3031 if (suspend || resume) {
3032 pmac_agp_bridge = bridge;
3033 pmac_agp_suspend = suspend;
3034 pmac_agp_resume = resume;
3035 return;
3036 }
3037 if (bridge != pmac_agp_bridge)
3038 return;
3039 pmac_agp_suspend = pmac_agp_resume = NULL;
3040 return;
3041}
3042EXPORT_SYMBOL(pmac_register_agp_pm);
3043
3044void pmac_suspend_agp_for_card(struct pci_dev *dev)
3045{
3046 if (pmac_agp_bridge == NULL || pmac_agp_suspend == NULL)
3047 return;
3048 if (pmac_agp_bridge->bus != dev->bus)
3049 return;
3050 pmac_agp_suspend(pmac_agp_bridge);
3051}
3052EXPORT_SYMBOL(pmac_suspend_agp_for_card);
3053
3054void pmac_resume_agp_for_card(struct pci_dev *dev)
3055{
3056 if (pmac_agp_bridge == NULL || pmac_agp_resume == NULL)
3057 return;
3058 if (pmac_agp_bridge->bus != dev->bus)
3059 return;
3060 pmac_agp_resume(pmac_agp_bridge);
3061}
3062EXPORT_SYMBOL(pmac_resume_agp_for_card);
diff --git a/arch/powerpc/platforms/powermac/pmac_low_i2c.c b/arch/powerpc/platforms/powermac/pmac_low_i2c.c
new file mode 100644
index 000000000000..f3f39e8e337a
--- /dev/null
+++ b/arch/powerpc/platforms/powermac/pmac_low_i2c.c
@@ -0,0 +1,523 @@
1/*
2 * arch/ppc/platforms/pmac_low_i2c.c
3 *
4 * Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * This file contains some low-level i2c access routines that
12 * need to be used by various bits of the PowerMac platform code
13 * at times where the real asynchronous & interrupt driven driver
14 * cannot be used. The API borrows some semantics from the darwin
15 * driver in order to ease the implementation of the platform
16 * properties parser
17 */
18
19#undef DEBUG
20
21#include <linux/config.h>
22#include <linux/types.h>
23#include <linux/sched.h>
24#include <linux/init.h>
25#include <linux/module.h>
26#include <linux/adb.h>
27#include <linux/pmu.h>
28#include <asm/keylargo.h>
29#include <asm/uninorth.h>
30#include <asm/io.h>
31#include <asm/prom.h>
32#include <asm/machdep.h>
33#include <asm/pmac_low_i2c.h>
34
35#define MAX_LOW_I2C_HOST 4
36
37#ifdef DEBUG
38#define DBG(x...) do {\
39 printk(KERN_DEBUG "KW:" x); \
40 } while(0)
41#else
42#define DBG(x...)
43#endif
44
45struct low_i2c_host;
46
47typedef int (*low_i2c_func_t)(struct low_i2c_host *host, u8 addr, u8 sub, u8 *data, int len);
48
49struct low_i2c_host
50{
51 struct device_node *np; /* OF device node */
52 struct semaphore mutex; /* Access mutex for use by i2c-keywest */
53 low_i2c_func_t func; /* Access function */
54 unsigned int is_open : 1; /* Poor man's access control */
55 int mode; /* Current mode */
56 int channel; /* Current channel */
57 int num_channels; /* Number of channels */
58 void __iomem *base; /* For keywest-i2c, base address */
59 int bsteps; /* And register stepping */
60 int speed; /* And speed */
61};
62
63static struct low_i2c_host low_i2c_hosts[MAX_LOW_I2C_HOST];
64
65/* No locking is necessary on allocation, we are running way before
66 * anything can race with us
67 */
68static struct low_i2c_host *find_low_i2c_host(struct device_node *np)
69{
70 int i;
71
72 for (i = 0; i < MAX_LOW_I2C_HOST; i++)
73 if (low_i2c_hosts[i].np == np)
74 return &low_i2c_hosts[i];
75 return NULL;
76}
77
78/*
79 *
80 * i2c-keywest implementation (UniNorth, U2, U3, Keylargo's)
81 *
82 */
83
84/*
85 * Keywest i2c definitions borrowed from drivers/i2c/i2c-keywest.h,
86 * should be moved somewhere in include/asm-ppc/
87 */
88/* Register indices */
89typedef enum {
90 reg_mode = 0,
91 reg_control,
92 reg_status,
93 reg_isr,
94 reg_ier,
95 reg_addr,
96 reg_subaddr,
97 reg_data
98} reg_t;
99
100
101/* Mode register */
102#define KW_I2C_MODE_100KHZ 0x00
103#define KW_I2C_MODE_50KHZ 0x01
104#define KW_I2C_MODE_25KHZ 0x02
105#define KW_I2C_MODE_DUMB 0x00
106#define KW_I2C_MODE_STANDARD 0x04
107#define KW_I2C_MODE_STANDARDSUB 0x08
108#define KW_I2C_MODE_COMBINED 0x0C
109#define KW_I2C_MODE_MODE_MASK 0x0C
110#define KW_I2C_MODE_CHAN_MASK 0xF0
111
112/* Control register */
113#define KW_I2C_CTL_AAK 0x01
114#define KW_I2C_CTL_XADDR 0x02
115#define KW_I2C_CTL_STOP 0x04
116#define KW_I2C_CTL_START 0x08
117
118/* Status register */
119#define KW_I2C_STAT_BUSY 0x01
120#define KW_I2C_STAT_LAST_AAK 0x02
121#define KW_I2C_STAT_LAST_RW 0x04
122#define KW_I2C_STAT_SDA 0x08
123#define KW_I2C_STAT_SCL 0x10
124
125/* IER & ISR registers */
126#define KW_I2C_IRQ_DATA 0x01
127#define KW_I2C_IRQ_ADDR 0x02
128#define KW_I2C_IRQ_STOP 0x04
129#define KW_I2C_IRQ_START 0x08
130#define KW_I2C_IRQ_MASK 0x0F
131
132/* State machine states */
133enum {
134 state_idle,
135 state_addr,
136 state_read,
137 state_write,
138 state_stop,
139 state_dead
140};
141
142#define WRONG_STATE(name) do {\
143 printk(KERN_DEBUG "KW: wrong state. Got %s, state: %s (isr: %02x)\n", \
144 name, __kw_state_names[state], isr); \
145 } while(0)
146
147static const char *__kw_state_names[] = {
148 "state_idle",
149 "state_addr",
150 "state_read",
151 "state_write",
152 "state_stop",
153 "state_dead"
154};
155
156static inline u8 __kw_read_reg(struct low_i2c_host *host, reg_t reg)
157{
158 return readb(host->base + (((unsigned int)reg) << host->bsteps));
159}
160
161static inline void __kw_write_reg(struct low_i2c_host *host, reg_t reg, u8 val)
162{
163 writeb(val, host->base + (((unsigned)reg) << host->bsteps));
164 (void)__kw_read_reg(host, reg_subaddr);
165}
166
167#define kw_write_reg(reg, val) __kw_write_reg(host, reg, val)
168#define kw_read_reg(reg) __kw_read_reg(host, reg)
169
170
171/* Don't schedule, the g5 fan controller is too
172 * timing sensitive
173 */
174static u8 kw_wait_interrupt(struct low_i2c_host* host)
175{
176 int i, j;
177 u8 isr;
178
179 for (i = 0; i < 100000; i++) {
180 isr = kw_read_reg(reg_isr) & KW_I2C_IRQ_MASK;
181 if (isr != 0)
182 return isr;
183
184 /* This code is used with the timebase frozen, we cannot rely
185 * on udelay ! For now, just use a bogus loop
186 */
187 for (j = 1; j < 10000; j++)
188 mb();
189 }
190 return isr;
191}
192
193static int kw_handle_interrupt(struct low_i2c_host *host, int state, int rw, int *rc, u8 **data, int *len, u8 isr)
194{
195 u8 ack;
196
197 DBG("kw_handle_interrupt(%s, isr: %x)\n", __kw_state_names[state], isr);
198
199 if (isr == 0) {
200 if (state != state_stop) {
201 DBG("KW: Timeout !\n");
202 *rc = -EIO;
203 goto stop;
204 }
205 if (state == state_stop) {
206 ack = kw_read_reg(reg_status);
207 if (!(ack & KW_I2C_STAT_BUSY)) {
208 state = state_idle;
209 kw_write_reg(reg_ier, 0x00);
210 }
211 }
212 return state;
213 }
214
215 if (isr & KW_I2C_IRQ_ADDR) {
216 ack = kw_read_reg(reg_status);
217 if (state != state_addr) {
218 kw_write_reg(reg_isr, KW_I2C_IRQ_ADDR);
219 WRONG_STATE("KW_I2C_IRQ_ADDR");
220 *rc = -EIO;
221 goto stop;
222 }
223 if ((ack & KW_I2C_STAT_LAST_AAK) == 0) {
224 *rc = -ENODEV;
225 DBG("KW: NAK on address\n");
226 return state_stop;
227 } else {
228 if (rw) {
229 state = state_read;
230 if (*len > 1)
231 kw_write_reg(reg_control, KW_I2C_CTL_AAK);
232 } else {
233 state = state_write;
234 kw_write_reg(reg_data, **data);
235 (*data)++; (*len)--;
236 }
237 }
238 kw_write_reg(reg_isr, KW_I2C_IRQ_ADDR);
239 }
240
241 if (isr & KW_I2C_IRQ_DATA) {
242 if (state == state_read) {
243 **data = kw_read_reg(reg_data);
244 (*data)++; (*len)--;
245 kw_write_reg(reg_isr, KW_I2C_IRQ_DATA);
246 if ((*len) == 0)
247 state = state_stop;
248 else if ((*len) == 1)
249 kw_write_reg(reg_control, 0);
250 } else if (state == state_write) {
251 ack = kw_read_reg(reg_status);
252 if ((ack & KW_I2C_STAT_LAST_AAK) == 0) {
253 DBG("KW: nack on data write\n");
254 *rc = -EIO;
255 goto stop;
256 } else if (*len) {
257 kw_write_reg(reg_data, **data);
258 (*data)++; (*len)--;
259 } else {
260 kw_write_reg(reg_control, KW_I2C_CTL_STOP);
261 state = state_stop;
262 *rc = 0;
263 }
264 kw_write_reg(reg_isr, KW_I2C_IRQ_DATA);
265 } else {
266 kw_write_reg(reg_isr, KW_I2C_IRQ_DATA);
267 WRONG_STATE("KW_I2C_IRQ_DATA");
268 if (state != state_stop) {
269 *rc = -EIO;
270 goto stop;
271 }
272 }
273 }
274
275 if (isr & KW_I2C_IRQ_STOP) {
276 kw_write_reg(reg_isr, KW_I2C_IRQ_STOP);
277 if (state != state_stop) {
278 WRONG_STATE("KW_I2C_IRQ_STOP");
279 *rc = -EIO;
280 }
281 return state_idle;
282 }
283
284 if (isr & KW_I2C_IRQ_START)
285 kw_write_reg(reg_isr, KW_I2C_IRQ_START);
286
287 return state;
288
289 stop:
290 kw_write_reg(reg_control, KW_I2C_CTL_STOP);
291 return state_stop;
292}
293
294static int keywest_low_i2c_func(struct low_i2c_host *host, u8 addr, u8 subaddr, u8 *data, int len)
295{
296 u8 mode_reg = host->speed;
297 int state = state_addr;
298 int rc = 0;
299
300 /* Setup mode & subaddress if any */
301 switch(host->mode) {
302 case pmac_low_i2c_mode_dumb:
303 printk(KERN_ERR "low_i2c: Dumb mode not supported !\n");
304 return -EINVAL;
305 case pmac_low_i2c_mode_std:
306 mode_reg |= KW_I2C_MODE_STANDARD;
307 break;
308 case pmac_low_i2c_mode_stdsub:
309 mode_reg |= KW_I2C_MODE_STANDARDSUB;
310 break;
311 case pmac_low_i2c_mode_combined:
312 mode_reg |= KW_I2C_MODE_COMBINED;
313 break;
314 }
315
316 /* Setup channel & clear pending irqs */
317 kw_write_reg(reg_isr, kw_read_reg(reg_isr));
318 kw_write_reg(reg_mode, mode_reg | (host->channel << 4));
319 kw_write_reg(reg_status, 0);
320
321 /* Set up address and r/w bit */
322 kw_write_reg(reg_addr, addr);
323
324 /* Set up the sub address */
325 if ((mode_reg & KW_I2C_MODE_MODE_MASK) == KW_I2C_MODE_STANDARDSUB
326 || (mode_reg & KW_I2C_MODE_MODE_MASK) == KW_I2C_MODE_COMBINED)
327 kw_write_reg(reg_subaddr, subaddr);
328
329 /* Start sending address & disable interrupt*/
330 kw_write_reg(reg_ier, 0 /*KW_I2C_IRQ_MASK*/);
331 kw_write_reg(reg_control, KW_I2C_CTL_XADDR);
332
333 /* State machine, to turn into an interrupt handler */
334 while(state != state_idle) {
335 u8 isr = kw_wait_interrupt(host);
336 state = kw_handle_interrupt(host, state, addr & 1, &rc, &data, &len, isr);
337 }
338
339 return rc;
340}
341
342static void keywest_low_i2c_add(struct device_node *np)
343{
344 struct low_i2c_host *host = find_low_i2c_host(NULL);
345 u32 *psteps, *prate, steps, aoffset = 0;
346 struct device_node *parent;
347
348 if (host == NULL) {
349 printk(KERN_ERR "low_i2c: Can't allocate host for %s\n",
350 np->full_name);
351 return;
352 }
353 memset(host, 0, sizeof(*host));
354
355 init_MUTEX(&host->mutex);
356 host->np = of_node_get(np);
357 psteps = (u32 *)get_property(np, "AAPL,address-step", NULL);
358 steps = psteps ? (*psteps) : 0x10;
359 for (host->bsteps = 0; (steps & 0x01) == 0; host->bsteps++)
360 steps >>= 1;
361 parent = of_get_parent(np);
362 host->num_channels = 1;
363 if (parent && parent->name[0] == 'u') {
364 host->num_channels = 2;
365 aoffset = 3;
366 }
367 /* Select interface rate */
368 host->speed = KW_I2C_MODE_100KHZ;
369 prate = (u32 *)get_property(np, "AAPL,i2c-rate", NULL);
370 if (prate) switch(*prate) {
371 case 100:
372 host->speed = KW_I2C_MODE_100KHZ;
373 break;
374 case 50:
375 host->speed = KW_I2C_MODE_50KHZ;
376 break;
377 case 25:
378 host->speed = KW_I2C_MODE_25KHZ;
379 break;
380 }
381
382 host->mode = pmac_low_i2c_mode_std;
383 host->base = ioremap(np->addrs[0].address + aoffset,
384 np->addrs[0].size);
385 host->func = keywest_low_i2c_func;
386}
387
388/*
389 *
390 * PMU implementation
391 *
392 */
393
394
395#ifdef CONFIG_ADB_PMU
396
397static int pmu_low_i2c_func(struct low_i2c_host *host, u8 addr, u8 sub, u8 *data, int len)
398{
399 // TODO
400 return -ENODEV;
401}
402
403static void pmu_low_i2c_add(struct device_node *np)
404{
405 struct low_i2c_host *host = find_low_i2c_host(NULL);
406
407 if (host == NULL) {
408 printk(KERN_ERR "low_i2c: Can't allocate host for %s\n",
409 np->full_name);
410 return;
411 }
412 memset(host, 0, sizeof(*host));
413
414 init_MUTEX(&host->mutex);
415 host->np = of_node_get(np);
416 host->num_channels = 3;
417 host->mode = pmac_low_i2c_mode_std;
418 host->func = pmu_low_i2c_func;
419}
420
421#endif /* CONFIG_ADB_PMU */
422
423void __init pmac_init_low_i2c(void)
424{
425 struct device_node *np;
426
427 /* Probe keywest-i2c busses */
428 np = of_find_compatible_node(NULL, "i2c", "keywest-i2c");
429 while(np) {
430 keywest_low_i2c_add(np);
431 np = of_find_compatible_node(np, "i2c", "keywest-i2c");
432 }
433
434#ifdef CONFIG_ADB_PMU
435 /* Probe PMU busses */
436 np = of_find_node_by_name(NULL, "via-pmu");
437 if (np)
438 pmu_low_i2c_add(np);
439#endif /* CONFIG_ADB_PMU */
440
441 /* TODO: Add CUDA support as well */
442}
443
444int pmac_low_i2c_lock(struct device_node *np)
445{
446 struct low_i2c_host *host = find_low_i2c_host(np);
447
448 if (!host)
449 return -ENODEV;
450 down(&host->mutex);
451 return 0;
452}
453EXPORT_SYMBOL(pmac_low_i2c_lock);
454
455int pmac_low_i2c_unlock(struct device_node *np)
456{
457 struct low_i2c_host *host = find_low_i2c_host(np);
458
459 if (!host)
460 return -ENODEV;
461 up(&host->mutex);
462 return 0;
463}
464EXPORT_SYMBOL(pmac_low_i2c_unlock);
465
466
467int pmac_low_i2c_open(struct device_node *np, int channel)
468{
469 struct low_i2c_host *host = find_low_i2c_host(np);
470
471 if (!host)
472 return -ENODEV;
473
474 if (channel >= host->num_channels)
475 return -EINVAL;
476
477 down(&host->mutex);
478 host->is_open = 1;
479 host->channel = channel;
480
481 return 0;
482}
483EXPORT_SYMBOL(pmac_low_i2c_open);
484
485int pmac_low_i2c_close(struct device_node *np)
486{
487 struct low_i2c_host *host = find_low_i2c_host(np);
488
489 if (!host)
490 return -ENODEV;
491
492 host->is_open = 0;
493 up(&host->mutex);
494
495 return 0;
496}
497EXPORT_SYMBOL(pmac_low_i2c_close);
498
499int pmac_low_i2c_setmode(struct device_node *np, int mode)
500{
501 struct low_i2c_host *host = find_low_i2c_host(np);
502
503 if (!host)
504 return -ENODEV;
505 WARN_ON(!host->is_open);
506 host->mode = mode;
507
508 return 0;
509}
510EXPORT_SYMBOL(pmac_low_i2c_setmode);
511
512int pmac_low_i2c_xfer(struct device_node *np, u8 addrdir, u8 subaddr, u8 *data, int len)
513{
514 struct low_i2c_host *host = find_low_i2c_host(np);
515
516 if (!host)
517 return -ENODEV;
518 WARN_ON(!host->is_open);
519
520 return host->func(host, addrdir, subaddr, data, len);
521}
522EXPORT_SYMBOL(pmac_low_i2c_xfer);
523
diff --git a/arch/powerpc/platforms/powermac/pmac_nvram.c b/arch/powerpc/platforms/powermac/pmac_nvram.c
new file mode 100644
index 000000000000..8c9b008c7226
--- /dev/null
+++ b/arch/powerpc/platforms/powermac/pmac_nvram.c
@@ -0,0 +1,584 @@
1/*
2 * arch/ppc/platforms/pmac_nvram.c
3 *
4 * Copyright (C) 2002 Benjamin Herrenschmidt (benh@kernel.crashing.org)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * Todo: - add support for the OF persistent properties
12 */
13#include <linux/config.h>
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/stddef.h>
17#include <linux/string.h>
18#include <linux/nvram.h>
19#include <linux/init.h>
20#include <linux/slab.h>
21#include <linux/delay.h>
22#include <linux/errno.h>
23#include <linux/adb.h>
24#include <linux/pmu.h>
25#include <linux/bootmem.h>
26#include <linux/completion.h>
27#include <linux/spinlock.h>
28#include <asm/sections.h>
29#include <asm/io.h>
30#include <asm/system.h>
31#include <asm/prom.h>
32#include <asm/machdep.h>
33#include <asm/nvram.h>
34
35#define DEBUG
36
37#ifdef DEBUG
38#define DBG(x...) printk(x)
39#else
40#define DBG(x...)
41#endif
42
43#define NVRAM_SIZE 0x2000 /* 8kB of non-volatile RAM */
44
45#define CORE99_SIGNATURE 0x5a
46#define CORE99_ADLER_START 0x14
47
48/* On Core99, nvram is either a sharp, a micron or an AMD flash */
49#define SM_FLASH_STATUS_DONE 0x80
50#define SM_FLASH_STATUS_ERR 0x38
51#define SM_FLASH_CMD_ERASE_CONFIRM 0xd0
52#define SM_FLASH_CMD_ERASE_SETUP 0x20
53#define SM_FLASH_CMD_RESET 0xff
54#define SM_FLASH_CMD_WRITE_SETUP 0x40
55#define SM_FLASH_CMD_CLEAR_STATUS 0x50
56#define SM_FLASH_CMD_READ_STATUS 0x70
57
58/* CHRP NVRAM header */
59struct chrp_header {
60 u8 signature;
61 u8 cksum;
62 u16 len;
63 char name[12];
64 u8 data[0];
65};
66
67struct core99_header {
68 struct chrp_header hdr;
69 u32 adler;
70 u32 generation;
71 u32 reserved[2];
72};
73
74/*
75 * Read and write the non-volatile RAM on PowerMacs and CHRP machines.
76 */
77static int nvram_naddrs;
78static volatile unsigned char *nvram_addr;
79static volatile unsigned char *nvram_data;
80static int nvram_mult, is_core_99;
81static int core99_bank = 0;
82static int nvram_partitions[3];
83static DEFINE_SPINLOCK(nv_lock);
84
85extern int pmac_newworld;
86extern int system_running;
87
88static int (*core99_write_bank)(int bank, u8* datas);
89static int (*core99_erase_bank)(int bank);
90
91static char *nvram_image;
92
93
94static unsigned char core99_nvram_read_byte(int addr)
95{
96 if (nvram_image == NULL)
97 return 0xff;
98 return nvram_image[addr];
99}
100
101static void core99_nvram_write_byte(int addr, unsigned char val)
102{
103 if (nvram_image == NULL)
104 return;
105 nvram_image[addr] = val;
106}
107
108
109static unsigned char direct_nvram_read_byte(int addr)
110{
111 return in_8(&nvram_data[(addr & (NVRAM_SIZE - 1)) * nvram_mult]);
112}
113
114static void direct_nvram_write_byte(int addr, unsigned char val)
115{
116 out_8(&nvram_data[(addr & (NVRAM_SIZE - 1)) * nvram_mult], val);
117}
118
119
120static unsigned char indirect_nvram_read_byte(int addr)
121{
122 unsigned char val;
123 unsigned long flags;
124
125 spin_lock_irqsave(&nv_lock, flags);
126 out_8(nvram_addr, addr >> 5);
127 val = in_8(&nvram_data[(addr & 0x1f) << 4]);
128 spin_unlock_irqrestore(&nv_lock, flags);
129
130 return val;
131}
132
133static void indirect_nvram_write_byte(int addr, unsigned char val)
134{
135 unsigned long flags;
136
137 spin_lock_irqsave(&nv_lock, flags);
138 out_8(nvram_addr, addr >> 5);
139 out_8(&nvram_data[(addr & 0x1f) << 4], val);
140 spin_unlock_irqrestore(&nv_lock, flags);
141}
142
143
144#ifdef CONFIG_ADB_PMU
145
146static void pmu_nvram_complete(struct adb_request *req)
147{
148 if (req->arg)
149 complete((struct completion *)req->arg);
150}
151
152static unsigned char pmu_nvram_read_byte(int addr)
153{
154 struct adb_request req;
155 DECLARE_COMPLETION(req_complete);
156
157 req.arg = system_state == SYSTEM_RUNNING ? &req_complete : NULL;
158 if (pmu_request(&req, pmu_nvram_complete, 3, PMU_READ_NVRAM,
159 (addr >> 8) & 0xff, addr & 0xff))
160 return 0xff;
161 if (system_state == SYSTEM_RUNNING)
162 wait_for_completion(&req_complete);
163 while (!req.complete)
164 pmu_poll();
165 return req.reply[0];
166}
167
168static void pmu_nvram_write_byte(int addr, unsigned char val)
169{
170 struct adb_request req;
171 DECLARE_COMPLETION(req_complete);
172
173 req.arg = system_state == SYSTEM_RUNNING ? &req_complete : NULL;
174 if (pmu_request(&req, pmu_nvram_complete, 4, PMU_WRITE_NVRAM,
175 (addr >> 8) & 0xff, addr & 0xff, val))
176 return;
177 if (system_state == SYSTEM_RUNNING)
178 wait_for_completion(&req_complete);
179 while (!req.complete)
180 pmu_poll();
181}
182
183#endif /* CONFIG_ADB_PMU */
184
185
186static u8 chrp_checksum(struct chrp_header* hdr)
187{
188 u8 *ptr;
189 u16 sum = hdr->signature;
190 for (ptr = (u8 *)&hdr->len; ptr < hdr->data; ptr++)
191 sum += *ptr;
192 while (sum > 0xFF)
193 sum = (sum & 0xFF) + (sum>>8);
194 return sum;
195}
196
197static u32 core99_calc_adler(u8 *buffer)
198{
199 int cnt;
200 u32 low, high;
201
202 buffer += CORE99_ADLER_START;
203 low = 1;
204 high = 0;
205 for (cnt=0; cnt<(NVRAM_SIZE-CORE99_ADLER_START); cnt++) {
206 if ((cnt % 5000) == 0) {
207 high %= 65521UL;
208 high %= 65521UL;
209 }
210 low += buffer[cnt];
211 high += low;
212 }
213 low %= 65521UL;
214 high %= 65521UL;
215
216 return (high << 16) | low;
217}
218
219static u32 core99_check(u8* datas)
220{
221 struct core99_header* hdr99 = (struct core99_header*)datas;
222
223 if (hdr99->hdr.signature != CORE99_SIGNATURE) {
224 DBG("Invalid signature\n");
225 return 0;
226 }
227 if (hdr99->hdr.cksum != chrp_checksum(&hdr99->hdr)) {
228 DBG("Invalid checksum\n");
229 return 0;
230 }
231 if (hdr99->adler != core99_calc_adler(datas)) {
232 DBG("Invalid adler\n");
233 return 0;
234 }
235 return hdr99->generation;
236}
237
238static int sm_erase_bank(int bank)
239{
240 int stat, i;
241 unsigned long timeout;
242
243 u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;
244
245 DBG("nvram: Sharp/Micron Erasing bank %d...\n", bank);
246
247 out_8(base, SM_FLASH_CMD_ERASE_SETUP);
248 out_8(base, SM_FLASH_CMD_ERASE_CONFIRM);
249 timeout = 0;
250 do {
251 if (++timeout > 1000000) {
252 printk(KERN_ERR "nvram: Sharp/Miron flash erase timeout !\n");
253 break;
254 }
255 out_8(base, SM_FLASH_CMD_READ_STATUS);
256 stat = in_8(base);
257 } while (!(stat & SM_FLASH_STATUS_DONE));
258
259 out_8(base, SM_FLASH_CMD_CLEAR_STATUS);
260 out_8(base, SM_FLASH_CMD_RESET);
261
262 for (i=0; i<NVRAM_SIZE; i++)
263 if (base[i] != 0xff) {
264 printk(KERN_ERR "nvram: Sharp/Micron flash erase failed !\n");
265 return -ENXIO;
266 }
267 return 0;
268}
269
270static int sm_write_bank(int bank, u8* datas)
271{
272 int i, stat = 0;
273 unsigned long timeout;
274
275 u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;
276
277 DBG("nvram: Sharp/Micron Writing bank %d...\n", bank);
278
279 for (i=0; i<NVRAM_SIZE; i++) {
280 out_8(base+i, SM_FLASH_CMD_WRITE_SETUP);
281 udelay(1);
282 out_8(base+i, datas[i]);
283 timeout = 0;
284 do {
285 if (++timeout > 1000000) {
286 printk(KERN_ERR "nvram: Sharp/Micron flash write timeout !\n");
287 break;
288 }
289 out_8(base, SM_FLASH_CMD_READ_STATUS);
290 stat = in_8(base);
291 } while (!(stat & SM_FLASH_STATUS_DONE));
292 if (!(stat & SM_FLASH_STATUS_DONE))
293 break;
294 }
295 out_8(base, SM_FLASH_CMD_CLEAR_STATUS);
296 out_8(base, SM_FLASH_CMD_RESET);
297 for (i=0; i<NVRAM_SIZE; i++)
298 if (base[i] != datas[i]) {
299 printk(KERN_ERR "nvram: Sharp/Micron flash write failed !\n");
300 return -ENXIO;
301 }
302 return 0;
303}
304
305static int amd_erase_bank(int bank)
306{
307 int i, stat = 0;
308 unsigned long timeout;
309
310 u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;
311
312 DBG("nvram: AMD Erasing bank %d...\n", bank);
313
314 /* Unlock 1 */
315 out_8(base+0x555, 0xaa);
316 udelay(1);
317 /* Unlock 2 */
318 out_8(base+0x2aa, 0x55);
319 udelay(1);
320
321 /* Sector-Erase */
322 out_8(base+0x555, 0x80);
323 udelay(1);
324 out_8(base+0x555, 0xaa);
325 udelay(1);
326 out_8(base+0x2aa, 0x55);
327 udelay(1);
328 out_8(base, 0x30);
329 udelay(1);
330
331 timeout = 0;
332 do {
333 if (++timeout > 1000000) {
334 printk(KERN_ERR "nvram: AMD flash erase timeout !\n");
335 break;
336 }
337 stat = in_8(base) ^ in_8(base);
338 } while (stat != 0);
339
340 /* Reset */
341 out_8(base, 0xf0);
342 udelay(1);
343
344 for (i=0; i<NVRAM_SIZE; i++)
345 if (base[i] != 0xff) {
346 printk(KERN_ERR "nvram: AMD flash erase failed !\n");
347 return -ENXIO;
348 }
349 return 0;
350}
351
352static int amd_write_bank(int bank, u8* datas)
353{
354 int i, stat = 0;
355 unsigned long timeout;
356
357 u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;
358
359 DBG("nvram: AMD Writing bank %d...\n", bank);
360
361 for (i=0; i<NVRAM_SIZE; i++) {
362 /* Unlock 1 */
363 out_8(base+0x555, 0xaa);
364 udelay(1);
365 /* Unlock 2 */
366 out_8(base+0x2aa, 0x55);
367 udelay(1);
368
369 /* Write single word */
370 out_8(base+0x555, 0xa0);
371 udelay(1);
372 out_8(base+i, datas[i]);
373
374 timeout = 0;
375 do {
376 if (++timeout > 1000000) {
377 printk(KERN_ERR "nvram: AMD flash write timeout !\n");
378 break;
379 }
380 stat = in_8(base) ^ in_8(base);
381 } while (stat != 0);
382 if (stat != 0)
383 break;
384 }
385
386 /* Reset */
387 out_8(base, 0xf0);
388 udelay(1);
389
390 for (i=0; i<NVRAM_SIZE; i++)
391 if (base[i] != datas[i]) {
392 printk(KERN_ERR "nvram: AMD flash write failed !\n");
393 return -ENXIO;
394 }
395 return 0;
396}
397
398static void __init lookup_partitions(void)
399{
400 u8 buffer[17];
401 int i, offset;
402 struct chrp_header* hdr;
403
404 if (pmac_newworld) {
405 nvram_partitions[pmac_nvram_OF] = -1;
406 nvram_partitions[pmac_nvram_XPRAM] = -1;
407 nvram_partitions[pmac_nvram_NR] = -1;
408 hdr = (struct chrp_header *)buffer;
409
410 offset = 0;
411 buffer[16] = 0;
412 do {
413 for (i=0;i<16;i++)
414 buffer[i] = nvram_read_byte(offset+i);
415 if (!strcmp(hdr->name, "common"))
416 nvram_partitions[pmac_nvram_OF] = offset + 0x10;
417 if (!strcmp(hdr->name, "APL,MacOS75")) {
418 nvram_partitions[pmac_nvram_XPRAM] = offset + 0x10;
419 nvram_partitions[pmac_nvram_NR] = offset + 0x110;
420 }
421 offset += (hdr->len * 0x10);
422 } while(offset < NVRAM_SIZE);
423 } else {
424 nvram_partitions[pmac_nvram_OF] = 0x1800;
425 nvram_partitions[pmac_nvram_XPRAM] = 0x1300;
426 nvram_partitions[pmac_nvram_NR] = 0x1400;
427 }
428 DBG("nvram: OF partition at 0x%x\n", nvram_partitions[pmac_nvram_OF]);
429 DBG("nvram: XP partition at 0x%x\n", nvram_partitions[pmac_nvram_XPRAM]);
430 DBG("nvram: NR partition at 0x%x\n", nvram_partitions[pmac_nvram_NR]);
431}
432
433static void core99_nvram_sync(void)
434{
435 struct core99_header* hdr99;
436 unsigned long flags;
437
438 if (!is_core_99 || !nvram_data || !nvram_image)
439 return;
440
441 spin_lock_irqsave(&nv_lock, flags);
442 if (!memcmp(nvram_image, (u8*)nvram_data + core99_bank*NVRAM_SIZE,
443 NVRAM_SIZE))
444 goto bail;
445
446 DBG("Updating nvram...\n");
447
448 hdr99 = (struct core99_header*)nvram_image;
449 hdr99->generation++;
450 hdr99->hdr.signature = CORE99_SIGNATURE;
451 hdr99->hdr.cksum = chrp_checksum(&hdr99->hdr);
452 hdr99->adler = core99_calc_adler(nvram_image);
453 core99_bank = core99_bank ? 0 : 1;
454 if (core99_erase_bank)
455 if (core99_erase_bank(core99_bank)) {
456 printk("nvram: Error erasing bank %d\n", core99_bank);
457 goto bail;
458 }
459 if (core99_write_bank)
460 if (core99_write_bank(core99_bank, nvram_image))
461 printk("nvram: Error writing bank %d\n", core99_bank);
462 bail:
463 spin_unlock_irqrestore(&nv_lock, flags);
464
465#ifdef DEBUG
466 mdelay(2000);
467#endif
468}
469
470void __init pmac_nvram_init(void)
471{
472 struct device_node *dp;
473
474 nvram_naddrs = 0;
475
476 dp = find_devices("nvram");
477 if (dp == NULL) {
478 printk(KERN_ERR "Can't find NVRAM device\n");
479 return;
480 }
481 nvram_naddrs = dp->n_addrs;
482 is_core_99 = device_is_compatible(dp, "nvram,flash");
483 if (is_core_99) {
484 int i;
485 u32 gen_bank0, gen_bank1;
486
487 if (nvram_naddrs < 1) {
488 printk(KERN_ERR "nvram: no address\n");
489 return;
490 }
491 nvram_image = alloc_bootmem(NVRAM_SIZE);
492 if (nvram_image == NULL) {
493 printk(KERN_ERR "nvram: can't allocate ram image\n");
494 return;
495 }
496 nvram_data = ioremap(dp->addrs[0].address, NVRAM_SIZE*2);
497 nvram_naddrs = 1; /* Make sure we get the correct case */
498
499 DBG("nvram: Checking bank 0...\n");
500
501 gen_bank0 = core99_check((u8 *)nvram_data);
502 gen_bank1 = core99_check((u8 *)nvram_data + NVRAM_SIZE);
503 core99_bank = (gen_bank0 < gen_bank1) ? 1 : 0;
504
505 DBG("nvram: gen0=%d, gen1=%d\n", gen_bank0, gen_bank1);
506 DBG("nvram: Active bank is: %d\n", core99_bank);
507
508 for (i=0; i<NVRAM_SIZE; i++)
509 nvram_image[i] = nvram_data[i + core99_bank*NVRAM_SIZE];
510
511 ppc_md.nvram_read_val = core99_nvram_read_byte;
512 ppc_md.nvram_write_val = core99_nvram_write_byte;
513 ppc_md.nvram_sync = core99_nvram_sync;
514 /*
515 * Maybe we could be smarter here though making an exclusive list
516 * of known flash chips is a bit nasty as older OF didn't provide us
517 * with a useful "compatible" entry. A solution would be to really
518 * identify the chip using flash id commands and base ourselves on
519 * a list of known chips IDs
520 */
521 if (device_is_compatible(dp, "amd-0137")) {
522 core99_erase_bank = amd_erase_bank;
523 core99_write_bank = amd_write_bank;
524 } else {
525 core99_erase_bank = sm_erase_bank;
526 core99_write_bank = sm_write_bank;
527 }
528 } else if (_machine == _MACH_chrp && nvram_naddrs == 1) {
529 nvram_data = ioremap(dp->addrs[0].address + isa_mem_base,
530 dp->addrs[0].size);
531 nvram_mult = 1;
532 ppc_md.nvram_read_val = direct_nvram_read_byte;
533 ppc_md.nvram_write_val = direct_nvram_write_byte;
534 } else if (nvram_naddrs == 1) {
535 nvram_data = ioremap(dp->addrs[0].address, dp->addrs[0].size);
536 nvram_mult = (dp->addrs[0].size + NVRAM_SIZE - 1) / NVRAM_SIZE;
537 ppc_md.nvram_read_val = direct_nvram_read_byte;
538 ppc_md.nvram_write_val = direct_nvram_write_byte;
539 } else if (nvram_naddrs == 2) {
540 nvram_addr = ioremap(dp->addrs[0].address, dp->addrs[0].size);
541 nvram_data = ioremap(dp->addrs[1].address, dp->addrs[1].size);
542 ppc_md.nvram_read_val = indirect_nvram_read_byte;
543 ppc_md.nvram_write_val = indirect_nvram_write_byte;
544 } else if (nvram_naddrs == 0 && sys_ctrler == SYS_CTRLER_PMU) {
545#ifdef CONFIG_ADB_PMU
546 nvram_naddrs = -1;
547 ppc_md.nvram_read_val = pmu_nvram_read_byte;
548 ppc_md.nvram_write_val = pmu_nvram_write_byte;
549#endif /* CONFIG_ADB_PMU */
550 } else {
551 printk(KERN_ERR "Don't know how to access NVRAM with %d addresses\n",
552 nvram_naddrs);
553 }
554 lookup_partitions();
555}
556
557int pmac_get_partition(int partition)
558{
559 return nvram_partitions[partition];
560}
561
562u8 pmac_xpram_read(int xpaddr)
563{
564 int offset = nvram_partitions[pmac_nvram_XPRAM];
565
566 if (offset < 0)
567 return 0xff;
568
569 return ppc_md.nvram_read_val(xpaddr + offset);
570}
571
572void pmac_xpram_write(int xpaddr, u8 data)
573{
574 int offset = nvram_partitions[pmac_nvram_XPRAM];
575
576 if (offset < 0)
577 return;
578
579 ppc_md.nvram_write_val(xpaddr + offset, data);
580}
581
582EXPORT_SYMBOL(pmac_get_partition);
583EXPORT_SYMBOL(pmac_xpram_read);
584EXPORT_SYMBOL(pmac_xpram_write);
diff --git a/arch/powerpc/platforms/powermac/pmac_pci.c b/arch/powerpc/platforms/powermac/pmac_pci.c
new file mode 100644
index 000000000000..40bcd3e55afb
--- /dev/null
+++ b/arch/powerpc/platforms/powermac/pmac_pci.c
@@ -0,0 +1,1341 @@
1/*
2 * Support for PCI bridges found on Power Macintoshes.
3 * At present the "bandit" and "chaos" bridges are supported.
4 * Fortunately you access configuration space in the same
5 * way with either bridge.
6 *
7 * Copyright (C) 2003 Benjamin Herrenschmuidt (benh@kernel.crashing.org)
8 * Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 */
15
16#include <linux/kernel.h>
17#include <linux/pci.h>
18#include <linux/delay.h>
19#include <linux/string.h>
20#include <linux/init.h>
21#include <linux/bootmem.h>
22
23#include <asm/sections.h>
24#include <asm/io.h>
25#include <asm/prom.h>
26#include <asm/pci-bridge.h>
27#include <asm/machdep.h>
28#include <asm/pmac_feature.h>
29
30#undef DEBUG
31
32#ifdef DEBUG
33#define DBG(x...) printk(x)
34#else
35#define DBG(x...)
36#endif
37
38static int add_bridge(struct device_node *dev);
39extern void pmac_check_ht_link(void);
40
41/* XXX Could be per-controller, but I don't think we risk anything by
42 * assuming we won't have both UniNorth and Bandit */
43static int has_uninorth;
44#ifdef CONFIG_POWER4
45static struct pci_controller *u3_agp;
46#endif /* CONFIG_POWER4 */
47
48extern u8 pci_cache_line_size;
49extern int pcibios_assign_bus_offset;
50
51struct device_node *k2_skiplist[2];
52
53/*
54 * Magic constants for enabling cache coherency in the bandit/PSX bridge.
55 */
56#define BANDIT_DEVID_2 8
57#define BANDIT_REVID 3
58
59#define BANDIT_DEVNUM 11
60#define BANDIT_MAGIC 0x50
61#define BANDIT_COHERENT 0x40
62
63static int __init fixup_one_level_bus_range(struct device_node *node, int higher)
64{
65 for (; node != 0;node = node->sibling) {
66 int * bus_range;
67 unsigned int *class_code;
68 int len;
69
70 /* For PCI<->PCI bridges or CardBus bridges, we go down */
71 class_code = (unsigned int *) get_property(node, "class-code", NULL);
72 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
73 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
74 continue;
75 bus_range = (int *) get_property(node, "bus-range", &len);
76 if (bus_range != NULL && len > 2 * sizeof(int)) {
77 if (bus_range[1] > higher)
78 higher = bus_range[1];
79 }
80 higher = fixup_one_level_bus_range(node->child, higher);
81 }
82 return higher;
83}
84
85/* This routine fixes the "bus-range" property of all bridges in the
86 * system since they tend to have their "last" member wrong on macs
87 *
88 * Note that the bus numbers manipulated here are OF bus numbers, they
89 * are not Linux bus numbers.
90 */
91static void __init fixup_bus_range(struct device_node *bridge)
92{
93 int * bus_range;
94 int len;
95
96 /* Lookup the "bus-range" property for the hose */
97 bus_range = (int *) get_property(bridge, "bus-range", &len);
98 if (bus_range == NULL || len < 2 * sizeof(int)) {
99 printk(KERN_WARNING "Can't get bus-range for %s\n",
100 bridge->full_name);
101 return;
102 }
103 bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]);
104}
105
106/*
107 * Apple MacRISC (U3, UniNorth, Bandit, Chaos) PCI controllers.
108 *
109 * The "Bandit" version is present in all early PCI PowerMacs,
110 * and up to the first ones using Grackle. Some machines may
111 * have 2 bandit controllers (2 PCI busses).
112 *
113 * "Chaos" is used in some "Bandit"-type machines as a bridge
114 * for the separate display bus. It is accessed the same
115 * way as bandit, but cannot be probed for devices. It therefore
116 * has its own config access functions.
117 *
118 * The "UniNorth" version is present in all Core99 machines
119 * (iBook, G4, new IMacs, and all the recent Apple machines).
120 * It contains 3 controllers in one ASIC.
121 *
122 * The U3 is the bridge used on G5 machines. It contains an
123 * AGP bus which is dealt with the old UniNorth access routines
124 * and a HyperTransport bus which uses its own set of access
125 * functions.
126 */
127
128#define MACRISC_CFA0(devfn, off) \
129 ((1 << (unsigned long)PCI_SLOT(dev_fn)) \
130 | (((unsigned long)PCI_FUNC(dev_fn)) << 8) \
131 | (((unsigned long)(off)) & 0xFCUL))
132
133#define MACRISC_CFA1(bus, devfn, off) \
134 ((((unsigned long)(bus)) << 16) \
135 |(((unsigned long)(devfn)) << 8) \
136 |(((unsigned long)(off)) & 0xFCUL) \
137 |1UL)
138
139static unsigned long macrisc_cfg_access(struct pci_controller* hose,
140 u8 bus, u8 dev_fn, u8 offset)
141{
142 unsigned int caddr;
143
144 if (bus == hose->first_busno) {
145 if (dev_fn < (11 << 3))
146 return 0;
147 caddr = MACRISC_CFA0(dev_fn, offset);
148 } else
149 caddr = MACRISC_CFA1(bus, dev_fn, offset);
150
151 /* Uninorth will return garbage if we don't read back the value ! */
152 do {
153 out_le32(hose->cfg_addr, caddr);
154 } while (in_le32(hose->cfg_addr) != caddr);
155
156 offset &= has_uninorth ? 0x07 : 0x03;
157 return ((unsigned long)hose->cfg_data) + offset;
158}
159
160static int macrisc_read_config(struct pci_bus *bus, unsigned int devfn,
161 int offset, int len, u32 *val)
162{
163 struct pci_controller *hose = bus->sysdata;
164 unsigned long addr;
165
166 addr = macrisc_cfg_access(hose, bus->number, devfn, offset);
167 if (!addr)
168 return PCIBIOS_DEVICE_NOT_FOUND;
169 /*
170 * Note: the caller has already checked that offset is
171 * suitably aligned and that len is 1, 2 or 4.
172 */
173 switch (len) {
174 case 1:
175 *val = in_8((u8 *)addr);
176 break;
177 case 2:
178 *val = in_le16((u16 *)addr);
179 break;
180 default:
181 *val = in_le32((u32 *)addr);
182 break;
183 }
184 return PCIBIOS_SUCCESSFUL;
185}
186
187static int macrisc_write_config(struct pci_bus *bus, unsigned int devfn,
188 int offset, int len, u32 val)
189{
190 struct pci_controller *hose = bus->sysdata;
191 unsigned long addr;
192
193 addr = macrisc_cfg_access(hose, bus->number, devfn, offset);
194 if (!addr)
195 return PCIBIOS_DEVICE_NOT_FOUND;
196 /*
197 * Note: the caller has already checked that offset is
198 * suitably aligned and that len is 1, 2 or 4.
199 */
200 switch (len) {
201 case 1:
202 out_8((u8 *)addr, val);
203 (void) in_8((u8 *)addr);
204 break;
205 case 2:
206 out_le16((u16 *)addr, val);
207 (void) in_le16((u16 *)addr);
208 break;
209 default:
210 out_le32((u32 *)addr, val);
211 (void) in_le32((u32 *)addr);
212 break;
213 }
214 return PCIBIOS_SUCCESSFUL;
215}
216
217static struct pci_ops macrisc_pci_ops =
218{
219 macrisc_read_config,
220 macrisc_write_config
221};
222
223/*
224 * Verifiy that a specific (bus, dev_fn) exists on chaos
225 */
226static int
227chaos_validate_dev(struct pci_bus *bus, int devfn, int offset)
228{
229 struct device_node *np;
230 u32 *vendor, *device;
231
232 np = pci_busdev_to_OF_node(bus, devfn);
233 if (np == NULL)
234 return PCIBIOS_DEVICE_NOT_FOUND;
235
236 vendor = (u32 *)get_property(np, "vendor-id", NULL);
237 device = (u32 *)get_property(np, "device-id", NULL);
238 if (vendor == NULL || device == NULL)
239 return PCIBIOS_DEVICE_NOT_FOUND;
240
241 if ((*vendor == 0x106b) && (*device == 3) && (offset >= 0x10)
242 && (offset != 0x14) && (offset != 0x18) && (offset <= 0x24))
243 return PCIBIOS_BAD_REGISTER_NUMBER;
244
245 return PCIBIOS_SUCCESSFUL;
246}
247
248static int
249chaos_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
250 int len, u32 *val)
251{
252 int result = chaos_validate_dev(bus, devfn, offset);
253 if (result == PCIBIOS_BAD_REGISTER_NUMBER)
254 *val = ~0U;
255 if (result != PCIBIOS_SUCCESSFUL)
256 return result;
257 return macrisc_read_config(bus, devfn, offset, len, val);
258}
259
260static int
261chaos_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
262 int len, u32 val)
263{
264 int result = chaos_validate_dev(bus, devfn, offset);
265 if (result != PCIBIOS_SUCCESSFUL)
266 return result;
267 return macrisc_write_config(bus, devfn, offset, len, val);
268}
269
270static struct pci_ops chaos_pci_ops =
271{
272 chaos_read_config,
273 chaos_write_config
274};
275
276#ifdef CONFIG_POWER4
277
278/*
279 * These versions of U3 HyperTransport config space access ops do not
280 * implement self-view of the HT host yet
281 */
282
283/*
284 * This function deals with some "special cases" devices.
285 *
286 * 0 -> No special case
287 * 1 -> Skip the device but act as if the access was successfull
288 * (return 0xff's on reads, eventually, cache config space
289 * accesses in a later version)
290 * -1 -> Hide the device (unsuccessful acess)
291 */
292static int u3_ht_skip_device(struct pci_controller *hose,
293 struct pci_bus *bus, unsigned int devfn)
294{
295 struct device_node *busdn, *dn;
296 int i;
297
298 /* We only allow config cycles to devices that are in OF device-tree
299 * as we are apparently having some weird things going on with some
300 * revs of K2 on recent G5s
301 */
302 if (bus->self)
303 busdn = pci_device_to_OF_node(bus->self);
304 else
305 busdn = hose->arch_data;
306 for (dn = busdn->child; dn; dn = dn->sibling)
307 if (dn->data && PCI_DN(dn)->devfn == devfn)
308 break;
309 if (dn == NULL)
310 return -1;
311
312 /*
313 * When a device in K2 is powered down, we die on config
314 * cycle accesses. Fix that here.
315 */
316 for (i=0; i<2; i++)
317 if (k2_skiplist[i] == dn)
318 return 1;
319
320 return 0;
321}
322
323#define U3_HT_CFA0(devfn, off) \
324 ((((unsigned long)devfn) << 8) | offset)
325#define U3_HT_CFA1(bus, devfn, off) \
326 (U3_HT_CFA0(devfn, off) \
327 + (((unsigned long)bus) << 16) \
328 + 0x01000000UL)
329
330static unsigned long u3_ht_cfg_access(struct pci_controller* hose,
331 u8 bus, u8 devfn, u8 offset)
332{
333 if (bus == hose->first_busno) {
334 /* For now, we don't self probe U3 HT bridge */
335 if (PCI_SLOT(devfn) == 0)
336 return 0;
337 return ((unsigned long)hose->cfg_data) + U3_HT_CFA0(devfn, offset);
338 } else
339 return ((unsigned long)hose->cfg_data) + U3_HT_CFA1(bus, devfn, offset);
340}
341
342static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
343 int offset, int len, u32 *val)
344{
345 struct pci_controller *hose = bus->sysdata;
346 unsigned long addr;
347
348 struct device_node *np = pci_busdev_to_OF_node(bus, devfn);
349 if (np == NULL)
350 return PCIBIOS_DEVICE_NOT_FOUND;
351
352 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
353 if (!addr)
354 return PCIBIOS_DEVICE_NOT_FOUND;
355
356 switch (u3_ht_skip_device(hose, bus, devfn)) {
357 case 0:
358 break;
359 case 1:
360 switch (len) {
361 case 1:
362 *val = 0xff; break;
363 case 2:
364 *val = 0xffff; break;
365 default:
366 *val = 0xfffffffful; break;
367 }
368 return PCIBIOS_SUCCESSFUL;
369 default:
370 return PCIBIOS_DEVICE_NOT_FOUND;
371 }
372
373 /*
374 * Note: the caller has already checked that offset is
375 * suitably aligned and that len is 1, 2 or 4.
376 */
377 switch (len) {
378 case 1:
379 *val = in_8((u8 *)addr);
380 break;
381 case 2:
382 *val = in_le16((u16 *)addr);
383 break;
384 default:
385 *val = in_le32((u32 *)addr);
386 break;
387 }
388 return PCIBIOS_SUCCESSFUL;
389}
390
391static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
392 int offset, int len, u32 val)
393{
394 struct pci_controller *hose = bus->sysdata;
395 unsigned long addr;
396
397 struct device_node *np = pci_busdev_to_OF_node(bus, devfn);
398 if (np == NULL)
399 return PCIBIOS_DEVICE_NOT_FOUND;
400
401 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
402 if (!addr)
403 return PCIBIOS_DEVICE_NOT_FOUND;
404
405 switch (u3_ht_skip_device(hose, bus, devfn)) {
406 case 0:
407 break;
408 case 1:
409 return PCIBIOS_SUCCESSFUL;
410 default:
411 return PCIBIOS_DEVICE_NOT_FOUND;
412 }
413
414 /*
415 * Note: the caller has already checked that offset is
416 * suitably aligned and that len is 1, 2 or 4.
417 */
418 switch (len) {
419 case 1:
420 out_8((u8 *)addr, val);
421 (void) in_8((u8 *)addr);
422 break;
423 case 2:
424 out_le16((u16 *)addr, val);
425 (void) in_le16((u16 *)addr);
426 break;
427 default:
428 out_le32((u32 *)addr, val);
429 (void) in_le32((u32 *)addr);
430 break;
431 }
432 return PCIBIOS_SUCCESSFUL;
433}
434
435static struct pci_ops u3_ht_pci_ops =
436{
437 u3_ht_read_config,
438 u3_ht_write_config
439};
440
441#endif /* CONFIG_POWER4 */
442
443/*
444 * For a bandit bridge, turn on cache coherency if necessary.
445 * N.B. we could clean this up using the hose ops directly.
446 */
447static void __init
448init_bandit(struct pci_controller *bp)
449{
450 unsigned int vendev, magic;
451 int rev;
452
453 /* read the word at offset 0 in config space for device 11 */
454 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + PCI_VENDOR_ID);
455 udelay(2);
456 vendev = in_le32(bp->cfg_data);
457 if (vendev == (PCI_DEVICE_ID_APPLE_BANDIT << 16) +
458 PCI_VENDOR_ID_APPLE) {
459 /* read the revision id */
460 out_le32(bp->cfg_addr,
461 (1UL << BANDIT_DEVNUM) + PCI_REVISION_ID);
462 udelay(2);
463 rev = in_8(bp->cfg_data);
464 if (rev != BANDIT_REVID)
465 printk(KERN_WARNING
466 "Unknown revision %d for bandit\n", rev);
467 } else if (vendev != (BANDIT_DEVID_2 << 16) + PCI_VENDOR_ID_APPLE) {
468 printk(KERN_WARNING "bandit isn't? (%x)\n", vendev);
469 return;
470 }
471
472 /* read the word at offset 0x50 */
473 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + BANDIT_MAGIC);
474 udelay(2);
475 magic = in_le32(bp->cfg_data);
476 if ((magic & BANDIT_COHERENT) != 0)
477 return;
478 magic |= BANDIT_COHERENT;
479 udelay(2);
480 out_le32(bp->cfg_data, magic);
481 printk(KERN_INFO "Cache coherency enabled for bandit/PSX\n");
482}
483
484
485/*
486 * Tweak the PCI-PCI bridge chip on the blue & white G3s.
487 */
488static void __init
489init_p2pbridge(void)
490{
491 struct device_node *p2pbridge;
492 struct pci_controller* hose;
493 u8 bus, devfn;
494 u16 val;
495
496 /* XXX it would be better here to identify the specific
497 PCI-PCI bridge chip we have. */
498 if ((p2pbridge = find_devices("pci-bridge")) == 0
499 || p2pbridge->parent == NULL
500 || strcmp(p2pbridge->parent->name, "pci") != 0)
501 return;
502 if (pci_device_from_OF_node(p2pbridge, &bus, &devfn) < 0) {
503 DBG("Can't find PCI infos for PCI<->PCI bridge\n");
504 return;
505 }
506 /* Warning: At this point, we have not yet renumbered all busses.
507 * So we must use OF walking to find out hose
508 */
509 hose = pci_find_hose_for_OF_device(p2pbridge);
510 if (!hose) {
511 DBG("Can't find hose for PCI<->PCI bridge\n");
512 return;
513 }
514 if (early_read_config_word(hose, bus, devfn,
515 PCI_BRIDGE_CONTROL, &val) < 0) {
516 printk(KERN_ERR "init_p2pbridge: couldn't read bridge control\n");
517 return;
518 }
519 val &= ~PCI_BRIDGE_CTL_MASTER_ABORT;
520 early_write_config_word(hose, bus, devfn, PCI_BRIDGE_CONTROL, val);
521}
522
523/*
524 * Some Apple desktop machines have a NEC PD720100A USB2 controller
525 * on the motherboard. Open Firmware, on these, will disable the
526 * EHCI part of it so it behaves like a pair of OHCI's. This fixup
527 * code re-enables it ;)
528 */
529static void __init
530fixup_nec_usb2(void)
531{
532 struct device_node *nec;
533
534 for (nec = NULL; (nec = of_find_node_by_name(nec, "usb")) != NULL;) {
535 struct pci_controller *hose;
536 u32 data, *prop;
537 u8 bus, devfn;
538
539 prop = (u32 *)get_property(nec, "vendor-id", NULL);
540 if (prop == NULL)
541 continue;
542 if (0x1033 != *prop)
543 continue;
544 prop = (u32 *)get_property(nec, "device-id", NULL);
545 if (prop == NULL)
546 continue;
547 if (0x0035 != *prop)
548 continue;
549 prop = (u32 *)get_property(nec, "reg", NULL);
550 if (prop == NULL)
551 continue;
552 devfn = (prop[0] >> 8) & 0xff;
553 bus = (prop[0] >> 16) & 0xff;
554 if (PCI_FUNC(devfn) != 0)
555 continue;
556 hose = pci_find_hose_for_OF_device(nec);
557 if (!hose)
558 continue;
559 early_read_config_dword(hose, bus, devfn, 0xe4, &data);
560 if (data & 1UL) {
561 printk("Found NEC PD720100A USB2 chip with disabled EHCI, fixing up...\n");
562 data &= ~1UL;
563 early_write_config_dword(hose, bus, devfn, 0xe4, data);
564 early_write_config_byte(hose, bus, devfn | 2, PCI_INTERRUPT_LINE,
565 nec->intrs[0].line);
566 }
567 }
568}
569
570void __init
571pmac_find_bridges(void)
572{
573 struct device_node *np, *root;
574 struct device_node *ht = NULL;
575
576 root = of_find_node_by_path("/");
577 if (root == NULL) {
578 printk(KERN_CRIT "pmac_find_bridges: can't find root of device tree\n");
579 return;
580 }
581 for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) {
582 if (np->name == NULL)
583 continue;
584 if (strcmp(np->name, "bandit") == 0
585 || strcmp(np->name, "chaos") == 0
586 || strcmp(np->name, "pci") == 0) {
587 if (add_bridge(np) == 0)
588 of_node_get(np);
589 }
590 if (strcmp(np->name, "ht") == 0) {
591 of_node_get(np);
592 ht = np;
593 }
594 }
595 of_node_put(root);
596
597 /* Probe HT last as it relies on the agp resources to be already
598 * setup
599 */
600 if (ht && add_bridge(ht) != 0)
601 of_node_put(ht);
602
603 init_p2pbridge();
604 fixup_nec_usb2();
605
606 /* We are still having some issues with the Xserve G4, enabling
607 * some offset between bus number and domains for now when we
608 * assign all busses should help for now
609 */
610 if (pci_assign_all_busses)
611 pcibios_assign_bus_offset = 0x10;
612
613#ifdef CONFIG_POWER4
614 /* There is something wrong with DMA on U3/HT. I haven't figured out
615 * the details yet, but if I set the cache line size to 128 bytes like
616 * it should, I'm getting memory corruption caused by devices like
617 * sungem (even without the MWI bit set, but maybe sungem doesn't
618 * care). Right now, it appears that setting up a 64 bytes line size
619 * works properly, 64 bytes beeing the max transfer size of HT, I
620 * suppose this is related the way HT/PCI are hooked together. I still
621 * need to dive into more specs though to be really sure of what's
622 * going on. --BenH.
623 *
624 * Ok, apparently, it's just that HT can't do more than 64 bytes
625 * transactions. MWI seem to be meaningless there as well, it may
626 * be worth nop'ing out pci_set_mwi too though I haven't done that
627 * yet.
628 *
629 * Note that it's a bit different for whatever is in the AGP slot.
630 * For now, I don't care, but this can become a real issue, we
631 * should probably hook pci_set_mwi anyway to make sure it sets
632 * the real cache line size in there.
633 */
634 if (machine_is_compatible("MacRISC4"))
635 pci_cache_line_size = 16; /* 64 bytes */
636
637 pmac_check_ht_link();
638#endif /* CONFIG_POWER4 */
639}
640
641#define GRACKLE_CFA(b, d, o) (0x80 | ((b) << 8) | ((d) << 16) \
642 | (((o) & ~3) << 24))
643
644#define GRACKLE_PICR1_STG 0x00000040
645#define GRACKLE_PICR1_LOOPSNOOP 0x00000010
646
647/* N.B. this is called before bridges is initialized, so we can't
648 use grackle_pcibios_{read,write}_config_dword. */
649static inline void grackle_set_stg(struct pci_controller* bp, int enable)
650{
651 unsigned int val;
652
653 out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8));
654 val = in_le32(bp->cfg_data);
655 val = enable? (val | GRACKLE_PICR1_STG) :
656 (val & ~GRACKLE_PICR1_STG);
657 out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8));
658 out_le32(bp->cfg_data, val);
659 (void)in_le32(bp->cfg_data);
660}
661
662static inline void grackle_set_loop_snoop(struct pci_controller *bp, int enable)
663{
664 unsigned int val;
665
666 out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8));
667 val = in_le32(bp->cfg_data);
668 val = enable? (val | GRACKLE_PICR1_LOOPSNOOP) :
669 (val & ~GRACKLE_PICR1_LOOPSNOOP);
670 out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8));
671 out_le32(bp->cfg_data, val);
672 (void)in_le32(bp->cfg_data);
673}
674
675static int __init
676setup_uninorth(struct pci_controller* hose, struct reg_property* addr)
677{
678 pci_assign_all_busses = 1;
679 has_uninorth = 1;
680 hose->ops = &macrisc_pci_ops;
681 hose->cfg_addr = ioremap(addr->address + 0x800000, 0x1000);
682 hose->cfg_data = ioremap(addr->address + 0xc00000, 0x1000);
683 /* We "know" that the bridge at f2000000 has the PCI slots. */
684 return addr->address == 0xf2000000;
685}
686
687static void __init
688setup_bandit(struct pci_controller* hose, struct reg_property* addr)
689{
690 hose->ops = &macrisc_pci_ops;
691 hose->cfg_addr = ioremap(addr->address + 0x800000, 0x1000);
692 hose->cfg_data = ioremap(addr->address + 0xc00000, 0x1000);
693 init_bandit(hose);
694}
695
696static void __init
697setup_chaos(struct pci_controller* hose, struct reg_property* addr)
698{
699 /* assume a `chaos' bridge */
700 hose->ops = &chaos_pci_ops;
701 hose->cfg_addr = ioremap(addr->address + 0x800000, 0x1000);
702 hose->cfg_data = ioremap(addr->address + 0xc00000, 0x1000);
703}
704
705#ifdef CONFIG_POWER4
706
707static void __init setup_u3_agp(struct pci_controller* hose)
708{
709 /* On G5, we move AGP up to high bus number so we don't need
710 * to reassign bus numbers for HT. If we ever have P2P bridges
711 * on AGP, we'll have to move pci_assign_all_busses to the
712 * pci_controller structure so we enable it for AGP and not for
713 * HT childs.
714 * We hard code the address because of the different size of
715 * the reg address cell, we shall fix that by killing struct
716 * reg_property and using some accessor functions instead
717 */
718 hose->first_busno = 0xf0;
719 hose->last_busno = 0xff;
720 has_uninorth = 1;
721 hose->ops = &macrisc_pci_ops;
722 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
723 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
724
725 u3_agp = hose;
726}
727
728static void __init setup_u3_ht(struct pci_controller* hose)
729{
730 struct device_node *np = (struct device_node *)hose->arch_data;
731 int i, cur;
732
733 hose->ops = &u3_ht_pci_ops;
734
735 /* We hard code the address because of the different size of
736 * the reg address cell, we shall fix that by killing struct
737 * reg_property and using some accessor functions instead
738 */
739 hose->cfg_data = (volatile unsigned char *)ioremap(0xf2000000, 0x02000000);
740
741 /*
742 * /ht node doesn't expose a "ranges" property, so we "remove" regions that
743 * have been allocated to AGP. So far, this version of the code doesn't assign
744 * any of the 0xfxxxxxxx "fine" memory regions to /ht.
745 * We need to fix that sooner or later by either parsing all child "ranges"
746 * properties or figuring out the U3 address space decoding logic and
747 * then read its configuration register (if any).
748 */
749 hose->io_base_phys = 0xf4000000;
750 hose->io_base_virt = ioremap(hose->io_base_phys, 0x00400000);
751 isa_io_base = (unsigned long) hose->io_base_virt;
752 hose->io_resource.name = np->full_name;
753 hose->io_resource.start = 0;
754 hose->io_resource.end = 0x003fffff;
755 hose->io_resource.flags = IORESOURCE_IO;
756 hose->pci_mem_offset = 0;
757 hose->first_busno = 0;
758 hose->last_busno = 0xef;
759 hose->mem_resources[0].name = np->full_name;
760 hose->mem_resources[0].start = 0x80000000;
761 hose->mem_resources[0].end = 0xefffffff;
762 hose->mem_resources[0].flags = IORESOURCE_MEM;
763
764 if (u3_agp == NULL) {
765 DBG("U3 has no AGP, using full resource range\n");
766 return;
767 }
768
769 /* We "remove" the AGP resources from the resources allocated to HT, that
770 * is we create "holes". However, that code does assumptions that so far
771 * happen to be true (cross fingers...), typically that resources in the
772 * AGP node are properly ordered
773 */
774 cur = 0;
775 for (i=0; i<3; i++) {
776 struct resource *res = &u3_agp->mem_resources[i];
777 if (res->flags != IORESOURCE_MEM)
778 continue;
779 /* We don't care about "fine" resources */
780 if (res->start >= 0xf0000000)
781 continue;
782 /* Check if it's just a matter of "shrinking" us in one direction */
783 if (hose->mem_resources[cur].start == res->start) {
784 DBG("U3/HT: shrink start of %d, %08lx -> %08lx\n",
785 cur, hose->mem_resources[cur].start, res->end + 1);
786 hose->mem_resources[cur].start = res->end + 1;
787 continue;
788 }
789 if (hose->mem_resources[cur].end == res->end) {
790 DBG("U3/HT: shrink end of %d, %08lx -> %08lx\n",
791 cur, hose->mem_resources[cur].end, res->start - 1);
792 hose->mem_resources[cur].end = res->start - 1;
793 continue;
794 }
795 /* No, it's not the case, we need a hole */
796 if (cur == 2) {
797 /* not enough resources to make a hole, we drop part of the range */
798 printk(KERN_WARNING "Running out of resources for /ht host !\n");
799 hose->mem_resources[cur].end = res->start - 1;
800 continue;
801 }
802 cur++;
803 DBG("U3/HT: hole, %d end at %08lx, %d start at %08lx\n",
804 cur-1, res->start - 1, cur, res->end + 1);
805 hose->mem_resources[cur].name = np->full_name;
806 hose->mem_resources[cur].flags = IORESOURCE_MEM;
807 hose->mem_resources[cur].start = res->end + 1;
808 hose->mem_resources[cur].end = hose->mem_resources[cur-1].end;
809 hose->mem_resources[cur-1].end = res->start - 1;
810 }
811}
812
813#endif /* CONFIG_POWER4 */
814
815void __init
816setup_grackle(struct pci_controller *hose)
817{
818 setup_indirect_pci(hose, 0xfec00000, 0xfee00000);
819 if (machine_is_compatible("AAPL,PowerBook1998"))
820 grackle_set_loop_snoop(hose, 1);
821#if 0 /* Disabled for now, HW problems ??? */
822 grackle_set_stg(hose, 1);
823#endif
824}
825
826static void __init pmac_process_bridge_OF_ranges(struct pci_controller *hose,
827 struct device_node *dev, int primary)
828{
829 static unsigned int static_lc_ranges[2024];
830 unsigned int *dt_ranges, *lc_ranges, *ranges, *prev;
831 unsigned int size;
832 int rlen = 0, orig_rlen;
833 int memno = 0;
834 struct resource *res;
835 int np, na = prom_n_addr_cells(dev);
836
837 np = na + 5;
838
839 /* First we try to merge ranges to fix a problem with some pmacs
840 * that can have more than 3 ranges, fortunately using contiguous
841 * addresses -- BenH
842 */
843 dt_ranges = (unsigned int *) get_property(dev, "ranges", &rlen);
844 if (!dt_ranges)
845 return;
846 /* lc_ranges = alloc_bootmem(rlen);*/
847 lc_ranges = static_lc_ranges;
848 if (!lc_ranges)
849 return; /* what can we do here ? */
850 memcpy(lc_ranges, dt_ranges, rlen);
851 orig_rlen = rlen;
852
853 /* Let's work on a copy of the "ranges" property instead of damaging
854 * the device-tree image in memory
855 */
856 ranges = lc_ranges;
857 prev = NULL;
858 while ((rlen -= np * sizeof(unsigned int)) >= 0) {
859 if (prev) {
860 if (prev[0] == ranges[0] && prev[1] == ranges[1] &&
861 (prev[2] + prev[na+4]) == ranges[2] &&
862 (prev[na+2] + prev[na+4]) == ranges[na+2]) {
863 prev[na+4] += ranges[na+4];
864 ranges[0] = 0;
865 ranges += np;
866 continue;
867 }
868 }
869 prev = ranges;
870 ranges += np;
871 }
872
873 /*
874 * The ranges property is laid out as an array of elements,
875 * each of which comprises:
876 * cells 0 - 2: a PCI address
877 * cells 3 or 3+4: a CPU physical address
878 * (size depending on dev->n_addr_cells)
879 * cells 4+5 or 5+6: the size of the range
880 */
881 ranges = lc_ranges;
882 rlen = orig_rlen;
883 while (ranges && (rlen -= np * sizeof(unsigned int)) >= 0) {
884 res = NULL;
885 size = ranges[na+4];
886 switch (ranges[0] >> 24) {
887 case 1: /* I/O space */
888 if (ranges[2] != 0)
889 break;
890 hose->io_base_phys = ranges[na+2];
891 /* limit I/O space to 16MB */
892 if (size > 0x01000000)
893 size = 0x01000000;
894 hose->io_base_virt = ioremap(ranges[na+2], size);
895 if (primary)
896 isa_io_base = (unsigned long) hose->io_base_virt;
897 res = &hose->io_resource;
898 res->flags = IORESOURCE_IO;
899 res->start = ranges[2];
900 break;
901 case 2: /* memory space */
902 memno = 0;
903 if (ranges[1] == 0 && ranges[2] == 0
904 && ranges[na+4] <= (16 << 20)) {
905 /* 1st 16MB, i.e. ISA memory area */
906#if 0
907 if (primary)
908 isa_mem_base = ranges[na+2];
909#endif
910 memno = 1;
911 }
912 while (memno < 3 && hose->mem_resources[memno].flags)
913 ++memno;
914 if (memno == 0)
915 hose->pci_mem_offset = ranges[na+2] - ranges[2];
916 if (memno < 3) {
917 res = &hose->mem_resources[memno];
918 res->flags = IORESOURCE_MEM;
919 res->start = ranges[na+2];
920 }
921 break;
922 }
923 if (res != NULL) {
924 res->name = dev->full_name;
925 res->end = res->start + size - 1;
926 res->parent = NULL;
927 res->sibling = NULL;
928 res->child = NULL;
929 }
930 ranges += np;
931 }
932}
933
934/*
935 * We assume that if we have a G3 powermac, we have one bridge called
936 * "pci" (a MPC106) and no bandit or chaos bridges, and contrariwise,
937 * if we have one or more bandit or chaos bridges, we don't have a MPC106.
938 */
939static int __init add_bridge(struct device_node *dev)
940{
941 int len;
942 struct pci_controller *hose;
943 struct reg_property *addr;
944 char* disp_name;
945 int *bus_range;
946 int primary = 1;
947
948 DBG("Adding PCI host bridge %s\n", dev->full_name);
949
950 addr = (struct reg_property *) get_property(dev, "reg", &len);
951 if (addr == NULL || len < sizeof(*addr)) {
952 printk(KERN_WARNING "Can't use %s: no address\n",
953 dev->full_name);
954 return -ENODEV;
955 }
956 bus_range = (int *) get_property(dev, "bus-range", &len);
957 if (bus_range == NULL || len < 2 * sizeof(int)) {
958 printk(KERN_WARNING "Can't get bus-range for %s, assume bus 0\n",
959 dev->full_name);
960 }
961
962 hose = pcibios_alloc_controller();
963 if (!hose)
964 return -ENOMEM;
965 hose->arch_data = dev;
966 hose->first_busno = bus_range ? bus_range[0] : 0;
967 hose->last_busno = bus_range ? bus_range[1] : 0xff;
968
969 disp_name = NULL;
970#ifdef CONFIG_POWER4
971 if (device_is_compatible(dev, "u3-agp")) {
972 setup_u3_agp(hose, addr);
973 disp_name = "U3-AGP";
974 primary = 0;
975 } else if (device_is_compatible(dev, "u3-ht")) {
976 setup_u3_ht(hose, addr);
977 disp_name = "U3-HT";
978 primary = 1;
979 } else
980#endif /* CONFIG_POWER4 */
981 if (device_is_compatible(dev, "uni-north")) {
982 primary = setup_uninorth(hose, addr);
983 disp_name = "UniNorth";
984 } else if (strcmp(dev->name, "pci") == 0) {
985 /* XXX assume this is a mpc106 (grackle) */
986 setup_grackle(hose);
987 disp_name = "Grackle (MPC106)";
988 } else if (strcmp(dev->name, "bandit") == 0) {
989 setup_bandit(hose, addr);
990 disp_name = "Bandit";
991 } else if (strcmp(dev->name, "chaos") == 0) {
992 setup_chaos(hose, addr);
993 disp_name = "Chaos";
994 primary = 0;
995 }
996 printk(KERN_INFO "Found %s PCI host bridge at 0x%08x. Firmware bus number: %d->%d\n",
997 disp_name, addr->address, hose->first_busno, hose->last_busno);
998 DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
999 hose, hose->cfg_addr, hose->cfg_data);
1000
1001 /* Interpret the "ranges" property */
1002 /* This also maps the I/O region and sets isa_io/mem_base */
1003 pci_process_bridge_OF_ranges(hose, dev, primary);
1004
1005 /* Fixup "bus-range" OF property */
1006 fixup_bus_range(dev);
1007
1008 return 0;
1009}
1010
1011static void __init
1012pcibios_fixup_OF_interrupts(void)
1013{
1014 struct pci_dev* dev = NULL;
1015
1016 /*
1017 * Open Firmware often doesn't initialize the
1018 * PCI_INTERRUPT_LINE config register properly, so we
1019 * should find the device node and apply the interrupt
1020 * obtained from the OF device-tree
1021 */
1022 for_each_pci_dev(dev) {
1023 struct device_node *node;
1024 node = pci_device_to_OF_node(dev);
1025 /* this is the node, see if it has interrupts */
1026 if (node && node->n_intrs > 0)
1027 dev->irq = node->intrs[0].line;
1028 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
1029 }
1030}
1031
1032void __init
1033pmac_pcibios_fixup(void)
1034{
1035 /* Fixup interrupts according to OF tree */
1036 pcibios_fixup_OF_interrupts();
1037}
1038
1039int
1040pmac_pci_enable_device_hook(struct pci_dev *dev, int initial)
1041{
1042 struct device_node* node;
1043 int updatecfg = 0;
1044 int uninorth_child;
1045
1046 node = pci_device_to_OF_node(dev);
1047
1048 /* We don't want to enable USB controllers absent from the OF tree
1049 * (iBook second controller)
1050 */
1051 if (dev->vendor == PCI_VENDOR_ID_APPLE
1052 && (dev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x10))
1053 && !node) {
1054 printk(KERN_INFO "Apple USB OHCI %s disabled by firmware\n",
1055 pci_name(dev));
1056 return -EINVAL;
1057 }
1058
1059 if (!node)
1060 return 0;
1061
1062 uninorth_child = node->parent &&
1063 device_is_compatible(node->parent, "uni-north");
1064
1065 /* Firewire & GMAC were disabled after PCI probe, the driver is
1066 * claiming them, we must re-enable them now.
1067 */
1068 if (uninorth_child && !strcmp(node->name, "firewire") &&
1069 (device_is_compatible(node, "pci106b,18") ||
1070 device_is_compatible(node, "pci106b,30") ||
1071 device_is_compatible(node, "pci11c1,5811"))) {
1072 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, node, 0, 1);
1073 pmac_call_feature(PMAC_FTR_1394_ENABLE, node, 0, 1);
1074 updatecfg = 1;
1075 }
1076 if (uninorth_child && !strcmp(node->name, "ethernet") &&
1077 device_is_compatible(node, "gmac")) {
1078 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, node, 0, 1);
1079 updatecfg = 1;
1080 }
1081
1082 if (updatecfg) {
1083 u16 cmd;
1084
1085 /*
1086 * Make sure PCI is correctly configured
1087 *
1088 * We use old pci_bios versions of the function since, by
1089 * default, gmac is not powered up, and so will be absent
1090 * from the kernel initial PCI lookup.
1091 *
1092 * Should be replaced by 2.4 new PCI mechanisms and really
1093 * register the device.
1094 */
1095 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1096 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
1097 pci_write_config_word(dev, PCI_COMMAND, cmd);
1098 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 16);
1099 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
1100 }
1101
1102 return 0;
1103}
1104
1105/* We power down some devices after they have been probed. They'll
1106 * be powered back on later on
1107 */
1108void __init
1109pmac_pcibios_after_init(void)
1110{
1111 struct device_node* nd;
1112
1113#ifdef CONFIG_BLK_DEV_IDE
1114 struct pci_dev *dev = NULL;
1115
1116 /* OF fails to initialize IDE controllers on macs
1117 * (and maybe other machines)
1118 *
1119 * Ideally, this should be moved to the IDE layer, but we need
1120 * to check specifically with Andre Hedrick how to do it cleanly
1121 * since the common IDE code seem to care about the fact that the
1122 * BIOS may have disabled a controller.
1123 *
1124 * -- BenH
1125 */
1126 for_each_pci_dev(dev) {
1127 if ((dev->class >> 16) == PCI_BASE_CLASS_STORAGE)
1128 pci_enable_device(dev);
1129 }
1130#endif /* CONFIG_BLK_DEV_IDE */
1131
1132 nd = find_devices("firewire");
1133 while (nd) {
1134 if (nd->parent && (device_is_compatible(nd, "pci106b,18") ||
1135 device_is_compatible(nd, "pci106b,30") ||
1136 device_is_compatible(nd, "pci11c1,5811"))
1137 && device_is_compatible(nd->parent, "uni-north")) {
1138 pmac_call_feature(PMAC_FTR_1394_ENABLE, nd, 0, 0);
1139 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, nd, 0, 0);
1140 }
1141 nd = nd->next;
1142 }
1143 nd = find_devices("ethernet");
1144 while (nd) {
1145 if (nd->parent && device_is_compatible(nd, "gmac")
1146 && device_is_compatible(nd->parent, "uni-north"))
1147 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, nd, 0, 0);
1148 nd = nd->next;
1149 }
1150}
1151
1152#ifdef CONFIG_PPC64
1153static void __init pmac_fixup_phb_resources(void)
1154{
1155 struct pci_controller *hose, *tmp;
1156
1157 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1158 unsigned long offset = (unsigned long)hose->io_base_virt - pci_io_base;
1159 hose->io_resource.start += offset;
1160 hose->io_resource.end += offset;
1161 printk(KERN_INFO "PCI Host %d, io start: %lx; io end: %lx\n",
1162 hose->global_number,
1163 hose->io_resource.start, hose->io_resource.end);
1164 }
1165}
1166
1167void __init pmac_pci_init(void)
1168{
1169 struct device_node *np, *root;
1170 struct device_node *ht = NULL;
1171
1172 /* Probe root PCI hosts, that is on U3 the AGP host and the
1173 * HyperTransport host. That one is actually "kept" around
1174 * and actually added last as it's resource management relies
1175 * on the AGP resources to have been setup first
1176 */
1177 root = of_find_node_by_path("/");
1178 if (root == NULL) {
1179 printk(KERN_CRIT "pmac_find_bridges: can't find root of device tree\n");
1180 return;
1181 }
1182 for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) {
1183 if (np->name == NULL)
1184 continue;
1185 if (strcmp(np->name, "pci") == 0) {
1186 if (add_bridge(np) == 0)
1187 of_node_get(np);
1188 }
1189 if (strcmp(np->name, "ht") == 0) {
1190 of_node_get(np);
1191 ht = np;
1192 }
1193 }
1194 of_node_put(root);
1195
1196 /* Now setup the HyperTransport host if we found any
1197 */
1198 if (ht && add_bridge(ht) != 0)
1199 of_node_put(ht);
1200
1201 /* Fixup the IO resources on our host bridges as the common code
1202 * does it only for childs of the host bridges
1203 */
1204 pmac_fixup_phb_resources();
1205
1206 /* Setup the linkage between OF nodes and PHBs */
1207 pci_devs_phb_init();
1208
1209 /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We
1210 * assume there is no P2P bridge on the AGP bus, which should be a
1211 * safe assumptions hopefully.
1212 */
1213 if (u3_agp) {
1214 struct device_node *np = u3_agp->arch_data;
1215 PCI_DN(np)->busno = 0xf0;
1216 for (np = np->child; np; np = np->sibling)
1217 PCI_DN(np)->busno = 0xf0;
1218 }
1219
1220 pmac_check_ht_link();
1221
1222 /* Tell pci.c to not use the common resource allocation mecanism */
1223 pci_probe_only = 1;
1224
1225 /* Allow all IO */
1226 io_page_mask = -1;
1227}
1228#endif
1229
1230#ifdef CONFIG_PPC32
1231void pmac_pci_fixup_cardbus(struct pci_dev* dev)
1232{
1233 if (_machine != _MACH_Pmac)
1234 return;
1235 /*
1236 * Fix the interrupt routing on the various cardbus bridges
1237 * used on powerbooks
1238 */
1239 if (dev->vendor != PCI_VENDOR_ID_TI)
1240 return;
1241 if (dev->device == PCI_DEVICE_ID_TI_1130 ||
1242 dev->device == PCI_DEVICE_ID_TI_1131) {
1243 u8 val;
1244 /* Enable PCI interrupt */
1245 if (pci_read_config_byte(dev, 0x91, &val) == 0)
1246 pci_write_config_byte(dev, 0x91, val | 0x30);
1247 /* Disable ISA interrupt mode */
1248 if (pci_read_config_byte(dev, 0x92, &val) == 0)
1249 pci_write_config_byte(dev, 0x92, val & ~0x06);
1250 }
1251 if (dev->device == PCI_DEVICE_ID_TI_1210 ||
1252 dev->device == PCI_DEVICE_ID_TI_1211 ||
1253 dev->device == PCI_DEVICE_ID_TI_1410 ||
1254 dev->device == PCI_DEVICE_ID_TI_1510) {
1255 u8 val;
1256 /* 0x8c == TI122X_IRQMUX, 2 says to route the INTA
1257 signal out the MFUNC0 pin */
1258 if (pci_read_config_byte(dev, 0x8c, &val) == 0)
1259 pci_write_config_byte(dev, 0x8c, (val & ~0x0f) | 2);
1260 /* Disable ISA interrupt mode */
1261 if (pci_read_config_byte(dev, 0x92, &val) == 0)
1262 pci_write_config_byte(dev, 0x92, val & ~0x06);
1263 }
1264}
1265
1266DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_ANY_ID, pmac_pci_fixup_cardbus);
1267
1268void pmac_pci_fixup_pciata(struct pci_dev* dev)
1269{
1270 u8 progif = 0;
1271
1272 /*
1273 * On PowerMacs, we try to switch any PCI ATA controller to
1274 * fully native mode
1275 */
1276 if (_machine != _MACH_Pmac)
1277 return;
1278 /* Some controllers don't have the class IDE */
1279 if (dev->vendor == PCI_VENDOR_ID_PROMISE)
1280 switch(dev->device) {
1281 case PCI_DEVICE_ID_PROMISE_20246:
1282 case PCI_DEVICE_ID_PROMISE_20262:
1283 case PCI_DEVICE_ID_PROMISE_20263:
1284 case PCI_DEVICE_ID_PROMISE_20265:
1285 case PCI_DEVICE_ID_PROMISE_20267:
1286 case PCI_DEVICE_ID_PROMISE_20268:
1287 case PCI_DEVICE_ID_PROMISE_20269:
1288 case PCI_DEVICE_ID_PROMISE_20270:
1289 case PCI_DEVICE_ID_PROMISE_20271:
1290 case PCI_DEVICE_ID_PROMISE_20275:
1291 case PCI_DEVICE_ID_PROMISE_20276:
1292 case PCI_DEVICE_ID_PROMISE_20277:
1293 goto good;
1294 }
1295 /* Others, check PCI class */
1296 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
1297 return;
1298 good:
1299 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1300 if ((progif & 5) != 5) {
1301 printk(KERN_INFO "Forcing PCI IDE into native mode: %s\n", pci_name(dev));
1302 (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5);
1303 if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) ||
1304 (progif & 5) != 5)
1305 printk(KERN_ERR "Rewrite of PROGIF failed !\n");
1306 }
1307}
1308DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pmac_pci_fixup_pciata);
1309#endif
1310
1311/*
1312 * Disable second function on K2-SATA, it's broken
1313 * and disable IO BARs on first one
1314 */
1315static void fixup_k2_sata(struct pci_dev* dev)
1316{
1317 int i;
1318 u16 cmd;
1319
1320 if (PCI_FUNC(dev->devfn) > 0) {
1321 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1322 cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1323 pci_write_config_word(dev, PCI_COMMAND, cmd);
1324 for (i = 0; i < 6; i++) {
1325 dev->resource[i].start = dev->resource[i].end = 0;
1326 dev->resource[i].flags = 0;
1327 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 0);
1328 }
1329 } else {
1330 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1331 cmd &= ~PCI_COMMAND_IO;
1332 pci_write_config_word(dev, PCI_COMMAND, cmd);
1333 for (i = 0; i < 5; i++) {
1334 dev->resource[i].start = dev->resource[i].end = 0;
1335 dev->resource[i].flags = 0;
1336 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 0);
1337 }
1338 }
1339}
1340DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 0x0240, fixup_k2_sata);
1341
diff --git a/arch/powerpc/platforms/powermac/pmac_pic.c b/arch/powerpc/platforms/powermac/pmac_pic.c
new file mode 100644
index 000000000000..bf3e1899a4cc
--- /dev/null
+++ b/arch/powerpc/platforms/powermac/pmac_pic.c
@@ -0,0 +1,655 @@
1/*
2 * Support for the interrupt controllers found on Power Macintosh,
3 * currently Apple's "Grand Central" interrupt controller in all
4 * it's incarnations. OpenPIC support used on newer machines is
5 * in a separate file
6 *
7 * Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
8 *
9 * Maintained by Benjamin Herrenschmidt (benh@kernel.crashing.org)
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
15 *
16 */
17
18#include <linux/config.h>
19#include <linux/stddef.h>
20#include <linux/init.h>
21#include <linux/sched.h>
22#include <linux/signal.h>
23#include <linux/pci.h>
24#include <linux/interrupt.h>
25#include <linux/sysdev.h>
26#include <linux/adb.h>
27#include <linux/pmu.h>
28
29#include <asm/sections.h>
30#include <asm/io.h>
31#include <asm/smp.h>
32#include <asm/prom.h>
33#include <asm/pci-bridge.h>
34#include <asm/time.h>
35#include <asm/open_pic.h>
36#include <asm/xmon.h>
37#include <asm/pmac_feature.h>
38#include <asm/mpic.h>
39
40#include "pmac_pic.h"
41
42/*
43 * XXX this should be in xmon.h, but putting it there means xmon.h
44 * has to include <linux/interrupt.h> (to get irqreturn_t), which
45 * causes all sorts of problems. -- paulus
46 */
47extern irqreturn_t xmon_irq(int, void *, struct pt_regs *);
48
49struct pmac_irq_hw {
50 unsigned int event;
51 unsigned int enable;
52 unsigned int ack;
53 unsigned int level;
54};
55
56/* Default addresses */
57static volatile struct pmac_irq_hw *pmac_irq_hw[4] = {
58 (struct pmac_irq_hw *) 0xf3000020,
59 (struct pmac_irq_hw *) 0xf3000010,
60 (struct pmac_irq_hw *) 0xf4000020,
61 (struct pmac_irq_hw *) 0xf4000010,
62};
63
64#define GC_LEVEL_MASK 0x3ff00000
65#define OHARE_LEVEL_MASK 0x1ff00000
66#define HEATHROW_LEVEL_MASK 0x1ff00000
67
68static int max_irqs;
69static int max_real_irqs;
70static u32 level_mask[4];
71
72static DEFINE_SPINLOCK(pmac_pic_lock);
73
74
75#define GATWICK_IRQ_POOL_SIZE 10
76static struct interrupt_info gatwick_int_pool[GATWICK_IRQ_POOL_SIZE];
77
78/*
79 * Mark an irq as "lost". This is only used on the pmac
80 * since it can lose interrupts (see pmac_set_irq_mask).
81 * -- Cort
82 */
83void
84__set_lost(unsigned long irq_nr, int nokick)
85{
86 if (!test_and_set_bit(irq_nr, ppc_lost_interrupts)) {
87 atomic_inc(&ppc_n_lost_interrupts);
88 if (!nokick)
89 set_dec(1);
90 }
91}
92
93static void
94pmac_mask_and_ack_irq(unsigned int irq_nr)
95{
96 unsigned long bit = 1UL << (irq_nr & 0x1f);
97 int i = irq_nr >> 5;
98 unsigned long flags;
99
100 if ((unsigned)irq_nr >= max_irqs)
101 return;
102
103 clear_bit(irq_nr, ppc_cached_irq_mask);
104 if (test_and_clear_bit(irq_nr, ppc_lost_interrupts))
105 atomic_dec(&ppc_n_lost_interrupts);
106 spin_lock_irqsave(&pmac_pic_lock, flags);
107 out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
108 out_le32(&pmac_irq_hw[i]->ack, bit);
109 do {
110 /* make sure ack gets to controller before we enable
111 interrupts */
112 mb();
113 } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
114 != (ppc_cached_irq_mask[i] & bit));
115 spin_unlock_irqrestore(&pmac_pic_lock, flags);
116}
117
118static void pmac_set_irq_mask(unsigned int irq_nr, int nokicklost)
119{
120 unsigned long bit = 1UL << (irq_nr & 0x1f);
121 int i = irq_nr >> 5;
122 unsigned long flags;
123
124 if ((unsigned)irq_nr >= max_irqs)
125 return;
126
127 spin_lock_irqsave(&pmac_pic_lock, flags);
128 /* enable unmasked interrupts */
129 out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
130
131 do {
132 /* make sure mask gets to controller before we
133 return to user */
134 mb();
135 } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
136 != (ppc_cached_irq_mask[i] & bit));
137
138 /*
139 * Unfortunately, setting the bit in the enable register
140 * when the device interrupt is already on *doesn't* set
141 * the bit in the flag register or request another interrupt.
142 */
143 if (bit & ppc_cached_irq_mask[i] & in_le32(&pmac_irq_hw[i]->level))
144 __set_lost((ulong)irq_nr, nokicklost);
145 spin_unlock_irqrestore(&pmac_pic_lock, flags);
146}
147
148/* When an irq gets requested for the first client, if it's an
149 * edge interrupt, we clear any previous one on the controller
150 */
151static unsigned int pmac_startup_irq(unsigned int irq_nr)
152{
153 unsigned long bit = 1UL << (irq_nr & 0x1f);
154 int i = irq_nr >> 5;
155
156 if ((irq_desc[irq_nr].status & IRQ_LEVEL) == 0)
157 out_le32(&pmac_irq_hw[i]->ack, bit);
158 set_bit(irq_nr, ppc_cached_irq_mask);
159 pmac_set_irq_mask(irq_nr, 0);
160
161 return 0;
162}
163
164static void pmac_mask_irq(unsigned int irq_nr)
165{
166 clear_bit(irq_nr, ppc_cached_irq_mask);
167 pmac_set_irq_mask(irq_nr, 0);
168 mb();
169}
170
171static void pmac_unmask_irq(unsigned int irq_nr)
172{
173 set_bit(irq_nr, ppc_cached_irq_mask);
174 pmac_set_irq_mask(irq_nr, 0);
175}
176
177static void pmac_end_irq(unsigned int irq_nr)
178{
179 if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))
180 && irq_desc[irq_nr].action) {
181 set_bit(irq_nr, ppc_cached_irq_mask);
182 pmac_set_irq_mask(irq_nr, 1);
183 }
184}
185
186
187struct hw_interrupt_type pmac_pic = {
188 .typename = " PMAC-PIC ",
189 .startup = pmac_startup_irq,
190 .enable = pmac_unmask_irq,
191 .disable = pmac_mask_irq,
192 .ack = pmac_mask_and_ack_irq,
193 .end = pmac_end_irq,
194};
195
196struct hw_interrupt_type gatwick_pic = {
197 .typename = " GATWICK ",
198 .startup = pmac_startup_irq,
199 .enable = pmac_unmask_irq,
200 .disable = pmac_mask_irq,
201 .ack = pmac_mask_and_ack_irq,
202 .end = pmac_end_irq,
203};
204
205static irqreturn_t gatwick_action(int cpl, void *dev_id, struct pt_regs *regs)
206{
207 int irq, bits;
208
209 for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) {
210 int i = irq >> 5;
211 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
212 /* We must read level interrupts from the level register */
213 bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]);
214 bits &= ppc_cached_irq_mask[i];
215 if (bits == 0)
216 continue;
217 irq += __ilog2(bits);
218 __do_IRQ(irq, regs);
219 return IRQ_HANDLED;
220 }
221 printk("gatwick irq not from gatwick pic\n");
222 return IRQ_NONE;
223}
224
225int
226pmac_get_irq(struct pt_regs *regs)
227{
228 int irq;
229 unsigned long bits = 0;
230
231#ifdef CONFIG_SMP
232 void psurge_smp_message_recv(struct pt_regs *);
233
234 /* IPI's are a hack on the powersurge -- Cort */
235 if ( smp_processor_id() != 0 ) {
236 psurge_smp_message_recv(regs);
237 return -2; /* ignore, already handled */
238 }
239#endif /* CONFIG_SMP */
240 for (irq = max_real_irqs; (irq -= 32) >= 0; ) {
241 int i = irq >> 5;
242 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
243 /* We must read level interrupts from the level register */
244 bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]);
245 bits &= ppc_cached_irq_mask[i];
246 if (bits == 0)
247 continue;
248 irq += __ilog2(bits);
249 break;
250 }
251
252 return irq;
253}
254
255/* This routine will fix some missing interrupt values in the device tree
256 * on the gatwick mac-io controller used by some PowerBooks
257 */
258static void __init
259pmac_fix_gatwick_interrupts(struct device_node *gw, int irq_base)
260{
261 struct device_node *node;
262 int count;
263
264 memset(gatwick_int_pool, 0, sizeof(gatwick_int_pool));
265 node = gw->child;
266 count = 0;
267 while(node)
268 {
269 /* Fix SCC */
270 if (strcasecmp(node->name, "escc") == 0)
271 if (node->child) {
272 if (node->child->n_intrs < 3) {
273 node->child->intrs = &gatwick_int_pool[count];
274 count += 3;
275 }
276 node->child->n_intrs = 3;
277 node->child->intrs[0].line = 15+irq_base;
278 node->child->intrs[1].line = 4+irq_base;
279 node->child->intrs[2].line = 5+irq_base;
280 printk(KERN_INFO "irq: fixed SCC on second controller (%d,%d,%d)\n",
281 node->child->intrs[0].line,
282 node->child->intrs[1].line,
283 node->child->intrs[2].line);
284 }
285 /* Fix media-bay & left SWIM */
286 if (strcasecmp(node->name, "media-bay") == 0) {
287 struct device_node* ya_node;
288
289 if (node->n_intrs == 0)
290 node->intrs = &gatwick_int_pool[count++];
291 node->n_intrs = 1;
292 node->intrs[0].line = 29+irq_base;
293 printk(KERN_INFO "irq: fixed media-bay on second controller (%d)\n",
294 node->intrs[0].line);
295
296 ya_node = node->child;
297 while(ya_node)
298 {
299 if (strcasecmp(ya_node->name, "floppy") == 0) {
300 if (ya_node->n_intrs < 2) {
301 ya_node->intrs = &gatwick_int_pool[count];
302 count += 2;
303 }
304 ya_node->n_intrs = 2;
305 ya_node->intrs[0].line = 19+irq_base;
306 ya_node->intrs[1].line = 1+irq_base;
307 printk(KERN_INFO "irq: fixed floppy on second controller (%d,%d)\n",
308 ya_node->intrs[0].line, ya_node->intrs[1].line);
309 }
310 if (strcasecmp(ya_node->name, "ata4") == 0) {
311 if (ya_node->n_intrs < 2) {
312 ya_node->intrs = &gatwick_int_pool[count];
313 count += 2;
314 }
315 ya_node->n_intrs = 2;
316 ya_node->intrs[0].line = 14+irq_base;
317 ya_node->intrs[1].line = 3+irq_base;
318 printk(KERN_INFO "irq: fixed ide on second controller (%d,%d)\n",
319 ya_node->intrs[0].line, ya_node->intrs[1].line);
320 }
321 ya_node = ya_node->sibling;
322 }
323 }
324 node = node->sibling;
325 }
326 if (count > 10) {
327 printk("WARNING !! Gatwick interrupt pool overflow\n");
328 printk(" GATWICK_IRQ_POOL_SIZE = %d\n", GATWICK_IRQ_POOL_SIZE);
329 printk(" requested = %d\n", count);
330 }
331}
332
333/*
334 * The PowerBook 3400/2400/3500 can have a combo ethernet/modem
335 * card which includes an ohare chip that acts as a second interrupt
336 * controller. If we find this second ohare, set it up and fix the
337 * interrupt value in the device tree for the ethernet chip.
338 */
339static int __init enable_second_ohare(void)
340{
341 unsigned char bus, devfn;
342 unsigned short cmd;
343 unsigned long addr;
344 struct device_node *irqctrler = find_devices("pci106b,7");
345 struct device_node *ether;
346
347 if (irqctrler == NULL || irqctrler->n_addrs <= 0)
348 return -1;
349 addr = (unsigned long) ioremap(irqctrler->addrs[0].address, 0x40);
350 pmac_irq_hw[1] = (volatile struct pmac_irq_hw *)(addr + 0x20);
351 max_irqs = 64;
352 if (pci_device_from_OF_node(irqctrler, &bus, &devfn) == 0) {
353 struct pci_controller* hose = pci_find_hose_for_OF_device(irqctrler);
354 if (!hose)
355 printk(KERN_ERR "Can't find PCI hose for OHare2 !\n");
356 else {
357 early_read_config_word(hose, bus, devfn, PCI_COMMAND, &cmd);
358 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
359 cmd &= ~PCI_COMMAND_IO;
360 early_write_config_word(hose, bus, devfn, PCI_COMMAND, cmd);
361 }
362 }
363
364 /* Fix interrupt for the modem/ethernet combo controller. The number
365 in the device tree (27) is bogus (correct for the ethernet-only
366 board but not the combo ethernet/modem board).
367 The real interrupt is 28 on the second controller -> 28+32 = 60.
368 */
369 ether = find_devices("pci1011,14");
370 if (ether && ether->n_intrs > 0) {
371 ether->intrs[0].line = 60;
372 printk(KERN_INFO "irq: Fixed ethernet IRQ to %d\n",
373 ether->intrs[0].line);
374 }
375
376 /* Return the interrupt number of the cascade */
377 return irqctrler->intrs[0].line;
378}
379
380static int pmac_u3_cascade(struct pt_regs *regs, void *data)
381{
382 return mpic_get_one_irq((struct mpic *)data, regs);
383}
384
385#ifdef CONFIG_XMON
386static struct irqaction xmon_action = {
387 .handler = xmon_irq,
388 .flags = 0,
389 .mask = CPU_MASK_NONE,
390 .name = "NMI - XMON"
391};
392#endif
393
394static struct irqaction gatwick_cascade_action = {
395 .handler = gatwick_action,
396 .flags = SA_INTERRUPT,
397 .mask = CPU_MASK_NONE,
398 .name = "cascade",
399};
400
401void __init pmac_pic_init(void)
402{
403 int i;
404 struct device_node *irqctrler = NULL;
405 struct device_node *irqctrler2 = NULL;
406 struct device_node *np;
407 unsigned long addr;
408 int irq_cascade = -1;
409 struct mpic *mpic1, *mpic2;
410
411 /* We first try to detect Apple's new Core99 chipset, since mac-io
412 * is quite different on those machines and contains an IBM MPIC2.
413 */
414 np = find_type_devices("open-pic");
415 while (np) {
416 if (np->parent && !strcmp(np->parent->name, "u3"))
417 irqctrler2 = np;
418 else
419 irqctrler = np;
420 np = np->next;
421 }
422 if (irqctrler != NULL && irqctrler->n_addrs > 0) {
423 unsigned char senses[128];
424
425 printk(KERN_INFO "PowerMac using OpenPIC irq controller at 0x%08x\n",
426 (unsigned int)irqctrler->addrs[0].address);
427
428 prom_get_irq_senses(senses, 0, 128);
429 mpic1 = mpic_alloc(irqctrler->addrs[0].address,
430 MPIC_PRIMARY | MPIC_WANTS_RESET,
431 0, 0, 128, 256, senses, 128, " K2-MPIC ");
432 BUG_ON(mpic1 == NULL);
433 mpic_init(mpic1);
434
435 if (irqctrler2 != NULL && irqctrler2->n_intrs > 0 &&
436 irqctrler2->n_addrs > 0) {
437 printk(KERN_INFO "Slave OpenPIC at 0x%08x hooked on IRQ %d\n",
438 (u32)irqctrler2->addrs[0].address,
439 irqctrler2->intrs[0].line);
440
441 pmac_call_feature(PMAC_FTR_ENABLE_MPIC, irqctrler2, 0, 0);
442 prom_get_irq_senses(senses, 128, 128 + 128);
443
444 /* We don't need to set MPIC_BROKEN_U3 here since we don't have
445 * hypertransport interrupts routed to it
446 */
447 mpic2 = mpic_alloc(irqctrler2->addrs[0].address,
448 MPIC_BIG_ENDIAN | MPIC_WANTS_RESET,
449 0, 128, 128, 0, senses, 128, " U3-MPIC ");
450 BUG_ON(mpic2 == NULL);
451 mpic_init(mpic2);
452 mpic_setup_cascade(irqctrler2->intrs[0].line,
453 pmac_u3_cascade, mpic2);
454 }
455 }
456
457 /* Get the level/edge settings, assume if it's not
458 * a Grand Central nor an OHare, then it's an Heathrow
459 * (or Paddington).
460 */
461 if (find_devices("gc"))
462 level_mask[0] = GC_LEVEL_MASK;
463 else if (find_devices("ohare")) {
464 level_mask[0] = OHARE_LEVEL_MASK;
465 /* We might have a second cascaded ohare */
466 level_mask[1] = OHARE_LEVEL_MASK;
467 } else {
468 level_mask[0] = HEATHROW_LEVEL_MASK;
469 level_mask[1] = 0;
470 /* We might have a second cascaded heathrow */
471 level_mask[2] = HEATHROW_LEVEL_MASK;
472 level_mask[3] = 0;
473 }
474
475 /*
476 * G3 powermacs and 1999 G3 PowerBooks have 64 interrupts,
477 * 1998 G3 Series PowerBooks have 128,
478 * other powermacs have 32.
479 * The combo ethernet/modem card for the Powerstar powerbooks
480 * (2400/3400/3500, ohare based) has a second ohare chip
481 * effectively making a total of 64.
482 */
483 max_irqs = max_real_irqs = 32;
484 irqctrler = find_devices("mac-io");
485 if (irqctrler)
486 {
487 max_real_irqs = 64;
488 if (irqctrler->next)
489 max_irqs = 128;
490 else
491 max_irqs = 64;
492 }
493 for ( i = 0; i < max_real_irqs ; i++ )
494 irq_desc[i].handler = &pmac_pic;
495
496 /* get addresses of first controller */
497 if (irqctrler) {
498 if (irqctrler->n_addrs > 0) {
499 addr = (unsigned long)
500 ioremap(irqctrler->addrs[0].address, 0x40);
501 for (i = 0; i < 2; ++i)
502 pmac_irq_hw[i] = (volatile struct pmac_irq_hw*)
503 (addr + (2 - i) * 0x10);
504 }
505
506 /* get addresses of second controller */
507 irqctrler = irqctrler->next;
508 if (irqctrler && irqctrler->n_addrs > 0) {
509 addr = (unsigned long)
510 ioremap(irqctrler->addrs[0].address, 0x40);
511 for (i = 2; i < 4; ++i)
512 pmac_irq_hw[i] = (volatile struct pmac_irq_hw*)
513 (addr + (4 - i) * 0x10);
514 irq_cascade = irqctrler->intrs[0].line;
515 if (device_is_compatible(irqctrler, "gatwick"))
516 pmac_fix_gatwick_interrupts(irqctrler, max_real_irqs);
517 }
518 } else {
519 /* older powermacs have a GC (grand central) or ohare at
520 f3000000, with interrupt control registers at f3000020. */
521 addr = (unsigned long) ioremap(0xf3000000, 0x40);
522 pmac_irq_hw[0] = (volatile struct pmac_irq_hw *) (addr + 0x20);
523 }
524
525 /* PowerBooks 3400 and 3500 can have a second controller in a second
526 ohare chip, on the combo ethernet/modem card */
527 if (machine_is_compatible("AAPL,3400/2400")
528 || machine_is_compatible("AAPL,3500"))
529 irq_cascade = enable_second_ohare();
530
531 /* disable all interrupts in all controllers */
532 for (i = 0; i * 32 < max_irqs; ++i)
533 out_le32(&pmac_irq_hw[i]->enable, 0);
534 /* mark level interrupts */
535 for (i = 0; i < max_irqs; i++)
536 if (level_mask[i >> 5] & (1UL << (i & 0x1f)))
537 irq_desc[i].status = IRQ_LEVEL;
538
539 /* get interrupt line of secondary interrupt controller */
540 if (irq_cascade >= 0) {
541 printk(KERN_INFO "irq: secondary controller on irq %d\n",
542 (int)irq_cascade);
543 for ( i = max_real_irqs ; i < max_irqs ; i++ )
544 irq_desc[i].handler = &gatwick_pic;
545 setup_irq(irq_cascade, &gatwick_cascade_action);
546 }
547 printk("System has %d possible interrupts\n", max_irqs);
548 if (max_irqs != max_real_irqs)
549 printk(KERN_DEBUG "%d interrupts on main controller\n",
550 max_real_irqs);
551
552#ifdef CONFIG_XMON
553 setup_irq(20, &xmon_action);
554#endif /* CONFIG_XMON */
555}
556
557#ifdef CONFIG_PM
558/*
559 * These procedures are used in implementing sleep on the powerbooks.
560 * sleep_save_intrs() saves the states of all interrupt enables
561 * and disables all interrupts except for the nominated one.
562 * sleep_restore_intrs() restores the states of all interrupt enables.
563 */
564unsigned long sleep_save_mask[2];
565
566/* This used to be passed by the PMU driver but that link got
567 * broken with the new driver model. We use this tweak for now...
568 */
569static int pmacpic_find_viaint(void)
570{
571 int viaint = -1;
572
573#ifdef CONFIG_ADB_PMU
574 struct device_node *np;
575
576 if (pmu_get_model() != PMU_OHARE_BASED)
577 goto not_found;
578 np = of_find_node_by_name(NULL, "via-pmu");
579 if (np == NULL)
580 goto not_found;
581 viaint = np->intrs[0].line;
582#endif /* CONFIG_ADB_PMU */
583
584not_found:
585 return viaint;
586}
587
588static int pmacpic_suspend(struct sys_device *sysdev, pm_message_t state)
589{
590 int viaint = pmacpic_find_viaint();
591
592 sleep_save_mask[0] = ppc_cached_irq_mask[0];
593 sleep_save_mask[1] = ppc_cached_irq_mask[1];
594 ppc_cached_irq_mask[0] = 0;
595 ppc_cached_irq_mask[1] = 0;
596 if (viaint > 0)
597 set_bit(viaint, ppc_cached_irq_mask);
598 out_le32(&pmac_irq_hw[0]->enable, ppc_cached_irq_mask[0]);
599 if (max_real_irqs > 32)
600 out_le32(&pmac_irq_hw[1]->enable, ppc_cached_irq_mask[1]);
601 (void)in_le32(&pmac_irq_hw[0]->event);
602 /* make sure mask gets to controller before we return to caller */
603 mb();
604 (void)in_le32(&pmac_irq_hw[0]->enable);
605
606 return 0;
607}
608
609static int pmacpic_resume(struct sys_device *sysdev)
610{
611 int i;
612
613 out_le32(&pmac_irq_hw[0]->enable, 0);
614 if (max_real_irqs > 32)
615 out_le32(&pmac_irq_hw[1]->enable, 0);
616 mb();
617 for (i = 0; i < max_real_irqs; ++i)
618 if (test_bit(i, sleep_save_mask))
619 pmac_unmask_irq(i);
620
621 return 0;
622}
623
624#endif /* CONFIG_PM */
625
626static struct sysdev_class pmacpic_sysclass = {
627 set_kset_name("pmac_pic"),
628};
629
630static struct sys_device device_pmacpic = {
631 .id = 0,
632 .cls = &pmacpic_sysclass,
633};
634
635static struct sysdev_driver driver_pmacpic = {
636#ifdef CONFIG_PM
637 .suspend = &pmacpic_suspend,
638 .resume = &pmacpic_resume,
639#endif /* CONFIG_PM */
640};
641
642static int __init init_pmacpic_sysfs(void)
643{
644 if (max_irqs == 0)
645 return -ENODEV;
646
647 printk(KERN_DEBUG "Registering pmac pic with sysfs...\n");
648 sysdev_class_register(&pmacpic_sysclass);
649 sysdev_register(&device_pmacpic);
650 sysdev_driver_register(&pmacpic_sysclass, &driver_pmacpic);
651 return 0;
652}
653
654subsys_initcall(init_pmacpic_sysfs);
655
diff --git a/arch/powerpc/platforms/powermac/pmac_pic.h b/arch/powerpc/platforms/powermac/pmac_pic.h
new file mode 100644
index 000000000000..664103dfeef9
--- /dev/null
+++ b/arch/powerpc/platforms/powermac/pmac_pic.h
@@ -0,0 +1,11 @@
1#ifndef __PPC_PLATFORMS_PMAC_PIC_H
2#define __PPC_PLATFORMS_PMAC_PIC_H
3
4#include <linux/irq.h>
5
6extern struct hw_interrupt_type pmac_pic;
7
8void pmac_pic_init(void);
9int pmac_get_irq(struct pt_regs *regs);
10
11#endif /* __PPC_PLATFORMS_PMAC_PIC_H */
diff --git a/arch/powerpc/platforms/powermac/pmac_setup.c b/arch/powerpc/platforms/powermac/pmac_setup.c
new file mode 100644
index 000000000000..dbc921a084cd
--- /dev/null
+++ b/arch/powerpc/platforms/powermac/pmac_setup.c
@@ -0,0 +1,662 @@
1/*
2 * arch/ppc/platforms/setup.c
3 *
4 * PowerPC version
5 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
6 *
7 * Adapted for Power Macintosh by Paul Mackerras
8 * Copyright (C) 1996 Paul Mackerras (paulus@cs.anu.edu.au)
9 *
10 * Derived from "arch/alpha/kernel/setup.c"
11 * Copyright (C) 1995 Linus Torvalds
12 *
13 * Maintained by Benjamin Herrenschmidt (benh@kernel.crashing.org)
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
19 *
20 */
21
22/*
23 * bootup setup stuff..
24 */
25
26#include <linux/config.h>
27#include <linux/init.h>
28#include <linux/errno.h>
29#include <linux/sched.h>
30#include <linux/kernel.h>
31#include <linux/mm.h>
32#include <linux/stddef.h>
33#include <linux/unistd.h>
34#include <linux/ptrace.h>
35#include <linux/slab.h>
36#include <linux/user.h>
37#include <linux/a.out.h>
38#include <linux/tty.h>
39#include <linux/string.h>
40#include <linux/delay.h>
41#include <linux/ioport.h>
42#include <linux/major.h>
43#include <linux/initrd.h>
44#include <linux/vt_kern.h>
45#include <linux/console.h>
46#include <linux/ide.h>
47#include <linux/pci.h>
48#include <linux/adb.h>
49#include <linux/cuda.h>
50#include <linux/pmu.h>
51#include <linux/irq.h>
52#include <linux/seq_file.h>
53#include <linux/root_dev.h>
54#include <linux/bitops.h>
55#include <linux/suspend.h>
56
57#include <asm/reg.h>
58#include <asm/sections.h>
59#include <asm/prom.h>
60#include <asm/system.h>
61#include <asm/pgtable.h>
62#include <asm/io.h>
63#include <asm/pci-bridge.h>
64#include <asm/ohare.h>
65#include <asm/mediabay.h>
66#include <asm/machdep.h>
67#include <asm/dma.h>
68#include <asm/bootx.h>
69#include <asm/cputable.h>
70#include <asm/btext.h>
71#include <asm/pmac_feature.h>
72#include <asm/time.h>
73#include <asm/of_device.h>
74#include <asm/mmu_context.h>
75
76#include "pmac_pic.h"
77
78#undef SHOW_GATWICK_IRQS
79
80extern long pmac_time_init(void);
81extern unsigned long pmac_get_rtc_time(void);
82extern int pmac_set_rtc_time(unsigned long nowtime);
83extern void pmac_read_rtc_time(void);
84extern void pmac_calibrate_decr(void);
85extern void pmac_pcibios_fixup(void);
86extern void pmac_find_bridges(void);
87extern unsigned long pmac_ide_get_base(int index);
88extern void pmac_ide_init_hwif_ports(hw_regs_t *hw,
89 unsigned long data_port, unsigned long ctrl_port, int *irq);
90
91extern void pmac_nvram_update(void);
92extern unsigned char pmac_nvram_read_byte(int addr);
93extern void pmac_nvram_write_byte(int addr, unsigned char val);
94extern int pmac_pci_enable_device_hook(struct pci_dev *dev, int initial);
95extern void pmac_pcibios_after_init(void);
96extern int of_show_percpuinfo(struct seq_file *m, int i);
97
98unsigned char drive_info;
99
100int ppc_override_l2cr = 0;
101int ppc_override_l2cr_value;
102int has_l2cache = 0;
103
104static int current_root_goodness = -1;
105
106extern int pmac_newworld;
107
108#define DEFAULT_ROOT_DEVICE Root_SDA1 /* sda1 - slightly silly choice */
109
110extern void zs_kgdb_hook(int tty_num);
111static void ohare_init(void);
112#ifdef CONFIG_BOOTX_TEXT
113static void pmac_progress(char *s, unsigned short hex);
114#endif
115
116sys_ctrler_t sys_ctrler = SYS_CTRLER_UNKNOWN;
117
118#ifdef CONFIG_SMP
119extern struct smp_ops_t psurge_smp_ops;
120extern struct smp_ops_t core99_smp_ops;
121#endif /* CONFIG_SMP */
122
123static int
124pmac_show_cpuinfo(struct seq_file *m)
125{
126 struct device_node *np;
127 char *pp;
128 int plen;
129 int mbmodel = pmac_call_feature(PMAC_FTR_GET_MB_INFO,
130 NULL, PMAC_MB_INFO_MODEL, 0);
131 unsigned int mbflags = (unsigned int)pmac_call_feature(PMAC_FTR_GET_MB_INFO,
132 NULL, PMAC_MB_INFO_FLAGS, 0);
133 char* mbname;
134
135 if (pmac_call_feature(PMAC_FTR_GET_MB_INFO, NULL, PMAC_MB_INFO_NAME, (int)&mbname) != 0)
136 mbname = "Unknown";
137
138 /* find motherboard type */
139 seq_printf(m, "machine\t\t: ");
140 np = find_devices("device-tree");
141 if (np != NULL) {
142 pp = (char *) get_property(np, "model", NULL);
143 if (pp != NULL)
144 seq_printf(m, "%s\n", pp);
145 else
146 seq_printf(m, "PowerMac\n");
147 pp = (char *) get_property(np, "compatible", &plen);
148 if (pp != NULL) {
149 seq_printf(m, "motherboard\t:");
150 while (plen > 0) {
151 int l = strlen(pp) + 1;
152 seq_printf(m, " %s", pp);
153 plen -= l;
154 pp += l;
155 }
156 seq_printf(m, "\n");
157 }
158 } else
159 seq_printf(m, "PowerMac\n");
160
161 /* print parsed model */
162 seq_printf(m, "detected as\t: %d (%s)\n", mbmodel, mbname);
163 seq_printf(m, "pmac flags\t: %08x\n", mbflags);
164
165 /* find l2 cache info */
166 np = find_devices("l2-cache");
167 if (np == 0)
168 np = find_type_devices("cache");
169 if (np != 0) {
170 unsigned int *ic = (unsigned int *)
171 get_property(np, "i-cache-size", NULL);
172 unsigned int *dc = (unsigned int *)
173 get_property(np, "d-cache-size", NULL);
174 seq_printf(m, "L2 cache\t:");
175 has_l2cache = 1;
176 if (get_property(np, "cache-unified", NULL) != 0 && dc) {
177 seq_printf(m, " %dK unified", *dc / 1024);
178 } else {
179 if (ic)
180 seq_printf(m, " %dK instruction", *ic / 1024);
181 if (dc)
182 seq_printf(m, "%s %dK data",
183 (ic? " +": ""), *dc / 1024);
184 }
185 pp = get_property(np, "ram-type", NULL);
186 if (pp)
187 seq_printf(m, " %s", pp);
188 seq_printf(m, "\n");
189 }
190
191 /* find ram info */
192 np = find_devices("memory");
193 if (np != 0) {
194 int n;
195 struct reg_property *reg = (struct reg_property *)
196 get_property(np, "reg", &n);
197
198 if (reg != 0) {
199 unsigned long total = 0;
200
201 for (n /= sizeof(struct reg_property); n > 0; --n)
202 total += (reg++)->size;
203 seq_printf(m, "memory\t\t: %luMB\n", total >> 20);
204 }
205 }
206
207 /* Checks "l2cr-value" property in the registry */
208 np = find_devices("cpus");
209 if (np == 0)
210 np = find_type_devices("cpu");
211 if (np != 0) {
212 unsigned int *l2cr = (unsigned int *)
213 get_property(np, "l2cr-value", NULL);
214 if (l2cr != 0) {
215 seq_printf(m, "l2cr override\t: 0x%x\n", *l2cr);
216 }
217 }
218
219 /* Indicate newworld/oldworld */
220 seq_printf(m, "pmac-generation\t: %s\n",
221 pmac_newworld ? "NewWorld" : "OldWorld");
222
223
224 return 0;
225}
226
227static int
228pmac_show_percpuinfo(struct seq_file *m, int i)
229{
230#ifdef CONFIG_CPU_FREQ_PMAC
231 extern unsigned int pmac_get_one_cpufreq(int i);
232 unsigned int freq = pmac_get_one_cpufreq(i);
233 if (freq != 0) {
234 seq_printf(m, "clock\t\t: %dMHz\n", freq/1000);
235 return 0;
236 }
237#endif /* CONFIG_CPU_FREQ_PMAC */
238 return of_show_percpuinfo(m, i);
239}
240
241static volatile u32 *sysctrl_regs;
242
243void __init
244pmac_setup_arch(void)
245{
246 struct device_node *cpu;
247 int *fp;
248 unsigned long pvr;
249
250 pvr = PVR_VER(mfspr(SPRN_PVR));
251
252 /* Set loops_per_jiffy to a half-way reasonable value,
253 for use until calibrate_delay gets called. */
254 cpu = find_type_devices("cpu");
255 if (cpu != 0) {
256 fp = (int *) get_property(cpu, "clock-frequency", NULL);
257 if (fp != 0) {
258 if (pvr == 4 || pvr >= 8)
259 /* 604, G3, G4 etc. */
260 loops_per_jiffy = *fp / HZ;
261 else
262 /* 601, 603, etc. */
263 loops_per_jiffy = *fp / (2*HZ);
264 } else
265 loops_per_jiffy = 50000000 / HZ;
266 }
267
268 /* this area has the CPU identification register
269 and some registers used by smp boards */
270 sysctrl_regs = (volatile u32 *) ioremap(0xf8000000, 0x1000);
271 ohare_init();
272
273 /* Lookup PCI hosts */
274 pmac_find_bridges();
275
276 /* Checks "l2cr-value" property in the registry */
277 if (cpu_has_feature(CPU_FTR_L2CR)) {
278 struct device_node *np = find_devices("cpus");
279 if (np == 0)
280 np = find_type_devices("cpu");
281 if (np != 0) {
282 unsigned int *l2cr = (unsigned int *)
283 get_property(np, "l2cr-value", NULL);
284 if (l2cr != 0) {
285 ppc_override_l2cr = 1;
286 ppc_override_l2cr_value = *l2cr;
287 _set_L2CR(0);
288 _set_L2CR(ppc_override_l2cr_value);
289 }
290 }
291 }
292
293 if (ppc_override_l2cr)
294 printk(KERN_INFO "L2CR overriden (0x%x), backside cache is %s\n",
295 ppc_override_l2cr_value, (ppc_override_l2cr_value & 0x80000000)
296 ? "enabled" : "disabled");
297
298#ifdef CONFIG_KGDB
299 zs_kgdb_hook(0);
300#endif
301
302#ifdef CONFIG_ADB_CUDA
303 find_via_cuda();
304#else
305 if (find_devices("via-cuda")) {
306 printk("WARNING ! Your machine is Cuda based but your kernel\n");
307 printk(" wasn't compiled with CONFIG_ADB_CUDA option !\n");
308 }
309#endif
310#ifdef CONFIG_ADB_PMU
311 find_via_pmu();
312#else
313 if (find_devices("via-pmu")) {
314 printk("WARNING ! Your machine is PMU based but your kernel\n");
315 printk(" wasn't compiled with CONFIG_ADB_PMU option !\n");
316 }
317#endif
318#ifdef CONFIG_NVRAM
319 pmac_nvram_init();
320#endif
321#ifdef CONFIG_BLK_DEV_INITRD
322 if (initrd_start)
323 ROOT_DEV = Root_RAM0;
324 else
325#endif
326 ROOT_DEV = DEFAULT_ROOT_DEVICE;
327
328#ifdef CONFIG_SMP
329 /* Check for Core99 */
330 if (find_devices("uni-n") || find_devices("u3"))
331 ppc_md.smp_ops = &core99_smp_ops;
332 else
333 ppc_md.smp_ops = &psurge_smp_ops;
334#endif /* CONFIG_SMP */
335
336 pci_create_OF_bus_map();
337}
338
339static void __init ohare_init(void)
340{
341 /*
342 * Turn on the L2 cache.
343 * We assume that we have a PSX memory controller iff
344 * we have an ohare I/O controller.
345 */
346 if (find_devices("ohare") != NULL) {
347 if (((sysctrl_regs[2] >> 24) & 0xf) >= 3) {
348 if (sysctrl_regs[4] & 0x10)
349 sysctrl_regs[4] |= 0x04000020;
350 else
351 sysctrl_regs[4] |= 0x04000000;
352 if(has_l2cache)
353 printk(KERN_INFO "Level 2 cache enabled\n");
354 }
355 }
356}
357
358extern char *bootpath;
359extern char *bootdevice;
360void *boot_host;
361int boot_target;
362int boot_part;
363extern dev_t boot_dev;
364
365#ifdef CONFIG_SCSI
366void __init
367note_scsi_host(struct device_node *node, void *host)
368{
369 int l;
370 char *p;
371
372 l = strlen(node->full_name);
373 if (bootpath != NULL && bootdevice != NULL
374 && strncmp(node->full_name, bootdevice, l) == 0
375 && (bootdevice[l] == '/' || bootdevice[l] == 0)) {
376 boot_host = host;
377 /*
378 * There's a bug in OF 1.0.5. (Why am I not surprised.)
379 * If you pass a path like scsi/sd@1:0 to canon, it returns
380 * something like /bandit@F2000000/gc@10/53c94@10000/sd@0,0
381 * That is, the scsi target number doesn't get preserved.
382 * So we pick the target number out of bootpath and use that.
383 */
384 p = strstr(bootpath, "/sd@");
385 if (p != NULL) {
386 p += 4;
387 boot_target = simple_strtoul(p, NULL, 10);
388 p = strchr(p, ':');
389 if (p != NULL)
390 boot_part = simple_strtoul(p + 1, NULL, 10);
391 }
392 }
393}
394#endif
395
396#if defined(CONFIG_BLK_DEV_IDE) && defined(CONFIG_BLK_DEV_IDE_PMAC)
397static dev_t __init
398find_ide_boot(void)
399{
400 char *p;
401 int n;
402 dev_t __init pmac_find_ide_boot(char *bootdevice, int n);
403
404 if (bootdevice == NULL)
405 return 0;
406 p = strrchr(bootdevice, '/');
407 if (p == NULL)
408 return 0;
409 n = p - bootdevice;
410
411 return pmac_find_ide_boot(bootdevice, n);
412}
413#endif /* CONFIG_BLK_DEV_IDE && CONFIG_BLK_DEV_IDE_PMAC */
414
415static void __init
416find_boot_device(void)
417{
418#if defined(CONFIG_BLK_DEV_IDE) && defined(CONFIG_BLK_DEV_IDE_PMAC)
419 boot_dev = find_ide_boot();
420#endif
421}
422
423static int initializing = 1;
424/* TODO: Merge the suspend-to-ram with the common code !!!
425 * currently, this is a stub implementation for suspend-to-disk
426 * only
427 */
428
429#ifdef CONFIG_SOFTWARE_SUSPEND
430
431static int pmac_pm_prepare(suspend_state_t state)
432{
433 printk(KERN_DEBUG "%s(%d)\n", __FUNCTION__, state);
434
435 return 0;
436}
437
438static int pmac_pm_enter(suspend_state_t state)
439{
440 printk(KERN_DEBUG "%s(%d)\n", __FUNCTION__, state);
441
442 /* Giveup the lazy FPU & vec so we don't have to back them
443 * up from the low level code
444 */
445 enable_kernel_fp();
446
447#ifdef CONFIG_ALTIVEC
448 if (cur_cpu_spec[0]->cpu_features & CPU_FTR_ALTIVEC)
449 enable_kernel_altivec();
450#endif /* CONFIG_ALTIVEC */
451
452 return 0;
453}
454
455static int pmac_pm_finish(suspend_state_t state)
456{
457 printk(KERN_DEBUG "%s(%d)\n", __FUNCTION__, state);
458
459 /* Restore userland MMU context */
460 set_context(current->active_mm->context, current->active_mm->pgd);
461
462 return 0;
463}
464
465static struct pm_ops pmac_pm_ops = {
466 .pm_disk_mode = PM_DISK_SHUTDOWN,
467 .prepare = pmac_pm_prepare,
468 .enter = pmac_pm_enter,
469 .finish = pmac_pm_finish,
470};
471
472#endif /* CONFIG_SOFTWARE_SUSPEND */
473
474static int pmac_late_init(void)
475{
476 initializing = 0;
477#ifdef CONFIG_SOFTWARE_SUSPEND
478 pm_set_ops(&pmac_pm_ops);
479#endif /* CONFIG_SOFTWARE_SUSPEND */
480 return 0;
481}
482
483late_initcall(pmac_late_init);
484
485/* can't be __init - can be called whenever a disk is first accessed */
486void
487note_bootable_part(dev_t dev, int part, int goodness)
488{
489 static int found_boot = 0;
490 char *p;
491
492 if (!initializing)
493 return;
494 if ((goodness <= current_root_goodness) &&
495 ROOT_DEV != DEFAULT_ROOT_DEVICE)
496 return;
497 p = strstr(saved_command_line, "root=");
498 if (p != NULL && (p == saved_command_line || p[-1] == ' '))
499 return;
500
501 if (!found_boot) {
502 find_boot_device();
503 found_boot = 1;
504 }
505 if (!boot_dev || dev == boot_dev) {
506 ROOT_DEV = dev + part;
507 boot_dev = 0;
508 current_root_goodness = goodness;
509 }
510}
511
512static void
513pmac_restart(char *cmd)
514{
515#ifdef CONFIG_ADB_CUDA
516 struct adb_request req;
517#endif /* CONFIG_ADB_CUDA */
518
519 switch (sys_ctrler) {
520#ifdef CONFIG_ADB_CUDA
521 case SYS_CTRLER_CUDA:
522 cuda_request(&req, NULL, 2, CUDA_PACKET,
523 CUDA_RESET_SYSTEM);
524 for (;;)
525 cuda_poll();
526 break;
527#endif /* CONFIG_ADB_CUDA */
528#ifdef CONFIG_ADB_PMU
529 case SYS_CTRLER_PMU:
530 pmu_restart();
531 break;
532#endif /* CONFIG_ADB_PMU */
533 default: ;
534 }
535}
536
537static void
538pmac_power_off(void)
539{
540#ifdef CONFIG_ADB_CUDA
541 struct adb_request req;
542#endif /* CONFIG_ADB_CUDA */
543
544 switch (sys_ctrler) {
545#ifdef CONFIG_ADB_CUDA
546 case SYS_CTRLER_CUDA:
547 cuda_request(&req, NULL, 2, CUDA_PACKET,
548 CUDA_POWERDOWN);
549 for (;;)
550 cuda_poll();
551 break;
552#endif /* CONFIG_ADB_CUDA */
553#ifdef CONFIG_ADB_PMU
554 case SYS_CTRLER_PMU:
555 pmu_shutdown();
556 break;
557#endif /* CONFIG_ADB_PMU */
558 default: ;
559 }
560}
561
562static void
563pmac_halt(void)
564{
565 pmac_power_off();
566}
567
568void __init
569pmac_init(unsigned long r3, unsigned long r4, unsigned long r5,
570 unsigned long r6, unsigned long r7)
571{
572 /* isa_io_base gets set in pmac_find_bridges */
573 isa_mem_base = PMAC_ISA_MEM_BASE;
574 pci_dram_offset = PMAC_PCI_DRAM_OFFSET;
575 ISA_DMA_THRESHOLD = ~0L;
576 DMA_MODE_READ = 1;
577 DMA_MODE_WRITE = 2;
578
579 ppc_md.setup_arch = pmac_setup_arch;
580 ppc_md.show_cpuinfo = pmac_show_cpuinfo;
581 ppc_md.show_percpuinfo = pmac_show_percpuinfo;
582 ppc_md.irq_canonicalize = NULL;
583 ppc_md.init_IRQ = pmac_pic_init;
584 ppc_md.get_irq = pmac_get_irq; /* Changed later on ... */
585
586 ppc_md.pcibios_fixup = pmac_pcibios_fixup;
587 ppc_md.pcibios_enable_device_hook = pmac_pci_enable_device_hook;
588 ppc_md.pcibios_after_init = pmac_pcibios_after_init;
589 ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
590
591 ppc_md.restart = pmac_restart;
592 ppc_md.power_off = pmac_power_off;
593 ppc_md.halt = pmac_halt;
594
595 ppc_md.time_init = pmac_time_init;
596 ppc_md.set_rtc_time = pmac_set_rtc_time;
597 ppc_md.get_rtc_time = pmac_get_rtc_time;
598 ppc_md.calibrate_decr = pmac_calibrate_decr;
599
600 ppc_md.feature_call = pmac_do_feature_call;
601
602#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
603#ifdef CONFIG_BLK_DEV_IDE_PMAC
604 ppc_ide_md.ide_init_hwif = pmac_ide_init_hwif_ports;
605 ppc_ide_md.default_io_base = pmac_ide_get_base;
606#endif /* CONFIG_BLK_DEV_IDE_PMAC */
607#endif /* defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE) */
608
609#ifdef CONFIG_BOOTX_TEXT
610 ppc_md.progress = pmac_progress;
611#endif /* CONFIG_BOOTX_TEXT */
612
613 if (ppc_md.progress) ppc_md.progress("pmac_init(): exit", 0);
614
615}
616
617#ifdef CONFIG_BOOTX_TEXT
618static void __init
619pmac_progress(char *s, unsigned short hex)
620{
621 if (boot_text_mapped) {
622 btext_drawstring(s);
623 btext_drawchar('\n');
624 }
625}
626#endif /* CONFIG_BOOTX_TEXT */
627
628static int __init
629pmac_declare_of_platform_devices(void)
630{
631 struct device_node *np;
632
633 np = find_devices("uni-n");
634 if (np) {
635 for (np = np->child; np != NULL; np = np->sibling)
636 if (strncmp(np->name, "i2c", 3) == 0) {
637 of_platform_device_create(np, "uni-n-i2c",
638 NULL);
639 break;
640 }
641 }
642 np = find_devices("u3");
643 if (np) {
644 for (np = np->child; np != NULL; np = np->sibling)
645 if (strncmp(np->name, "i2c", 3) == 0) {
646 of_platform_device_create(np, "u3-i2c",
647 NULL);
648 break;
649 }
650 }
651
652 np = find_devices("valkyrie");
653 if (np)
654 of_platform_device_create(np, "valkyrie", NULL);
655 np = find_devices("platinum");
656 if (np)
657 of_platform_device_create(np, "platinum", NULL);
658
659 return 0;
660}
661
662device_initcall(pmac_declare_of_platform_devices);
diff --git a/arch/powerpc/platforms/powermac/pmac_sleep.S b/arch/powerpc/platforms/powermac/pmac_sleep.S
new file mode 100644
index 000000000000..88419c77ac43
--- /dev/null
+++ b/arch/powerpc/platforms/powermac/pmac_sleep.S
@@ -0,0 +1,396 @@
1/*
2 * This file contains sleep low-level functions for PowerBook G3.
3 * Copyright (C) 1999 Benjamin Herrenschmidt (benh@kernel.crashing.org)
4 * and Paul Mackerras (paulus@samba.org).
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 */
12
13#include <linux/config.h>
14#include <asm/processor.h>
15#include <asm/page.h>
16#include <asm/ppc_asm.h>
17#include <asm/cputable.h>
18#include <asm/cache.h>
19#include <asm/thread_info.h>
20#include <asm/asm-offsets.h>
21
22#define MAGIC 0x4c617273 /* 'Lars' */
23
24/*
25 * Structure for storing CPU registers on the stack.
26 */
27#define SL_SP 0
28#define SL_PC 4
29#define SL_MSR 8
30#define SL_SDR1 0xc
31#define SL_SPRG0 0x10 /* 4 sprg's */
32#define SL_DBAT0 0x20
33#define SL_IBAT0 0x28
34#define SL_DBAT1 0x30
35#define SL_IBAT1 0x38
36#define SL_DBAT2 0x40
37#define SL_IBAT2 0x48
38#define SL_DBAT3 0x50
39#define SL_IBAT3 0x58
40#define SL_TB 0x60
41#define SL_R2 0x68
42#define SL_CR 0x6c
43#define SL_R12 0x70 /* r12 to r31 */
44#define SL_SIZE (SL_R12 + 80)
45
46 .section .text
47 .align 5
48
49#if defined(CONFIG_PM) || defined(CONFIG_CPU_FREQ_PMAC)
50
51/* This gets called by via-pmu.c late during the sleep process.
52 * The PMU was already send the sleep command and will shut us down
53 * soon. We need to save all that is needed and setup the wakeup
54 * vector that will be called by the ROM on wakeup
55 */
56_GLOBAL(low_sleep_handler)
57#ifndef CONFIG_6xx
58 blr
59#else
60 mflr r0
61 stw r0,4(r1)
62 stwu r1,-SL_SIZE(r1)
63 mfcr r0
64 stw r0,SL_CR(r1)
65 stw r2,SL_R2(r1)
66 stmw r12,SL_R12(r1)
67
68 /* Save MSR & SDR1 */
69 mfmsr r4
70 stw r4,SL_MSR(r1)
71 mfsdr1 r4
72 stw r4,SL_SDR1(r1)
73
74 /* Get a stable timebase and save it */
751: mftbu r4
76 stw r4,SL_TB(r1)
77 mftb r5
78 stw r5,SL_TB+4(r1)
79 mftbu r3
80 cmpw r3,r4
81 bne 1b
82
83 /* Save SPRGs */
84 mfsprg r4,0
85 stw r4,SL_SPRG0(r1)
86 mfsprg r4,1
87 stw r4,SL_SPRG0+4(r1)
88 mfsprg r4,2
89 stw r4,SL_SPRG0+8(r1)
90 mfsprg r4,3
91 stw r4,SL_SPRG0+12(r1)
92
93 /* Save BATs */
94 mfdbatu r4,0
95 stw r4,SL_DBAT0(r1)
96 mfdbatl r4,0
97 stw r4,SL_DBAT0+4(r1)
98 mfdbatu r4,1
99 stw r4,SL_DBAT1(r1)
100 mfdbatl r4,1
101 stw r4,SL_DBAT1+4(r1)
102 mfdbatu r4,2
103 stw r4,SL_DBAT2(r1)
104 mfdbatl r4,2
105 stw r4,SL_DBAT2+4(r1)
106 mfdbatu r4,3
107 stw r4,SL_DBAT3(r1)
108 mfdbatl r4,3
109 stw r4,SL_DBAT3+4(r1)
110 mfibatu r4,0
111 stw r4,SL_IBAT0(r1)
112 mfibatl r4,0
113 stw r4,SL_IBAT0+4(r1)
114 mfibatu r4,1
115 stw r4,SL_IBAT1(r1)
116 mfibatl r4,1
117 stw r4,SL_IBAT1+4(r1)
118 mfibatu r4,2
119 stw r4,SL_IBAT2(r1)
120 mfibatl r4,2
121 stw r4,SL_IBAT2+4(r1)
122 mfibatu r4,3
123 stw r4,SL_IBAT3(r1)
124 mfibatl r4,3
125 stw r4,SL_IBAT3+4(r1)
126
127 /* Backup various CPU config stuffs */
128 bl __save_cpu_setup
129
130 /* The ROM can wake us up via 2 different vectors:
131 * - On wallstreet & lombard, we must write a magic
132 * value 'Lars' at address 4 and a pointer to a
133 * memory location containing the PC to resume from
134 * at address 0.
135 * - On Core99, we must store the wakeup vector at
136 * address 0x80 and eventually it's parameters
137 * at address 0x84. I've have some trouble with those
138 * parameters however and I no longer use them.
139 */
140 lis r5,grackle_wake_up@ha
141 addi r5,r5,grackle_wake_up@l
142 tophys(r5,r5)
143 stw r5,SL_PC(r1)
144 lis r4,KERNELBASE@h
145 tophys(r5,r1)
146 addi r5,r5,SL_PC
147 lis r6,MAGIC@ha
148 addi r6,r6,MAGIC@l
149 stw r5,0(r4)
150 stw r6,4(r4)
151 /* Setup stuffs at 0x80-0x84 for Core99 */
152 lis r3,core99_wake_up@ha
153 addi r3,r3,core99_wake_up@l
154 tophys(r3,r3)
155 stw r3,0x80(r4)
156 stw r5,0x84(r4)
157 /* Store a pointer to our backup storage into
158 * a kernel global
159 */
160 lis r3,sleep_storage@ha
161 addi r3,r3,sleep_storage@l
162 stw r5,0(r3)
163
164 .globl low_cpu_die
165low_cpu_die:
166 /* Flush & disable all caches */
167 bl flush_disable_caches
168
169 /* Turn off data relocation. */
170 mfmsr r3 /* Save MSR in r7 */
171 rlwinm r3,r3,0,28,26 /* Turn off DR bit */
172 sync
173 mtmsr r3
174 isync
175
176BEGIN_FTR_SECTION
177 /* Flush any pending L2 data prefetches to work around HW bug */
178 sync
179 lis r3,0xfff0
180 lwz r0,0(r3) /* perform cache-inhibited load to ROM */
181 sync /* (caches are disabled at this point) */
182END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
183
184/*
185 * Set the HID0 and MSR for sleep.
186 */
187 mfspr r2,SPRN_HID0
188 rlwinm r2,r2,0,10,7 /* clear doze, nap */
189 oris r2,r2,HID0_SLEEP@h
190 sync
191 isync
192 mtspr SPRN_HID0,r2
193 sync
194
195/* This loop puts us back to sleep in case we have a spurrious
196 * wakeup so that the host bridge properly stays asleep. The
197 * CPU will be turned off, either after a known time (about 1
198 * second) on wallstreet & lombard, or as soon as the CPU enters
199 * SLEEP mode on core99
200 */
201 mfmsr r2
202 oris r2,r2,MSR_POW@h
2031: sync
204 mtmsr r2
205 isync
206 b 1b
207
208/*
209 * Here is the resume code.
210 */
211
212
213/*
214 * Core99 machines resume here
215 * r4 has the physical address of SL_PC(sp) (unused)
216 */
217_GLOBAL(core99_wake_up)
218 /* Make sure HID0 no longer contains any sleep bit and that data cache
219 * is disabled
220 */
221 mfspr r3,SPRN_HID0
222 rlwinm r3,r3,0,11,7 /* clear SLEEP, NAP, DOZE bits */
223 rlwinm 3,r3,0,18,15 /* clear DCE, ICE */
224 mtspr SPRN_HID0,r3
225 sync
226 isync
227
228 /* sanitize MSR */
229 mfmsr r3
230 ori r3,r3,MSR_EE|MSR_IP
231 xori r3,r3,MSR_EE|MSR_IP
232 sync
233 isync
234 mtmsr r3
235 sync
236 isync
237
238 /* Recover sleep storage */
239 lis r3,sleep_storage@ha
240 addi r3,r3,sleep_storage@l
241 tophys(r3,r3)
242 lwz r1,0(r3)
243
244 /* Pass thru to older resume code ... */
245/*
246 * Here is the resume code for older machines.
247 * r1 has the physical address of SL_PC(sp).
248 */
249
250grackle_wake_up:
251
252 /* Restore the kernel's segment registers before
253 * we do any r1 memory access as we are not sure they
254 * are in a sane state above the first 256Mb region
255 */
256 li r0,16 /* load up segment register values */
257 mtctr r0 /* for context 0 */
258 lis r3,0x2000 /* Ku = 1, VSID = 0 */
259 li r4,0
2603: mtsrin r3,r4
261 addi r3,r3,0x111 /* increment VSID */
262 addis r4,r4,0x1000 /* address of next segment */
263 bdnz 3b
264 sync
265 isync
266
267 subi r1,r1,SL_PC
268
269 /* Restore various CPU config stuffs */
270 bl __restore_cpu_setup
271
272 /* Make sure all FPRs have been initialized */
273 bl reloc_offset
274 bl __init_fpu_registers
275
276 /* Invalidate & enable L1 cache, we don't care about
277 * whatever the ROM may have tried to write to memory
278 */
279 bl __inval_enable_L1
280
281 /* Restore the BATs, and SDR1. Then we can turn on the MMU. */
282 lwz r4,SL_SDR1(r1)
283 mtsdr1 r4
284 lwz r4,SL_SPRG0(r1)
285 mtsprg 0,r4
286 lwz r4,SL_SPRG0+4(r1)
287 mtsprg 1,r4
288 lwz r4,SL_SPRG0+8(r1)
289 mtsprg 2,r4
290 lwz r4,SL_SPRG0+12(r1)
291 mtsprg 3,r4
292
293 lwz r4,SL_DBAT0(r1)
294 mtdbatu 0,r4
295 lwz r4,SL_DBAT0+4(r1)
296 mtdbatl 0,r4
297 lwz r4,SL_DBAT1(r1)
298 mtdbatu 1,r4
299 lwz r4,SL_DBAT1+4(r1)
300 mtdbatl 1,r4
301 lwz r4,SL_DBAT2(r1)
302 mtdbatu 2,r4
303 lwz r4,SL_DBAT2+4(r1)
304 mtdbatl 2,r4
305 lwz r4,SL_DBAT3(r1)
306 mtdbatu 3,r4
307 lwz r4,SL_DBAT3+4(r1)
308 mtdbatl 3,r4
309 lwz r4,SL_IBAT0(r1)
310 mtibatu 0,r4
311 lwz r4,SL_IBAT0+4(r1)
312 mtibatl 0,r4
313 lwz r4,SL_IBAT1(r1)
314 mtibatu 1,r4
315 lwz r4,SL_IBAT1+4(r1)
316 mtibatl 1,r4
317 lwz r4,SL_IBAT2(r1)
318 mtibatu 2,r4
319 lwz r4,SL_IBAT2+4(r1)
320 mtibatl 2,r4
321 lwz r4,SL_IBAT3(r1)
322 mtibatu 3,r4
323 lwz r4,SL_IBAT3+4(r1)
324 mtibatl 3,r4
325
326BEGIN_FTR_SECTION
327 li r4,0
328 mtspr SPRN_DBAT4U,r4
329 mtspr SPRN_DBAT4L,r4
330 mtspr SPRN_DBAT5U,r4
331 mtspr SPRN_DBAT5L,r4
332 mtspr SPRN_DBAT6U,r4
333 mtspr SPRN_DBAT6L,r4
334 mtspr SPRN_DBAT7U,r4
335 mtspr SPRN_DBAT7L,r4
336 mtspr SPRN_IBAT4U,r4
337 mtspr SPRN_IBAT4L,r4
338 mtspr SPRN_IBAT5U,r4
339 mtspr SPRN_IBAT5L,r4
340 mtspr SPRN_IBAT6U,r4
341 mtspr SPRN_IBAT6L,r4
342 mtspr SPRN_IBAT7U,r4
343 mtspr SPRN_IBAT7L,r4
344END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS)
345
346 /* Flush all TLBs */
347 lis r4,0x1000
3481: addic. r4,r4,-0x1000
349 tlbie r4
350 blt 1b
351 sync
352
353 /* restore the MSR and turn on the MMU */
354 lwz r3,SL_MSR(r1)
355 bl turn_on_mmu
356
357 /* get back the stack pointer */
358 tovirt(r1,r1)
359
360 /* Restore TB */
361 li r3,0
362 mttbl r3
363 lwz r3,SL_TB(r1)
364 lwz r4,SL_TB+4(r1)
365 mttbu r3
366 mttbl r4
367
368 /* Restore the callee-saved registers and return */
369 lwz r0,SL_CR(r1)
370 mtcr r0
371 lwz r2,SL_R2(r1)
372 lmw r12,SL_R12(r1)
373 addi r1,r1,SL_SIZE
374 lwz r0,4(r1)
375 mtlr r0
376 blr
377
378turn_on_mmu:
379 mflr r4
380 tovirt(r4,r4)
381 mtsrr0 r4
382 mtsrr1 r3
383 sync
384 isync
385 rfi
386
387#endif /* defined(CONFIG_PM) || defined(CONFIG_CPU_FREQ) */
388
389 .section .data
390 .balign L1_CACHE_LINE_SIZE
391sleep_storage:
392 .long 0
393 .balign L1_CACHE_LINE_SIZE, 0
394
395#endif /* CONFIG_6xx */
396 .section .text
diff --git a/arch/powerpc/platforms/powermac/pmac_smp.c b/arch/powerpc/platforms/powermac/pmac_smp.c
new file mode 100644
index 000000000000..995e9095d865
--- /dev/null
+++ b/arch/powerpc/platforms/powermac/pmac_smp.c
@@ -0,0 +1,716 @@
1/*
2 * SMP support for power macintosh.
3 *
4 * We support both the old "powersurge" SMP architecture
5 * and the current Core99 (G4 PowerMac) machines.
6 *
7 * Note that we don't support the very first rev. of
8 * Apple/DayStar 2 CPUs board, the one with the funky
9 * watchdog. Hopefully, none of these should be there except
10 * maybe internally to Apple. I should probably still add some
11 * code to detect this card though and disable SMP. --BenH.
12 *
13 * Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net)
14 * and Ben Herrenschmidt <benh@kernel.crashing.org>.
15 *
16 * Support for DayStar quad CPU cards
17 * Copyright (C) XLR8, Inc. 1994-2000
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version
22 * 2 of the License, or (at your option) any later version.
23 */
24#include <linux/config.h>
25#include <linux/kernel.h>
26#include <linux/sched.h>
27#include <linux/smp.h>
28#include <linux/smp_lock.h>
29#include <linux/interrupt.h>
30#include <linux/kernel_stat.h>
31#include <linux/delay.h>
32#include <linux/init.h>
33#include <linux/spinlock.h>
34#include <linux/errno.h>
35#include <linux/hardirq.h>
36#include <linux/cpu.h>
37
38#include <asm/ptrace.h>
39#include <asm/atomic.h>
40#include <asm/irq.h>
41#include <asm/page.h>
42#include <asm/pgtable.h>
43#include <asm/sections.h>
44#include <asm/io.h>
45#include <asm/prom.h>
46#include <asm/smp.h>
47#include <asm/residual.h>
48#include <asm/machdep.h>
49#include <asm/pmac_feature.h>
50#include <asm/time.h>
51#include <asm/open_pic.h>
52#include <asm/cacheflush.h>
53#include <asm/keylargo.h>
54
55/*
56 * Powersurge (old powermac SMP) support.
57 */
58
59extern void __secondary_start_pmac_0(void);
60
61/* Addresses for powersurge registers */
62#define HAMMERHEAD_BASE 0xf8000000
63#define HHEAD_CONFIG 0x90
64#define HHEAD_SEC_INTR 0xc0
65
66/* register for interrupting the primary processor on the powersurge */
67/* N.B. this is actually the ethernet ROM! */
68#define PSURGE_PRI_INTR 0xf3019000
69
70/* register for storing the start address for the secondary processor */
71/* N.B. this is the PCI config space address register for the 1st bridge */
72#define PSURGE_START 0xf2800000
73
74/* Daystar/XLR8 4-CPU card */
75#define PSURGE_QUAD_REG_ADDR 0xf8800000
76
77#define PSURGE_QUAD_IRQ_SET 0
78#define PSURGE_QUAD_IRQ_CLR 1
79#define PSURGE_QUAD_IRQ_PRIMARY 2
80#define PSURGE_QUAD_CKSTOP_CTL 3
81#define PSURGE_QUAD_PRIMARY_ARB 4
82#define PSURGE_QUAD_BOARD_ID 6
83#define PSURGE_QUAD_WHICH_CPU 7
84#define PSURGE_QUAD_CKSTOP_RDBK 8
85#define PSURGE_QUAD_RESET_CTL 11
86
87#define PSURGE_QUAD_OUT(r, v) (out_8(quad_base + ((r) << 4) + 4, (v)))
88#define PSURGE_QUAD_IN(r) (in_8(quad_base + ((r) << 4) + 4) & 0x0f)
89#define PSURGE_QUAD_BIS(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) | (v)))
90#define PSURGE_QUAD_BIC(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) & ~(v)))
91
92/* virtual addresses for the above */
93static volatile u8 __iomem *hhead_base;
94static volatile u8 __iomem *quad_base;
95static volatile u32 __iomem *psurge_pri_intr;
96static volatile u8 __iomem *psurge_sec_intr;
97static volatile u32 __iomem *psurge_start;
98
99/* values for psurge_type */
100#define PSURGE_NONE -1
101#define PSURGE_DUAL 0
102#define PSURGE_QUAD_OKEE 1
103#define PSURGE_QUAD_COTTON 2
104#define PSURGE_QUAD_ICEGRASS 3
105
106/* what sort of powersurge board we have */
107static int psurge_type = PSURGE_NONE;
108
109/* L2 and L3 cache settings to pass from CPU0 to CPU1 */
110volatile static long int core99_l2_cache;
111volatile static long int core99_l3_cache;
112
113/* Timebase freeze GPIO */
114static unsigned int core99_tb_gpio;
115
116/* Sync flag for HW tb sync */
117static volatile int sec_tb_reset = 0;
118static unsigned int pri_tb_hi, pri_tb_lo;
119static unsigned int pri_tb_stamp;
120
121static void __devinit core99_init_caches(int cpu)
122{
123 if (!cpu_has_feature(CPU_FTR_L2CR))
124 return;
125
126 if (cpu == 0) {
127 core99_l2_cache = _get_L2CR();
128 printk("CPU0: L2CR is %lx\n", core99_l2_cache);
129 } else {
130 printk("CPU%d: L2CR was %lx\n", cpu, _get_L2CR());
131 _set_L2CR(0);
132 _set_L2CR(core99_l2_cache);
133 printk("CPU%d: L2CR set to %lx\n", cpu, core99_l2_cache);
134 }
135
136 if (!cpu_has_feature(CPU_FTR_L3CR))
137 return;
138
139 if (cpu == 0){
140 core99_l3_cache = _get_L3CR();
141 printk("CPU0: L3CR is %lx\n", core99_l3_cache);
142 } else {
143 printk("CPU%d: L3CR was %lx\n", cpu, _get_L3CR());
144 _set_L3CR(0);
145 _set_L3CR(core99_l3_cache);
146 printk("CPU%d: L3CR set to %lx\n", cpu, core99_l3_cache);
147 }
148}
149
150/*
151 * Set and clear IPIs for powersurge.
152 */
153static inline void psurge_set_ipi(int cpu)
154{
155 if (psurge_type == PSURGE_NONE)
156 return;
157 if (cpu == 0)
158 in_be32(psurge_pri_intr);
159 else if (psurge_type == PSURGE_DUAL)
160 out_8(psurge_sec_intr, 0);
161 else
162 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_SET, 1 << cpu);
163}
164
165static inline void psurge_clr_ipi(int cpu)
166{
167 if (cpu > 0) {
168 switch(psurge_type) {
169 case PSURGE_DUAL:
170 out_8(psurge_sec_intr, ~0);
171 case PSURGE_NONE:
172 break;
173 default:
174 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, 1 << cpu);
175 }
176 }
177}
178
179/*
180 * On powersurge (old SMP powermac architecture) we don't have
181 * separate IPIs for separate messages like openpic does. Instead
182 * we have a bitmap for each processor, where a 1 bit means that
183 * the corresponding message is pending for that processor.
184 * Ideally each cpu's entry would be in a different cache line.
185 * -- paulus.
186 */
187static unsigned long psurge_smp_message[NR_CPUS];
188
189void psurge_smp_message_recv(struct pt_regs *regs)
190{
191 int cpu = smp_processor_id();
192 int msg;
193
194 /* clear interrupt */
195 psurge_clr_ipi(cpu);
196
197 if (num_online_cpus() < 2)
198 return;
199
200 /* make sure there is a message there */
201 for (msg = 0; msg < 4; msg++)
202 if (test_and_clear_bit(msg, &psurge_smp_message[cpu]))
203 smp_message_recv(msg, regs);
204}
205
206irqreturn_t psurge_primary_intr(int irq, void *d, struct pt_regs *regs)
207{
208 psurge_smp_message_recv(regs);
209 return IRQ_HANDLED;
210}
211
212static void smp_psurge_message_pass(int target, int msg, unsigned long data,
213 int wait)
214{
215 int i;
216
217 if (num_online_cpus() < 2)
218 return;
219
220 for (i = 0; i < NR_CPUS; i++) {
221 if (!cpu_online(i))
222 continue;
223 if (target == MSG_ALL
224 || (target == MSG_ALL_BUT_SELF && i != smp_processor_id())
225 || target == i) {
226 set_bit(msg, &psurge_smp_message[i]);
227 psurge_set_ipi(i);
228 }
229 }
230}
231
232/*
233 * Determine a quad card presence. We read the board ID register, we
234 * force the data bus to change to something else, and we read it again.
235 * It it's stable, then the register probably exist (ugh !)
236 */
237static int __init psurge_quad_probe(void)
238{
239 int type;
240 unsigned int i;
241
242 type = PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID);
243 if (type < PSURGE_QUAD_OKEE || type > PSURGE_QUAD_ICEGRASS
244 || type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
245 return PSURGE_DUAL;
246
247 /* looks OK, try a slightly more rigorous test */
248 /* bogus is not necessarily cacheline-aligned,
249 though I don't suppose that really matters. -- paulus */
250 for (i = 0; i < 100; i++) {
251 volatile u32 bogus[8];
252 bogus[(0+i)%8] = 0x00000000;
253 bogus[(1+i)%8] = 0x55555555;
254 bogus[(2+i)%8] = 0xFFFFFFFF;
255 bogus[(3+i)%8] = 0xAAAAAAAA;
256 bogus[(4+i)%8] = 0x33333333;
257 bogus[(5+i)%8] = 0xCCCCCCCC;
258 bogus[(6+i)%8] = 0xCCCCCCCC;
259 bogus[(7+i)%8] = 0x33333333;
260 wmb();
261 asm volatile("dcbf 0,%0" : : "r" (bogus) : "memory");
262 mb();
263 if (type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
264 return PSURGE_DUAL;
265 }
266 return type;
267}
268
269static void __init psurge_quad_init(void)
270{
271 int procbits;
272
273 if (ppc_md.progress) ppc_md.progress("psurge_quad_init", 0x351);
274 procbits = ~PSURGE_QUAD_IN(PSURGE_QUAD_WHICH_CPU);
275 if (psurge_type == PSURGE_QUAD_ICEGRASS)
276 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
277 else
278 PSURGE_QUAD_BIC(PSURGE_QUAD_CKSTOP_CTL, procbits);
279 mdelay(33);
280 out_8(psurge_sec_intr, ~0);
281 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, procbits);
282 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
283 if (psurge_type != PSURGE_QUAD_ICEGRASS)
284 PSURGE_QUAD_BIS(PSURGE_QUAD_CKSTOP_CTL, procbits);
285 PSURGE_QUAD_BIC(PSURGE_QUAD_PRIMARY_ARB, procbits);
286 mdelay(33);
287 PSURGE_QUAD_BIC(PSURGE_QUAD_RESET_CTL, procbits);
288 mdelay(33);
289 PSURGE_QUAD_BIS(PSURGE_QUAD_PRIMARY_ARB, procbits);
290 mdelay(33);
291}
292
293static int __init smp_psurge_probe(void)
294{
295 int i, ncpus;
296
297 /* We don't do SMP on the PPC601 -- paulus */
298 if (PVR_VER(mfspr(SPRN_PVR)) == 1)
299 return 1;
300
301 /*
302 * The powersurge cpu board can be used in the generation
303 * of powermacs that have a socket for an upgradeable cpu card,
304 * including the 7500, 8500, 9500, 9600.
305 * The device tree doesn't tell you if you have 2 cpus because
306 * OF doesn't know anything about the 2nd processor.
307 * Instead we look for magic bits in magic registers,
308 * in the hammerhead memory controller in the case of the
309 * dual-cpu powersurge board. -- paulus.
310 */
311 if (find_devices("hammerhead") == NULL)
312 return 1;
313
314 hhead_base = ioremap(HAMMERHEAD_BASE, 0x800);
315 quad_base = ioremap(PSURGE_QUAD_REG_ADDR, 1024);
316 psurge_sec_intr = hhead_base + HHEAD_SEC_INTR;
317
318 psurge_type = psurge_quad_probe();
319 if (psurge_type != PSURGE_DUAL) {
320 psurge_quad_init();
321 /* All released cards using this HW design have 4 CPUs */
322 ncpus = 4;
323 } else {
324 iounmap(quad_base);
325 if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) {
326 /* not a dual-cpu card */
327 iounmap(hhead_base);
328 psurge_type = PSURGE_NONE;
329 return 1;
330 }
331 ncpus = 2;
332 }
333
334 psurge_start = ioremap(PSURGE_START, 4);
335 psurge_pri_intr = ioremap(PSURGE_PRI_INTR, 4);
336
337 /* this is not actually strictly necessary -- paulus. */
338 for (i = 1; i < ncpus; ++i)
339 smp_hw_index[i] = i;
340
341 if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352);
342
343 return ncpus;
344}
345
346static void __init smp_psurge_kick_cpu(int nr)
347{
348 unsigned long start = __pa(__secondary_start_pmac_0) + nr * 8;
349 unsigned long a;
350
351 /* may need to flush here if secondary bats aren't setup */
352 for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32)
353 asm volatile("dcbf 0,%0" : : "r" (a) : "memory");
354 asm volatile("sync");
355
356 if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu", 0x353);
357
358 out_be32(psurge_start, start);
359 mb();
360
361 psurge_set_ipi(nr);
362 udelay(10);
363 psurge_clr_ipi(nr);
364
365 if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354);
366}
367
368/*
369 * With the dual-cpu powersurge board, the decrementers and timebases
370 * of both cpus are frozen after the secondary cpu is started up,
371 * until we give the secondary cpu another interrupt. This routine
372 * uses this to get the timebases synchronized.
373 * -- paulus.
374 */
375static void __init psurge_dual_sync_tb(int cpu_nr)
376{
377 int t;
378
379 set_dec(tb_ticks_per_jiffy);
380 set_tb(0, 0);
381 last_jiffy_stamp(cpu_nr) = 0;
382
383 if (cpu_nr > 0) {
384 mb();
385 sec_tb_reset = 1;
386 return;
387 }
388
389 /* wait for the secondary to have reset its TB before proceeding */
390 for (t = 10000000; t > 0 && !sec_tb_reset; --t)
391 ;
392
393 /* now interrupt the secondary, starting both TBs */
394 psurge_set_ipi(1);
395
396 smp_tb_synchronized = 1;
397}
398
399static struct irqaction psurge_irqaction = {
400 .handler = psurge_primary_intr,
401 .flags = SA_INTERRUPT,
402 .mask = CPU_MASK_NONE,
403 .name = "primary IPI",
404};
405
406static void __init smp_psurge_setup_cpu(int cpu_nr)
407{
408
409 if (cpu_nr == 0) {
410 /* If we failed to start the second CPU, we should still
411 * send it an IPI to start the timebase & DEC or we might
412 * have them stuck.
413 */
414 if (num_online_cpus() < 2) {
415 if (psurge_type == PSURGE_DUAL)
416 psurge_set_ipi(1);
417 return;
418 }
419 /* reset the entry point so if we get another intr we won't
420 * try to startup again */
421 out_be32(psurge_start, 0x100);
422 if (setup_irq(30, &psurge_irqaction))
423 printk(KERN_ERR "Couldn't get primary IPI interrupt");
424 }
425
426 if (psurge_type == PSURGE_DUAL)
427 psurge_dual_sync_tb(cpu_nr);
428}
429
430void __init smp_psurge_take_timebase(void)
431{
432 /* Dummy implementation */
433}
434
435void __init smp_psurge_give_timebase(void)
436{
437 /* Dummy implementation */
438}
439
440static int __init smp_core99_probe(void)
441{
442#ifdef CONFIG_6xx
443 extern int powersave_nap;
444#endif
445 struct device_node *cpus, *firstcpu;
446 int i, ncpus = 0, boot_cpu = -1;
447 u32 *tbprop = NULL;
448
449 if (ppc_md.progress) ppc_md.progress("smp_core99_probe", 0x345);
450 cpus = firstcpu = find_type_devices("cpu");
451 while(cpus != NULL) {
452 u32 *regprop = (u32 *)get_property(cpus, "reg", NULL);
453 char *stateprop = (char *)get_property(cpus, "state", NULL);
454 if (regprop != NULL && stateprop != NULL &&
455 !strncmp(stateprop, "running", 7))
456 boot_cpu = *regprop;
457 ++ncpus;
458 cpus = cpus->next;
459 }
460 if (boot_cpu == -1)
461 printk(KERN_WARNING "Couldn't detect boot CPU !\n");
462 if (boot_cpu != 0)
463 printk(KERN_WARNING "Boot CPU is %d, unsupported setup !\n", boot_cpu);
464
465 if (machine_is_compatible("MacRISC4")) {
466 extern struct smp_ops_t core99_smp_ops;
467
468 core99_smp_ops.take_timebase = smp_generic_take_timebase;
469 core99_smp_ops.give_timebase = smp_generic_give_timebase;
470 } else {
471 if (firstcpu != NULL)
472 tbprop = (u32 *)get_property(firstcpu, "timebase-enable", NULL);
473 if (tbprop)
474 core99_tb_gpio = *tbprop;
475 else
476 core99_tb_gpio = KL_GPIO_TB_ENABLE;
477 }
478
479 if (ncpus > 1) {
480 mpic_request_ipis();
481 for (i = 1; i < ncpus; ++i)
482 smp_hw_index[i] = i;
483#ifdef CONFIG_6xx
484 powersave_nap = 0;
485#endif
486 core99_init_caches(0);
487 }
488
489 return ncpus;
490}
491
492static void __devinit smp_core99_kick_cpu(int nr)
493{
494 unsigned long save_vector, new_vector;
495 unsigned long flags;
496
497 volatile unsigned long *vector
498 = ((volatile unsigned long *)(KERNELBASE+0x100));
499 if (nr < 0 || nr > 3)
500 return;
501 if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu", 0x346);
502
503 local_irq_save(flags);
504 local_irq_disable();
505
506 /* Save reset vector */
507 save_vector = *vector;
508
509 /* Setup fake reset vector that does
510 * b __secondary_start_pmac_0 + nr*8 - KERNELBASE
511 */
512 new_vector = (unsigned long) __secondary_start_pmac_0 + nr * 8;
513 *vector = 0x48000002 + new_vector - KERNELBASE;
514
515 /* flush data cache and inval instruction cache */
516 flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
517
518 /* Put some life in our friend */
519 pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0);
520
521 /* FIXME: We wait a bit for the CPU to take the exception, I should
522 * instead wait for the entry code to set something for me. Well,
523 * ideally, all that crap will be done in prom.c and the CPU left
524 * in a RAM-based wait loop like CHRP.
525 */
526 mdelay(1);
527
528 /* Restore our exception vector */
529 *vector = save_vector;
530 flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
531
532 local_irq_restore(flags);
533 if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347);
534}
535
536static void __devinit smp_core99_setup_cpu(int cpu_nr)
537{
538 /* Setup L2/L3 */
539 if (cpu_nr != 0)
540 core99_init_caches(cpu_nr);
541
542 /* Setup openpic */
543 mpic_setup_this_cpu();
544
545 if (cpu_nr == 0) {
546#ifdef CONFIG_POWER4
547 extern void g5_phy_disable_cpu1(void);
548
549 /* If we didn't start the second CPU, we must take
550 * it off the bus
551 */
552 if (machine_is_compatible("MacRISC4") &&
553 num_online_cpus() < 2)
554 g5_phy_disable_cpu1();
555#endif /* CONFIG_POWER4 */
556 if (ppc_md.progress) ppc_md.progress("core99_setup_cpu 0 done", 0x349);
557 }
558}
559
560/* not __init, called in sleep/wakeup code */
561void smp_core99_take_timebase(void)
562{
563 unsigned long flags;
564
565 /* tell the primary we're here */
566 sec_tb_reset = 1;
567 mb();
568
569 /* wait for the primary to set pri_tb_hi/lo */
570 while (sec_tb_reset < 2)
571 mb();
572
573 /* set our stuff the same as the primary */
574 local_irq_save(flags);
575 set_dec(1);
576 set_tb(pri_tb_hi, pri_tb_lo);
577 last_jiffy_stamp(smp_processor_id()) = pri_tb_stamp;
578 mb();
579
580 /* tell the primary we're done */
581 sec_tb_reset = 0;
582 mb();
583 local_irq_restore(flags);
584}
585
586/* not __init, called in sleep/wakeup code */
587void smp_core99_give_timebase(void)
588{
589 unsigned long flags;
590 unsigned int t;
591
592 /* wait for the secondary to be in take_timebase */
593 for (t = 100000; t > 0 && !sec_tb_reset; --t)
594 udelay(10);
595 if (!sec_tb_reset) {
596 printk(KERN_WARNING "Timeout waiting sync on second CPU\n");
597 return;
598 }
599
600 /* freeze the timebase and read it */
601 /* disable interrupts so the timebase is disabled for the
602 shortest possible time */
603 local_irq_save(flags);
604 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 4);
605 pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0);
606 mb();
607 pri_tb_hi = get_tbu();
608 pri_tb_lo = get_tbl();
609 pri_tb_stamp = last_jiffy_stamp(smp_processor_id());
610 mb();
611
612 /* tell the secondary we're ready */
613 sec_tb_reset = 2;
614 mb();
615
616 /* wait for the secondary to have taken it */
617 for (t = 100000; t > 0 && sec_tb_reset; --t)
618 udelay(10);
619 if (sec_tb_reset)
620 printk(KERN_WARNING "Timeout waiting sync(2) on second CPU\n");
621 else
622 smp_tb_synchronized = 1;
623
624 /* Now, restart the timebase by leaving the GPIO to an open collector */
625 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 0);
626 pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0);
627 local_irq_restore(flags);
628}
629
630void smp_core99_message_pass(int target, int msg, unsigned long data, int wait)
631{
632 cpumask_t mask = CPU_MASK_ALL;
633 /* make sure we're sending something that translates to an IPI */
634 if (msg > 0x3) {
635 printk("SMP %d: smp_message_pass: unknown msg %d\n",
636 smp_processor_id(), msg);
637 return;
638 }
639 switch (target) {
640 case MSG_ALL:
641 mpic_send_ipi(msg, mask);
642 break;
643 case MSG_ALL_BUT_SELF:
644 cpu_clear(smp_processor_id(), mask);
645 mpic_send_ipi(msg, mask);
646 break;
647 default:
648 mpic_send_ipi(msg, cpumask_of_cpu(target));
649 break;
650 }
651}
652
653
654/* PowerSurge-style Macs */
655struct smp_ops_t psurge_smp_ops = {
656 .message_pass = smp_psurge_message_pass,
657 .probe = smp_psurge_probe,
658 .kick_cpu = smp_psurge_kick_cpu,
659 .setup_cpu = smp_psurge_setup_cpu,
660 .give_timebase = smp_psurge_give_timebase,
661 .take_timebase = smp_psurge_take_timebase,
662};
663
664/* Core99 Macs (dual G4s) */
665struct smp_ops_t core99_smp_ops = {
666 .message_pass = smp_core99_message_pass,
667 .probe = smp_core99_probe,
668 .kick_cpu = smp_core99_kick_cpu,
669 .setup_cpu = smp_core99_setup_cpu,
670 .give_timebase = smp_core99_give_timebase,
671 .take_timebase = smp_core99_take_timebase,
672};
673
674#ifdef CONFIG_HOTPLUG_CPU
675
676int __cpu_disable(void)
677{
678 cpu_clear(smp_processor_id(), cpu_online_map);
679
680 /* XXX reset cpu affinity here */
681 openpic_set_priority(0xf);
682 asm volatile("mtdec %0" : : "r" (0x7fffffff));
683 mb();
684 udelay(20);
685 asm volatile("mtdec %0" : : "r" (0x7fffffff));
686 return 0;
687}
688
689extern void low_cpu_die(void) __attribute__((noreturn)); /* in pmac_sleep.S */
690static int cpu_dead[NR_CPUS];
691
692void cpu_die(void)
693{
694 local_irq_disable();
695 cpu_dead[smp_processor_id()] = 1;
696 mb();
697 low_cpu_die();
698}
699
700void __cpu_die(unsigned int cpu)
701{
702 int timeout;
703
704 timeout = 1000;
705 while (!cpu_dead[cpu]) {
706 if (--timeout == 0) {
707 printk("CPU %u refused to die!\n", cpu);
708 break;
709 }
710 msleep(1);
711 }
712 cpu_callin_map[cpu] = 0;
713 cpu_dead[cpu] = 0;
714}
715
716#endif
diff --git a/arch/powerpc/platforms/powermac/pmac_time.c b/arch/powerpc/platforms/powermac/pmac_time.c
new file mode 100644
index 000000000000..ff6adff36cb8
--- /dev/null
+++ b/arch/powerpc/platforms/powermac/pmac_time.c
@@ -0,0 +1,291 @@
1/*
2 * Support for periodic interrupts (100 per second) and for getting
3 * the current time from the RTC on Power Macintoshes.
4 *
5 * We use the decrementer register for our periodic interrupts.
6 *
7 * Paul Mackerras August 1996.
8 * Copyright (C) 1996 Paul Mackerras.
9 */
10#include <linux/config.h>
11#include <linux/errno.h>
12#include <linux/sched.h>
13#include <linux/kernel.h>
14#include <linux/param.h>
15#include <linux/string.h>
16#include <linux/mm.h>
17#include <linux/init.h>
18#include <linux/time.h>
19#include <linux/adb.h>
20#include <linux/cuda.h>
21#include <linux/pmu.h>
22#include <linux/hardirq.h>
23
24#include <asm/sections.h>
25#include <asm/prom.h>
26#include <asm/system.h>
27#include <asm/io.h>
28#include <asm/pgtable.h>
29#include <asm/machdep.h>
30#include <asm/time.h>
31#include <asm/nvram.h>
32
33/* Apparently the RTC stores seconds since 1 Jan 1904 */
34#define RTC_OFFSET 2082844800
35
36/*
37 * Calibrate the decrementer frequency with the VIA timer 1.
38 */
39#define VIA_TIMER_FREQ_6 4700000 /* time 1 frequency * 6 */
40
41/* VIA registers */
42#define RS 0x200 /* skip between registers */
43#define T1CL (4*RS) /* Timer 1 ctr/latch (low 8 bits) */
44#define T1CH (5*RS) /* Timer 1 counter (high 8 bits) */
45#define T1LL (6*RS) /* Timer 1 latch (low 8 bits) */
46#define T1LH (7*RS) /* Timer 1 latch (high 8 bits) */
47#define ACR (11*RS) /* Auxiliary control register */
48#define IFR (13*RS) /* Interrupt flag register */
49
50/* Bits in ACR */
51#define T1MODE 0xc0 /* Timer 1 mode */
52#define T1MODE_CONT 0x40 /* continuous interrupts */
53
54/* Bits in IFR and IER */
55#define T1_INT 0x40 /* Timer 1 interrupt */
56
57extern struct timezone sys_tz;
58
59long __init
60pmac_time_init(void)
61{
62#ifdef CONFIG_NVRAM
63 s32 delta = 0;
64 int dst;
65
66 delta = ((s32)pmac_xpram_read(PMAC_XPRAM_MACHINE_LOC + 0x9)) << 16;
67 delta |= ((s32)pmac_xpram_read(PMAC_XPRAM_MACHINE_LOC + 0xa)) << 8;
68 delta |= pmac_xpram_read(PMAC_XPRAM_MACHINE_LOC + 0xb);
69 if (delta & 0x00800000UL)
70 delta |= 0xFF000000UL;
71 dst = ((pmac_xpram_read(PMAC_XPRAM_MACHINE_LOC + 0x8) & 0x80) != 0);
72 printk("GMT Delta read from XPRAM: %d minutes, DST: %s\n", delta/60,
73 dst ? "on" : "off");
74 return delta;
75#else
76 return 0;
77#endif
78}
79
80unsigned long
81pmac_get_rtc_time(void)
82{
83#if defined(CONFIG_ADB_CUDA) || defined(CONFIG_ADB_PMU)
84 struct adb_request req;
85 unsigned long now;
86#endif
87
88 /* Get the time from the RTC */
89 switch (sys_ctrler) {
90#ifdef CONFIG_ADB_CUDA
91 case SYS_CTRLER_CUDA:
92 if (cuda_request(&req, NULL, 2, CUDA_PACKET, CUDA_GET_TIME) < 0)
93 return 0;
94 while (!req.complete)
95 cuda_poll();
96 if (req.reply_len != 7)
97 printk(KERN_ERR "pmac_get_rtc_time: got %d byte reply\n",
98 req.reply_len);
99 now = (req.reply[3] << 24) + (req.reply[4] << 16)
100 + (req.reply[5] << 8) + req.reply[6];
101 return now - RTC_OFFSET;
102#endif /* CONFIG_ADB_CUDA */
103#ifdef CONFIG_ADB_PMU
104 case SYS_CTRLER_PMU:
105 if (pmu_request(&req, NULL, 1, PMU_READ_RTC) < 0)
106 return 0;
107 while (!req.complete)
108 pmu_poll();
109 if (req.reply_len != 4)
110 printk(KERN_ERR "pmac_get_rtc_time: got %d byte reply\n",
111 req.reply_len);
112 now = (req.reply[0] << 24) + (req.reply[1] << 16)
113 + (req.reply[2] << 8) + req.reply[3];
114 return now - RTC_OFFSET;
115#endif /* CONFIG_ADB_PMU */
116 default: ;
117 }
118 return 0;
119}
120
121int
122pmac_set_rtc_time(unsigned long nowtime)
123{
124#if defined(CONFIG_ADB_CUDA) || defined(CONFIG_ADB_PMU)
125 struct adb_request req;
126#endif
127
128 nowtime += RTC_OFFSET;
129
130 switch (sys_ctrler) {
131#ifdef CONFIG_ADB_CUDA
132 case SYS_CTRLER_CUDA:
133 if (cuda_request(&req, NULL, 6, CUDA_PACKET, CUDA_SET_TIME,
134 nowtime >> 24, nowtime >> 16, nowtime >> 8, nowtime) < 0)
135 return 0;
136 while (!req.complete)
137 cuda_poll();
138 if ((req.reply_len != 3) && (req.reply_len != 7))
139 printk(KERN_ERR "pmac_set_rtc_time: got %d byte reply\n",
140 req.reply_len);
141 return 1;
142#endif /* CONFIG_ADB_CUDA */
143#ifdef CONFIG_ADB_PMU
144 case SYS_CTRLER_PMU:
145 if (pmu_request(&req, NULL, 5, PMU_SET_RTC,
146 nowtime >> 24, nowtime >> 16, nowtime >> 8, nowtime) < 0)
147 return 0;
148 while (!req.complete)
149 pmu_poll();
150 if (req.reply_len != 0)
151 printk(KERN_ERR "pmac_set_rtc_time: got %d byte reply\n",
152 req.reply_len);
153 return 1;
154#endif /* CONFIG_ADB_PMU */
155 default:
156 return 0;
157 }
158}
159
160/*
161 * Calibrate the decrementer register using VIA timer 1.
162 * This is used both on powermacs and CHRP machines.
163 */
164int __init
165via_calibrate_decr(void)
166{
167 struct device_node *vias;
168 volatile unsigned char __iomem *via;
169 int count = VIA_TIMER_FREQ_6 / 100;
170 unsigned int dstart, dend;
171
172 vias = find_devices("via-cuda");
173 if (vias == 0)
174 vias = find_devices("via-pmu");
175 if (vias == 0)
176 vias = find_devices("via");
177 if (vias == 0 || vias->n_addrs == 0)
178 return 0;
179 via = ioremap(vias->addrs[0].address, vias->addrs[0].size);
180
181 /* set timer 1 for continuous interrupts */
182 out_8(&via[ACR], (via[ACR] & ~T1MODE) | T1MODE_CONT);
183 /* set the counter to a small value */
184 out_8(&via[T1CH], 2);
185 /* set the latch to `count' */
186 out_8(&via[T1LL], count);
187 out_8(&via[T1LH], count >> 8);
188 /* wait until it hits 0 */
189 while ((in_8(&via[IFR]) & T1_INT) == 0)
190 ;
191 dstart = get_dec();
192 /* clear the interrupt & wait until it hits 0 again */
193 in_8(&via[T1CL]);
194 while ((in_8(&via[IFR]) & T1_INT) == 0)
195 ;
196 dend = get_dec();
197
198 tb_ticks_per_jiffy = (dstart - dend) / (6 * (HZ/100));
199 tb_to_us = mulhwu_scale_factor(dstart - dend, 60000);
200
201 printk(KERN_INFO "via_calibrate_decr: ticks per jiffy = %u (%u ticks)\n",
202 tb_ticks_per_jiffy, dstart - dend);
203
204 iounmap(via);
205
206 return 1;
207}
208
209#ifdef CONFIG_PM
210/*
211 * Reset the time after a sleep.
212 */
213static int
214time_sleep_notify(struct pmu_sleep_notifier *self, int when)
215{
216 static unsigned long time_diff;
217 unsigned long flags;
218 unsigned long seq;
219
220 switch (when) {
221 case PBOOK_SLEEP_NOW:
222 do {
223 seq = read_seqbegin_irqsave(&xtime_lock, flags);
224 time_diff = xtime.tv_sec - pmac_get_rtc_time();
225 } while (read_seqretry_irqrestore(&xtime_lock, seq, flags));
226 break;
227 case PBOOK_WAKE:
228 write_seqlock_irqsave(&xtime_lock, flags);
229 xtime.tv_sec = pmac_get_rtc_time() + time_diff;
230 xtime.tv_nsec = 0;
231 last_rtc_update = xtime.tv_sec;
232 write_sequnlock_irqrestore(&xtime_lock, flags);
233 break;
234 }
235 return PBOOK_SLEEP_OK;
236}
237
238static struct pmu_sleep_notifier time_sleep_notifier = {
239 time_sleep_notify, SLEEP_LEVEL_MISC,
240};
241#endif /* CONFIG_PM */
242
243/*
244 * Query the OF and get the decr frequency.
245 * This was taken from the pmac time_init() when merging the prep/pmac
246 * time functions.
247 */
248void __init
249pmac_calibrate_decr(void)
250{
251 struct device_node *cpu;
252 unsigned int freq, *fp;
253
254#ifdef CONFIG_PM
255 pmu_register_sleep_notifier(&time_sleep_notifier);
256#endif /* CONFIG_PM */
257
258 /* We assume MacRISC2 machines have correct device-tree
259 * calibration. That's better since the VIA itself seems
260 * to be slightly off. --BenH
261 */
262 if (!machine_is_compatible("MacRISC2") &&
263 !machine_is_compatible("MacRISC3") &&
264 !machine_is_compatible("MacRISC4"))
265 if (via_calibrate_decr())
266 return;
267
268 /* Special case: QuickSilver G4s seem to have a badly calibrated
269 * timebase-frequency in OF, VIA is much better on these. We should
270 * probably implement calibration based on the KL timer on these
271 * machines anyway... -BenH
272 */
273 if (machine_is_compatible("PowerMac3,5"))
274 if (via_calibrate_decr())
275 return;
276 /*
277 * The cpu node should have a timebase-frequency property
278 * to tell us the rate at which the decrementer counts.
279 */
280 cpu = find_type_devices("cpu");
281 if (cpu == 0)
282 panic("can't find cpu node in time_init");
283 fp = (unsigned int *) get_property(cpu, "timebase-frequency", NULL);
284 if (fp == 0)
285 panic("can't get cpu timebase frequency");
286 freq = *fp;
287 printk("time_init: decrementer frequency = %u.%.6u MHz\n",
288 freq/1000000, freq%1000000);
289 tb_ticks_per_jiffy = freq / HZ;
290 tb_to_us = mulhwu_scale_factor(freq, 1000000);
291}
diff --git a/arch/powerpc/platforms/prep/Kconfig b/arch/powerpc/platforms/prep/Kconfig
new file mode 100644
index 000000000000..673ac47a1626
--- /dev/null
+++ b/arch/powerpc/platforms/prep/Kconfig
@@ -0,0 +1,22 @@
1
2config PREP_RESIDUAL
3 bool "Support for PReP Residual Data"
4 depends on PPC_PREP
5 help
6 Some PReP systems have residual data passed to the kernel by the
7 firmware. This allows detection of memory size, devices present and
8 other useful pieces of information. Sometimes this information is
9 not present or incorrect, in which case it could lead to the machine
10 behaving incorrectly. If this happens, either disable PREP_RESIDUAL
11 or pass the 'noresidual' option to the kernel.
12
13 If you are running a PReP system, say Y here, otherwise say N.
14
15config PROC_PREPRESIDUAL
16 bool "Support for reading of PReP Residual Data in /proc"
17 depends on PREP_RESIDUAL && PROC_FS
18 help
19 Enabling this option will create a /proc/residual file which allows
20 you to get at the residual data on PReP systems. You will need a tool
21 (lsresidual) to parse it. If you aren't on a PReP system, you don't
22 want this.
diff --git a/arch/powerpc/platforms/pseries/Kconfig b/arch/powerpc/platforms/pseries/Kconfig
new file mode 100644
index 000000000000..7a3b6fc4d976
--- /dev/null
+++ b/arch/powerpc/platforms/pseries/Kconfig
@@ -0,0 +1,47 @@
1
2config PPC_SPLPAR
3 depends on PPC_PSERIES
4 bool "Support for shared-processor logical partitions"
5 default n
6 help
7 Enabling this option will make the kernel run more efficiently
8 on logically-partitioned pSeries systems which use shared
9 processors, that is, which share physical processors between
10 two or more partitions.
11
12config HMT
13 bool "Hardware multithreading"
14 depends on SMP && PPC_PSERIES && BROKEN
15 help
16 This option enables hardware multithreading on RS64 cpus.
17 pSeries systems p620 and p660 have such a cpu type.
18
19config EEH
20 bool "PCI Extended Error Handling (EEH)" if EMBEDDED
21 depends on PPC_PSERIES
22 default y if !EMBEDDED
23
24config PPC_RTAS
25 bool
26 depends on PPC_PSERIES || PPC_BPA
27 default y
28
29config RTAS_PROC
30 bool "Proc interface to RTAS"
31 depends on PPC_RTAS
32 default y
33
34config RTAS_FLASH
35 tristate "Firmware flash interface"
36 depends on PPC64 && RTAS_PROC
37
38config SCANLOG
39 tristate "Scanlog dump interface"
40 depends on RTAS_PROC && PPC_PSERIES
41
42config LPARCFG
43 tristate "LPAR Configuration Data"
44 depends on PPC_PSERIES || PPC_ISERIES
45 help
46 Provide system capacity information via human readable
47 <key word>=<value> pairs through a /proc/ppc64/lparcfg interface.
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-03 12:12:28 -0500