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authorArnd Bergmann <arnd@arndb.de>2014-03-17 10:17:07 -0400
committerArnd Bergmann <arnd@arndb.de>2014-03-17 10:17:07 -0400
commit38edc2da5014e70e46a724d97c3ef3dde106331b (patch)
tree590499bacd062e8dd74c6f05a7d811dd714a2d70 /arch/powerpc/platforms/pseries/pci.c
parent937b5991ca7717ceba99014f2ad3f51c85cdb9ad (diff)
parent28b191118c11719bb27db621425a70be28a40e08 (diff)
Merge tag 'omap-for-v3.15/dt-overo-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
Updates to the .dts files to support more Gumstix boards. These are sent separately from the rest of the .dts changes as these depend on the fixes merged into v3.14-rc4, and needed a bit more time to get updated on the fixes. * tag 'omap-for-v3.15/dt-overo-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: Add support for the Overo Summit ARM: dts: Add support for the Overo Chestnut43 ARM: dts: Add support for the Overo Alto35 ARM: dts: Add support for the Overo Gallop43 ARM: dts: Add support for the Overo Palo43 ARM: dts: overo: Add LIS33DE accelerometer ARM: dts: overo: Create a file for common Gumstix peripherals ARM: dts: overo: Push uart3 pinmux down to expansion board ARM: dts: omap3-tobi: Add AT24C01 EEPROM ARM: dts: omap3-tobi: Use include file omap-gpmc-smsc9221 ARM: dts: omap: Add common file for SMSC9221 ARM: dts: omap3-overo: Add HSUSB PHY ARM: dts: omap3-overo: Enable WiFi/BT combo ARM: dts: omap3-overo: Add missing pinctrl ARM: dts: omap3-tobi: Add missing pinctrl ARM: dts: overo: reorganize include files Signed-off-by: Arnd Bergmann <arnd@arndb.de> Conflicts: arch/arm/boot/dts/omap3-overo.dtsi
Diffstat (limited to 'arch/powerpc/platforms/pseries/pci.c')
-rw-r--r--arch/powerpc/platforms/pseries/pci.c22
1 files changed, 15 insertions, 7 deletions
diff --git a/arch/powerpc/platforms/pseries/pci.c b/arch/powerpc/platforms/pseries/pci.c
index 70670a2d9cf2..c413ec158ff5 100644
--- a/arch/powerpc/platforms/pseries/pci.c
+++ b/arch/powerpc/platforms/pseries/pci.c
@@ -113,7 +113,8 @@ int pseries_root_bridge_prepare(struct pci_host_bridge *bridge)
113{ 113{
114 struct device_node *dn, *pdn; 114 struct device_node *dn, *pdn;
115 struct pci_bus *bus; 115 struct pci_bus *bus;
116 const __be32 *pcie_link_speed_stats; 116 u32 pcie_link_speed_stats[2];
117 int rc;
117 118
118 bus = bridge->bus; 119 bus = bridge->bus;
119 120
@@ -122,38 +123,45 @@ int pseries_root_bridge_prepare(struct pci_host_bridge *bridge)
122 return 0; 123 return 0;
123 124
124 for (pdn = dn; pdn != NULL; pdn = of_get_next_parent(pdn)) { 125 for (pdn = dn; pdn != NULL; pdn = of_get_next_parent(pdn)) {
125 pcie_link_speed_stats = of_get_property(pdn, 126 rc = of_property_read_u32_array(pdn,
126 "ibm,pcie-link-speed-stats", NULL); 127 "ibm,pcie-link-speed-stats",
127 if (pcie_link_speed_stats) 128 &pcie_link_speed_stats[0], 2);
129 if (!rc)
128 break; 130 break;
129 } 131 }
130 132
131 of_node_put(pdn); 133 of_node_put(pdn);
132 134
133 if (!pcie_link_speed_stats) { 135 if (rc) {
134 pr_err("no ibm,pcie-link-speed-stats property\n"); 136 pr_err("no ibm,pcie-link-speed-stats property\n");
135 return 0; 137 return 0;
136 } 138 }
137 139
138 switch (be32_to_cpup(pcie_link_speed_stats)) { 140 switch (pcie_link_speed_stats[0]) {
139 case 0x01: 141 case 0x01:
140 bus->max_bus_speed = PCIE_SPEED_2_5GT; 142 bus->max_bus_speed = PCIE_SPEED_2_5GT;
141 break; 143 break;
142 case 0x02: 144 case 0x02:
143 bus->max_bus_speed = PCIE_SPEED_5_0GT; 145 bus->max_bus_speed = PCIE_SPEED_5_0GT;
144 break; 146 break;
147 case 0x04:
148 bus->max_bus_speed = PCIE_SPEED_8_0GT;
149 break;
145 default: 150 default:
146 bus->max_bus_speed = PCI_SPEED_UNKNOWN; 151 bus->max_bus_speed = PCI_SPEED_UNKNOWN;
147 break; 152 break;
148 } 153 }
149 154
150 switch (be32_to_cpup(pcie_link_speed_stats)) { 155 switch (pcie_link_speed_stats[1]) {
151 case 0x01: 156 case 0x01:
152 bus->cur_bus_speed = PCIE_SPEED_2_5GT; 157 bus->cur_bus_speed = PCIE_SPEED_2_5GT;
153 break; 158 break;
154 case 0x02: 159 case 0x02:
155 bus->cur_bus_speed = PCIE_SPEED_5_0GT; 160 bus->cur_bus_speed = PCIE_SPEED_5_0GT;
156 break; 161 break;
162 case 0x04:
163 bus->cur_bus_speed = PCIE_SPEED_8_0GT;
164 break;
157 default: 165 default:
158 bus->cur_bus_speed = PCI_SPEED_UNKNOWN; 166 bus->cur_bus_speed = PCI_SPEED_UNKNOWN;
159 break; 167 break;