powerpc/eeh: Make the delay for PE reset unified

Basically, we have 3 types of resets to fulfil PE reset: fundamental,
hot and PHB reset. For the later 2 cases, we need PCI bus reset hold
and settlement delay as specified by PCI spec. PowerNV and pSeries
platforms are running on top of different firmware and some of the
delays have been covered by underly firmware (PowerNV).

The patch makes the delays unified to be done in backend, instead of
EEH core.

Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

1 files changed, 9 insertions, 1 deletions

diff --git a/arch/powerpc/platforms/pseries/eeh_pseries.c b/arch/powerpc/platforms/pseries/eeh_pseries.c
index 2f1ba64fc831..0bec0c02c5e7 100644
--- a/arch/powerpc/platforms/pseries/eeh_pseries.c
+++ b/arch/powerpc/platforms/pseries/eeh_pseries.c
@@ -532,11 +532,19 @@ static int pseries_eeh_reset(struct eeh_pe *pe, int option)
         /* If fundamental-reset not supported, try hot-reset */
         if (option == EEH_RESET_FUNDAMENTAL &&
             ret == -8) {
+                option = EEH_RESET_HOT;
                 ret = rtas_call(ibm_set_slot_reset, 4, 1, NULL,
                                 config_addr, BUID_HI(pe->phb->buid),
-                                BUID_LO(pe->phb->buid), EEH_RESET_HOT);
+                                BUID_LO(pe->phb->buid), option);
         }
 
+        /* We need reset hold or settlement delay */
+        if (option == EEH_RESET_FUNDAMENTAL ||
+            option == EEH_RESET_HOT)
+                msleep(EEH_PE_RST_HOLD_TIME);
+        else
+                msleep(EEH_PE_RST_SETTLE_TIME);
+
         return ret;
 }