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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2009-07-16 15:36:57 -0400
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2009-08-19 20:12:28 -0400
commitc5a8c0c99f67ae8a784faafbaaea1529825796e2 (patch)
tree731b07d0ac0414dbeac5ce940fe59a04a8d63c3f /arch/powerpc/platforms/iseries
parentee43eb788b3a06425fffb912677e2e1c8b00dd3b (diff)
powerpc: Remove use of a second scratch SPRG in STAB code
The STAB code used on Power3 and RS/64 uses a second scratch SPRG to save a GPR in order to decide whether to go to do_stab_bolted_* or to handle a normal data access exception. This prevents our scheme of freeing SPRG3 which is user visible for user uses since we cannot use SPRG0 which, on RS/64, seems to be read-only for supervisor mode (like POWER4). This reworks the STAB exception entry to use the PACA as temporary storage instead. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/platforms/iseries')
-rw-r--r--arch/powerpc/platforms/iseries/exception.S37
1 files changed, 24 insertions, 13 deletions
diff --git a/arch/powerpc/platforms/iseries/exception.S b/arch/powerpc/platforms/iseries/exception.S
index 2b8075979237..5369653dcf6a 100644
--- a/arch/powerpc/platforms/iseries/exception.S
+++ b/arch/powerpc/platforms/iseries/exception.S
@@ -128,25 +128,36 @@ iSeries_secondary_smp_loop:
128data_access_iSeries: 128data_access_iSeries:
129 mtspr SPRN_SPRG_SCRATCH0,r13 129 mtspr SPRN_SPRG_SCRATCH0,r13
130BEGIN_FTR_SECTION 130BEGIN_FTR_SECTION
131 mtspr SPRN_SPRG_SCRATCH1,r12 131 mfspr r13,SPRN_SPRG_PACA
132 mfspr r13,SPRN_DAR 132 std r9,PACA_EXSLB+EX_R9(r13)
133 mfspr r12,SPRN_DSISR 133 std r10,PACA_EXSLB+EX_R10(r13)
134 srdi r13,r13,60 134 mfspr r10,SPRN_DAR
135 rlwimi r13,r12,16,0x20 135 mfspr r9,SPRN_DSISR
136 mfcr r12 136 srdi r10,r10,60
137 cmpwi r13,0x2c 137 rlwimi r10,r9,16,0x20
138 mfcr r9
139 cmpwi r10,0x2c
138 beq .do_stab_bolted_iSeries 140 beq .do_stab_bolted_iSeries
139 mtcrf 0x80,r12 141 ld r10,PACA_EXSLB+EX_R10(r13)
140 mfspr r12,SPRN_SPRG_SCRATCH1 142 std r11,PACA_EXGEN+EX_R11(r13)
141END_FTR_SECTION_IFCLR(CPU_FTR_SLB) 143 ld r11,PACA_EXSLB+EX_R9(r13)
144 std r12,PACA_EXGEN+EX_R12(r13)
145 mfspr r12,SPRN_SPRG_SCRATCH0
146 std r10,PACA_EXGEN+EX_R10(r13)
147 std r11,PACA_EXGEN+EX_R9(r13)
148 std r12,PACA_EXGEN+EX_R13(r13)
149 EXCEPTION_PROLOG_ISERIES_1
150FTR_SECTION_ELSE
142 EXCEPTION_PROLOG_1(PACA_EXGEN) 151 EXCEPTION_PROLOG_1(PACA_EXGEN)
143 EXCEPTION_PROLOG_ISERIES_1 152 EXCEPTION_PROLOG_ISERIES_1
153ALT_FTR_SECTION_END_IFCLR(CPU_FTR_SLB)
144 b data_access_common 154 b data_access_common
145 155
146.do_stab_bolted_iSeries: 156.do_stab_bolted_iSeries:
147 mtcrf 0x80,r12 157 std r11,PACA_EXSLB+EX_R11(r13)
148 mfspr r12,SPRN_SPRG_SCRATCH1 158 std r12,PACA_EXSLB+EX_R12(r13)
149 EXCEPTION_PROLOG_1(PACA_EXSLB) 159 mfspr r10,SPRN_SPRG_SCRATCH0
160 std r10,PACA_EXSLB+EX_R13(r13)
150 EXCEPTION_PROLOG_ISERIES_1 161 EXCEPTION_PROLOG_ISERIES_1
151 b .do_stab_bolted 162 b .do_stab_bolted
152 163