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authorMichael Ellerman <mpe@ellerman.id.au>2015-03-19 00:15:20 -0400
committerMichael Ellerman <mpe@ellerman.id.au>2015-04-07 03:15:13 -0400
commitbf4981a00636347ddcef3fc008e4dd979380a851 (patch)
treef0493e9836174d170dafc2576ce6838f41f435c3 /arch/powerpc/platforms/cell/celleb_scc_pciex.c
parent646b54f2f2041473495f166479e3e17fd59a9dd1 (diff)
powerpc: Remove the celleb support
The celleb code has seen no actual development for ~7 years. We (maintainers) have no access to test hardware, and it is highly likely the code has bit-rotted. As far as we're aware the hardware was never widely available, and is certainly no longer available, and no one on the list has shown any interest in it over the years. So remove it. If anyone has one and cares please speak up. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Jeremy Kerr <jk@ozlabs.org>
Diffstat (limited to 'arch/powerpc/platforms/cell/celleb_scc_pciex.c')
-rw-r--r--arch/powerpc/platforms/cell/celleb_scc_pciex.c538
1 files changed, 0 insertions, 538 deletions
diff --git a/arch/powerpc/platforms/cell/celleb_scc_pciex.c b/arch/powerpc/platforms/cell/celleb_scc_pciex.c
deleted file mode 100644
index 94170e4f2ce7..000000000000
--- a/arch/powerpc/platforms/cell/celleb_scc_pciex.c
+++ /dev/null
@@ -1,538 +0,0 @@
1/*
2 * Support for Celleb PCI-Express.
3 *
4 * (C) Copyright 2007-2008 TOSHIBA CORPORATION
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#undef DEBUG
22
23#include <linux/kernel.h>
24#include <linux/pci.h>
25#include <linux/string.h>
26#include <linux/slab.h>
27#include <linux/init.h>
28#include <linux/delay.h>
29#include <linux/interrupt.h>
30
31#include <asm/io.h>
32#include <asm/irq.h>
33#include <asm/iommu.h>
34#include <asm/byteorder.h>
35
36#include "celleb_scc.h"
37#include "celleb_pci.h"
38
39#define PEX_IN(base, off) in_be32((void __iomem *)(base) + (off))
40#define PEX_OUT(base, off, data) out_be32((void __iomem *)(base) + (off), (data))
41
42static void scc_pciex_io_flush(struct iowa_bus *bus)
43{
44 (void)PEX_IN(bus->phb->cfg_addr, PEXDMRDEN0);
45}
46
47/*
48 * Memory space access to device on PCIEX
49 */
50#define PCIEX_MMIO_READ(name, ret) \
51static ret scc_pciex_##name(const PCI_IO_ADDR addr) \
52{ \
53 ret val = __do_##name(addr); \
54 scc_pciex_io_flush(iowa_mem_find_bus(addr)); \
55 return val; \
56}
57
58#define PCIEX_MMIO_READ_STR(name) \
59static void scc_pciex_##name(const PCI_IO_ADDR addr, void *buf, \
60 unsigned long count) \
61{ \
62 __do_##name(addr, buf, count); \
63 scc_pciex_io_flush(iowa_mem_find_bus(addr)); \
64}
65
66PCIEX_MMIO_READ(readb, u8)
67PCIEX_MMIO_READ(readw, u16)
68PCIEX_MMIO_READ(readl, u32)
69PCIEX_MMIO_READ(readq, u64)
70PCIEX_MMIO_READ(readw_be, u16)
71PCIEX_MMIO_READ(readl_be, u32)
72PCIEX_MMIO_READ(readq_be, u64)
73PCIEX_MMIO_READ_STR(readsb)
74PCIEX_MMIO_READ_STR(readsw)
75PCIEX_MMIO_READ_STR(readsl)
76
77static void scc_pciex_memcpy_fromio(void *dest, const PCI_IO_ADDR src,
78 unsigned long n)
79{
80 __do_memcpy_fromio(dest, src, n);
81 scc_pciex_io_flush(iowa_mem_find_bus(src));
82}
83
84/*
85 * I/O port access to devices on PCIEX.
86 */
87
88static inline unsigned long get_bus_address(struct pci_controller *phb,
89 unsigned long port)
90{
91 return port - ((unsigned long)(phb->io_base_virt) - _IO_BASE);
92}
93
94static u32 scc_pciex_read_port(struct pci_controller *phb,
95 unsigned long port, int size)
96{
97 unsigned int byte_enable;
98 unsigned int cmd, shift;
99 unsigned long addr;
100 u32 data, ret;
101
102 BUG_ON(((port & 0x3ul) + size) > 4);
103
104 addr = get_bus_address(phb, port);
105 shift = addr & 0x3ul;
106 byte_enable = ((1 << size) - 1) << shift;
107 cmd = PEXDCMND_IO_READ | (byte_enable << PEXDCMND_BYTE_EN_SHIFT);
108 PEX_OUT(phb->cfg_addr, PEXDADRS, (addr & ~0x3ul));
109 PEX_OUT(phb->cfg_addr, PEXDCMND, cmd);
110 data = PEX_IN(phb->cfg_addr, PEXDRDATA);
111 ret = (data >> (shift * 8)) & (0xFFFFFFFF >> ((4 - size) * 8));
112
113 pr_debug("PCIEX:PIO READ:port=0x%lx, addr=0x%lx, size=%d, be=%x,"
114 " cmd=%x, data=%x, ret=%x\n", port, addr, size, byte_enable,
115 cmd, data, ret);
116
117 return ret;
118}
119
120static void scc_pciex_write_port(struct pci_controller *phb,
121 unsigned long port, int size, u32 val)
122{
123 unsigned int byte_enable;
124 unsigned int cmd, shift;
125 unsigned long addr;
126 u32 data;
127
128 BUG_ON(((port & 0x3ul) + size) > 4);
129
130 addr = get_bus_address(phb, port);
131 shift = addr & 0x3ul;
132 byte_enable = ((1 << size) - 1) << shift;
133 cmd = PEXDCMND_IO_WRITE | (byte_enable << PEXDCMND_BYTE_EN_SHIFT);
134 data = (val & (0xFFFFFFFF >> (4 - size) * 8)) << (shift * 8);
135 PEX_OUT(phb->cfg_addr, PEXDADRS, (addr & ~0x3ul));
136 PEX_OUT(phb->cfg_addr, PEXDCMND, cmd);
137 PEX_OUT(phb->cfg_addr, PEXDWDATA, data);
138
139 pr_debug("PCIEX:PIO WRITE:port=0x%lx, addr=%lx, size=%d, val=%x,"
140 " be=%x, cmd=%x, data=%x\n", port, addr, size, val,
141 byte_enable, cmd, data);
142}
143
144static u8 __scc_pciex_inb(struct pci_controller *phb, unsigned long port)
145{
146 return (u8)scc_pciex_read_port(phb, port, 1);
147}
148
149static u16 __scc_pciex_inw(struct pci_controller *phb, unsigned long port)
150{
151 u32 data;
152 if ((port & 0x3ul) < 3)
153 data = scc_pciex_read_port(phb, port, 2);
154 else {
155 u32 d1 = scc_pciex_read_port(phb, port, 1);
156 u32 d2 = scc_pciex_read_port(phb, port + 1, 1);
157 data = d1 | (d2 << 8);
158 }
159 return (u16)data;
160}
161
162static u32 __scc_pciex_inl(struct pci_controller *phb, unsigned long port)
163{
164 unsigned int mod = port & 0x3ul;
165 u32 data;
166 if (mod == 0)
167 data = scc_pciex_read_port(phb, port, 4);
168 else {
169 u32 d1 = scc_pciex_read_port(phb, port, 4 - mod);
170 u32 d2 = scc_pciex_read_port(phb, port + 1, mod);
171 data = d1 | (d2 << (mod * 8));
172 }
173 return data;
174}
175
176static void __scc_pciex_outb(struct pci_controller *phb,
177 u8 val, unsigned long port)
178{
179 scc_pciex_write_port(phb, port, 1, (u32)val);
180}
181
182static void __scc_pciex_outw(struct pci_controller *phb,
183 u16 val, unsigned long port)
184{
185 if ((port & 0x3ul) < 3)
186 scc_pciex_write_port(phb, port, 2, (u32)val);
187 else {
188 u32 d1 = val & 0x000000FF;
189 u32 d2 = (val & 0x0000FF00) >> 8;
190 scc_pciex_write_port(phb, port, 1, d1);
191 scc_pciex_write_port(phb, port + 1, 1, d2);
192 }
193}
194
195static void __scc_pciex_outl(struct pci_controller *phb,
196 u32 val, unsigned long port)
197{
198 unsigned int mod = port & 0x3ul;
199 if (mod == 0)
200 scc_pciex_write_port(phb, port, 4, val);
201 else {
202 u32 d1 = val & (0xFFFFFFFFul >> (mod * 8));
203 u32 d2 = val >> ((4 - mod) * 8);
204 scc_pciex_write_port(phb, port, 4 - mod, d1);
205 scc_pciex_write_port(phb, port + 1, mod, d2);
206 }
207}
208
209#define PCIEX_PIO_FUNC(size, name) \
210static u##size scc_pciex_in##name(unsigned long port) \
211{ \
212 struct iowa_bus *bus = iowa_pio_find_bus(port); \
213 u##size data = __scc_pciex_in##name(bus->phb, port); \
214 scc_pciex_io_flush(bus); \
215 return data; \
216} \
217static void scc_pciex_ins##name(unsigned long p, void *b, unsigned long c) \
218{ \
219 struct iowa_bus *bus = iowa_pio_find_bus(p); \
220 __le##size *dst = b; \
221 for (; c != 0; c--, dst++) \
222 *dst = cpu_to_le##size(__scc_pciex_in##name(bus->phb, p)); \
223 scc_pciex_io_flush(bus); \
224} \
225static void scc_pciex_out##name(u##size val, unsigned long port) \
226{ \
227 struct iowa_bus *bus = iowa_pio_find_bus(port); \
228 __scc_pciex_out##name(bus->phb, val, port); \
229} \
230static void scc_pciex_outs##name(unsigned long p, const void *b, \
231 unsigned long c) \
232{ \
233 struct iowa_bus *bus = iowa_pio_find_bus(p); \
234 const __le##size *src = b; \
235 for (; c != 0; c--, src++) \
236 __scc_pciex_out##name(bus->phb, le##size##_to_cpu(*src), p); \
237}
238#define __le8 u8
239#define cpu_to_le8(x) (x)
240#define le8_to_cpu(x) (x)
241PCIEX_PIO_FUNC(8, b)
242PCIEX_PIO_FUNC(16, w)
243PCIEX_PIO_FUNC(32, l)
244
245static struct ppc_pci_io scc_pciex_ops = {
246 .readb = scc_pciex_readb,
247 .readw = scc_pciex_readw,
248 .readl = scc_pciex_readl,
249 .readq = scc_pciex_readq,
250 .readw_be = scc_pciex_readw_be,
251 .readl_be = scc_pciex_readl_be,
252 .readq_be = scc_pciex_readq_be,
253 .readsb = scc_pciex_readsb,
254 .readsw = scc_pciex_readsw,
255 .readsl = scc_pciex_readsl,
256 .memcpy_fromio = scc_pciex_memcpy_fromio,
257 .inb = scc_pciex_inb,
258 .inw = scc_pciex_inw,
259 .inl = scc_pciex_inl,
260 .outb = scc_pciex_outb,
261 .outw = scc_pciex_outw,
262 .outl = scc_pciex_outl,
263 .insb = scc_pciex_insb,
264 .insw = scc_pciex_insw,
265 .insl = scc_pciex_insl,
266 .outsb = scc_pciex_outsb,
267 .outsw = scc_pciex_outsw,
268 .outsl = scc_pciex_outsl,
269};
270
271static int __init scc_pciex_iowa_init(struct iowa_bus *bus, void *data)
272{
273 dma_addr_t dummy_page_da;
274 void *dummy_page_va;
275
276 dummy_page_va = kmalloc(PAGE_SIZE, GFP_KERNEL);
277 if (!dummy_page_va) {
278 pr_err("PCIEX:Alloc dummy_page_va failed\n");
279 return -1;
280 }
281
282 dummy_page_da = dma_map_single(bus->phb->parent, dummy_page_va,
283 PAGE_SIZE, DMA_FROM_DEVICE);
284 if (dma_mapping_error(bus->phb->parent, dummy_page_da)) {
285 pr_err("PCIEX:Map dummy page failed.\n");
286 kfree(dummy_page_va);
287 return -1;
288 }
289
290 PEX_OUT(bus->phb->cfg_addr, PEXDMRDADR0, dummy_page_da);
291
292 return 0;
293}
294
295/*
296 * config space access
297 */
298#define MK_PEXDADRS(bus_no, dev_no, func_no, addr) \
299 ((uint32_t)(((addr) & ~0x3UL) | \
300 ((bus_no) << PEXDADRS_BUSNO_SHIFT) | \
301 ((dev_no) << PEXDADRS_DEVNO_SHIFT) | \
302 ((func_no) << PEXDADRS_FUNCNO_SHIFT)))
303
304#define MK_PEXDCMND_BYTE_EN(addr, size) \
305 ((((0x1 << (size))-1) << ((addr) & 0x3)) << PEXDCMND_BYTE_EN_SHIFT)
306#define MK_PEXDCMND(cmd, addr, size) ((cmd) | MK_PEXDCMND_BYTE_EN(addr, size))
307
308static uint32_t config_read_pciex_dev(unsigned int __iomem *base,
309 uint64_t bus_no, uint64_t dev_no, uint64_t func_no,
310 uint64_t off, uint64_t size)
311{
312 uint32_t ret;
313 uint32_t addr, cmd;
314
315 addr = MK_PEXDADRS(bus_no, dev_no, func_no, off);
316 cmd = MK_PEXDCMND(PEXDCMND_CONFIG_READ, off, size);
317 PEX_OUT(base, PEXDADRS, addr);
318 PEX_OUT(base, PEXDCMND, cmd);
319 ret = (PEX_IN(base, PEXDRDATA)
320 >> ((off & (4-size)) * 8)) & ((0x1 << (size * 8)) - 1);
321 return ret;
322}
323
324static void config_write_pciex_dev(unsigned int __iomem *base, uint64_t bus_no,
325 uint64_t dev_no, uint64_t func_no, uint64_t off, uint64_t size,
326 uint32_t data)
327{
328 uint32_t addr, cmd;
329
330 addr = MK_PEXDADRS(bus_no, dev_no, func_no, off);
331 cmd = MK_PEXDCMND(PEXDCMND_CONFIG_WRITE, off, size);
332 PEX_OUT(base, PEXDADRS, addr);
333 PEX_OUT(base, PEXDCMND, cmd);
334 PEX_OUT(base, PEXDWDATA,
335 (data & ((0x1 << (size * 8)) - 1)) << ((off & (4-size)) * 8));
336}
337
338#define MK_PEXCADRS_BYTE_EN(off, len) \
339 ((((0x1 << (len)) - 1) << ((off) & 0x3)) << PEXCADRS_BYTE_EN_SHIFT)
340#define MK_PEXCADRS(cmd, addr, size) \
341 ((cmd) | MK_PEXCADRS_BYTE_EN(addr, size) | ((addr) & ~0x3))
342static uint32_t config_read_pciex_rc(unsigned int __iomem *base,
343 uint32_t where, uint32_t size)
344{
345 PEX_OUT(base, PEXCADRS, MK_PEXCADRS(PEXCADRS_CMD_READ, where, size));
346 return (PEX_IN(base, PEXCRDATA)
347 >> ((where & (4 - size)) * 8)) & ((0x1 << (size * 8)) - 1);
348}
349
350static void config_write_pciex_rc(unsigned int __iomem *base, uint32_t where,
351 uint32_t size, uint32_t val)
352{
353 uint32_t data;
354
355 data = (val & ((0x1 << (size * 8)) - 1)) << ((where & (4 - size)) * 8);
356 PEX_OUT(base, PEXCADRS, MK_PEXCADRS(PEXCADRS_CMD_WRITE, where, size));
357 PEX_OUT(base, PEXCWDATA, data);
358}
359
360/* Interfaces */
361/* Note: Work-around
362 * On SCC PCIEXC, one device is seen on all 32 dev_no.
363 * As SCC PCIEXC can have only one device on the bus, we look only one dev_no.
364 * (dev_no = 1)
365 */
366static int scc_pciex_read_config(struct pci_bus *bus, unsigned int devfn,
367 int where, int size, unsigned int *val)
368{
369 struct pci_controller *phb = pci_bus_to_host(bus);
370
371 if (bus->number == phb->first_busno && PCI_SLOT(devfn) != 1) {
372 *val = ~0;
373 return PCIBIOS_DEVICE_NOT_FOUND;
374 }
375
376 if (bus->number == 0 && PCI_SLOT(devfn) == 0)
377 *val = config_read_pciex_rc(phb->cfg_addr, where, size);
378 else
379 *val = config_read_pciex_dev(phb->cfg_addr, bus->number,
380 PCI_SLOT(devfn), PCI_FUNC(devfn), where, size);
381
382 return PCIBIOS_SUCCESSFUL;
383}
384
385static int scc_pciex_write_config(struct pci_bus *bus, unsigned int devfn,
386 int where, int size, unsigned int val)
387{
388 struct pci_controller *phb = pci_bus_to_host(bus);
389
390 if (bus->number == phb->first_busno && PCI_SLOT(devfn) != 1)
391 return PCIBIOS_DEVICE_NOT_FOUND;
392
393 if (bus->number == 0 && PCI_SLOT(devfn) == 0)
394 config_write_pciex_rc(phb->cfg_addr, where, size, val);
395 else
396 config_write_pciex_dev(phb->cfg_addr, bus->number,
397 PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, val);
398 return PCIBIOS_SUCCESSFUL;
399}
400
401static struct pci_ops scc_pciex_pci_ops = {
402 .read = scc_pciex_read_config,
403 .write = scc_pciex_write_config,
404};
405
406static void pciex_clear_intr_all(unsigned int __iomem *base)
407{
408 PEX_OUT(base, PEXAERRSTS, 0xffffffff);
409 PEX_OUT(base, PEXPRERRSTS, 0xffffffff);
410 PEX_OUT(base, PEXINTSTS, 0xffffffff);
411}
412
413#if 0
414static void pciex_disable_intr_all(unsigned int *base)
415{
416 PEX_OUT(base, PEXINTMASK, 0x0);
417 PEX_OUT(base, PEXAERRMASK, 0x0);
418 PEX_OUT(base, PEXPRERRMASK, 0x0);
419 PEX_OUT(base, PEXVDMASK, 0x0);
420}
421#endif
422
423static void pciex_enable_intr_all(unsigned int __iomem *base)
424{
425 PEX_OUT(base, PEXINTMASK, 0x0000e7f1);
426 PEX_OUT(base, PEXAERRMASK, 0x03ff01ff);
427 PEX_OUT(base, PEXPRERRMASK, 0x0001010f);
428 PEX_OUT(base, PEXVDMASK, 0x00000001);
429}
430
431static void pciex_check_status(unsigned int __iomem *base)
432{
433 uint32_t err = 0;
434 uint32_t intsts, aerr, prerr, rcvcp, lenerr;
435 uint32_t maea, maec;
436
437 intsts = PEX_IN(base, PEXINTSTS);
438 aerr = PEX_IN(base, PEXAERRSTS);
439 prerr = PEX_IN(base, PEXPRERRSTS);
440 rcvcp = PEX_IN(base, PEXRCVCPLIDA);
441 lenerr = PEX_IN(base, PEXLENERRIDA);
442
443 if (intsts || aerr || prerr || rcvcp || lenerr)
444 err = 1;
445
446 pr_info("PCEXC interrupt!!\n");
447 pr_info("PEXINTSTS :0x%08x\n", intsts);
448 pr_info("PEXAERRSTS :0x%08x\n", aerr);
449 pr_info("PEXPRERRSTS :0x%08x\n", prerr);
450 pr_info("PEXRCVCPLIDA :0x%08x\n", rcvcp);
451 pr_info("PEXLENERRIDA :0x%08x\n", lenerr);
452
453 /* print detail of Protection Error */
454 if (intsts & 0x00004000) {
455 uint32_t i, n;
456 for (i = 0; i < 4; i++) {
457 n = 1 << i;
458 if (prerr & n) {
459 maea = PEX_IN(base, PEXMAEA(i));
460 maec = PEX_IN(base, PEXMAEC(i));
461 pr_info("PEXMAEC%d :0x%08x\n", i, maec);
462 pr_info("PEXMAEA%d :0x%08x\n", i, maea);
463 }
464 }
465 }
466
467 if (err)
468 pciex_clear_intr_all(base);
469}
470
471static irqreturn_t pciex_handle_internal_irq(int irq, void *dev_id)
472{
473 struct pci_controller *phb = dev_id;
474
475 pr_debug("PCIEX:pciex_handle_internal_irq(irq=%d)\n", irq);
476
477 BUG_ON(phb->cfg_addr == NULL);
478
479 pciex_check_status(phb->cfg_addr);
480
481 return IRQ_HANDLED;
482}
483
484static __init int celleb_setup_pciex(struct device_node *node,
485 struct pci_controller *phb)
486{
487 struct resource r;
488 int virq;
489
490 /* SMMIO registers; used inside this file */
491 if (of_address_to_resource(node, 0, &r)) {
492 pr_err("PCIEXC:Failed to get config resource.\n");
493 return 1;
494 }
495 phb->cfg_addr = ioremap(r.start, resource_size(&r));
496 if (!phb->cfg_addr) {
497 pr_err("PCIEXC:Failed to remap SMMIO region.\n");
498 return 1;
499 }
500
501 /* Not use cfg_data, cmd and data regs are near address reg */
502 phb->cfg_data = NULL;
503
504 /* set pci_ops */
505 phb->ops = &scc_pciex_pci_ops;
506
507 /* internal interrupt handler */
508 virq = irq_of_parse_and_map(node, 1);
509 if (!virq) {
510 pr_err("PCIEXC:Failed to map irq\n");
511 goto error;
512 }
513 if (request_irq(virq, pciex_handle_internal_irq,
514 0, "pciex", (void *)phb)) {
515 pr_err("PCIEXC:Failed to request irq\n");
516 goto error;
517 }
518
519 /* enable all interrupts */
520 pciex_clear_intr_all(phb->cfg_addr);
521 pciex_enable_intr_all(phb->cfg_addr);
522 /* MSI: TBD */
523
524 return 0;
525
526error:
527 phb->cfg_data = NULL;
528 if (phb->cfg_addr)
529 iounmap(phb->cfg_addr);
530 phb->cfg_addr = NULL;
531 return 1;
532}
533
534struct celleb_phb_spec celleb_pciex_spec __initdata = {
535 .setup = celleb_setup_pciex,
536 .ops = &scc_pciex_ops,
537 .iowa_init = &scc_pciex_iowa_init,
538};
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-30 00:19:44 -0400