[POWERPC] celleb: Add support for PCI Express

This adds support for PCI Express port on Celleb.  I/O space of this
PCI Express port is not mapped in memory space.  So we use the
io-workaround mechanism to make accesses indirect.

Signed-off-by: Kou Ishizaki <kou.ishizaki@toshiba.co.jp>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Paul Mackerras <paulus@samba.org>

1 files changed, 87 insertions, 0 deletions

diff --git a/arch/powerpc/platforms/cell/celleb_scc.h b/arch/powerpc/platforms/cell/celleb_scc.h
index 6be1542a6e66..b596a711c348 100644
--- a/arch/powerpc/platforms/cell/celleb_scc.h
+++ b/arch/powerpc/platforms/cell/celleb_scc.h
@@ -125,6 +125,93 @@
 /* bits for SCC_EPCI_CNTOPT */
 #define SCC_EPCI_CNTOPT_O2PMB   0x00000002
 
+/* SCC PCIEXC SMMIO registers */
+#define PEXCADRS                0x000
+#define PEXCWDATA               0x004
+#define PEXCRDATA               0x008
+#define PEXDADRS                0x010
+#define PEXDCMND                0x014
+#define PEXDWDATA               0x018
+#define PEXDRDATA               0x01c
+#define PEXREQID                0x020
+#define PEXTIDMAP               0x024
+#define PEXINTMASK              0x028
+#define PEXINTSTS               0x02c
+#define PEXAERRMASK             0x030
+#define PEXAERRSTS              0x034
+#define PEXPRERRMASK            0x040
+#define PEXPRERRSTS             0x044
+#define PEXPRERRID01            0x048
+#define PEXPRERRID23            0x04c
+#define PEXVDMASK               0x050
+#define PEXVDSTS                0x054
+#define PEXRCVCPLIDA            0x060
+#define PEXLENERRIDA            0x068
+#define PEXPHYPLLST             0x070
+#define PEXDMRDEN0              0x100
+#define PEXDMRDADR0             0x104
+#define PEXDMRDENX              0x110
+#define PEXDMRDADRX             0x114
+#define PEXECMODE               0xf00
+#define PEXMAEA(n)              (0xf50 + (8 * n))
+#define PEXMAEC(n)              (0xf54 + (8 * n))
+#define PEXCCRCTRL              0xff0
+
+/* SCC PCIEXC bits and shifts for PEXCADRS */
+#define PEXCADRS_BYTE_EN_SHIFT          20
+#define PEXCADRS_CMD_SHIFT              16
+#define PEXCADRS_CMD_READ               (0xa << PEXCADRS_CMD_SHIFT)
+#define PEXCADRS_CMD_WRITE              (0xb << PEXCADRS_CMD_SHIFT)
+
+/* SCC PCIEXC shifts for PEXDADRS */
+#define PEXDADRS_BUSNO_SHIFT            20
+#define PEXDADRS_DEVNO_SHIFT            15
+#define PEXDADRS_FUNCNO_SHIFT           12
+
+/* SCC PCIEXC bits and shifts for PEXDCMND */
+#define PEXDCMND_BYTE_EN_SHIFT          4
+#define PEXDCMND_IO_READ                0x2
+#define PEXDCMND_IO_WRITE               0x3
+#define PEXDCMND_CONFIG_READ            0xa
+#define PEXDCMND_CONFIG_WRITE           0xb
+
+/* SCC PCIEXC bits for PEXPHYPLLST */
+#define PEXPHYPLLST_PEXPHYAPLLST        0x00000001
+
+/* SCC PCIEXC bits for PEXECMODE */
+#define PEXECMODE_ALL_THROUGH           0x00000000
+#define PEXECMODE_ALL_8BIT              0x00550155
+#define PEXECMODE_ALL_16BIT             0x00aa02aa
+
+/* SCC PCIEXC bits for PEXCCRCTRL */
+#define PEXCCRCTRL_PEXIPCOREEN          0x00040000
+#define PEXCCRCTRL_PEXIPCONTEN          0x00020000
+#define PEXCCRCTRL_PEXPHYPLLEN          0x00010000
+#define PEXCCRCTRL_PCIEXCAOCKEN         0x00000100
+
+/* SCC PCIEXC port configuration registers */
+#define PEXTCERRCHK             0x21c
+#define PEXTAMAPB0              0x220
+#define PEXTAMAPL0              0x224
+#define PEXTAMAPB(n)            (PEXTAMAPB0 + 8 * (n))
+#define PEXTAMAPL(n)            (PEXTAMAPL0 + 8 * (n))
+#define PEXCHVC0P               0x500
+#define PEXCHVC0NP              0x504
+#define PEXCHVC0C               0x508
+#define PEXCDVC0P               0x50c
+#define PEXCDVC0NP              0x510
+#define PEXCDVC0C               0x514
+#define PEXCHVCXP               0x518
+#define PEXCHVCXNP              0x51c
+#define PEXCHVCXC               0x520
+#define PEXCDVCXP               0x524
+#define PEXCDVCXNP              0x528
+#define PEXCDVCXC               0x52c
+#define PEXCTTRG                0x530
+#define PEXTSCTRL               0x700
+#define PEXTSSTS                0x704
+#define PEXSKPCTRL              0x708
+
 /* UHC registers */
 #define SCC_UHC_CKRCTRL         0xff0
 #define SCC_UHC_ECMODE          0xf00