[POWERPC] PIKA Warp: Update platform code to support Rev B boards

* Switched from 64M NOR/64M NAND to 4M NOR/256M NAND.
* Full DTM support including critical temperature.
* Added POST information.
* Removed LED function, moved to new LED driver.
* Moved ad7414 to new style I2C initialization.

Signed-off-by: Sean MacLennan <smaclennan@pikatech.com>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>

1 files changed, 37 insertions, 12 deletions

diff --git a/arch/powerpc/platforms/44x/warp-nand.c b/arch/powerpc/platforms/44x/warp-nand.c
index 9150318cfc56..d293c702e734 100644
--- a/arch/powerpc/platforms/44x/warp-nand.c
+++ b/arch/powerpc/platforms/44x/warp-nand.c
@@ -11,8 +11,10 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/ndfc.h>
+#include <linux/of.h>
 #include <asm/machdep.h>
 
+
 #ifdef CONFIG_MTD_NAND_NDFC
 
 #define CS_NAND_0       1       /* use chip select 1 for NAND device 0 */
@@ -35,13 +37,23 @@ static struct mtd_partition nand_parts[] = {
         {
                 .name   = "root",
                 .offset = 0x0200000,
-                .size   = 0x3400000
+                .size   = 0x3E00000
+        },
+        {
+                .name   = "persistent",
+                .offset = 0x4000000,
+                .size   = 0x4000000
         },
         {
-                .name   = "user",
-                .offset = 0x3600000,
-                .size   = 0x0A00000
+                .name   = "persistent1",
+                .offset = 0x8000000,
+                .size   = 0x4000000
         },
+        {
+                .name   = "persistent2",
+                .offset = 0xC000000,
+                .size   = 0x4000000
+        }
 };
 
 struct ndfc_controller_settings warp_ndfc_settings = {
@@ -67,19 +79,15 @@ static struct platform_device warp_ndfc_device = {
         .resource = &warp_ndfc,
 };
 
-static struct nand_ecclayout nand_oob_16 = {
-        .eccbytes = 3,
-        .eccpos = { 0, 1, 2, 3, 6, 7 },
-        .oobfree = { {.offset = 8, .length = 16} }
-};
-
+/* Do NOT set the ecclayout: let it default so it is correct for both
+ * 64M and 256M flash chips.
+ */
 static struct platform_nand_chip warp_nand_chip0 = {
         .nr_chips = 1,
         .chip_offset = CS_NAND_0,
         .nr_partitions = ARRAY_SIZE(nand_parts),
         .partitions = nand_parts,
-        .chip_delay = 50,
-        .ecclayout = &nand_oob_16,
+        .chip_delay = 20,
         .priv = &warp_chip0_settings,
 };
 
@@ -96,6 +104,23 @@ static struct platform_device warp_nand_device = {
 
 static int warp_setup_nand_flash(void)
 {
+        struct device_node *np;
+
+        /* Try to detect a rev A based on NOR size. */
+        np = of_find_compatible_node(NULL, NULL, "cfi-flash");
+        if (np) {
+                struct property *pp;
+
+                pp = of_find_property(np, "reg", NULL);
+                if (pp && (pp->length == 12)) {
+                        u32 *v = pp->value;
+                        if (v[2] == 0x4000000)
+                                /* Rev A = 64M NAND */
+                                warp_nand_chip0.nr_partitions = 2;
+                }
+                of_node_put(np);
+        }
+
         platform_device_register(&warp_ndfc_device);
         platform_device_register(&warp_nand_device);