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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2009-03-19 15:34:08 -0400
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2009-03-23 22:47:33 -0400
commit8d1cf34e7ad5c7738ce20d20bd7f002f562cb8b5 (patch)
treef731b8b2d3e71e7287bed977bdd7fc9ea6942d45 /arch/powerpc/mm
parent2a7d55fda58eb4e3652252d4f71222bd1ff90c5e (diff)
powerpc/mm: Tweak PTE bit combination definitions
This patch tweaks the way some PTE bit combinations are defined, in such a way that the 32 and 64-bit variant become almost identical and that will make it easier to bring in a new common pte-* file for the new variant of the Book3-E support. The combination of bits defining access to kernel pages are now clearly separated from the combination used by userspace and the core VM. The resulting generated code should remain identical unless I made a mistake. Note: While at it, I removed a non-sensical statement related to CONFIG_KGDB in ppc_mmu_32.c which could cause kernel mappings to be user accessible when that option is enabled. Probably something that bitrot. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/mm')
-rw-r--r--arch/powerpc/mm/fsl_booke_mmu.c2
-rw-r--r--arch/powerpc/mm/pgtable_32.c4
-rw-r--r--arch/powerpc/mm/ppc_mmu_32.c10
3 files changed, 5 insertions, 11 deletions
diff --git a/arch/powerpc/mm/fsl_booke_mmu.c b/arch/powerpc/mm/fsl_booke_mmu.c
index 985b6c361ab4..bb3d65998e6b 100644
--- a/arch/powerpc/mm/fsl_booke_mmu.c
+++ b/arch/powerpc/mm/fsl_booke_mmu.c
@@ -162,7 +162,7 @@ unsigned long __init mmu_mapin_ram(void)
162 phys_addr_t phys = memstart_addr; 162 phys_addr_t phys = memstart_addr;
163 163
164 while (cam[tlbcam_index] && tlbcam_index < ARRAY_SIZE(cam)) { 164 while (cam[tlbcam_index] && tlbcam_index < ARRAY_SIZE(cam)) {
165 settlbcam(tlbcam_index, virt, phys, cam[tlbcam_index], _PAGE_KERNEL, 0); 165 settlbcam(tlbcam_index, virt, phys, cam[tlbcam_index], PAGE_KERNEL_X, 0);
166 virt += cam[tlbcam_index]; 166 virt += cam[tlbcam_index];
167 phys += cam[tlbcam_index]; 167 phys += cam[tlbcam_index];
168 tlbcam_index++; 168 tlbcam_index++;
diff --git a/arch/powerpc/mm/pgtable_32.c b/arch/powerpc/mm/pgtable_32.c
index 0f8c4371dfab..430d0908fa50 100644
--- a/arch/powerpc/mm/pgtable_32.c
+++ b/arch/powerpc/mm/pgtable_32.c
@@ -164,7 +164,7 @@ __ioremap_caller(phys_addr_t addr, unsigned long size, unsigned long flags,
164 164
165 /* Make sure we have the base flags */ 165 /* Make sure we have the base flags */
166 if ((flags & _PAGE_PRESENT) == 0) 166 if ((flags & _PAGE_PRESENT) == 0)
167 flags |= _PAGE_KERNEL; 167 flags |= PAGE_KERNEL;
168 168
169 /* Non-cacheable page cannot be coherent */ 169 /* Non-cacheable page cannot be coherent */
170 if (flags & _PAGE_NO_CACHE) 170 if (flags & _PAGE_NO_CACHE)
@@ -296,7 +296,7 @@ void __init mapin_ram(void)
296 p = memstart_addr + s; 296 p = memstart_addr + s;
297 for (; s < total_lowmem; s += PAGE_SIZE) { 297 for (; s < total_lowmem; s += PAGE_SIZE) {
298 ktext = ((char *) v >= _stext && (char *) v < etext); 298 ktext = ((char *) v >= _stext && (char *) v < etext);
299 f = ktext ?_PAGE_RAM_TEXT : _PAGE_RAM; 299 f = ktext ? PAGE_KERNEL_TEXT : PAGE_KERNEL;
300 map_page(v, p, f); 300 map_page(v, p, f);
301#ifdef CONFIG_PPC_STD_MMU_32 301#ifdef CONFIG_PPC_STD_MMU_32
302 if (ktext) 302 if (ktext)
diff --git a/arch/powerpc/mm/ppc_mmu_32.c b/arch/powerpc/mm/ppc_mmu_32.c
index fe65c405412c..2d2a87e10154 100644
--- a/arch/powerpc/mm/ppc_mmu_32.c
+++ b/arch/powerpc/mm/ppc_mmu_32.c
@@ -74,9 +74,6 @@ unsigned long p_mapped_by_bats(phys_addr_t pa)
74 74
75unsigned long __init mmu_mapin_ram(void) 75unsigned long __init mmu_mapin_ram(void)
76{ 76{
77#ifdef CONFIG_POWER4
78 return 0;
79#else
80 unsigned long tot, bl, done; 77 unsigned long tot, bl, done;
81 unsigned long max_size = (256<<20); 78 unsigned long max_size = (256<<20);
82 79
@@ -95,7 +92,7 @@ unsigned long __init mmu_mapin_ram(void)
95 break; 92 break;
96 } 93 }
97 94
98 setbat(2, PAGE_OFFSET, 0, bl, _PAGE_RAM); 95 setbat(2, PAGE_OFFSET, 0, bl, PAGE_KERNEL_X);
99 done = (unsigned long)bat_addrs[2].limit - PAGE_OFFSET + 1; 96 done = (unsigned long)bat_addrs[2].limit - PAGE_OFFSET + 1;
100 if ((done < tot) && !bat_addrs[3].limit) { 97 if ((done < tot) && !bat_addrs[3].limit) {
101 /* use BAT3 to cover a bit more */ 98 /* use BAT3 to cover a bit more */
@@ -103,12 +100,11 @@ unsigned long __init mmu_mapin_ram(void)
103 for (bl = 128<<10; bl < max_size; bl <<= 1) 100 for (bl = 128<<10; bl < max_size; bl <<= 1)
104 if (bl * 2 > tot) 101 if (bl * 2 > tot)
105 break; 102 break;
106 setbat(3, PAGE_OFFSET+done, done, bl, _PAGE_RAM); 103 setbat(3, PAGE_OFFSET+done, done, bl, PAGE_KERNEL_X);
107 done = (unsigned long)bat_addrs[3].limit - PAGE_OFFSET + 1; 104 done = (unsigned long)bat_addrs[3].limit - PAGE_OFFSET + 1;
108 } 105 }
109 106
110 return done; 107 return done;
111#endif
112} 108}
113 109
114/* 110/*
@@ -136,9 +132,7 @@ void __init setbat(int index, unsigned long virt, phys_addr_t phys,
136 wimgxpp |= (flags & _PAGE_RW)? BPP_RW: BPP_RX; 132 wimgxpp |= (flags & _PAGE_RW)? BPP_RW: BPP_RX;
137 bat[1].batu = virt | (bl << 2) | 2; /* Vs=1, Vp=0 */ 133 bat[1].batu = virt | (bl << 2) | 2; /* Vs=1, Vp=0 */
138 bat[1].batl = BAT_PHYS_ADDR(phys) | wimgxpp; 134 bat[1].batl = BAT_PHYS_ADDR(phys) | wimgxpp;
139#ifndef CONFIG_KGDB /* want user access for breakpoints */
140 if (flags & _PAGE_USER) 135 if (flags & _PAGE_USER)
141#endif
142 bat[1].batu |= 1; /* Vp = 1 */ 136 bat[1].batu |= 1; /* Vp = 1 */
143 if (flags & _PAGE_GUARDED) { 137 if (flags & _PAGE_GUARDED) {
144 /* G bit must be zero in IBATs */ 138 /* G bit must be zero in IBATs */