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authorScott Wood <scottwood@freescale.com>2014-03-10 18:29:38 -0400
committerScott Wood <scottwood@freescale.com>2014-03-19 20:57:27 -0400
commit609af38f8fc0f1dab993b2c67f90d07f761ea902 (patch)
treea8d0383323961cc1dd7aeb331c7c29a8ed478995 /arch/powerpc/mm
parent31f712482894d723e38490139eb03156a5d3eb59 (diff)
powerpc/booke64: Critical and machine check exception support
Add special state saving for critical and machine check exceptions. Most of this code could be used to handle debug exceptions taken from kernel space, but actually doing so is outside the scope of this patch. The various critical and machine check exceptions now point to their real handlers, rather than hanging the kernel. Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'arch/powerpc/mm')
-rw-r--r--arch/powerpc/mm/tlb_nohash.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
index b37a58e1c92d..ae3d5b799b90 100644
--- a/arch/powerpc/mm/tlb_nohash.c
+++ b/arch/powerpc/mm/tlb_nohash.c
@@ -144,6 +144,15 @@ int mmu_vmemmap_psize; /* Page size used for the virtual mem map */
144int book3e_htw_mode; /* HW tablewalk? Value is PPC_HTW_* */ 144int book3e_htw_mode; /* HW tablewalk? Value is PPC_HTW_* */
145unsigned long linear_map_top; /* Top of linear mapping */ 145unsigned long linear_map_top; /* Top of linear mapping */
146 146
147
148/*
149 * Number of bytes to add to SPRN_SPRG_TLB_EXFRAME on crit/mcheck/debug
150 * exceptions. This is used for bolted and e6500 TLB miss handlers which
151 * do not modify this SPRG in the TLB miss code; for other TLB miss handlers,
152 * this is set to zero.
153 */
154int extlb_level_exc;
155
147#endif /* CONFIG_PPC64 */ 156#endif /* CONFIG_PPC64 */
148 157
149#ifdef CONFIG_PPC_FSL_BOOK3E 158#ifdef CONFIG_PPC_FSL_BOOK3E
@@ -559,6 +568,7 @@ static void setup_mmu_htw(void)
559 break; 568 break;
560#ifdef CONFIG_PPC_FSL_BOOK3E 569#ifdef CONFIG_PPC_FSL_BOOK3E
561 case PPC_HTW_E6500: 570 case PPC_HTW_E6500:
571 extlb_level_exc = EX_TLB_SIZE;
562 patch_exception(0x1c0, exc_data_tlb_miss_e6500_book3e); 572 patch_exception(0x1c0, exc_data_tlb_miss_e6500_book3e);
563 patch_exception(0x1e0, exc_instruction_tlb_miss_e6500_book3e); 573 patch_exception(0x1e0, exc_instruction_tlb_miss_e6500_book3e);
564 break; 574 break;
@@ -652,6 +662,7 @@ static void __early_init_mmu(int boot_cpu)
652 memblock_enforce_memory_limit(linear_map_top); 662 memblock_enforce_memory_limit(linear_map_top);
653 663
654 if (book3e_htw_mode == PPC_HTW_NONE) { 664 if (book3e_htw_mode == PPC_HTW_NONE) {
665 extlb_level_exc = EX_TLB_SIZE;
655 patch_exception(0x1c0, exc_data_tlb_miss_bolted_book3e); 666 patch_exception(0x1c0, exc_data_tlb_miss_bolted_book3e);
656 patch_exception(0x1e0, 667 patch_exception(0x1e0,
657 exc_instruction_tlb_miss_bolted_book3e); 668 exc_instruction_tlb_miss_bolted_book3e);