diff options
author | Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> | 2012-09-09 22:52:55 -0400 |
---|---|---|
committer | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2012-09-17 02:31:51 -0400 |
commit | 048ee0993ec8360abb0b51bdf8f8721e9ed62ec4 (patch) | |
tree | a26ea6b76ae86d366fcff10dd54a4ecbbd29c8fb /arch/powerpc/mm | |
parent | 735cafc32b661f08a266a8d754e6cfbd82c11704 (diff) |
powerpc/mm: Add 64TB support
Increase max addressable range to 64TB. This is not tested on
real hardware yet.
Reviewed-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/mm')
-rw-r--r-- | arch/powerpc/mm/slb_low.S | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S index f6a262555ef2..1a16ca227757 100644 --- a/arch/powerpc/mm/slb_low.S +++ b/arch/powerpc/mm/slb_low.S | |||
@@ -56,6 +56,12 @@ _GLOBAL(slb_allocate_realmode) | |||
56 | */ | 56 | */ |
57 | _GLOBAL(slb_miss_kernel_load_linear) | 57 | _GLOBAL(slb_miss_kernel_load_linear) |
58 | li r11,0 | 58 | li r11,0 |
59 | li r9,0x1 | ||
60 | /* | ||
61 | * for 1T we shift 12 bits more. slb_finish_load_1T will do | ||
62 | * the necessary adjustment | ||
63 | */ | ||
64 | rldimi r10,r9,(CONTEXT_BITS + USER_ESID_BITS),0 | ||
59 | BEGIN_FTR_SECTION | 65 | BEGIN_FTR_SECTION |
60 | b slb_finish_load | 66 | b slb_finish_load |
61 | END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT) | 67 | END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT) |
@@ -85,6 +91,12 @@ _GLOBAL(slb_miss_kernel_load_vmemmap) | |||
85 | _GLOBAL(slb_miss_kernel_load_io) | 91 | _GLOBAL(slb_miss_kernel_load_io) |
86 | li r11,0 | 92 | li r11,0 |
87 | 6: | 93 | 6: |
94 | li r9,0x1 | ||
95 | /* | ||
96 | * for 1T we shift 12 bits more. slb_finish_load_1T will do | ||
97 | * the necessary adjustment | ||
98 | */ | ||
99 | rldimi r10,r9,(CONTEXT_BITS + USER_ESID_BITS),0 | ||
88 | BEGIN_FTR_SECTION | 100 | BEGIN_FTR_SECTION |
89 | b slb_finish_load | 101 | b slb_finish_load |
90 | END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT) | 102 | END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT) |