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authorLucas De Marchi <lucas.demarchi@profusion.mobi>2011-03-30 21:57:33 -0400
committerLucas De Marchi <lucas.demarchi@profusion.mobi>2011-03-31 10:26:23 -0400
commit25985edcedea6396277003854657b5f3cb31a628 (patch)
treef026e810210a2ee7290caeb737c23cb6472b7c38 /arch/powerpc/mm/tlb_low_64e.S
parent6aba74f2791287ec407e0f92487a725a25908067 (diff)
Fix common misspellings
Fixes generated by 'codespell' and manually reviewed. Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
Diffstat (limited to 'arch/powerpc/mm/tlb_low_64e.S')
-rw-r--r--arch/powerpc/mm/tlb_low_64e.S4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/powerpc/mm/tlb_low_64e.S b/arch/powerpc/mm/tlb_low_64e.S
index 8526bd9d2aa3..33cf704e4e1b 100644
--- a/arch/powerpc/mm/tlb_low_64e.S
+++ b/arch/powerpc/mm/tlb_low_64e.S
@@ -192,7 +192,7 @@ normal_tlb_miss:
192 or r10,r15,r14 192 or r10,r15,r14
193 193
194BEGIN_MMU_FTR_SECTION 194BEGIN_MMU_FTR_SECTION
195 /* Set the TLB reservation and seach for existing entry. Then load 195 /* Set the TLB reservation and search for existing entry. Then load
196 * the entry. 196 * the entry.
197 */ 197 */
198 PPC_TLBSRX_DOT(0,r16) 198 PPC_TLBSRX_DOT(0,r16)
@@ -425,7 +425,7 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_TLBRSRV)
425 425
426virt_page_table_tlb_miss_fault: 426virt_page_table_tlb_miss_fault:
427 /* If we fault here, things are a little bit tricky. We need to call 427 /* If we fault here, things are a little bit tricky. We need to call
428 * either data or instruction store fault, and we need to retreive 428 * either data or instruction store fault, and we need to retrieve
429 * the original fault address and ESR (for data). 429 * the original fault address and ESR (for data).
430 * 430 *
431 * The thing is, we know that in normal circumstances, this is 431 * The thing is, we know that in normal circumstances, this is