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authorDavid Gibson <david@gibson.dropbear.id.au>2007-04-30 00:06:25 -0400
committerPaul Mackerras <paulus@samba.org>2007-05-02 06:04:29 -0400
commit57d7909e0d2dd54567ae775e22b14076b777042a (patch)
tree6f2e14e0bbb92ff138ae89468136668e58e60d1f /arch/powerpc/mm/44x_mmu.c
parentc3e8011ad1bf4791a9c6d70ac1b377df93a9f5af (diff)
[POWERPC] Revise PPC44x MMU code for arch/powerpc
This patch takes the definitions for the PPC44x MMU (a software loaded TLB) from asm-ppc/mmu.h, cleans them up of things no longer necessary in arch/powerpc and puts them in a new asm-powerpc/mmu_44x.h file. It also substantially simplifies arch/powerpc/mm/44x_mmu.c and makes a couple of small fixes necessary for the 44x MMU code to build and work properly in arch/powerpc. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc/mm/44x_mmu.c')
-rw-r--r--arch/powerpc/mm/44x_mmu.c82
1 files changed, 19 insertions, 63 deletions
diff --git a/arch/powerpc/mm/44x_mmu.c b/arch/powerpc/mm/44x_mmu.c
index 0a0a0487b334..ca4dcb07a939 100644
--- a/arch/powerpc/mm/44x_mmu.c
+++ b/arch/powerpc/mm/44x_mmu.c
@@ -24,73 +24,38 @@
24 * 24 *
25 */ 25 */
26 26
27#include <linux/signal.h>
28#include <linux/sched.h>
29#include <linux/kernel.h>
30#include <linux/errno.h>
31#include <linux/string.h>
32#include <linux/types.h>
33#include <linux/ptrace.h>
34#include <linux/mman.h>
35#include <linux/mm.h>
36#include <linux/swap.h>
37#include <linux/stddef.h>
38#include <linux/vmalloc.h>
39#include <linux/init.h> 27#include <linux/init.h>
40#include <linux/delay.h>
41#include <linux/highmem.h>
42
43#include <asm/pgalloc.h>
44#include <asm/prom.h>
45#include <asm/io.h>
46#include <asm/mmu_context.h>
47#include <asm/pgtable.h>
48#include <asm/mmu.h> 28#include <asm/mmu.h>
49#include <asm/uaccess.h> 29#include <asm/system.h>
50#include <asm/smp.h> 30#include <asm/page.h>
51#include <asm/bootx.h>
52#include <asm/machdep.h>
53#include <asm/setup.h>
54 31
55#include "mmu_decl.h" 32#include "mmu_decl.h"
56 33
57extern char etext[], _stext[];
58
59/* Used by the 44x TLB replacement exception handler. 34/* Used by the 44x TLB replacement exception handler.
60 * Just needed it declared someplace. 35 * Just needed it declared someplace.
61 */ 36 */
62unsigned int tlb_44x_index = 0; 37unsigned int tlb_44x_index; /* = 0 */
63unsigned int tlb_44x_hwater = 62; 38unsigned int tlb_44x_hwater = PPC44x_TLB_SIZE - 1 - PPC44x_EARLY_TLBS;
64 39
65/* 40/*
66 * "Pins" a 256MB TLB entry in AS0 for kernel lowmem 41 * "Pins" a 256MB TLB entry in AS0 for kernel lowmem
67 */ 42 */
68static void __init 43static void __init ppc44x_pin_tlb(unsigned int virt, unsigned int phys)
69ppc44x_pin_tlb(int slot, unsigned int virt, unsigned int phys)
70{ 44{
71 unsigned long attrib = 0; 45 __asm__ __volatile__(
72 46 "tlbwe %2,%3,%4\n"
73 __asm__ __volatile__("\ 47 "tlbwe %1,%3,%5\n"
74 clrrwi %2,%2,10\n\ 48 "tlbwe %0,%3,%6\n"
75 ori %2,%2,%4\n\
76 clrrwi %1,%1,10\n\
77 li %0,0\n\
78 ori %0,%0,%5\n\
79 tlbwe %2,%3,%6\n\
80 tlbwe %1,%3,%7\n\
81 tlbwe %0,%3,%8"
82 : 49 :
83 : "r" (attrib), "r" (phys), "r" (virt), "r" (slot), 50 : "r" (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G),
84 "i" (PPC44x_TLB_VALID | PPC44x_TLB_256M), 51 "r" (phys),
85 "i" (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G), 52 "r" (virt | PPC44x_TLB_VALID | PPC44x_TLB_256M),
53 "r" (tlb_44x_hwater--), /* slot for this TLB entry */
86 "i" (PPC44x_TLB_PAGEID), 54 "i" (PPC44x_TLB_PAGEID),
87 "i" (PPC44x_TLB_XLAT), 55 "i" (PPC44x_TLB_XLAT),
88 "i" (PPC44x_TLB_ATTRIB)); 56 "i" (PPC44x_TLB_ATTRIB));
89} 57}
90 58
91/*
92 * MMU_init_hw does the chip-specific initialization of the MMU hardware.
93 */
94void __init MMU_init_hw(void) 59void __init MMU_init_hw(void)
95{ 60{
96 flush_instruction_cache(); 61 flush_instruction_cache();
@@ -98,22 +63,13 @@ void __init MMU_init_hw(void)
98 63
99unsigned long __init mmu_mapin_ram(void) 64unsigned long __init mmu_mapin_ram(void)
100{ 65{
101 unsigned int pinned_tlbs = 1; 66 unsigned long addr;
102 int i;
103
104 /* Determine number of entries necessary to cover lowmem */
105 pinned_tlbs = (unsigned int)
106 (_ALIGN(total_lowmem, PPC_PIN_SIZE) >> PPC44x_PIN_SHIFT);
107
108 /* Write upper watermark to save location */
109 tlb_44x_hwater = PPC44x_LOW_SLOT - pinned_tlbs;
110 67
111 /* If necessary, set additional pinned TLBs */ 68 /* Pin in enough TLBs to cover any lowmem not covered by the
112 if (pinned_tlbs > 1) 69 * initial 256M mapping established in head_44x.S */
113 for (i = (PPC44x_LOW_SLOT-(pinned_tlbs-1)); i < PPC44x_LOW_SLOT; i++) { 70 for (addr = PPC_PIN_SIZE; addr < total_lowmem;
114 unsigned int phys_addr = (PPC44x_LOW_SLOT-i) * PPC_PIN_SIZE; 71 addr += PPC_PIN_SIZE)
115 ppc44x_pin_tlb(i, phys_addr+PAGE_OFFSET, phys_addr); 72 ppc44x_pin_tlb(addr + PAGE_OFFSET, addr);
116 }
117 73
118 return total_lowmem; 74 return total_lowmem;
119} 75}