Merge branch 'wip-2.6.34' into old-private-masterarchived-private-master

6 files changed, 80 insertions, 68 deletions

diff --git a/arch/powerpc/lib/copy_32.S b/arch/powerpc/lib/copy_32.S
index c657de59abca..74a7f4130b4c 100644
--- a/arch/powerpc/lib/copy_32.S
+++ b/arch/powerpc/lib/copy_32.S
@@ -98,20 +98,7 @@ _GLOBAL(cacheable_memzero)
         bdnz    4b
 3:      mtctr   r9
         li      r7,4
-#if !defined(CONFIG_8xx)
 10:     dcbz    r7,r6
-#else
-10:     stw     r4, 4(r6)
-        stw     r4, 8(r6)
-        stw     r4, 12(r6)
-        stw     r4, 16(r6)
-#if CACHE_LINE_SIZE >= 32
-        stw     r4, 20(r6)
-        stw     r4, 24(r6)
-        stw     r4, 28(r6)
-        stw     r4, 32(r6)
-#endif /* CACHE_LINE_SIZE */
-#endif
         addi    r6,r6,CACHELINE_BYTES
         bdnz    10b
         clrlwi  r5,r8,32-LG_CACHELINE_BYTES
@@ -200,9 +187,7 @@ _GLOBAL(cacheable_memcpy)
         mtctr   r0
         beq     63f
 53:
-#if !defined(CONFIG_8xx)
         dcbz    r11,r6
-#endif
         COPY_16_BYTES
 #if L1_CACHE_BYTES >= 32
         COPY_16_BYTES
@@ -356,14 +341,6 @@ _GLOBAL(__copy_tofrom_user)
         li      r11,4
         beq     63f
 
-#ifdef CONFIG_8xx
-        /* Don't use prefetch on 8xx */
-        mtctr   r0
-        li      r0,0
-53:     COPY_16_BYTES_WITHEX(0)
-        bdnz    53b
-
-#else /* not CONFIG_8xx */
         /* Here we decide how far ahead to prefetch the source */
         li      r3,4
         cmpwi   r0,1
@@ -416,7 +393,6 @@ _GLOBAL(__copy_tofrom_user)
         li      r3,4
         li      r7,0
         bne     114b
-#endif /* CONFIG_8xx */
 
 63:     srwi.   r0,r5,2
         mtctr   r0
diff --git a/arch/powerpc/lib/copypage_64.S b/arch/powerpc/lib/copypage_64.S
index 75f3267fdc30..4d4eeb900486 100644
--- a/arch/powerpc/lib/copypage_64.S
+++ b/arch/powerpc/lib/copypage_64.S
@@ -26,11 +26,11 @@ BEGIN_FTR_SECTION
         srd     r8,r5,r11
 
         mtctr   r8
-setup:
+.Lsetup:
         dcbt    r9,r4
         dcbz    r9,r3
         add     r9,r9,r12
-        bdnz    setup
+        bdnz    .Lsetup
 END_FTR_SECTION_IFSET(CPU_FTR_CP_USE_DCBTZ)
         addi    r3,r3,-8
         srdi    r8,r5,7         /* page is copied in 128 byte strides */
@@ -43,62 +43,62 @@ END_FTR_SECTION_IFSET(CPU_FTR_CP_USE_DCBTZ)
         ld      r7,16(r4)
         ldu     r8,24(r4)
 1:      std     r5,8(r3)
-        ld      r9,8(r4)
         std     r6,16(r3)
+        ld      r9,8(r4)
         ld      r10,16(r4)
         std     r7,24(r3)
-        ld      r11,24(r4)
         std     r8,32(r3)
+        ld      r11,24(r4)
         ld      r12,32(r4)
         std     r9,40(r3)
-        ld      r5,40(r4)
         std     r10,48(r3)
+        ld      r5,40(r4)
         ld      r6,48(r4)
         std     r11,56(r3)
-        ld      r7,56(r4)
         std     r12,64(r3)
+        ld      r7,56(r4)
         ld      r8,64(r4)
         std     r5,72(r3)
-        ld      r9,72(r4)
         std     r6,80(r3)
+        ld      r9,72(r4)
         ld      r10,80(r4)
         std     r7,88(r3)
-        ld      r11,88(r4)
         std     r8,96(r3)
+        ld      r11,88(r4)
         ld      r12,96(r4)
         std     r9,104(r3)
-        ld      r5,104(r4)
         std     r10,112(r3)
+        ld      r5,104(r4)
         ld      r6,112(r4)
         std     r11,120(r3)
-        ld      r7,120(r4)
         stdu    r12,128(r3)
+        ld      r7,120(r4)
         ldu     r8,128(r4)
         bdnz    1b
 
         std     r5,8(r3)
-        ld      r9,8(r4)
         std     r6,16(r3)
+        ld      r9,8(r4)
         ld      r10,16(r4)
         std     r7,24(r3)
-        ld      r11,24(r4)
         std     r8,32(r3)
+        ld      r11,24(r4)
         ld      r12,32(r4)
         std     r9,40(r3)
-        ld      r5,40(r4)
         std     r10,48(r3)
+        ld      r5,40(r4)
         ld      r6,48(r4)
         std     r11,56(r3)
-        ld      r7,56(r4)
         std     r12,64(r3)
+        ld      r7,56(r4)
         ld      r8,64(r4)
         std     r5,72(r3)
-        ld      r9,72(r4)
         std     r6,80(r3)
+        ld      r9,72(r4)
         ld      r10,80(r4)
         std     r7,88(r3)
-        ld      r11,88(r4)
         std     r8,96(r3)
+        ld      r11,88(r4)
         ld      r12,96(r4)
         std     r9,104(r3)
         std     r10,112(r3)
diff --git a/arch/powerpc/lib/copyuser_64.S b/arch/powerpc/lib/copyuser_64.S
index 693b14a778fa..578b625d6a3c 100644
--- a/arch/powerpc/lib/copyuser_64.S
+++ b/arch/powerpc/lib/copyuser_64.S
@@ -44,37 +44,55 @@ BEGIN_FTR_SECTION
         andi.   r0,r4,7
         bne     .Lsrc_unaligned
 END_FTR_SECTION_IFCLR(CPU_FTR_UNALIGNED_LD_STD)
-        srdi    r7,r5,4
-20:     ld      r9,0(r4)
-        addi    r4,r4,-8
-        mtctr   r7
-        andi.   r5,r5,7
-        bf      cr7*4+0,22f
-        addi    r3,r3,8
-        addi    r4,r4,8
-        mr      r8,r9
-        blt     cr1,72f
-21:     ld      r9,8(r4)
-70:     std     r8,8(r3)
-22:     ldu     r8,16(r4)
-71:     stdu    r9,16(r3)
+        blt     cr1,.Ldo_tail           /* if < 16 bytes to copy */
+        srdi    r0,r5,5
+        cmpdi   cr1,r0,0
+20:     ld      r7,0(r4)
+220:    ld      r6,8(r4)
+        addi    r4,r4,16
+        mtctr   r0
+        andi.   r0,r5,0x10
+        beq     22f
+        addi    r3,r3,16
+        addi    r4,r4,-16
+        mr      r9,r7
+        mr      r8,r6
+        beq     cr1,72f
+21:     ld      r7,16(r4)
+221:    ld      r6,24(r4)
+        addi    r4,r4,32
+70:     std     r9,0(r3)
+270:    std     r8,8(r3)
+22:     ld      r9,0(r4)
+222:    ld      r8,8(r4)
+71:     std     r7,16(r3)
+271:    std     r6,24(r3)
+        addi    r3,r3,32
         bdnz    21b
-72:     std     r8,8(r3)
+72:     std     r9,0(r3)
+272:    std     r8,8(r3)
+        andi.   r5,r5,0xf
         beq+    3f
-        addi    r3,r3,16
+        addi    r4,r4,16
 .Ldo_tail:
-        bf      cr7*4+1,1f
-23:     lwz     r9,8(r4)
+        addi    r3,r3,16
+        bf      cr7*4+0,246f
+244:    ld      r9,0(r4)
+        addi    r4,r4,8
+245:    std     r9,0(r3)
+        addi    r3,r3,8
+246:    bf      cr7*4+1,1f
+23:     lwz     r9,0(r4)
         addi    r4,r4,4
 73:     stw     r9,0(r3)
         addi    r3,r3,4
 1:      bf      cr7*4+2,2f
-44:     lhz     r9,8(r4)
+44:     lhz     r9,0(r4)
         addi    r4,r4,2
 74:     sth     r9,0(r3)
         addi    r3,r3,2
 2:      bf      cr7*4+3,3f
-45:     lbz     r9,8(r4)
+45:     lbz     r9,0(r4)
 75:     stb     r9,0(r3)
 3:      li      r3,0
         blr
@@ -220,7 +238,9 @@ END_FTR_SECTION_IFCLR(CPU_FTR_UNALIGNED_LD_STD)
 131:
         addi    r3,r3,8
 120:
+320:
 122:
+322:
 124:
 125:
 126:
@@ -229,9 +249,11 @@ END_FTR_SECTION_IFCLR(CPU_FTR_UNALIGNED_LD_STD)
 129:
 133:
         addi    r3,r3,8
-121:
 132:
         addi    r3,r3,8
+121:
+321:
+344:
 134:
 135:
 138:
@@ -303,18 +325,22 @@ END_FTR_SECTION_IFCLR(CPU_FTR_UNALIGNED_LD_STD)
 183:
         add     r3,r3,r7
         b       1f
+371:
 180:
         addi    r3,r3,8
 171:
 177:
         addi    r3,r3,8
-170:
-172:
+370:
+372:
 176:
 178:
         addi    r3,r3,4
 185:
         addi    r3,r3,4
+170:
+172:
+345:
 173:
 174:
 175:
@@ -341,11 +367,19 @@ END_FTR_SECTION_IFCLR(CPU_FTR_UNALIGNED_LD_STD)
         .section __ex_table,"a"
         .align  3
         .llong  20b,120b
+        .llong  220b,320b
         .llong  21b,121b
+        .llong  221b,321b
         .llong  70b,170b
+        .llong  270b,370b
         .llong  22b,122b
+        .llong  222b,322b
         .llong  71b,171b
+        .llong  271b,371b
         .llong  72b,172b
+        .llong  272b,372b
+        .llong  244b,344b
+        .llong  245b,345b
         .llong  23b,123b
         .llong  73b,173b
         .llong  44b,144b
diff --git a/arch/powerpc/lib/devres.c b/arch/powerpc/lib/devres.c
index 292115d98ea9..deac4d30daf4 100644
--- a/arch/powerpc/lib/devres.c
+++ b/arch/powerpc/lib/devres.c
@@ -8,6 +8,7 @@
  */
 
 #include <linux/device.h>       /* devres_*(), devm_ioremap_release() */
+#include <linux/gfp.h>
 #include <linux/io.h>           /* ioremap_flags() */
 #include <linux/module.h>       /* EXPORT_SYMBOL() */
 
diff --git a/arch/powerpc/lib/feature-fixups.c b/arch/powerpc/lib/feature-fixups.c
index 7e8865bcd683..e640175b65ae 100644
--- a/arch/powerpc/lib/feature-fixups.c
+++ b/arch/powerpc/lib/feature-fixups.c
@@ -112,7 +112,8 @@ void do_feature_fixups(unsigned long value, void *fixup_start, void *fixup_end)
 
 void do_lwsync_fixups(unsigned long value, void *fixup_start, void *fixup_end)
 {
-        unsigned int *start, *end, *dest;
+        long *start, *end;
+        unsigned int *dest;
 
         if (!(value & CPU_FTR_LWSYNC))
                 return ;
diff --git a/arch/powerpc/lib/locks.c b/arch/powerpc/lib/locks.c
index 79d0fa3a470d..58e14fba11b1 100644
--- a/arch/powerpc/lib/locks.c
+++ b/arch/powerpc/lib/locks.c
@@ -25,7 +25,7 @@
 #include <asm/smp.h>
 #include <asm/firmware.h>
 
-void __spin_yield(raw_spinlock_t *lock)
+void __spin_yield(arch_spinlock_t *lock)
 {
         unsigned int lock_value, holder_cpu, yield_count;
 
@@ -55,7 +55,7 @@ void __spin_yield(raw_spinlock_t *lock)
  * This turns out to be the same for read and write locks, since
  * we only know the holder if it is write-locked.
  */
-void __rw_yield(raw_rwlock_t *rw)
+void __rw_yield(arch_rwlock_t *rw)
 {
         int lock_value;
         unsigned int holder_cpu, yield_count;
@@ -82,7 +82,7 @@ void __rw_yield(raw_rwlock_t *rw)
 }
 #endif
 
-void __raw_spin_unlock_wait(raw_spinlock_t *lock)
+void arch_spin_unlock_wait(arch_spinlock_t *lock)
 {
         while (lock->slock) {
                 HMT_low();
@@ -92,4 +92,4 @@ void __raw_spin_unlock_wait(raw_spinlock_t *lock)
         HMT_medium();
 }
 
-EXPORT_SYMBOL(__raw_spin_unlock_wait);
+EXPORT_SYMBOL(arch_spin_unlock_wait);