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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2009-03-23 22:38:30 -0400
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2009-03-23 22:38:30 -0400
commit9e41d9597e7825ec20d690013d32bcec5f3fe16a (patch)
treeac6fea59e9a4a1c2183d6bbd6ffa760680673afb /arch/powerpc/kernel
parent77ecfe8d427f554fabbf258e9d789f1d4c3afd63 (diff)
parent8e0ee43bc2c3e19db56a4adaa9a9b04ce885cd84 (diff)
Merge commit 'origin/master' into next
Diffstat (limited to 'arch/powerpc/kernel')
-rw-r--r--arch/powerpc/kernel/head_32.S15
1 files changed, 12 insertions, 3 deletions
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
index f8c2e6b6f457..d0bad4b93a9c 100644
--- a/arch/powerpc/kernel/head_32.S
+++ b/arch/powerpc/kernel/head_32.S
@@ -514,8 +514,11 @@ InstructionTLBMiss:
514 and r1,r1,r2 /* writable if _RW and _DIRTY */ 514 and r1,r1,r2 /* writable if _RW and _DIRTY */
515 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */ 515 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
516 rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */ 516 rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */
517 ori r1,r1,0xe14 /* clear out reserved bits and M */ 517 ori r1,r1,0xe04 /* clear out reserved bits */
518 andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */ 518 andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
519BEGIN_FTR_SECTION
520 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
521END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
519 mtspr SPRN_RPA,r1 522 mtspr SPRN_RPA,r1
520 mfspr r3,SPRN_IMISS 523 mfspr r3,SPRN_IMISS
521 tlbli r3 524 tlbli r3
@@ -588,8 +591,11 @@ DataLoadTLBMiss:
588 and r1,r1,r2 /* writable if _RW and _DIRTY */ 591 and r1,r1,r2 /* writable if _RW and _DIRTY */
589 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */ 592 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
590 rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */ 593 rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */
591 ori r1,r1,0xe14 /* clear out reserved bits and M */ 594 ori r1,r1,0xe04 /* clear out reserved bits */
592 andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */ 595 andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
596BEGIN_FTR_SECTION
597 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
598END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
593 mtspr SPRN_RPA,r1 599 mtspr SPRN_RPA,r1
594 mfspr r3,SPRN_DMISS 600 mfspr r3,SPRN_DMISS
595 tlbld r3 601 tlbld r3
@@ -656,8 +662,11 @@ DataStoreTLBMiss:
656 stw r3,0(r2) /* update PTE (accessed/dirty bits) */ 662 stw r3,0(r2) /* update PTE (accessed/dirty bits) */
657 /* Convert linux-style PTE to low word of PPC-style PTE */ 663 /* Convert linux-style PTE to low word of PPC-style PTE */
658 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */ 664 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
659 li r1,0xe15 /* clear out reserved bits and M */ 665 li r1,0xe05 /* clear out reserved bits & PP lsb */
660 andc r1,r3,r1 /* PP = user? 2: 0 */ 666 andc r1,r3,r1 /* PP = user? 2: 0 */
667BEGIN_FTR_SECTION
668 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
669END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
661 mtspr SPRN_RPA,r1 670 mtspr SPRN_RPA,r1
662 mfspr r3,SPRN_DMISS 671 mfspr r3,SPRN_DMISS
663 tlbld r3 672 tlbld r3